drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 /* The caprices of the preprocessor require that this be declared right here */
  27 #define CREATE_TRACE_POINTS
  28
  29 #include "dm_services_types.h"
  30 #include "dc.h"
  31 #include "dc/inc/core_types.h"
  32 #include "dal_asic_id.h"
  33
  34 #include "vid.h"
  35 #include "amdgpu.h"
  36 #include "amdgpu_display.h"
  37 #include "amdgpu_ucode.h"
  38 #include "atom.h"
  39 #include "amdgpu_dm.h"
  40 #include "amdgpu_pm.h"
  41
  42 #include "amd_shared.h"
  43 #include "amdgpu_dm_irq.h"
  44 #include "dm_helpers.h"
  45 #include "amdgpu_dm_mst_types.h"
  46 #if defined(CONFIG_DEBUG_FS)
  47 #include "amdgpu_dm_debugfs.h"
  48 #endif
  49
  50 #include "ivsrcid/ivsrcid_vislands30.h"
  51
  52 #include <linux/module.h>
  53 #include <linux/moduleparam.h>
  54 #include <linux/version.h>
  55 #include <linux/types.h>
  56 #include <linux/pm_runtime.h>
  57 #include <linux/pci.h>
  58 #include <linux/firmware.h>
  59 #include <linux/component.h>
  60
  61 #include <drm/drm_atomic.h>
  62 #include <drm/drm_atomic_uapi.h>
  63 #include <drm/drm_atomic_helper.h>
  64 #include <drm/drm_dp_mst_helper.h>
  65 #include <drm/drm_fb_helper.h>
  66 #include <drm/drm_fourcc.h>
  67 #include <drm/drm_edid.h>
  68 #include <drm/drm_vblank.h>
  69 #include <drm/drm_audio_component.h>
  70
  71 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
  72 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
  73
  74 #include "dcn/dcn_1_0_offset.h"
  75 #include "dcn/dcn_1_0_sh_mask.h"
  76 #include "soc15_hw_ip.h"
  77 #include "vega10_ip_offset.h"
  78
  79 #include "soc15_common.h"
  80 #endif
  81
  82 #include "modules/inc/mod_freesync.h"
  83 #include "modules/power/power_helpers.h"
  84 #include "modules/inc/mod_info_packet.h"
  85
  86 #define FIRMWARE_RAVEN_DMCU             "amdgpu/raven_dmcu.bin"
  87 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
  88
  89 /**
  90  * DOC: overview
  91  *
  92  * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
  93  * **dm**) sits between DRM and DC. It acts as a liason, converting DRM
  94  * requests into DC requests, and DC responses into DRM responses.
  95  *
  96  * The root control structure is &struct amdgpu_display_manager.
  97  */
  98
  99 /* basic init/fini API */
 100 static int amdgpu_dm_init(struct amdgpu_device *adev);
 101 static void amdgpu_dm_fini(struct amdgpu_device *adev);
 102
 103 /*
 104  * initializes drm_device display related structures, based on the information
 105  * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
 106  * drm_encoder, drm_mode_config
 107  *
 108  * Returns 0 on success
 109  */
 110 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
 111 /* removes and deallocates the drm structures, created by the above function */
 112 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
 113
 114 static void
 115 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
 116
 117 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
 118                                 struct drm_plane *plane,
 119                                 unsigned long possible_crtcs,
 120                                 const struct dc_plane_cap *plane_cap);
 121 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
 122                                struct drm_plane *plane,
 123                                uint32_t link_index);
 124 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
 125                                     struct amdgpu_dm_connector *amdgpu_dm_connector,
 126                                     uint32_t link_index,
 127                                     struct amdgpu_encoder *amdgpu_encoder);
 128 static int amdgpu_dm_encoder_init(struct drm_device *dev,
 129                                   struct amdgpu_encoder *aencoder,
 130                                   uint32_t link_index);
 131
 132 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
 133
 134 static int amdgpu_dm_atomic_commit(struct drm_device *dev,
 135                                    struct drm_atomic_state *state,
 136                                    bool nonblock);
 137
 138 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
 139
 140 static int amdgpu_dm_atomic_check(struct drm_device *dev,
 141                                   struct drm_atomic_state *state);
 142
 143 static void handle_cursor_update(struct drm_plane *plane,
 144                                  struct drm_plane_state *old_plane_state);
 145
 146 /*
 147  * dm_vblank_get_counter
 148  *
 149  * @brief
 150  * Get counter for number of vertical blanks
 151  *
 152  * @param
 153  * struct amdgpu_device *adev - [in] desired amdgpu device
 154  * int disp_idx - [in] which CRTC to get the counter from
 155  *
 156  * @return
 157  * Counter for vertical blanks
 158  */
 159 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 160 {
 161         if (crtc >= adev->mode_info.num_crtc)
 162                 return 0;
 163         else {
 164                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 165                 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
 166                                 acrtc->base.state);
 167
 168
 169                 if (acrtc_state->stream == NULL) {
 170                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 171                                   crtc);
 172                         return 0;
 173                 }
 174
 175                 return dc_stream_get_vblank_counter(acrtc_state->stream);
 176         }
 177 }
 178
 179 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 180                                   u32 *vbl, u32 *position)
 181 {
 182         uint32_t v_blank_start, v_blank_end, h_position, v_position;
 183
 184         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 185                 return -EINVAL;
 186         else {
 187                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 188                 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
 189                                                 acrtc->base.state);
 190
 191                 if (acrtc_state->stream ==  NULL) {
 192                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 193                                   crtc);
 194                         return 0;
 195                 }
 196
 197                 /*
 198                  * TODO rework base driver to use values directly.
 199                  * for now parse it back into reg-format
 200                  */
 201                 dc_stream_get_scanoutpos(acrtc_state->stream,
 202                                          &v_blank_start,
 203                                          &v_blank_end,
 204                                          &h_position,
 205                                          &v_position);
 206
 207                 *position = v_position | (h_position << 16);
 208                 *vbl = v_blank_start | (v_blank_end << 16);
 209         }
 210
 211         return 0;
 212 }
 213
 214 static bool dm_is_idle(void *handle)
 215 {
 216         /* XXX todo */
 217         return true;
 218 }
 219
 220 static int dm_wait_for_idle(void *handle)
 221 {
 222         /* XXX todo */
 223         return 0;
 224 }
 225
 226 static bool dm_check_soft_reset(void *handle)
 227 {
 228         return false;
 229 }
 230
 231 static int dm_soft_reset(void *handle)
 232 {
 233         /* XXX todo */
 234         return 0;
 235 }
 236
 237 static struct amdgpu_crtc *
 238 get_crtc_by_otg_inst(struct amdgpu_device *adev,
 239                      int otg_inst)
 240 {
 241         struct drm_device *dev = adev->ddev;
 242         struct drm_crtc *crtc;
 243         struct amdgpu_crtc *amdgpu_crtc;
 244
 245         if (otg_inst == -1) {
 246                 WARN_ON(1);
 247                 return adev->mode_info.crtcs[0];
 248         }
 249
 250         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 251                 amdgpu_crtc = to_amdgpu_crtc(crtc);
 252
 253                 if (amdgpu_crtc->otg_inst == otg_inst)
 254                         return amdgpu_crtc;
 255         }
 256
 257         return NULL;
 258 }
 259
 260 static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state)
 261 {
 262         return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||
 263                dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
 264 }
 265
 266 static void dm_pflip_high_irq(void *interrupt_params)
 267 {
 268         struct amdgpu_crtc *amdgpu_crtc;
 269         struct common_irq_params *irq_params = interrupt_params;
 270         struct amdgpu_device *adev = irq_params->adev;
 271         unsigned long flags;
 272         struct drm_pending_vblank_event *e;
 273         struct dm_crtc_state *acrtc_state;
 274         uint32_t vpos, hpos, v_blank_start, v_blank_end;
 275         bool vrr_active;
 276
 277         amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
 278
 279         /* IRQ could occur when in initial stage */
 280         /* TODO work and BO cleanup */
 281         if (amdgpu_crtc == NULL) {
 282                 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
 283                 return;
 284         }
 285
 286         spin_lock_irqsave(&adev->ddev->event_lock, flags);
 287
 288         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
 289                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
 290                                                  amdgpu_crtc->pflip_status,
 291                                                  AMDGPU_FLIP_SUBMITTED,
 292                                                  amdgpu_crtc->crtc_id,
 293                                                  amdgpu_crtc);
 294                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 295                 return;
 296         }
 297
 298         /* page flip completed. */
 299         e = amdgpu_crtc->event;
 300         amdgpu_crtc->event = NULL;
 301
 302         if (!e)
 303                 WARN_ON(1);
 304
 305         acrtc_state = to_dm_crtc_state(amdgpu_crtc->base.state);
 306         vrr_active = amdgpu_dm_vrr_active(acrtc_state);
 307
 308         /* Fixed refresh rate, or VRR scanout position outside front-porch? */
 309         if (!vrr_active ||
 310             !dc_stream_get_scanoutpos(acrtc_state->stream, &v_blank_start,
 311                                       &v_blank_end, &hpos, &vpos) ||
 312             (vpos < v_blank_start)) {
 313                 /* Update to correct count and vblank timestamp if racing with
 314                  * vblank irq. This also updates to the correct vblank timestamp
 315                  * even in VRR mode, as scanout is past the front-porch atm.
 316                  */
 317                 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
 318
 319                 /* Wake up userspace by sending the pageflip event with proper
 320                  * count and timestamp of vblank of flip completion.
 321                  */
 322                 if (e) {
 323                         drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
 324
 325                         /* Event sent, so done with vblank for this flip */
 326                         drm_crtc_vblank_put(&amdgpu_crtc->base);
 327                 }
 328         } else if (e) {
 329                 /* VRR active and inside front-porch: vblank count and
 330                  * timestamp for pageflip event will only be up to date after
 331                  * drm_crtc_handle_vblank() has been executed from late vblank
 332                  * irq handler after start of back-porch (vline 0). We queue the
 333                  * pageflip event for send-out by drm_crtc_handle_vblank() with
 334                  * updated timestamp and count, once it runs after us.
 335                  *
 336                  * We need to open-code this instead of using the helper
 337                  * drm_crtc_arm_vblank_event(), as that helper would
 338                  * call drm_crtc_accurate_vblank_count(), which we must
 339                  * not call in VRR mode while we are in front-porch!
 340                  */
 341
 342                 /* sequence will be replaced by real count during send-out. */
 343                 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
 344                 e->pipe = amdgpu_crtc->crtc_id;
 345
 346                 list_add_tail(&e->base.link, &adev->ddev->vblank_event_list);
 347                 e = NULL;
 348         }
 349
 350         /* Keep track of vblank of this flip for flip throttling. We use the
 351          * cooked hw counter, as that one incremented at start of this vblank
 352          * of pageflip completion, so last_flip_vblank is the forbidden count
 353          * for queueing new pageflips if vsync + VRR is enabled.
 354          */
 355         amdgpu_crtc->last_flip_vblank = amdgpu_get_vblank_counter_kms(adev->ddev,
 356                                                         amdgpu_crtc->crtc_id);
 357
 358         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 359         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 360
 361         DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
 362                          amdgpu_crtc->crtc_id, amdgpu_crtc,
 363                          vrr_active, (int) !e);
 364 }
 365
 366 static void dm_vupdate_high_irq(void *interrupt_params)
 367 {
 368         struct common_irq_params *irq_params = interrupt_params;
 369         struct amdgpu_device *adev = irq_params->adev;
 370         struct amdgpu_crtc *acrtc;
 371         struct dm_crtc_state *acrtc_state;
 372         unsigned long flags;
 373
 374         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
 375
 376         if (acrtc) {
 377                 acrtc_state = to_dm_crtc_state(acrtc->base.state);
 378
 379                 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
 380                                  amdgpu_dm_vrr_active(acrtc_state));
 381
 382                 /* Core vblank handling is done here after end of front-porch in
 383                  * vrr mode, as vblank timestamping will give valid results
 384                  * while now done after front-porch. This will also deliver
 385                  * page-flip completion events that have been queued to us
 386                  * if a pageflip happened inside front-porch.
 387                  */
 388                 if (amdgpu_dm_vrr_active(acrtc_state)) {
 389                         drm_crtc_handle_vblank(&acrtc->base);
 390
 391                         /* BTR processing for pre-DCE12 ASICs */
 392                         if (acrtc_state->stream &&
 393                             adev->family < AMDGPU_FAMILY_AI) {
 394                                 spin_lock_irqsave(&adev->ddev->event_lock, flags);
 395                                 mod_freesync_handle_v_update(
 396                                     adev->dm.freesync_module,
 397                                     acrtc_state->stream,
 398                                     &acrtc_state->vrr_params);
 399
 400                                 dc_stream_adjust_vmin_vmax(
 401                                     adev->dm.dc,
 402                                     acrtc_state->stream,
 403                                     &acrtc_state->vrr_params.adjust);
 404                                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 405                         }
 406                 }
 407         }
 408 }
 409
 410 static void dm_crtc_high_irq(void *interrupt_params)
 411 {
 412         struct common_irq_params *irq_params = interrupt_params;
 413         struct amdgpu_device *adev = irq_params->adev;
 414         struct amdgpu_crtc *acrtc;
 415         struct dm_crtc_state *acrtc_state;
 416         unsigned long flags;
 417
 418         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
 419
 420         if (acrtc) {
 421                 acrtc_state = to_dm_crtc_state(acrtc->base.state);
 422
 423                 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
 424                                  amdgpu_dm_vrr_active(acrtc_state));
 425
 426                 /* Core vblank handling at start of front-porch is only possible
 427                  * in non-vrr mode, as only there vblank timestamping will give
 428                  * valid results while done in front-porch. Otherwise defer it
 429                  * to dm_vupdate_high_irq after end of front-porch.
 430                  */
 431                 if (!amdgpu_dm_vrr_active(acrtc_state))
 432                         drm_crtc_handle_vblank(&acrtc->base);
 433
 434                 /* Following stuff must happen at start of vblank, for crc
 435                  * computation and below-the-range btr support in vrr mode.
 436                  */
 437                 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
 438
 439                 if (acrtc_state->stream && adev->family >= AMDGPU_FAMILY_AI &&
 440                     acrtc_state->vrr_params.supported &&
 441                     acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) {
 442                         spin_lock_irqsave(&adev->ddev->event_lock, flags);
 443                         mod_freesync_handle_v_update(
 444                                 adev->dm.freesync_module,
 445                                 acrtc_state->stream,
 446                                 &acrtc_state->vrr_params);
 447
 448                         dc_stream_adjust_vmin_vmax(
 449                                 adev->dm.dc,
 450                                 acrtc_state->stream,
 451                                 &acrtc_state->vrr_params.adjust);
 452                         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 453                 }
 454         }
 455 }
 456
 457 static int dm_set_clockgating_state(void *handle,
 458                   enum amd_clockgating_state state)
 459 {
 460         return 0;
 461 }
 462
 463 static int dm_set_powergating_state(void *handle,
 464                   enum amd_powergating_state state)
 465 {
 466         return 0;
 467 }
 468
 469 /* Prototypes of private functions */
 470 static int dm_early_init(void* handle);
 471
 472 /* Allocate memory for FBC compressed data  */
 473 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 474 {
 475         struct drm_device *dev = connector->dev;
 476         struct amdgpu_device *adev = dev->dev_private;
 477         struct dm_comressor_info *compressor = &adev->dm.compressor;
 478         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
 479         struct drm_display_mode *mode;
 480         unsigned long max_size = 0;
 481
 482         if (adev->dm.dc->fbc_compressor == NULL)
 483                 return;
 484
 485         if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
 486                 return;
 487
 488         if (compressor->bo_ptr)
 489                 return;
 490
 491
 492         list_for_each_entry(mode, &connector->modes, head) {
 493                 if (max_size < mode->htotal * mode->vtotal)
 494                         max_size = mode->htotal * mode->vtotal;
 495         }
 496
 497         if (max_size) {
 498                 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
 499                             AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
 500                             &compressor->gpu_addr, &compressor->cpu_addr);
 501
 502                 if (r)
 503                         DRM_ERROR("DM: Failed to initialize FBC\n");
 504                 else {
 505                         adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
 506                         DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
 507                 }
 508
 509         }
 510
 511 }
 512
 513 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
 514                                           int pipe, bool *enabled,
 515                                           unsigned char *buf, int max_bytes)
 516 {
 517         struct drm_device *dev = dev_get_drvdata(kdev);
 518         struct amdgpu_device *adev = dev->dev_private;
 519         struct drm_connector *connector;
 520         struct drm_connector_list_iter conn_iter;
 521         struct amdgpu_dm_connector *aconnector;
 522         int ret = 0;
 523
 524         *enabled = false;
 525
 526         mutex_lock(&adev->dm.audio_lock);
 527
 528         drm_connector_list_iter_begin(dev, &conn_iter);
 529         drm_for_each_connector_iter(connector, &conn_iter) {
 530                 aconnector = to_amdgpu_dm_connector(connector);
 531                 if (aconnector->audio_inst != port)
 532                         continue;
 533
 534                 *enabled = true;
 535                 ret = drm_eld_size(connector->eld);
 536                 memcpy(buf, connector->eld, min(max_bytes, ret));
 537
 538                 break;
 539         }
 540         drm_connector_list_iter_end(&conn_iter);
 541
 542         mutex_unlock(&adev->dm.audio_lock);
 543
 544         DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
 545
 546         return ret;
 547 }
 548
 549 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
 550         .get_eld = amdgpu_dm_audio_component_get_eld,
 551 };
 552
 553 static int amdgpu_dm_audio_component_bind(struct device *kdev,
 554                                        struct device *hda_kdev, void *data)
 555 {
 556         struct drm_device *dev = dev_get_drvdata(kdev);
 557         struct amdgpu_device *adev = dev->dev_private;
 558         struct drm_audio_component *acomp = data;
 559
 560         acomp->ops = &amdgpu_dm_audio_component_ops;
 561         acomp->dev = kdev;
 562         adev->dm.audio_component = acomp;
 563
 564         return 0;
 565 }
 566
 567 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
 568                                           struct device *hda_kdev, void *data)
 569 {
 570         struct drm_device *dev = dev_get_drvdata(kdev);
 571         struct amdgpu_device *adev = dev->dev_private;
 572         struct drm_audio_component *acomp = data;
 573
 574         acomp->ops = NULL;
 575         acomp->dev = NULL;
 576         adev->dm.audio_component = NULL;
 577 }
 578
 579 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
 580         .bind   = amdgpu_dm_audio_component_bind,
 581         .unbind = amdgpu_dm_audio_component_unbind,
 582 };
 583
 584 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
 585 {
 586         int i, ret;
 587
 588         if (!amdgpu_audio)
 589                 return 0;
 590
 591         adev->mode_info.audio.enabled = true;
 592
 593         adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
 594
 595         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
 596                 adev->mode_info.audio.pin[i].channels = -1;
 597                 adev->mode_info.audio.pin[i].rate = -1;
 598                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
 599                 adev->mode_info.audio.pin[i].status_bits = 0;
 600                 adev->mode_info.audio.pin[i].category_code = 0;
 601                 adev->mode_info.audio.pin[i].connected = false;
 602                 adev->mode_info.audio.pin[i].id =
 603                         adev->dm.dc->res_pool->audios[i]->inst;
 604                 adev->mode_info.audio.pin[i].offset = 0;
 605         }
 606
 607         ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
 608         if (ret < 0)
 609                 return ret;
 610
 611         adev->dm.audio_registered = true;
 612
 613         return 0;
 614 }
 615
 616 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
 617 {
 618         if (!amdgpu_audio)
 619                 return;
 620
 621         if (!adev->mode_info.audio.enabled)
 622                 return;
 623
 624         if (adev->dm.audio_registered) {
 625                 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
 626                 adev->dm.audio_registered = false;
 627         }
 628
 629         /* TODO: Disable audio? */
 630
 631         adev->mode_info.audio.enabled = false;
 632 }
 633
 634 void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
 635 {
 636         struct drm_audio_component *acomp = adev->dm.audio_component;
 637
 638         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
 639                 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
 640
 641                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
 642                                                  pin, -1);
 643         }
 644 }
 645
 646 static int amdgpu_dm_init(struct amdgpu_device *adev)
 647 {
 648         struct dc_init_data init_data;
 649         adev->dm.ddev = adev->ddev;
 650         adev->dm.adev = adev;
 651
 652         /* Zero all the fields */
 653         memset(&init_data, 0, sizeof(init_data));
 654
 655         mutex_init(&adev->dm.dc_lock);
 656         mutex_init(&adev->dm.audio_lock);
 657
 658         if(amdgpu_dm_irq_init(adev)) {
 659                 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
 660                 goto error;
 661         }
 662
 663         init_data.asic_id.chip_family = adev->family;
 664
 665         init_data.asic_id.pci_revision_id = adev->rev_id;
 666         init_data.asic_id.hw_internal_rev = adev->external_rev_id;
 667
 668         init_data.asic_id.vram_width = adev->gmc.vram_width;
 669         /* TODO: initialize init_data.asic_id.vram_type here!!!! */
 670         init_data.asic_id.atombios_base_address =
 671                 adev->mode_info.atom_context->bios;
 672
 673         init_data.driver = adev;
 674
 675         adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
 676
 677         if (!adev->dm.cgs_device) {
 678                 DRM_ERROR("amdgpu: failed to create cgs device.\n");
 679                 goto error;
 680         }
 681
 682         init_data.cgs_device = adev->dm.cgs_device;
 683
 684         init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
 685
 686         /*
 687          * TODO debug why this doesn't work on Raven
 688          */
 689         if (adev->flags & AMD_IS_APU &&
 690             adev->asic_type >= CHIP_CARRIZO &&
 691             adev->asic_type < CHIP_RAVEN)
 692                 init_data.flags.gpu_vm_support = true;
 693
 694         if (amdgpu_dc_feature_mask & DC_FBC_MASK)
 695                 init_data.flags.fbc_support = true;
 696
 697         init_data.flags.power_down_display_on_boot = true;
 698
 699 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
 700         init_data.soc_bounding_box = adev->dm.soc_bounding_box;
 701 #endif
 702
 703         /* Display Core create. */
 704         adev->dm.dc = dc_create(&init_data);
 705
 706         if (adev->dm.dc) {
 707                 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
 708         } else {
 709                 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
 710                 goto error;
 711         }
 712
 713         adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
 714         if (!adev->dm.freesync_module) {
 715                 DRM_ERROR(
 716                 "amdgpu: failed to initialize freesync_module.\n");
 717         } else
 718                 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
 719                                 adev->dm.freesync_module);
 720
 721         amdgpu_dm_init_color_mod();
 722
 723         if (amdgpu_dm_initialize_drm_device(adev)) {
 724                 DRM_ERROR(
 725                 "amdgpu: failed to initialize sw for display support.\n");
 726                 goto error;
 727         }
 728
 729         /* Update the actual used number of crtc */
 730         adev->mode_info.num_crtc = adev->dm.display_indexes_num;
 731
 732         /* TODO: Add_display_info? */
 733
 734         /* TODO use dynamic cursor width */
 735         adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
 736         adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
 737
 738         if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
 739                 DRM_ERROR(
 740                 "amdgpu: failed to initialize sw for display support.\n");
 741                 goto error;
 742         }
 743
 744 #if defined(CONFIG_DEBUG_FS)
 745         if (dtn_debugfs_init(adev))
 746                 DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n");
 747 #endif
 748
 749         DRM_DEBUG_DRIVER("KMS initialized.\n");
 750
 751         return 0;
 752 error:
 753         amdgpu_dm_fini(adev);
 754
 755         return -EINVAL;
 756 }
 757
 758 static void amdgpu_dm_fini(struct amdgpu_device *adev)
 759 {
 760         amdgpu_dm_audio_fini(adev);
 761
 762         amdgpu_dm_destroy_drm_device(&adev->dm);
 763
 764         /* DC Destroy TODO: Replace destroy DAL */
 765         if (adev->dm.dc)
 766                 dc_destroy(&adev->dm.dc);
 767         /*
 768          * TODO: pageflip, vlank interrupt
 769          *
 770          * amdgpu_dm_irq_fini(adev);
 771          */
 772
 773         if (adev->dm.cgs_device) {
 774                 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
 775                 adev->dm.cgs_device = NULL;
 776         }
 777         if (adev->dm.freesync_module) {
 778                 mod_freesync_destroy(adev->dm.freesync_module);
 779                 adev->dm.freesync_module = NULL;
 780         }
 781
 782         mutex_destroy(&adev->dm.audio_lock);
 783         mutex_destroy(&adev->dm.dc_lock);
 784
 785         return;
 786 }
 787
 788 static int load_dmcu_fw(struct amdgpu_device *adev)
 789 {
 790         const char *fw_name_dmcu = NULL;
 791         int r;
 792         const struct dmcu_firmware_header_v1_0 *hdr;
 793
 794         switch(adev->asic_type) {
 795         case CHIP_BONAIRE:
 796         case CHIP_HAWAII:
 797         case CHIP_KAVERI:
 798         case CHIP_KABINI:
 799         case CHIP_MULLINS:
 800         case CHIP_TONGA:
 801         case CHIP_FIJI:
 802         case CHIP_CARRIZO:
 803         case CHIP_STONEY:
 804         case CHIP_POLARIS11:
 805         case CHIP_POLARIS10:
 806         case CHIP_POLARIS12:
 807         case CHIP_VEGAM:
 808         case CHIP_VEGA10:
 809         case CHIP_VEGA12:
 810         case CHIP_VEGA20:
 811         case CHIP_NAVI10:
 812                 return 0;
 813         case CHIP_RAVEN:
 814                 if (ASICREV_IS_PICASSO(adev->external_rev_id))
 815                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
 816                 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
 817                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
 818                 else
 819                         return 0;
 820                 break;
 821         default:
 822                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
 823                 return -EINVAL;
 824         }
 825
 826         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 827                 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
 828                 return 0;
 829         }
 830
 831         r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev);
 832         if (r == -ENOENT) {
 833                 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
 834                 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
 835                 adev->dm.fw_dmcu = NULL;
 836                 return 0;
 837         }
 838         if (r) {
 839                 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",
 840                         fw_name_dmcu);
 841                 return r;
 842         }
 843
 844         r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
 845         if (r) {
 846                 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
 847                         fw_name_dmcu);
 848                 release_firmware(adev->dm.fw_dmcu);
 849                 adev->dm.fw_dmcu = NULL;
 850                 return r;
 851         }
 852
 853         hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
 854         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
 855         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
 856         adev->firmware.fw_size +=
 857                 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
 858
 859         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
 860         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
 861         adev->firmware.fw_size +=
 862                 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
 863
 864         adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
 865
 866         DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
 867
 868         return 0;
 869 }
 870
 871 static int dm_sw_init(void *handle)
 872 {
 873         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 874
 875         return load_dmcu_fw(adev);
 876 }
 877
 878 static int dm_sw_fini(void *handle)
 879 {
 880         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 881
 882         if(adev->dm.fw_dmcu) {
 883                 release_firmware(adev->dm.fw_dmcu);
 884                 adev->dm.fw_dmcu = NULL;
 885         }
 886
 887         return 0;
 888 }
 889
 890 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
 891 {
 892         struct amdgpu_dm_connector *aconnector;
 893         struct drm_connector *connector;
 894         int ret = 0;
 895
 896         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
 897
 898         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 899                 aconnector = to_amdgpu_dm_connector(connector);
 900                 if (aconnector->dc_link->type == dc_connection_mst_branch &&
 901                     aconnector->mst_mgr.aux) {
 902                         DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
 903                                         aconnector, aconnector->base.base.id);
 904
 905                         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
 906                         if (ret < 0) {
 907                                 DRM_ERROR("DM_MST: Failed to start MST\n");
 908                                 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
 909                                 return ret;
 910                                 }
 911                         }
 912         }
 913
 914         drm_modeset_unlock(&dev->mode_config.connection_mutex);
 915         return ret;
 916 }
 917
 918 static int dm_late_init(void *handle)
 919 {
 920         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 921
 922         struct dmcu_iram_parameters params;
 923         unsigned int linear_lut[16];
 924         int i;
 925         struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
 926         bool ret = false;
 927
 928         for (i = 0; i < 16; i++)
 929                 linear_lut[i] = 0xFFFF * i / 15;
 930
 931         params.set = 0;
 932         params.backlight_ramping_start = 0xCCCC;
 933         params.backlight_ramping_reduction = 0xCCCCCCCC;
 934         params.backlight_lut_array_size = 16;
 935         params.backlight_lut_array = linear_lut;
 936
 937         /* todo will enable for navi10 */
 938         if (adev->asic_type <= CHIP_RAVEN) {
 939                 ret = dmcu_load_iram(dmcu, params);
 940
 941                 if (!ret)
 942                         return -EINVAL;
 943         }
 944
 945         return detect_mst_link_for_all_connectors(adev->ddev);
 946 }
 947
 948 static void s3_handle_mst(struct drm_device *dev, bool suspend)
 949 {
 950         struct amdgpu_dm_connector *aconnector;
 951         struct drm_connector *connector;
 952         struct drm_dp_mst_topology_mgr *mgr;
 953         int ret;
 954         bool need_hotplug = false;
 955
 956         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
 957
 958         list_for_each_entry(connector, &dev->mode_config.connector_list,
 959                             head) {
 960                 aconnector = to_amdgpu_dm_connector(connector);
 961                 if (aconnector->dc_link->type != dc_connection_mst_branch ||
 962                     aconnector->mst_port)
 963                         continue;
 964
 965                 mgr = &aconnector->mst_mgr;
 966
 967                 if (suspend) {
 968                         drm_dp_mst_topology_mgr_suspend(mgr);
 969                 } else {
 970                         ret = drm_dp_mst_topology_mgr_resume(mgr);
 971                         if (ret < 0) {
 972                                 drm_dp_mst_topology_mgr_set_mst(mgr, false);
 973                                 need_hotplug = true;
 974                         }
 975                 }
 976         }
 977
 978         drm_modeset_unlock(&dev->mode_config.connection_mutex);
 979
 980         if (need_hotplug)
 981                 drm_kms_helper_hotplug_event(dev);
 982 }
 983
 984 /**
 985  * dm_hw_init() - Initialize DC device
 986  * @handle: The base driver device containing the amdpgu_dm device.
 987  *
 988  * Initialize the &struct amdgpu_display_manager device. This involves calling
 989  * the initializers of each DM component, then populating the struct with them.
 990  *
 991  * Although the function implies hardware initialization, both hardware and
 992  * software are initialized here. Splitting them out to their relevant init
 993  * hooks is a future TODO item.
 994  *
 995  * Some notable things that are initialized here:
 996  *
 997  * - Display Core, both software and hardware
 998  * - DC modules that we need (freesync and color management)
 999  * - DRM software states
1000  * - Interrupt sources and handlers
1001  * - Vblank support
1002  * - Debug FS entries, if enabled
1003  */
1004 static int dm_hw_init(void *handle)
1005 {
1006         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1007         /* Create DAL display manager */
1008         amdgpu_dm_init(adev);
1009         amdgpu_dm_hpd_init(adev);
1010
1011         return 0;
1012 }
1013
1014 /**
1015  * dm_hw_fini() - Teardown DC device
1016  * @handle: The base driver device containing the amdpgu_dm device.
1017  *
1018  * Teardown components within &struct amdgpu_display_manager that require
1019  * cleanup. This involves cleaning up the DRM device, DC, and any modules that
1020  * were loaded. Also flush IRQ workqueues and disable them.
1021  */
1022 static int dm_hw_fini(void *handle)
1023 {
1024         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1025
1026         amdgpu_dm_hpd_fini(adev);
1027
1028         amdgpu_dm_irq_fini(adev);
1029         amdgpu_dm_fini(adev);
1030         return 0;
1031 }
1032
1033 static int dm_suspend(void *handle)
1034 {
1035         struct amdgpu_device *adev = handle;
1036         struct amdgpu_display_manager *dm = &adev->dm;
1037         int ret = 0;
1038
1039         WARN_ON(adev->dm.cached_state);
1040         adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
1041
1042         s3_handle_mst(adev->ddev, true);
1043
1044         amdgpu_dm_irq_suspend(adev);
1045
1046
1047         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
1048
1049         return ret;
1050 }
1051
1052 static struct amdgpu_dm_connector *
1053 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
1054                                              struct drm_crtc *crtc)
1055 {
1056         uint32_t i;
1057         struct drm_connector_state *new_con_state;
1058         struct drm_connector *connector;
1059         struct drm_crtc *crtc_from_state;
1060
1061         for_each_new_connector_in_state(state, connector, new_con_state, i) {
1062                 crtc_from_state = new_con_state->crtc;
1063
1064                 if (crtc_from_state == crtc)
1065                         return to_amdgpu_dm_connector(connector);
1066         }
1067
1068         return NULL;
1069 }
1070
1071 static void emulated_link_detect(struct dc_link *link)
1072 {
1073         struct dc_sink_init_data sink_init_data = { 0 };
1074         struct display_sink_capability sink_caps = { 0 };
1075         enum dc_edid_status edid_status;
1076         struct dc_context *dc_ctx = link->ctx;
1077         struct dc_sink *sink = NULL;
1078         struct dc_sink *prev_sink = NULL;
1079
1080         link->type = dc_connection_none;
1081         prev_sink = link->local_sink;
1082
1083         if (prev_sink != NULL)
1084                 dc_sink_retain(prev_sink);
1085
1086         switch (link->connector_signal) {
1087         case SIGNAL_TYPE_HDMI_TYPE_A: {
1088                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1089                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
1090                 break;
1091         }
1092
1093         case SIGNAL_TYPE_DVI_SINGLE_LINK: {
1094                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1095                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1096                 break;
1097         }
1098
1099         case SIGNAL_TYPE_DVI_DUAL_LINK: {
1100                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1101                 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1102                 break;
1103         }
1104
1105         case SIGNAL_TYPE_LVDS: {
1106                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1107                 sink_caps.signal = SIGNAL_TYPE_LVDS;
1108                 break;
1109         }
1110
1111         case SIGNAL_TYPE_EDP: {
1112                 sink_caps.transaction_type =
1113                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
1114                 sink_caps.signal = SIGNAL_TYPE_EDP;
1115                 break;
1116         }
1117
1118         case SIGNAL_TYPE_DISPLAY_PORT: {
1119                 sink_caps.transaction_type =
1120                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
1121                 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
1122                 break;
1123         }
1124
1125         default:
1126                 DC_ERROR("Invalid connector type! signal:%d\n",
1127                         link->connector_signal);
1128                 return;
1129         }
1130
1131         sink_init_data.link = link;
1132         sink_init_data.sink_signal = sink_caps.signal;
1133
1134         sink = dc_sink_create(&sink_init_data);
1135         if (!sink) {
1136                 DC_ERROR("Failed to create sink!\n");
1137                 return;
1138         }
1139
1140         /* dc_sink_create returns a new reference */
1141         link->local_sink = sink;
1142
1143         edid_status = dm_helpers_read_local_edid(
1144                         link->ctx,
1145                         link,
1146                         sink);
1147
1148         if (edid_status != EDID_OK)
1149                 DC_ERROR("Failed to read EDID");
1150
1151 }
1152
1153 static int dm_resume(void *handle)
1154 {
1155         struct amdgpu_device *adev = handle;
1156         struct drm_device *ddev = adev->ddev;
1157         struct amdgpu_display_manager *dm = &adev->dm;
1158         struct amdgpu_dm_connector *aconnector;
1159         struct drm_connector *connector;
1160         struct drm_crtc *crtc;
1161         struct drm_crtc_state *new_crtc_state;
1162         struct dm_crtc_state *dm_new_crtc_state;
1163         struct drm_plane *plane;
1164         struct drm_plane_state *new_plane_state;
1165         struct dm_plane_state *dm_new_plane_state;
1166         struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
1167         enum dc_connection_type new_connection_type = dc_connection_none;
1168         int i;
1169
1170         /* Recreate dc_state - DC invalidates it when setting power state to S3. */
1171         dc_release_state(dm_state->context);
1172         dm_state->context = dc_create_state(dm->dc);
1173         /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
1174         dc_resource_state_construct(dm->dc, dm_state->context);
1175
1176         /* power on hardware */
1177         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
1178
1179         /* program HPD filter */
1180         dc_resume(dm->dc);
1181
1182         /* On resume we need to  rewrite the MSTM control bits to enamble MST*/
1183         s3_handle_mst(ddev, false);
1184
1185         /*
1186          * early enable HPD Rx IRQ, should be done before set mode as short
1187          * pulse interrupts are used for MST
1188          */
1189         amdgpu_dm_irq_resume_early(adev);
1190
1191         /* Do detection*/
1192         list_for_each_entry(connector, &ddev->mode_config.connector_list, head) {
1193                 aconnector = to_amdgpu_dm_connector(connector);
1194
1195                 /*
1196                  * this is the case when traversing through already created
1197                  * MST connectors, should be skipped
1198                  */
1199                 if (aconnector->mst_port)
1200                         continue;
1201
1202                 mutex_lock(&aconnector->hpd_lock);
1203                 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
1204                         DRM_ERROR("KMS: Failed to detect connector\n");
1205
1206                 if (aconnector->base.force && new_connection_type == dc_connection_none)
1207                         emulated_link_detect(aconnector->dc_link);
1208                 else
1209                         dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
1210
1211                 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
1212                         aconnector->fake_enable = false;
1213
1214                 if (aconnector->dc_sink)
1215                         dc_sink_release(aconnector->dc_sink);
1216                 aconnector->dc_sink = NULL;
1217                 amdgpu_dm_update_connector_after_detect(aconnector);
1218                 mutex_unlock(&aconnector->hpd_lock);
1219         }
1220
1221         /* Force mode set in atomic commit */
1222         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
1223                 new_crtc_state->active_changed = true;
1224
1225         /*
1226          * atomic_check is expected to create the dc states. We need to release
1227          * them here, since they were duplicated as part of the suspend
1228          * procedure.
1229          */
1230         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
1231                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1232                 if (dm_new_crtc_state->stream) {
1233                         WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
1234                         dc_stream_release(dm_new_crtc_state->stream);
1235                         dm_new_crtc_state->stream = NULL;
1236                 }
1237         }
1238
1239         for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
1240                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
1241                 if (dm_new_plane_state->dc_state) {
1242                         WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
1243                         dc_plane_state_release(dm_new_plane_state->dc_state);
1244                         dm_new_plane_state->dc_state = NULL;
1245                 }
1246         }
1247
1248         drm_atomic_helper_resume(ddev, dm->cached_state);
1249
1250         dm->cached_state = NULL;
1251
1252         amdgpu_dm_irq_resume_late(adev);
1253
1254         return 0;
1255 }
1256
1257 /**
1258  * DOC: DM Lifecycle
1259  *
1260  * DM (and consequently DC) is registered in the amdgpu base driver as a IP
1261  * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
1262  * the base driver's device list to be initialized and torn down accordingly.
1263  *
1264  * The functions to do so are provided as hooks in &struct amd_ip_funcs.
1265  */
1266
1267 static const struct amd_ip_funcs amdgpu_dm_funcs = {
1268         .name = "dm",
1269         .early_init = dm_early_init,
1270         .late_init = dm_late_init,
1271         .sw_init = dm_sw_init,
1272         .sw_fini = dm_sw_fini,
1273         .hw_init = dm_hw_init,
1274         .hw_fini = dm_hw_fini,
1275         .suspend = dm_suspend,
1276         .resume = dm_resume,
1277         .is_idle = dm_is_idle,
1278         .wait_for_idle = dm_wait_for_idle,
1279         .check_soft_reset = dm_check_soft_reset,
1280         .soft_reset = dm_soft_reset,
1281         .set_clockgating_state = dm_set_clockgating_state,
1282         .set_powergating_state = dm_set_powergating_state,
1283 };
1284
1285 const struct amdgpu_ip_block_version dm_ip_block =
1286 {
1287         .type = AMD_IP_BLOCK_TYPE_DCE,
1288         .major = 1,
1289         .minor = 0,
1290         .rev = 0,
1291         .funcs = &amdgpu_dm_funcs,
1292 };
1293
1294
1295 /**
1296  * DOC: atomic
1297  *
1298  * *WIP*
1299  */
1300
1301 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
1302         .fb_create = amdgpu_display_user_framebuffer_create,
1303         .output_poll_changed = drm_fb_helper_output_poll_changed,
1304         .atomic_check = amdgpu_dm_atomic_check,
1305         .atomic_commit = amdgpu_dm_atomic_commit,
1306 };
1307
1308 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
1309         .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
1310 };
1311
1312 static void
1313 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
1314 {
1315         struct drm_connector *connector = &aconnector->base;
1316         struct drm_device *dev = connector->dev;
1317         struct dc_sink *sink;
1318
1319         /* MST handled by drm_mst framework */
1320         if (aconnector->mst_mgr.mst_state == true)
1321                 return;
1322
1323
1324         sink = aconnector->dc_link->local_sink;
1325         if (sink)
1326                 dc_sink_retain(sink);
1327
1328         /*
1329          * Edid mgmt connector gets first update only in mode_valid hook and then
1330          * the connector sink is set to either fake or physical sink depends on link status.
1331          * Skip if already done during boot.
1332          */
1333         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
1334                         && aconnector->dc_em_sink) {
1335
1336                 /*
1337                  * For S3 resume with headless use eml_sink to fake stream
1338                  * because on resume connector->sink is set to NULL
1339                  */
1340                 mutex_lock(&dev->mode_config.mutex);
1341
1342                 if (sink) {
1343                         if (aconnector->dc_sink) {
1344                                 amdgpu_dm_update_freesync_caps(connector, NULL);
1345                                 /*
1346                                  * retain and release below are used to
1347                                  * bump up refcount for sink because the link doesn't point
1348                                  * to it anymore after disconnect, so on next crtc to connector
1349                                  * reshuffle by UMD we will get into unwanted dc_sink release
1350                                  */
1351                                 dc_sink_release(aconnector->dc_sink);
1352                         }
1353                         aconnector->dc_sink = sink;
1354                         dc_sink_retain(aconnector->dc_sink);
1355                         amdgpu_dm_update_freesync_caps(connector,
1356                                         aconnector->edid);
1357                 } else {
1358                         amdgpu_dm_update_freesync_caps(connector, NULL);
1359                         if (!aconnector->dc_sink) {
1360                                 aconnector->dc_sink = aconnector->dc_em_sink;
1361                                 dc_sink_retain(aconnector->dc_sink);
1362                         }
1363                 }
1364
1365                 mutex_unlock(&dev->mode_config.mutex);
1366
1367                 if (sink)
1368                         dc_sink_release(sink);
1369                 return;
1370         }
1371
1372         /*
1373          * TODO: temporary guard to look for proper fix
1374          * if this sink is MST sink, we should not do anything
1375          */
1376         if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1377                 dc_sink_release(sink);
1378                 return;
1379         }
1380
1381         if (aconnector->dc_sink == sink) {
1382                 /*
1383                  * We got a DP short pulse (Link Loss, DP CTS, etc...).
1384                  * Do nothing!!
1385                  */
1386                 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
1387                                 aconnector->connector_id);
1388                 if (sink)
1389                         dc_sink_release(sink);
1390                 return;
1391         }
1392
1393         DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
1394                 aconnector->connector_id, aconnector->dc_sink, sink);
1395
1396         mutex_lock(&dev->mode_config.mutex);
1397
1398         /*
1399          * 1. Update status of the drm connector
1400          * 2. Send an event and let userspace tell us what to do
1401          */
1402         if (sink) {
1403                 /*
1404                  * TODO: check if we still need the S3 mode update workaround.
1405                  * If yes, put it here.
1406                  */
1407                 if (aconnector->dc_sink)
1408                         amdgpu_dm_update_freesync_caps(connector, NULL);
1409
1410                 aconnector->dc_sink = sink;
1411                 dc_sink_retain(aconnector->dc_sink);
1412                 if (sink->dc_edid.length == 0) {
1413                         aconnector->edid = NULL;
1414                         drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
1415                 } else {
1416                         aconnector->edid =
1417                                 (struct edid *) sink->dc_edid.raw_edid;
1418
1419
1420                         drm_connector_update_edid_property(connector,
1421                                         aconnector->edid);
1422                         drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
1423                                             aconnector->edid);
1424                 }
1425                 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
1426
1427         } else {
1428                 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
1429                 amdgpu_dm_update_freesync_caps(connector, NULL);
1430                 drm_connector_update_edid_property(connector, NULL);
1431                 aconnector->num_modes = 0;
1432                 dc_sink_release(aconnector->dc_sink);
1433                 aconnector->dc_sink = NULL;
1434                 aconnector->edid = NULL;
1435         }
1436
1437         mutex_unlock(&dev->mode_config.mutex);
1438
1439         if (sink)
1440                 dc_sink_release(sink);
1441 }
1442
1443 static void handle_hpd_irq(void *param)
1444 {
1445         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
1446         struct drm_connector *connector = &aconnector->base;
1447         struct drm_device *dev = connector->dev;
1448         enum dc_connection_type new_connection_type = dc_connection_none;
1449
1450         /*
1451          * In case of failure or MST no need to update connector status or notify the OS
1452          * since (for MST case) MST does this in its own context.
1453          */
1454         mutex_lock(&aconnector->hpd_lock);
1455
1456         if (aconnector->fake_enable)
1457                 aconnector->fake_enable = false;
1458
1459         if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
1460                 DRM_ERROR("KMS: Failed to detect connector\n");
1461
1462         if (aconnector->base.force && new_connection_type == dc_connection_none) {
1463                 emulated_link_detect(aconnector->dc_link);
1464
1465
1466                 drm_modeset_lock_all(dev);
1467                 dm_restore_drm_connector_state(dev, connector);
1468                 drm_modeset_unlock_all(dev);
1469
1470                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1471                         drm_kms_helper_hotplug_event(dev);
1472
1473         } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
1474                 amdgpu_dm_update_connector_after_detect(aconnector);
1475
1476
1477                 drm_modeset_lock_all(dev);
1478                 dm_restore_drm_connector_state(dev, connector);
1479                 drm_modeset_unlock_all(dev);
1480
1481                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1482                         drm_kms_helper_hotplug_event(dev);
1483         }
1484         mutex_unlock(&aconnector->hpd_lock);
1485
1486 }
1487
1488 static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
1489 {
1490         uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
1491         uint8_t dret;
1492         bool new_irq_handled = false;
1493         int dpcd_addr;
1494         int dpcd_bytes_to_read;
1495
1496         const int max_process_count = 30;
1497         int process_count = 0;
1498
1499         const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
1500
1501         if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
1502                 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
1503                 /* DPCD 0x200 - 0x201 for downstream IRQ */
1504                 dpcd_addr = DP_SINK_COUNT;
1505         } else {
1506                 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
1507                 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
1508                 dpcd_addr = DP_SINK_COUNT_ESI;
1509         }
1510
1511         dret = drm_dp_dpcd_read(
1512                 &aconnector->dm_dp_aux.aux,
1513                 dpcd_addr,
1514                 esi,
1515                 dpcd_bytes_to_read);
1516
1517         while (dret == dpcd_bytes_to_read &&
1518                 process_count < max_process_count) {
1519                 uint8_t retry;
1520                 dret = 0;
1521
1522                 process_count++;
1523
1524                 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
1525                 /* handle HPD short pulse irq */
1526                 if (aconnector->mst_mgr.mst_state)
1527                         drm_dp_mst_hpd_irq(
1528                                 &aconnector->mst_mgr,
1529                                 esi,
1530                                 &new_irq_handled);
1531
1532                 if (new_irq_handled) {
1533                         /* ACK at DPCD to notify down stream */
1534                         const int ack_dpcd_bytes_to_write =
1535                                 dpcd_bytes_to_read - 1;
1536
1537                         for (retry = 0; retry < 3; retry++) {
1538                                 uint8_t wret;
1539
1540                                 wret = drm_dp_dpcd_write(
1541                                         &aconnector->dm_dp_aux.aux,
1542                                         dpcd_addr + 1,
1543                                         &esi[1],
1544                                         ack_dpcd_bytes_to_write);
1545                                 if (wret == ack_dpcd_bytes_to_write)
1546                                         break;
1547                         }
1548
1549                         /* check if there is new irq to be handled */
1550                         dret = drm_dp_dpcd_read(
1551                                 &aconnector->dm_dp_aux.aux,
1552                                 dpcd_addr,
1553                                 esi,
1554                                 dpcd_bytes_to_read);
1555
1556                         new_irq_handled = false;
1557                 } else {
1558                         break;
1559                 }
1560         }
1561
1562         if (process_count == max_process_count)
1563                 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
1564 }
1565
1566 static void handle_hpd_rx_irq(void *param)
1567 {
1568         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
1569         struct drm_connector *connector = &aconnector->base;
1570         struct drm_device *dev = connector->dev;
1571         struct dc_link *dc_link = aconnector->dc_link;
1572         bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
1573         enum dc_connection_type new_connection_type = dc_connection_none;
1574
1575         /*
1576          * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
1577          * conflict, after implement i2c helper, this mutex should be
1578          * retired.
1579          */
1580         if (dc_link->type != dc_connection_mst_branch)
1581                 mutex_lock(&aconnector->hpd_lock);
1582
1583         if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) &&
1584                         !is_mst_root_connector) {
1585                 /* Downstream Port status changed. */
1586                 if (!dc_link_detect_sink(dc_link, &new_connection_type))
1587                         DRM_ERROR("KMS: Failed to detect connector\n");
1588
1589                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1590                         emulated_link_detect(dc_link);
1591
1592                         if (aconnector->fake_enable)
1593                                 aconnector->fake_enable = false;
1594
1595                         amdgpu_dm_update_connector_after_detect(aconnector);
1596
1597
1598                         drm_modeset_lock_all(dev);
1599                         dm_restore_drm_connector_state(dev, connector);
1600                         drm_modeset_unlock_all(dev);
1601
1602                         drm_kms_helper_hotplug_event(dev);
1603                 } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
1604
1605                         if (aconnector->fake_enable)
1606                                 aconnector->fake_enable = false;
1607
1608                         amdgpu_dm_update_connector_after_detect(aconnector);
1609
1610
1611                         drm_modeset_lock_all(dev);
1612                         dm_restore_drm_connector_state(dev, connector);
1613                         drm_modeset_unlock_all(dev);
1614
1615                         drm_kms_helper_hotplug_event(dev);
1616                 }
1617         }
1618         if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
1619             (dc_link->type == dc_connection_mst_branch))
1620                 dm_handle_hpd_rx_irq(aconnector);
1621
1622         if (dc_link->type != dc_connection_mst_branch) {
1623                 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
1624                 mutex_unlock(&aconnector->hpd_lock);
1625         }
1626 }
1627
1628 static void register_hpd_handlers(struct amdgpu_device *adev)
1629 {
1630         struct drm_device *dev = adev->ddev;
1631         struct drm_connector *connector;
1632         struct amdgpu_dm_connector *aconnector;
1633         const struct dc_link *dc_link;
1634         struct dc_interrupt_params int_params = {0};
1635
1636         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1637         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1638
1639         list_for_each_entry(connector,
1640                         &dev->mode_config.connector_list, head) {
1641
1642                 aconnector = to_amdgpu_dm_connector(connector);
1643                 dc_link = aconnector->dc_link;
1644
1645                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1646                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1647                         int_params.irq_source = dc_link->irq_source_hpd;
1648
1649                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
1650                                         handle_hpd_irq,
1651                                         (void *) aconnector);
1652                 }
1653
1654                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1655
1656                         /* Also register for DP short pulse (hpd_rx). */
1657                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1658                         int_params.irq_source = dc_link->irq_source_hpd_rx;
1659
1660                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
1661                                         handle_hpd_rx_irq,
1662                                         (void *) aconnector);
1663                 }
1664         }
1665 }
1666
1667 /* Register IRQ sources and initialize IRQ callbacks */
1668 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1669 {
1670         struct dc *dc = adev->dm.dc;
1671         struct common_irq_params *c_irq_params;
1672         struct dc_interrupt_params int_params = {0};
1673         int r;
1674         int i;
1675         unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
1676
1677         if (adev->asic_type >= CHIP_VEGA10)
1678                 client_id = SOC15_IH_CLIENTID_DCE;
1679
1680         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1681         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1682
1683         /*
1684          * Actions of amdgpu_irq_add_id():
1685          * 1. Register a set() function with base driver.
1686          *    Base driver will call set() function to enable/disable an
1687          *    interrupt in DC hardware.
1688          * 2. Register amdgpu_dm_irq_handler().
1689          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1690          *    coming from DC hardware.
1691          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1692          *    for acknowledging and handling. */
1693
1694         /* Use VBLANK interrupt */
1695         for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
1696                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
1697                 if (r) {
1698                         DRM_ERROR("Failed to add crtc irq id!\n");
1699                         return r;
1700                 }
1701
1702                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1703                 int_params.irq_source =
1704                         dc_interrupt_to_irq_source(dc, i, 0);
1705
1706                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1707
1708                 c_irq_params->adev = adev;
1709                 c_irq_params->irq_src = int_params.irq_source;
1710
1711                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1712                                 dm_crtc_high_irq, c_irq_params);
1713         }
1714
1715         /* Use VUPDATE interrupt */
1716         for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
1717                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
1718                 if (r) {
1719                         DRM_ERROR("Failed to add vupdate irq id!\n");
1720                         return r;
1721                 }
1722
1723                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1724                 int_params.irq_source =
1725                         dc_interrupt_to_irq_source(dc, i, 0);
1726
1727                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
1728
1729                 c_irq_params->adev = adev;
1730                 c_irq_params->irq_src = int_params.irq_source;
1731
1732                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1733                                 dm_vupdate_high_irq, c_irq_params);
1734         }
1735
1736         /* Use GRPH_PFLIP interrupt */
1737         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1738                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
1739                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
1740                 if (r) {
1741                         DRM_ERROR("Failed to add page flip irq id!\n");
1742                         return r;
1743                 }
1744
1745                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1746                 int_params.irq_source =
1747                         dc_interrupt_to_irq_source(dc, i, 0);
1748
1749                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1750
1751                 c_irq_params->adev = adev;
1752                 c_irq_params->irq_src = int_params.irq_source;
1753
1754                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1755                                 dm_pflip_high_irq, c_irq_params);
1756
1757         }
1758
1759         /* HPD */
1760         r = amdgpu_irq_add_id(adev, client_id,
1761                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
1762         if (r) {
1763                 DRM_ERROR("Failed to add hpd irq id!\n");
1764                 return r;
1765         }
1766
1767         register_hpd_handlers(adev);
1768
1769         return 0;
1770 }
1771
1772 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1773 /* Register IRQ sources and initialize IRQ callbacks */
1774 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1775 {
1776         struct dc *dc = adev->dm.dc;
1777         struct common_irq_params *c_irq_params;
1778         struct dc_interrupt_params int_params = {0};
1779         int r;
1780         int i;
1781
1782         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1783         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1784
1785         /*
1786          * Actions of amdgpu_irq_add_id():
1787          * 1. Register a set() function with base driver.
1788          *    Base driver will call set() function to enable/disable an
1789          *    interrupt in DC hardware.
1790          * 2. Register amdgpu_dm_irq_handler().
1791          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1792          *    coming from DC hardware.
1793          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1794          *    for acknowledging and handling.
1795          */
1796
1797         /* Use VSTARTUP interrupt */
1798         for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1799                         i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1800                         i++) {
1801                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
1802
1803                 if (r) {
1804                         DRM_ERROR("Failed to add crtc irq id!\n");
1805                         return r;
1806                 }
1807
1808                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1809                 int_params.irq_source =
1810                         dc_interrupt_to_irq_source(dc, i, 0);
1811
1812                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1813
1814                 c_irq_params->adev = adev;
1815                 c_irq_params->irq_src = int_params.irq_source;
1816
1817                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1818                                 dm_crtc_high_irq, c_irq_params);
1819         }
1820
1821         /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
1822          * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
1823          * to trigger at end of each vblank, regardless of state of the lock,
1824          * matching DCE behaviour.
1825          */
1826         for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
1827              i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
1828              i++) {
1829                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
1830
1831                 if (r) {
1832                         DRM_ERROR("Failed to add vupdate irq id!\n");
1833                         return r;
1834                 }
1835
1836                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1837                 int_params.irq_source =
1838                         dc_interrupt_to_irq_source(dc, i, 0);
1839
1840                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
1841
1842                 c_irq_params->adev = adev;
1843                 c_irq_params->irq_src = int_params.irq_source;
1844
1845                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1846                                 dm_vupdate_high_irq, c_irq_params);
1847         }
1848
1849         /* Use GRPH_PFLIP interrupt */
1850         for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1851                         i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1852                         i++) {
1853                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
1854                 if (r) {
1855                         DRM_ERROR("Failed to add page flip irq id!\n");
1856                         return r;
1857                 }
1858
1859                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1860                 int_params.irq_source =
1861                         dc_interrupt_to_irq_source(dc, i, 0);
1862
1863                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1864
1865                 c_irq_params->adev = adev;
1866                 c_irq_params->irq_src = int_params.irq_source;
1867
1868                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1869                                 dm_pflip_high_irq, c_irq_params);
1870
1871         }
1872
1873         /* HPD */
1874         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
1875                         &adev->hpd_irq);
1876         if (r) {
1877                 DRM_ERROR("Failed to add hpd irq id!\n");
1878                 return r;
1879         }
1880
1881         register_hpd_handlers(adev);
1882
1883         return 0;
1884 }
1885 #endif
1886
1887 /*
1888  * Acquires the lock for the atomic state object and returns
1889  * the new atomic state.
1890  *
1891  * This should only be called during atomic check.
1892  */
1893 static int dm_atomic_get_state(struct drm_atomic_state *state,
1894                                struct dm_atomic_state **dm_state)
1895 {
1896         struct drm_device *dev = state->dev;
1897         struct amdgpu_device *adev = dev->dev_private;
1898         struct amdgpu_display_manager *dm = &adev->dm;
1899         struct drm_private_state *priv_state;
1900
1901         if (*dm_state)
1902                 return 0;
1903
1904         priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
1905         if (IS_ERR(priv_state))
1906                 return PTR_ERR(priv_state);
1907
1908         *dm_state = to_dm_atomic_state(priv_state);
1909
1910         return 0;
1911 }
1912
1913 struct dm_atomic_state *
1914 dm_atomic_get_new_state(struct drm_atomic_state *state)
1915 {
1916         struct drm_device *dev = state->dev;
1917         struct amdgpu_device *adev = dev->dev_private;
1918         struct amdgpu_display_manager *dm = &adev->dm;
1919         struct drm_private_obj *obj;
1920         struct drm_private_state *new_obj_state;
1921         int i;
1922
1923         for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
1924                 if (obj->funcs == dm->atomic_obj.funcs)
1925                         return to_dm_atomic_state(new_obj_state);
1926         }
1927
1928         return NULL;
1929 }
1930
1931 struct dm_atomic_state *
1932 dm_atomic_get_old_state(struct drm_atomic_state *state)
1933 {
1934         struct drm_device *dev = state->dev;
1935         struct amdgpu_device *adev = dev->dev_private;
1936         struct amdgpu_display_manager *dm = &adev->dm;
1937         struct drm_private_obj *obj;
1938         struct drm_private_state *old_obj_state;
1939         int i;
1940
1941         for_each_old_private_obj_in_state(state, obj, old_obj_state, i) {
1942                 if (obj->funcs == dm->atomic_obj.funcs)
1943                         return to_dm_atomic_state(old_obj_state);
1944         }
1945
1946         return NULL;
1947 }
1948
1949 static struct drm_private_state *
1950 dm_atomic_duplicate_state(struct drm_private_obj *obj)
1951 {
1952         struct dm_atomic_state *old_state, *new_state;
1953
1954         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
1955         if (!new_state)
1956                 return NULL;
1957
1958         __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
1959
1960         old_state = to_dm_atomic_state(obj->state);
1961
1962         if (old_state && old_state->context)
1963                 new_state->context = dc_copy_state(old_state->context);
1964
1965         if (!new_state->context) {
1966                 kfree(new_state);
1967                 return NULL;
1968         }
1969
1970         return &new_state->base;
1971 }
1972
1973 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
1974                                     struct drm_private_state *state)
1975 {
1976         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
1977
1978         if (dm_state && dm_state->context)
1979                 dc_release_state(dm_state->context);
1980
1981         kfree(dm_state);
1982 }
1983
1984 static struct drm_private_state_funcs dm_atomic_state_funcs = {
1985         .atomic_duplicate_state = dm_atomic_duplicate_state,
1986         .atomic_destroy_state = dm_atomic_destroy_state,
1987 };
1988
1989 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1990 {
1991         struct dm_atomic_state *state;
1992         int r;
1993
1994         adev->mode_info.mode_config_initialized = true;
1995
1996         adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
1997         adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
1998
1999         adev->ddev->mode_config.max_width = 16384;
2000         adev->ddev->mode_config.max_height = 16384;
2001
2002         adev->ddev->mode_config.preferred_depth = 24;
2003         adev->ddev->mode_config.prefer_shadow = 1;
2004         /* indicates support for immediate flip */
2005         adev->ddev->mode_config.async_page_flip = true;
2006
2007         adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
2008
2009         state = kzalloc(sizeof(*state), GFP_KERNEL);
2010         if (!state)
2011                 return -ENOMEM;
2012
2013         state->context = dc_create_state(adev->dm.dc);
2014         if (!state->context) {
2015                 kfree(state);
2016                 return -ENOMEM;
2017         }
2018
2019         dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
2020
2021         drm_atomic_private_obj_init(adev->ddev,
2022                                     &adev->dm.atomic_obj,
2023                                     &state->base,
2024                                     &dm_atomic_state_funcs);
2025
2026         r = amdgpu_display_modeset_create_props(adev);
2027         if (r)
2028                 return r;
2029
2030         r = amdgpu_dm_audio_init(adev);
2031         if (r)
2032                 return r;
2033
2034         return 0;
2035 }
2036
2037 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
2038 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
2039
2040 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2041         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2042
2043 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm)
2044 {
2045 #if defined(CONFIG_ACPI)
2046         struct amdgpu_dm_backlight_caps caps;
2047
2048         if (dm->backlight_caps.caps_valid)
2049                 return;
2050
2051         amdgpu_acpi_get_backlight_caps(dm->adev, &caps);
2052         if (caps.caps_valid) {
2053                 dm->backlight_caps.min_input_signal = caps.min_input_signal;
2054                 dm->backlight_caps.max_input_signal = caps.max_input_signal;
2055                 dm->backlight_caps.caps_valid = true;
2056         } else {
2057                 dm->backlight_caps.min_input_signal =
2058                                 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
2059                 dm->backlight_caps.max_input_signal =
2060                                 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
2061         }
2062 #else
2063         dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
2064         dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
2065 #endif
2066 }
2067
2068 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
2069 {
2070         struct amdgpu_display_manager *dm = bl_get_data(bd);
2071         struct amdgpu_dm_backlight_caps caps;
2072         uint32_t brightness = bd->props.brightness;
2073
2074         amdgpu_dm_update_backlight_caps(dm);
2075         caps = dm->backlight_caps;
2076         /*
2077          * The brightness input is in the range 0-255
2078          * It needs to be rescaled to be between the
2079          * requested min and max input signal
2080          *
2081          * It also needs to be scaled up by 0x101 to
2082          * match the DC interface which has a range of
2083          * 0 to 0xffff
2084          */
2085         brightness =
2086                 brightness
2087                 * 0x101
2088                 * (caps.max_input_signal - caps.min_input_signal)
2089                 / AMDGPU_MAX_BL_LEVEL
2090                 + caps.min_input_signal * 0x101;
2091
2092         if (dc_link_set_backlight_level(dm->backlight_link,
2093                         brightness, 0))
2094                 return 0;
2095         else
2096                 return 1;
2097 }
2098
2099 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
2100 {
2101         struct amdgpu_display_manager *dm = bl_get_data(bd);
2102         int ret = dc_link_get_backlight_level(dm->backlight_link);
2103
2104         if (ret == DC_ERROR_UNEXPECTED)
2105                 return bd->props.brightness;
2106         return ret;
2107 }
2108
2109 static const struct backlight_ops amdgpu_dm_backlight_ops = {
2110         .get_brightness = amdgpu_dm_backlight_get_brightness,
2111         .update_status  = amdgpu_dm_backlight_update_status,
2112 };
2113
2114 static void
2115 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
2116 {
2117         char bl_name[16];
2118         struct backlight_properties props = { 0 };
2119
2120         amdgpu_dm_update_backlight_caps(dm);
2121
2122         props.max_brightness = AMDGPU_MAX_BL_LEVEL;
2123         props.brightness = AMDGPU_MAX_BL_LEVEL;
2124         props.type = BACKLIGHT_RAW;
2125
2126         snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
2127                         dm->adev->ddev->primary->index);
2128
2129         dm->backlight_dev = backlight_device_register(bl_name,
2130                         dm->adev->ddev->dev,
2131                         dm,
2132                         &amdgpu_dm_backlight_ops,
2133                         &props);
2134
2135         if (IS_ERR(dm->backlight_dev))
2136                 DRM_ERROR("DM: Backlight registration failed!\n");
2137         else
2138                 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
2139 }
2140
2141 #endif
2142
2143 static int initialize_plane(struct amdgpu_display_manager *dm,
2144                             struct amdgpu_mode_info *mode_info, int plane_id,
2145                             enum drm_plane_type plane_type,
2146                             const struct dc_plane_cap *plane_cap)
2147 {
2148         struct drm_plane *plane;
2149         unsigned long possible_crtcs;
2150         int ret = 0;
2151
2152         plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
2153         if (!plane) {
2154                 DRM_ERROR("KMS: Failed to allocate plane\n");
2155                 return -ENOMEM;
2156         }
2157         plane->type = plane_type;
2158
2159         /*
2160          * HACK: IGT tests expect that the primary plane for a CRTC
2161          * can only have one possible CRTC. Only expose support for
2162          * any CRTC if they're not going to be used as a primary plane
2163          * for a CRTC - like overlay or underlay planes.
2164          */
2165         possible_crtcs = 1 << plane_id;
2166         if (plane_id >= dm->dc->caps.max_streams)
2167                 possible_crtcs = 0xff;
2168
2169         ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
2170
2171         if (ret) {
2172                 DRM_ERROR("KMS: Failed to initialize plane\n");
2173                 kfree(plane);
2174                 return ret;
2175         }
2176
2177         if (mode_info)
2178                 mode_info->planes[plane_id] = plane;
2179
2180         return ret;
2181 }
2182
2183
2184 static void register_backlight_device(struct amdgpu_display_manager *dm,
2185                                       struct dc_link *link)
2186 {
2187 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2188         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2189
2190         if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
2191             link->type != dc_connection_none) {
2192                 /*
2193                  * Event if registration failed, we should continue with
2194                  * DM initialization because not having a backlight control
2195                  * is better then a black screen.
2196                  */
2197                 amdgpu_dm_register_backlight_device(dm);
2198
2199                 if (dm->backlight_dev)
2200                         dm->backlight_link = link;
2201         }
2202 #endif
2203 }
2204
2205
2206 /*
2207  * In this architecture, the association
2208  * connector -> encoder -> crtc
2209  * id not really requried. The crtc and connector will hold the
2210  * display_index as an abstraction to use with DAL component
2211  *
2212  * Returns 0 on success
2213  */
2214 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
2215 {
2216         struct amdgpu_display_manager *dm = &adev->dm;
2217         int32_t i;
2218         struct amdgpu_dm_connector *aconnector = NULL;
2219         struct amdgpu_encoder *aencoder = NULL;
2220         struct amdgpu_mode_info *mode_info = &adev->mode_info;
2221         uint32_t link_cnt;
2222         int32_t primary_planes;
2223         enum dc_connection_type new_connection_type = dc_connection_none;
2224         const struct dc_plane_cap *plane;
2225
2226         link_cnt = dm->dc->caps.max_links;
2227         if (amdgpu_dm_mode_config_init(dm->adev)) {
2228                 DRM_ERROR("DM: Failed to initialize mode config\n");
2229                 return -EINVAL;
2230         }
2231
2232         /* There is one primary plane per CRTC */
2233         primary_planes = dm->dc->caps.max_streams;
2234         ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
2235
2236         /*
2237          * Initialize primary planes, implicit planes for legacy IOCTLS.
2238          * Order is reversed to match iteration order in atomic check.
2239          */
2240         for (i = (primary_planes - 1); i >= 0; i--) {
2241                 plane = &dm->dc->caps.planes[i];
2242
2243                 if (initialize_plane(dm, mode_info, i,
2244                                      DRM_PLANE_TYPE_PRIMARY, plane)) {
2245                         DRM_ERROR("KMS: Failed to initialize primary plane\n");
2246                         goto fail;
2247                 }
2248         }
2249
2250         /*
2251          * Initialize overlay planes, index starting after primary planes.
2252          * These planes have a higher DRM index than the primary planes since
2253          * they should be considered as having a higher z-order.
2254          * Order is reversed to match iteration order in atomic check.
2255          *
2256          * Only support DCN for now, and only expose one so we don't encourage
2257          * userspace to use up all the pipes.
2258          */
2259         for (i = 0; i < dm->dc->caps.max_planes; ++i) {
2260                 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
2261
2262                 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
2263                         continue;
2264
2265                 if (!plane->blends_with_above || !plane->blends_with_below)
2266                         continue;
2267
2268                 if (!plane->pixel_format_support.argb8888)
2269                         continue;
2270
2271                 if (initialize_plane(dm, NULL, primary_planes + i,
2272                                      DRM_PLANE_TYPE_OVERLAY, plane)) {
2273                         DRM_ERROR("KMS: Failed to initialize overlay plane\n");
2274                         goto fail;
2275                 }
2276
2277                 /* Only create one overlay plane. */
2278                 break;
2279         }
2280
2281         for (i = 0; i < dm->dc->caps.max_streams; i++)
2282                 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
2283                         DRM_ERROR("KMS: Failed to initialize crtc\n");
2284                         goto fail;
2285                 }
2286
2287         dm->display_indexes_num = dm->dc->caps.max_streams;
2288
2289         /* loops over all connectors on the board */
2290         for (i = 0; i < link_cnt; i++) {
2291                 struct dc_link *link = NULL;
2292
2293                 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
2294                         DRM_ERROR(
2295                                 "KMS: Cannot support more than %d display indexes\n",
2296                                         AMDGPU_DM_MAX_DISPLAY_INDEX);
2297                         continue;
2298                 }
2299
2300                 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
2301                 if (!aconnector)
2302                         goto fail;
2303
2304                 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
2305                 if (!aencoder)
2306                         goto fail;
2307
2308                 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
2309                         DRM_ERROR("KMS: Failed to initialize encoder\n");
2310                         goto fail;
2311                 }
2312
2313                 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
2314                         DRM_ERROR("KMS: Failed to initialize connector\n");
2315                         goto fail;
2316                 }
2317
2318                 link = dc_get_link_at_index(dm->dc, i);
2319
2320                 if (!dc_link_detect_sink(link, &new_connection_type))
2321                         DRM_ERROR("KMS: Failed to detect connector\n");
2322
2323                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2324                         emulated_link_detect(link);
2325                         amdgpu_dm_update_connector_after_detect(aconnector);
2326
2327                 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) {
2328                         amdgpu_dm_update_connector_after_detect(aconnector);
2329                         register_backlight_device(dm, link);
2330                 }
2331
2332
2333         }
2334
2335         /* Software is initialized. Now we can register interrupt handlers. */
2336         switch (adev->asic_type) {
2337         case CHIP_BONAIRE:
2338         case CHIP_HAWAII:
2339         case CHIP_KAVERI:
2340         case CHIP_KABINI:
2341         case CHIP_MULLINS:
2342         case CHIP_TONGA:
2343         case CHIP_FIJI:
2344         case CHIP_CARRIZO:
2345         case CHIP_STONEY:
2346         case CHIP_POLARIS11:
2347         case CHIP_POLARIS10:
2348         case CHIP_POLARIS12:
2349         case CHIP_VEGAM:
2350         case CHIP_VEGA10:
2351         case CHIP_VEGA12:
2352         case CHIP_VEGA20:
2353                 if (dce110_register_irq_handlers(dm->adev)) {
2354                         DRM_ERROR("DM: Failed to initialize IRQ\n");
2355                         goto fail;
2356                 }
2357                 break;
2358 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2359         case CHIP_RAVEN:
2360 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
2361         case CHIP_NAVI10:
2362 #endif
2363                 if (dcn10_register_irq_handlers(dm->adev)) {
2364                         DRM_ERROR("DM: Failed to initialize IRQ\n");
2365                         goto fail;
2366                 }
2367                 break;
2368 #endif
2369         default:
2370                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2371                 goto fail;
2372         }
2373
2374         if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
2375                 dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
2376
2377         return 0;
2378 fail:
2379         kfree(aencoder);
2380         kfree(aconnector);
2381
2382         return -EINVAL;
2383 }
2384
2385 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
2386 {
2387         drm_mode_config_cleanup(dm->ddev);
2388         drm_atomic_private_obj_fini(&dm->atomic_obj);
2389         return;
2390 }
2391
2392 /******************************************************************************
2393  * amdgpu_display_funcs functions
2394  *****************************************************************************/
2395
2396 /*
2397  * dm_bandwidth_update - program display watermarks
2398  *
2399  * @adev: amdgpu_device pointer
2400  *
2401  * Calculate and program the display watermarks and line buffer allocation.
2402  */
2403 static void dm_bandwidth_update(struct amdgpu_device *adev)
2404 {
2405         /* TODO: implement later */
2406 }
2407
2408 static const struct amdgpu_display_funcs dm_display_funcs = {
2409         .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
2410         .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
2411         .backlight_set_level = NULL, /* never called for DC */
2412         .backlight_get_level = NULL, /* never called for DC */
2413         .hpd_sense = NULL,/* called unconditionally */
2414         .hpd_set_polarity = NULL, /* called unconditionally */
2415         .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
2416         .page_flip_get_scanoutpos =
2417                 dm_crtc_get_scanoutpos,/* called unconditionally */
2418         .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
2419         .add_connector = NULL, /* VBIOS parsing. DAL does it. */
2420 };
2421
2422 #if defined(CONFIG_DEBUG_KERNEL_DC)
2423
2424 static ssize_t s3_debug_store(struct device *device,
2425                               struct device_attribute *attr,
2426                               const char *buf,
2427                               size_t count)
2428 {
2429         int ret;
2430         int s3_state;
2431         struct pci_dev *pdev = to_pci_dev(device);
2432         struct drm_device *drm_dev = pci_get_drvdata(pdev);
2433         struct amdgpu_device *adev = drm_dev->dev_private;
2434
2435         ret = kstrtoint(buf, 0, &s3_state);
2436
2437         if (ret == 0) {
2438                 if (s3_state) {
2439                         dm_resume(adev);
2440                         drm_kms_helper_hotplug_event(adev->ddev);
2441                 } else
2442                         dm_suspend(adev);
2443         }
2444
2445         return ret == 0 ? count : 0;
2446 }
2447
2448 DEVICE_ATTR_WO(s3_debug);
2449
2450 #endif
2451
2452 static int dm_early_init(void *handle)
2453 {
2454         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2455
2456         switch (adev->asic_type) {
2457         case CHIP_BONAIRE:
2458         case CHIP_HAWAII:
2459                 adev->mode_info.num_crtc = 6;
2460                 adev->mode_info.num_hpd = 6;
2461                 adev->mode_info.num_dig = 6;
2462                 break;
2463         case CHIP_KAVERI:
2464                 adev->mode_info.num_crtc = 4;
2465                 adev->mode_info.num_hpd = 6;
2466                 adev->mode_info.num_dig = 7;
2467                 break;
2468         case CHIP_KABINI:
2469         case CHIP_MULLINS:
2470                 adev->mode_info.num_crtc = 2;
2471                 adev->mode_info.num_hpd = 6;
2472                 adev->mode_info.num_dig = 6;
2473                 break;
2474         case CHIP_FIJI:
2475         case CHIP_TONGA:
2476                 adev->mode_info.num_crtc = 6;
2477                 adev->mode_info.num_hpd = 6;
2478                 adev->mode_info.num_dig = 7;
2479                 break;
2480         case CHIP_CARRIZO:
2481                 adev->mode_info.num_crtc = 3;
2482                 adev->mode_info.num_hpd = 6;
2483                 adev->mode_info.num_dig = 9;
2484                 break;
2485         case CHIP_STONEY:
2486                 adev->mode_info.num_crtc = 2;
2487                 adev->mode_info.num_hpd = 6;
2488                 adev->mode_info.num_dig = 9;
2489                 break;
2490         case CHIP_POLARIS11:
2491         case CHIP_POLARIS12:
2492                 adev->mode_info.num_crtc = 5;
2493                 adev->mode_info.num_hpd = 5;
2494                 adev->mode_info.num_dig = 5;
2495                 break;
2496         case CHIP_POLARIS10:
2497         case CHIP_VEGAM:
2498                 adev->mode_info.num_crtc = 6;
2499                 adev->mode_info.num_hpd = 6;
2500                 adev->mode_info.num_dig = 6;
2501                 break;
2502         case CHIP_VEGA10:
2503         case CHIP_VEGA12:
2504         case CHIP_VEGA20:
2505                 adev->mode_info.num_crtc = 6;
2506                 adev->mode_info.num_hpd = 6;
2507                 adev->mode_info.num_dig = 6;
2508                 break;
2509 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2510         case CHIP_RAVEN:
2511                 adev->mode_info.num_crtc = 4;
2512                 adev->mode_info.num_hpd = 4;
2513                 adev->mode_info.num_dig = 4;
2514                 break;
2515 #endif
2516 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
2517         case CHIP_NAVI10:
2518                 adev->mode_info.num_crtc = 6;
2519                 adev->mode_info.num_hpd = 6;
2520                 adev->mode_info.num_dig = 6;
2521                 break;
2522 #endif
2523         default:
2524                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2525                 return -EINVAL;
2526         }
2527
2528         amdgpu_dm_set_irq_funcs(adev);
2529
2530         if (adev->mode_info.funcs == NULL)
2531                 adev->mode_info.funcs = &dm_display_funcs;
2532
2533         /*
2534          * Note: Do NOT change adev->audio_endpt_rreg and
2535          * adev->audio_endpt_wreg because they are initialised in
2536          * amdgpu_device_init()
2537          */
2538 #if defined(CONFIG_DEBUG_KERNEL_DC)
2539         device_create_file(
2540                 adev->ddev->dev,
2541                 &dev_attr_s3_debug);
2542 #endif
2543
2544         return 0;
2545 }
2546
2547 static bool modeset_required(struct drm_crtc_state *crtc_state,
2548                              struct dc_stream_state *new_stream,
2549                              struct dc_stream_state *old_stream)
2550 {
2551         if (!drm_atomic_crtc_needs_modeset(crtc_state))
2552                 return false;
2553
2554         if (!crtc_state->enable)
2555                 return false;
2556
2557         return crtc_state->active;
2558 }
2559
2560 static bool modereset_required(struct drm_crtc_state *crtc_state)
2561 {
2562         if (!drm_atomic_crtc_needs_modeset(crtc_state))
2563                 return false;
2564
2565         return !crtc_state->enable || !crtc_state->active;
2566 }
2567
2568 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
2569 {
2570         drm_encoder_cleanup(encoder);
2571         kfree(encoder);
2572 }
2573
2574 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
2575         .destroy = amdgpu_dm_encoder_destroy,
2576 };
2577
2578
2579 static int fill_dc_scaling_info(const struct drm_plane_state *state,
2580                                 struct dc_scaling_info *scaling_info)
2581 {
2582         int scale_w, scale_h;
2583
2584         memset(scaling_info, 0, sizeof(*scaling_info));
2585
2586         /* Source is fixed 16.16 but we ignore mantissa for now... */
2587         scaling_info->src_rect.x = state->src_x >> 16;
2588         scaling_info->src_rect.y = state->src_y >> 16;
2589
2590         scaling_info->src_rect.width = state->src_w >> 16;
2591         if (scaling_info->src_rect.width == 0)
2592                 return -EINVAL;
2593
2594         scaling_info->src_rect.height = state->src_h >> 16;
2595         if (scaling_info->src_rect.height == 0)
2596                 return -EINVAL;
2597
2598         scaling_info->dst_rect.x = state->crtc_x;
2599         scaling_info->dst_rect.y = state->crtc_y;
2600
2601         if (state->crtc_w == 0)
2602                 return -EINVAL;
2603
2604         scaling_info->dst_rect.width = state->crtc_w;
2605
2606         if (state->crtc_h == 0)
2607                 return -EINVAL;
2608
2609         scaling_info->dst_rect.height = state->crtc_h;
2610
2611         /* DRM doesn't specify clipping on destination output. */
2612         scaling_info->clip_rect = scaling_info->dst_rect;
2613
2614         /* TODO: Validate scaling per-format with DC plane caps */
2615         scale_w = scaling_info->dst_rect.width * 1000 /
2616                   scaling_info->src_rect.width;
2617
2618         if (scale_w < 250 || scale_w > 16000)
2619                 return -EINVAL;
2620
2621         scale_h = scaling_info->dst_rect.height * 1000 /
2622                   scaling_info->src_rect.height;
2623
2624         if (scale_h < 250 || scale_h > 16000)
2625                 return -EINVAL;
2626
2627         /*
2628          * The "scaling_quality" can be ignored for now, quality = 0 has DC
2629          * assume reasonable defaults based on the format.
2630          */
2631
2632         return 0;
2633 }
2634
2635 static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
2636                        uint64_t *tiling_flags)
2637 {
2638         struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
2639         int r = amdgpu_bo_reserve(rbo, false);
2640
2641         if (unlikely(r)) {
2642                 /* Don't show error message when returning -ERESTARTSYS */
2643                 if (r != -ERESTARTSYS)
2644                         DRM_ERROR("Unable to reserve buffer: %d\n", r);
2645                 return r;
2646         }
2647
2648         if (tiling_flags)
2649                 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
2650
2651         amdgpu_bo_unreserve(rbo);
2652
2653         return r;
2654 }
2655
2656 static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags)
2657 {
2658         uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B);
2659
2660         return offset ? (address + offset * 256) : 0;
2661 }
2662
2663 static int
2664 fill_plane_dcc_attributes(struct amdgpu_device *adev,
2665                           const struct amdgpu_framebuffer *afb,
2666                           const enum surface_pixel_format format,
2667                           const enum dc_rotation_angle rotation,
2668                           const union plane_size *plane_size,
2669                           const union dc_tiling_info *tiling_info,
2670                           const uint64_t info,
2671                           struct dc_plane_dcc_param *dcc,
2672                           struct dc_plane_address *address)
2673 {
2674         struct dc *dc = adev->dm.dc;
2675         struct dc_dcc_surface_param input;
2676         struct dc_surface_dcc_cap output;
2677         uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B);
2678         uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0;
2679         uint64_t dcc_address;
2680
2681         memset(&input, 0, sizeof(input));
2682         memset(&output, 0, sizeof(output));
2683
2684         if (!offset)
2685                 return 0;
2686
2687         if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
2688                 return 0;
2689
2690         if (!dc->cap_funcs.get_dcc_compression_cap)
2691                 return -EINVAL;
2692
2693         input.format = format;
2694         input.surface_size.width = plane_size->grph.surface_size.width;
2695         input.surface_size.height = plane_size->grph.surface_size.height;
2696         input.swizzle_mode = tiling_info->gfx9.swizzle;
2697
2698         if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180)
2699                 input.scan = SCAN_DIRECTION_HORIZONTAL;
2700         else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270)
2701                 input.scan = SCAN_DIRECTION_VERTICAL;
2702
2703         if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output))
2704                 return -EINVAL;
2705
2706         if (!output.capable)
2707                 return -EINVAL;
2708
2709         if (i64b == 0 && output.grph.rgb.independent_64b_blks != 0)
2710                 return -EINVAL;
2711
2712         dcc->enable = 1;
2713         dcc->grph.meta_pitch =
2714                 AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1;
2715         dcc->grph.independent_64b_blks = i64b;
2716
2717         dcc_address = get_dcc_address(afb->address, info);
2718         address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
2719         address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
2720
2721         return 0;
2722 }
2723
2724 static int
2725 fill_plane_buffer_attributes(struct amdgpu_device *adev,
2726                              const struct amdgpu_framebuffer *afb,
2727                              const enum surface_pixel_format format,
2728                              const enum dc_rotation_angle rotation,
2729                              const uint64_t tiling_flags,
2730                              union dc_tiling_info *tiling_info,
2731                              union plane_size *plane_size,
2732                              struct dc_plane_dcc_param *dcc,
2733                              struct dc_plane_address *address)
2734 {
2735         const struct drm_framebuffer *fb = &afb->base;
2736         int ret;
2737
2738         memset(tiling_info, 0, sizeof(*tiling_info));
2739         memset(plane_size, 0, sizeof(*plane_size));
2740         memset(dcc, 0, sizeof(*dcc));
2741         memset(address, 0, sizeof(*address));
2742
2743         if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
2744                 plane_size->grph.surface_size.x = 0;
2745                 plane_size->grph.surface_size.y = 0;
2746                 plane_size->grph.surface_size.width = fb->width;
2747                 plane_size->grph.surface_size.height = fb->height;
2748                 plane_size->grph.surface_pitch =
2749                         fb->pitches[0] / fb->format->cpp[0];
2750
2751                 address->type = PLN_ADDR_TYPE_GRAPHICS;
2752                 address->grph.addr.low_part = lower_32_bits(afb->address);
2753                 address->grph.addr.high_part = upper_32_bits(afb->address);
2754         } else if (format < SURFACE_PIXEL_FORMAT_INVALID) {
2755                 uint64_t chroma_addr = afb->address + fb->offsets[1];
2756
2757                 plane_size->video.luma_size.x = 0;
2758                 plane_size->video.luma_size.y = 0;
2759                 plane_size->video.luma_size.width = fb->width;
2760                 plane_size->video.luma_size.height = fb->height;
2761                 plane_size->video.luma_pitch =
2762                         fb->pitches[0] / fb->format->cpp[0];
2763
2764                 plane_size->video.chroma_size.x = 0;
2765                 plane_size->video.chroma_size.y = 0;
2766                 /* TODO: set these based on surface format */
2767                 plane_size->video.chroma_size.width = fb->width / 2;
2768                 plane_size->video.chroma_size.height = fb->height / 2;
2769
2770                 plane_size->video.chroma_pitch =
2771                         fb->pitches[1] / fb->format->cpp[1];
2772
2773                 address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
2774                 address->video_progressive.luma_addr.low_part =
2775                         lower_32_bits(afb->address);
2776                 address->video_progressive.luma_addr.high_part =
2777                         upper_32_bits(afb->address);
2778                 address->video_progressive.chroma_addr.low_part =
2779                         lower_32_bits(chroma_addr);
2780                 address->video_progressive.chroma_addr.high_part =
2781                         upper_32_bits(chroma_addr);
2782         }
2783
2784         /* Fill GFX8 params */
2785         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
2786                 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
2787
2788                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2789                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2790                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2791                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2792                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2793
2794                 /* XXX fix me for VI */
2795                 tiling_info->gfx8.num_banks = num_banks;
2796                 tiling_info->gfx8.array_mode =
2797                                 DC_ARRAY_2D_TILED_THIN1;
2798                 tiling_info->gfx8.tile_split = tile_split;
2799                 tiling_info->gfx8.bank_width = bankw;
2800                 tiling_info->gfx8.bank_height = bankh;
2801                 tiling_info->gfx8.tile_aspect = mtaspect;
2802                 tiling_info->gfx8.tile_mode =
2803                                 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
2804         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
2805                         == DC_ARRAY_1D_TILED_THIN1) {
2806                 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
2807         }
2808
2809         tiling_info->gfx8.pipe_config =
2810                         AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2811
2812         if (adev->asic_type == CHIP_VEGA10 ||
2813             adev->asic_type == CHIP_VEGA12 ||
2814             adev->asic_type == CHIP_VEGA20 ||
2815 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
2816             adev->asic_type == CHIP_NAVI10 ||
2817 #endif
2818             adev->asic_type == CHIP_RAVEN) {
2819                 /* Fill GFX9 params */
2820                 tiling_info->gfx9.num_pipes =
2821                         adev->gfx.config.gb_addr_config_fields.num_pipes;
2822                 tiling_info->gfx9.num_banks =
2823                         adev->gfx.config.gb_addr_config_fields.num_banks;
2824                 tiling_info->gfx9.pipe_interleave =
2825                         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
2826                 tiling_info->gfx9.num_shader_engines =
2827                         adev->gfx.config.gb_addr_config_fields.num_se;
2828                 tiling_info->gfx9.max_compressed_frags =
2829                         adev->gfx.config.gb_addr_config_fields.max_compress_frags;
2830                 tiling_info->gfx9.num_rb_per_se =
2831                         adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
2832                 tiling_info->gfx9.swizzle =
2833                         AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
2834                 tiling_info->gfx9.shaderEnable = 1;
2835
2836                 ret = fill_plane_dcc_attributes(adev, afb, format, rotation,
2837                                                 plane_size, tiling_info,
2838                                                 tiling_flags, dcc, address);
2839                 if (ret)
2840                         return ret;
2841         }
2842
2843         return 0;
2844 }
2845
2846 static void
2847 fill_blending_from_plane_state(const struct drm_plane_state *plane_state,
2848                                bool *per_pixel_alpha, bool *global_alpha,
2849                                int *global_alpha_value)
2850 {
2851         *per_pixel_alpha = false;
2852         *global_alpha = false;
2853         *global_alpha_value = 0xff;
2854
2855         if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY)
2856                 return;
2857
2858         if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
2859                 static const uint32_t alpha_formats[] = {
2860                         DRM_FORMAT_ARGB8888,
2861                         DRM_FORMAT_RGBA8888,
2862                         DRM_FORMAT_ABGR8888,
2863                 };
2864                 uint32_t format = plane_state->fb->format->format;
2865                 unsigned int i;
2866
2867                 for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) {
2868                         if (format == alpha_formats[i]) {
2869                                 *per_pixel_alpha = true;
2870                                 break;
2871                         }
2872                 }
2873         }
2874
2875         if (plane_state->alpha < 0xffff) {
2876                 *global_alpha = true;
2877                 *global_alpha_value = plane_state->alpha >> 8;
2878         }
2879 }
2880
2881 static int
2882 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
2883                             const enum surface_pixel_format format,
2884                             enum dc_color_space *color_space)
2885 {
2886         bool full_range;
2887
2888         *color_space = COLOR_SPACE_SRGB;
2889
2890         /* DRM color properties only affect non-RGB formats. */
2891         if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
2892                 return 0;
2893
2894         full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
2895
2896         switch (plane_state->color_encoding) {
2897         case DRM_COLOR_YCBCR_BT601:
2898                 if (full_range)
2899                         *color_space = COLOR_SPACE_YCBCR601;
2900                 else
2901                         *color_space = COLOR_SPACE_YCBCR601_LIMITED;
2902                 break;
2903
2904         case DRM_COLOR_YCBCR_BT709:
2905                 if (full_range)
2906                         *color_space = COLOR_SPACE_YCBCR709;
2907                 else
2908                         *color_space = COLOR_SPACE_YCBCR709_LIMITED;
2909                 break;
2910
2911         case DRM_COLOR_YCBCR_BT2020:
2912                 if (full_range)
2913                         *color_space = COLOR_SPACE_2020_YCBCR;
2914                 else
2915                         return -EINVAL;
2916                 break;
2917
2918         default:
2919                 return -EINVAL;
2920         }
2921
2922         return 0;
2923 }
2924
2925 static int
2926 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
2927                             const struct drm_plane_state *plane_state,
2928                             const uint64_t tiling_flags,
2929                             struct dc_plane_info *plane_info,
2930                             struct dc_plane_address *address)
2931 {
2932         const struct drm_framebuffer *fb = plane_state->fb;
2933         const struct amdgpu_framebuffer *afb =
2934                 to_amdgpu_framebuffer(plane_state->fb);
2935         struct drm_format_name_buf format_name;
2936         int ret;
2937
2938         memset(plane_info, 0, sizeof(*plane_info));
2939
2940         switch (fb->format->format) {
2941         case DRM_FORMAT_C8:
2942                 plane_info->format =
2943                         SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
2944                 break;
2945         case DRM_FORMAT_RGB565:
2946                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
2947                 break;
2948         case DRM_FORMAT_XRGB8888:
2949         case DRM_FORMAT_ARGB8888:
2950                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
2951                 break;
2952         case DRM_FORMAT_XRGB2101010:
2953         case DRM_FORMAT_ARGB2101010:
2954                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
2955                 break;
2956         case DRM_FORMAT_XBGR2101010:
2957         case DRM_FORMAT_ABGR2101010:
2958                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
2959                 break;
2960         case DRM_FORMAT_XBGR8888:
2961         case DRM_FORMAT_ABGR8888:
2962                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
2963                 break;
2964         case DRM_FORMAT_NV21:
2965                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
2966                 break;
2967         case DRM_FORMAT_NV12:
2968                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
2969                 break;
2970         default:
2971                 DRM_ERROR(
2972                         "Unsupported screen format %s\n",
2973                         drm_get_format_name(fb->format->format, &format_name));
2974                 return -EINVAL;
2975         }
2976
2977         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
2978         case DRM_MODE_ROTATE_0:
2979                 plane_info->rotation = ROTATION_ANGLE_0;
2980                 break;
2981         case DRM_MODE_ROTATE_90:
2982                 plane_info->rotation = ROTATION_ANGLE_90;
2983                 break;
2984         case DRM_MODE_ROTATE_180:
2985                 plane_info->rotation = ROTATION_ANGLE_180;
2986                 break;
2987         case DRM_MODE_ROTATE_270:
2988                 plane_info->rotation = ROTATION_ANGLE_270;
2989                 break;
2990         default:
2991                 plane_info->rotation = ROTATION_ANGLE_0;
2992                 break;
2993         }
2994
2995         plane_info->visible = true;
2996         plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
2997
2998         ret = fill_plane_color_attributes(plane_state, plane_info->format,
2999                                           &plane_info->color_space);
3000         if (ret)
3001                 return ret;
3002
3003         ret = fill_plane_buffer_attributes(adev, afb, plane_info->format,
3004                                            plane_info->rotation, tiling_flags,
3005                                            &plane_info->tiling_info,
3006                                            &plane_info->plane_size,
3007                                            &plane_info->dcc, address);
3008         if (ret)
3009                 return ret;
3010
3011         fill_blending_from_plane_state(
3012                 plane_state, &plane_info->per_pixel_alpha,
3013                 &plane_info->global_alpha, &plane_info->global_alpha_value);
3014
3015         return 0;
3016 }
3017
3018 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
3019                                     struct dc_plane_state *dc_plane_state,
3020                                     struct drm_plane_state *plane_state,
3021                                     struct drm_crtc_state *crtc_state)
3022 {
3023         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
3024         const struct amdgpu_framebuffer *amdgpu_fb =
3025                 to_amdgpu_framebuffer(plane_state->fb);
3026         struct dc_scaling_info scaling_info;
3027         struct dc_plane_info plane_info;
3028         uint64_t tiling_flags;
3029         int ret;
3030
3031         ret = fill_dc_scaling_info(plane_state, &scaling_info);
3032         if (ret)
3033                 return ret;
3034
3035         dc_plane_state->src_rect = scaling_info.src_rect;
3036         dc_plane_state->dst_rect = scaling_info.dst_rect;
3037         dc_plane_state->clip_rect = scaling_info.clip_rect;
3038         dc_plane_state->scaling_quality = scaling_info.scaling_quality;
3039
3040         ret = get_fb_info(amdgpu_fb, &tiling_flags);
3041         if (ret)
3042                 return ret;
3043
3044         ret = fill_dc_plane_info_and_addr(adev, plane_state, tiling_flags,
3045                                           &plane_info,
3046                                           &dc_plane_state->address);
3047         if (ret)
3048                 return ret;
3049
3050         dc_plane_state->format = plane_info.format;
3051         dc_plane_state->color_space = plane_info.color_space;
3052         dc_plane_state->format = plane_info.format;
3053         dc_plane_state->plane_size = plane_info.plane_size;
3054         dc_plane_state->rotation = plane_info.rotation;
3055         dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
3056         dc_plane_state->stereo_format = plane_info.stereo_format;
3057         dc_plane_state->tiling_info = plane_info.tiling_info;
3058         dc_plane_state->visible = plane_info.visible;
3059         dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
3060         dc_plane_state->global_alpha = plane_info.global_alpha;
3061         dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
3062         dc_plane_state->dcc = plane_info.dcc;
3063
3064         /*
3065          * Always set input transfer function, since plane state is refreshed
3066          * every time.
3067          */
3068         ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
3069         if (ret)
3070                 return ret;
3071
3072         return 0;
3073 }
3074
3075 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
3076                                            const struct dm_connector_state *dm_state,
3077                                            struct dc_stream_state *stream)
3078 {
3079         enum amdgpu_rmx_type rmx_type;
3080
3081         struct rect src = { 0 }; /* viewport in composition space*/
3082         struct rect dst = { 0 }; /* stream addressable area */
3083
3084         /* no mode. nothing to be done */
3085         if (!mode)
3086                 return;
3087
3088         /* Full screen scaling by default */
3089         src.width = mode->hdisplay;
3090         src.height = mode->vdisplay;
3091         dst.width = stream->timing.h_addressable;
3092         dst.height = stream->timing.v_addressable;
3093
3094         if (dm_state) {
3095                 rmx_type = dm_state->scaling;
3096                 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
3097                         if (src.width * dst.height <
3098                                         src.height * dst.width) {
3099                                 /* height needs less upscaling/more downscaling */
3100                                 dst.width = src.width *
3101                                                 dst.height / src.height;
3102                         } else {
3103                                 /* width needs less upscaling/more downscaling */
3104                                 dst.height = src.height *
3105                                                 dst.width / src.width;
3106                         }
3107                 } else if (rmx_type == RMX_CENTER) {
3108                         dst = src;
3109                 }
3110
3111                 dst.x = (stream->timing.h_addressable - dst.width) / 2;
3112                 dst.y = (stream->timing.v_addressable - dst.height) / 2;
3113
3114                 if (dm_state->underscan_enable) {
3115                         dst.x += dm_state->underscan_hborder / 2;
3116                         dst.y += dm_state->underscan_vborder / 2;
3117                         dst.width -= dm_state->underscan_hborder;
3118                         dst.height -= dm_state->underscan_vborder;
3119                 }
3120         }
3121
3122         stream->src = src;
3123         stream->dst = dst;
3124
3125         DRM_DEBUG_DRIVER("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
3126                         dst.x, dst.y, dst.width, dst.height);
3127
3128 }
3129
3130 static enum dc_color_depth
3131 convert_color_depth_from_display_info(const struct drm_connector *connector,
3132                                       const struct drm_connector_state *state)
3133 {
3134         uint32_t bpc = connector->display_info.bpc;
3135
3136         if (!state)
3137                 state = connector->state;
3138
3139         if (state) {
3140                 bpc = state->max_bpc;
3141                 /* Round down to the nearest even number. */
3142                 bpc = bpc - (bpc & 1);
3143         }
3144
3145         switch (bpc) {
3146         case 0:
3147                 /*
3148                  * Temporary Work around, DRM doesn't parse color depth for
3149                  * EDID revision before 1.4
3150                  * TODO: Fix edid parsing
3151                  */
3152                 return COLOR_DEPTH_888;
3153         case 6:
3154                 return COLOR_DEPTH_666;
3155         case 8:
3156                 return COLOR_DEPTH_888;
3157         case 10:
3158                 return COLOR_DEPTH_101010;
3159         case 12:
3160                 return COLOR_DEPTH_121212;
3161         case 14:
3162                 return COLOR_DEPTH_141414;
3163         case 16:
3164                 return COLOR_DEPTH_161616;
3165         default:
3166                 return COLOR_DEPTH_UNDEFINED;
3167         }
3168 }
3169
3170 static enum dc_aspect_ratio
3171 get_aspect_ratio(const struct drm_display_mode *mode_in)
3172 {
3173         /* 1-1 mapping, since both enums follow the HDMI spec. */
3174         return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
3175 }
3176
3177 static enum dc_color_space
3178 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
3179 {
3180         enum dc_color_space color_space = COLOR_SPACE_SRGB;
3181
3182         switch (dc_crtc_timing->pixel_encoding) {
3183         case PIXEL_ENCODING_YCBCR422:
3184         case PIXEL_ENCODING_YCBCR444:
3185         case PIXEL_ENCODING_YCBCR420:
3186         {
3187                 /*
3188                  * 27030khz is the separation point between HDTV and SDTV
3189                  * according to HDMI spec, we use YCbCr709 and YCbCr601
3190                  * respectively
3191                  */
3192                 if (dc_crtc_timing->pix_clk_100hz > 270300) {
3193                         if (dc_crtc_timing->flags.Y_ONLY)
3194                                 color_space =
3195                                         COLOR_SPACE_YCBCR709_LIMITED;
3196                         else
3197                                 color_space = COLOR_SPACE_YCBCR709;
3198                 } else {
3199                         if (dc_crtc_timing->flags.Y_ONLY)
3200                                 color_space =
3201                                         COLOR_SPACE_YCBCR601_LIMITED;
3202                         else
3203                                 color_space = COLOR_SPACE_YCBCR601;
3204                 }
3205
3206         }
3207         break;
3208         case PIXEL_ENCODING_RGB:
3209                 color_space = COLOR_SPACE_SRGB;
3210                 break;
3211
3212         default:
3213                 WARN_ON(1);
3214                 break;
3215         }
3216
3217         return color_space;
3218 }
3219
3220 static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out)
3221 {
3222         if (timing_out->display_color_depth <= COLOR_DEPTH_888)
3223                 return;
3224
3225         timing_out->display_color_depth--;
3226 }
3227
3228 static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out,
3229                                                 const struct drm_display_info *info)
3230 {
3231         int normalized_clk;
3232         if (timing_out->display_color_depth <= COLOR_DEPTH_888)
3233                 return;
3234         do {
3235                 normalized_clk = timing_out->pix_clk_100hz / 10;
3236                 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
3237                 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
3238                         normalized_clk /= 2;
3239                 /* Adjusting pix clock following on HDMI spec based on colour depth */
3240                 switch (timing_out->display_color_depth) {
3241                 case COLOR_DEPTH_101010:
3242                         normalized_clk = (normalized_clk * 30) / 24;
3243                         break;
3244                 case COLOR_DEPTH_121212:
3245                         normalized_clk = (normalized_clk * 36) / 24;
3246                         break;
3247                 case COLOR_DEPTH_161616:
3248                         normalized_clk = (normalized_clk * 48) / 24;
3249                         break;
3250                 default:
3251                         return;
3252                 }
3253                 if (normalized_clk <= info->max_tmds_clock)
3254                         return;
3255                 reduce_mode_colour_depth(timing_out);
3256
3257         } while (timing_out->display_color_depth > COLOR_DEPTH_888);
3258
3259 }
3260
3261 static void fill_stream_properties_from_drm_display_mode(
3262         struct dc_stream_state *stream,
3263         const struct drm_display_mode *mode_in,
3264         const struct drm_connector *connector,
3265         const struct drm_connector_state *connector_state,
3266         const struct dc_stream_state *old_stream)
3267 {
3268         struct dc_crtc_timing *timing_out = &stream->timing;
3269         const struct drm_display_info *info = &connector->display_info;
3270
3271         memset(timing_out, 0, sizeof(struct dc_crtc_timing));
3272
3273         timing_out->h_border_left = 0;
3274         timing_out->h_border_right = 0;
3275         timing_out->v_border_top = 0;
3276         timing_out->v_border_bottom = 0;
3277         /* TODO: un-hardcode */
3278         if (drm_mode_is_420_only(info, mode_in)
3279                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
3280                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
3281         else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
3282                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
3283                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
3284         else
3285                 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
3286
3287         timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
3288         timing_out->display_color_depth = convert_color_depth_from_display_info(
3289                 connector, connector_state);
3290         timing_out->scan_type = SCANNING_TYPE_NODATA;
3291         timing_out->hdmi_vic = 0;
3292
3293         if(old_stream) {
3294                 timing_out->vic = old_stream->timing.vic;
3295                 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
3296                 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
3297         } else {
3298                 timing_out->vic = drm_match_cea_mode(mode_in);
3299                 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
3300                         timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
3301                 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
3302                         timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
3303         }
3304
3305         timing_out->h_addressable = mode_in->crtc_hdisplay;
3306         timing_out->h_total = mode_in->crtc_htotal;
3307         timing_out->h_sync_width =
3308                 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
3309         timing_out->h_front_porch =
3310                 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
3311         timing_out->v_total = mode_in->crtc_vtotal;
3312         timing_out->v_addressable = mode_in->crtc_vdisplay;
3313         timing_out->v_front_porch =
3314                 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
3315         timing_out->v_sync_width =
3316                 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
3317         timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
3318         timing_out->aspect_ratio = get_aspect_ratio(mode_in);
3319
3320         stream->output_color_space = get_output_color_space(timing_out);
3321
3322         stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
3323         stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
3324         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
3325                 adjust_colour_depth_from_display_info(timing_out, info);
3326 }
3327
3328 static void fill_audio_info(struct audio_info *audio_info,
3329                             const struct drm_connector *drm_connector,
3330                             const struct dc_sink *dc_sink)
3331 {
3332         int i = 0;
3333         int cea_revision = 0;
3334         const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
3335
3336         audio_info->manufacture_id = edid_caps->manufacturer_id;
3337         audio_info->product_id = edid_caps->product_id;
3338
3339         cea_revision = drm_connector->display_info.cea_rev;
3340
3341         strscpy(audio_info->display_name,
3342                 edid_caps->display_name,
3343                 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
3344
3345         if (cea_revision >= 3) {
3346                 audio_info->mode_count = edid_caps->audio_mode_count;
3347
3348                 for (i = 0; i < audio_info->mode_count; ++i) {
3349                         audio_info->modes[i].format_code =
3350                                         (enum audio_format_code)
3351                                         (edid_caps->audio_modes[i].format_code);
3352                         audio_info->modes[i].channel_count =
3353                                         edid_caps->audio_modes[i].channel_count;
3354                         audio_info->modes[i].sample_rates.all =
3355                                         edid_caps->audio_modes[i].sample_rate;
3356                         audio_info->modes[i].sample_size =
3357                                         edid_caps->audio_modes[i].sample_size;
3358                 }
3359         }
3360
3361         audio_info->flags.all = edid_caps->speaker_flags;
3362
3363         /* TODO: We only check for the progressive mode, check for interlace mode too */
3364         if (drm_connector->latency_present[0]) {
3365                 audio_info->video_latency = drm_connector->video_latency[0];
3366                 audio_info->audio_latency = drm_connector->audio_latency[0];
3367         }
3368
3369         /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
3370
3371 }
3372
3373 static void
3374 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
3375                                       struct drm_display_mode *dst_mode)
3376 {
3377         dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
3378         dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
3379         dst_mode->crtc_clock = src_mode->crtc_clock;
3380         dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
3381         dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
3382         dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
3383         dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
3384         dst_mode->crtc_htotal = src_mode->crtc_htotal;
3385         dst_mode->crtc_hskew = src_mode->crtc_hskew;
3386         dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
3387         dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
3388         dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
3389         dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
3390         dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
3391 }
3392
3393 static void
3394 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
3395                                         const struct drm_display_mode *native_mode,
3396                                         bool scale_enabled)
3397 {
3398         if (scale_enabled) {
3399                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
3400         } else if (native_mode->clock == drm_mode->clock &&
3401                         native_mode->htotal == drm_mode->htotal &&
3402                         native_mode->vtotal == drm_mode->vtotal) {
3403                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
3404         } else {
3405                 /* no scaling nor amdgpu inserted, no need to patch */
3406         }
3407 }
3408
3409 static struct dc_sink *
3410 create_fake_sink(struct amdgpu_dm_connector *aconnector)
3411 {
3412         struct dc_sink_init_data sink_init_data = { 0 };
3413         struct dc_sink *sink = NULL;
3414         sink_init_data.link = aconnector->dc_link;
3415         sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
3416
3417         sink = dc_sink_create(&sink_init_data);
3418         if (!sink) {
3419                 DRM_ERROR("Failed to create sink!\n");
3420                 return NULL;
3421         }
3422         sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
3423
3424         return sink;
3425 }
3426
3427 static void set_multisync_trigger_params(
3428                 struct dc_stream_state *stream)
3429 {
3430         if (stream->triggered_crtc_reset.enabled) {
3431                 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
3432                 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
3433         }
3434 }
3435
3436 static void set_master_stream(struct dc_stream_state *stream_set[],
3437                               int stream_count)
3438 {
3439         int j, highest_rfr = 0, master_stream = 0;
3440
3441         for (j = 0;  j < stream_count; j++) {
3442                 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
3443                         int refresh_rate = 0;
3444
3445                         refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
3446                                 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
3447                         if (refresh_rate > highest_rfr) {
3448                                 highest_rfr = refresh_rate;
3449                                 master_stream = j;
3450                         }
3451                 }
3452         }
3453         for (j = 0;  j < stream_count; j++) {
3454                 if (stream_set[j])
3455                         stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
3456         }
3457 }
3458
3459 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
3460 {
3461         int i = 0;
3462
3463         if (context->stream_count < 2)
3464                 return;
3465         for (i = 0; i < context->stream_count ; i++) {
3466                 if (!context->streams[i])
3467                         continue;
3468                 /*
3469                  * TODO: add a function to read AMD VSDB bits and set
3470                  * crtc_sync_master.multi_sync_enabled flag
3471                  * For now it's set to false
3472                  */
3473                 set_multisync_trigger_params(context->streams[i]);
3474         }
3475         set_master_stream(context->streams, context->stream_count);
3476 }
3477
3478 static struct dc_stream_state *
3479 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
3480                        const struct drm_display_mode *drm_mode,
3481                        const struct dm_connector_state *dm_state,
3482                        const struct dc_stream_state *old_stream)
3483 {
3484         struct drm_display_mode *preferred_mode = NULL;
3485         struct drm_connector *drm_connector;
3486         const struct drm_connector_state *con_state =
3487                 dm_state ? &dm_state->base : NULL;
3488         struct dc_stream_state *stream = NULL;
3489         struct drm_display_mode mode = *drm_mode;
3490         bool native_mode_found = false;
3491         bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
3492         int mode_refresh;
3493         int preferred_refresh = 0;
3494
3495         struct dc_sink *sink = NULL;
3496         if (aconnector == NULL) {
3497                 DRM_ERROR("aconnector is NULL!\n");
3498                 return stream;
3499         }
3500
3501         drm_connector = &aconnector->base;
3502
3503         if (!aconnector->dc_sink) {
3504                 sink = create_fake_sink(aconnector);
3505                 if (!sink)
3506                         return stream;
3507         } else {
3508                 sink = aconnector->dc_sink;
3509                 dc_sink_retain(sink);
3510         }
3511
3512         stream = dc_create_stream_for_sink(sink);
3513
3514         if (stream == NULL) {
3515                 DRM_ERROR("Failed to create stream for sink!\n");
3516                 goto finish;
3517         }
3518
3519         stream->dm_stream_context = aconnector;
3520
3521         list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
3522                 /* Search for preferred mode */
3523                 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
3524                         native_mode_found = true;
3525                         break;
3526                 }
3527         }
3528         if (!native_mode_found)
3529                 preferred_mode = list_first_entry_or_null(
3530                                 &aconnector->base.modes,
3531                                 struct drm_display_mode,
3532                                 head);
3533
3534         mode_refresh = drm_mode_vrefresh(&mode);
3535
3536         if (preferred_mode == NULL) {
3537                 /*
3538                  * This may not be an error, the use case is when we have no
3539                  * usermode calls to reset and set mode upon hotplug. In this
3540                  * case, we call set mode ourselves to restore the previous mode
3541                  * and the modelist may not be filled in in time.
3542                  */
3543                 DRM_DEBUG_DRIVER("No preferred mode found\n");
3544         } else {
3545                 decide_crtc_timing_for_drm_display_mode(
3546                                 &mode, preferred_mode,
3547                                 dm_state ? (dm_state->scaling != RMX_OFF) : false);
3548                 preferred_refresh = drm_mode_vrefresh(preferred_mode);
3549         }
3550
3551         if (!dm_state)
3552                 drm_mode_set_crtcinfo(&mode, 0);
3553
3554         /*
3555         * If scaling is enabled and refresh rate didn't change
3556         * we copy the vic and polarities of the old timings
3557         */
3558         if (!scale || mode_refresh != preferred_refresh)
3559                 fill_stream_properties_from_drm_display_mode(stream,
3560                         &mode, &aconnector->base, con_state, NULL);
3561         else
3562                 fill_stream_properties_from_drm_display_mode(stream,
3563                         &mode, &aconnector->base, con_state, old_stream);
3564
3565 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
3566         /* stream->timing.flags.DSC = 0; */
3567         /*  */
3568         /* if (aconnector->dc_link && */
3569         /*              aconnector->dc_link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT #<{(|&& */
3570         /*              aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.is_dsc_supported|)}>#) */
3571         /*      if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc, */
3572         /*                      &aconnector->dc_link->dpcd_caps.dsc_caps, */
3573         /*                      dc_link_bandwidth_kbps(aconnector->dc_link, dc_link_get_link_cap(aconnector->dc_link)), */
3574         /*                      &stream->timing, */
3575         /*                      &stream->timing.dsc_cfg)) */
3576         /*              stream->timing.flags.DSC = 1; */
3577 #endif
3578
3579         update_stream_scaling_settings(&mode, dm_state, stream);
3580
3581         fill_audio_info(
3582                 &stream->audio_info,
3583                 drm_connector,
3584                 sink);
3585
3586         update_stream_signal(stream, sink);
3587
3588 finish:
3589         dc_sink_release(sink);
3590
3591         return stream;
3592 }
3593
3594 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
3595 {
3596         drm_crtc_cleanup(crtc);
3597         kfree(crtc);
3598 }
3599
3600 static void dm_crtc_destroy_state(struct drm_crtc *crtc,
3601                                   struct drm_crtc_state *state)
3602 {
3603         struct dm_crtc_state *cur = to_dm_crtc_state(state);
3604
3605         /* TODO Destroy dc_stream objects are stream object is flattened */
3606         if (cur->stream)
3607                 dc_stream_release(cur->stream);
3608
3609
3610         __drm_atomic_helper_crtc_destroy_state(state);
3611
3612
3613         kfree(state);
3614 }
3615
3616 static void dm_crtc_reset_state(struct drm_crtc *crtc)
3617 {
3618         struct dm_crtc_state *state;
3619
3620         if (crtc->state)
3621                 dm_crtc_destroy_state(crtc, crtc->state);
3622
3623         state = kzalloc(sizeof(*state), GFP_KERNEL);
3624         if (WARN_ON(!state))
3625                 return;
3626
3627         crtc->state = &state->base;
3628         crtc->state->crtc = crtc;
3629
3630 }
3631
3632 static struct drm_crtc_state *
3633 dm_crtc_duplicate_state(struct drm_crtc *crtc)
3634 {
3635         struct dm_crtc_state *state, *cur;
3636
3637         cur = to_dm_crtc_state(crtc->state);
3638
3639         if (WARN_ON(!crtc->state))
3640                 return NULL;
3641
3642         state = kzalloc(sizeof(*state), GFP_KERNEL);
3643         if (!state)
3644                 return NULL;
3645
3646         __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
3647
3648         if (cur->stream) {
3649                 state->stream = cur->stream;
3650                 dc_stream_retain(state->stream);
3651         }
3652
3653         state->active_planes = cur->active_planes;
3654         state->interrupts_enabled = cur->interrupts_enabled;
3655         state->vrr_params = cur->vrr_params;
3656         state->vrr_infopacket = cur->vrr_infopacket;
3657         state->abm_level = cur->abm_level;
3658         state->vrr_supported = cur->vrr_supported;
3659         state->freesync_config = cur->freesync_config;
3660         state->crc_enabled = cur->crc_enabled;
3661         state->cm_has_degamma = cur->cm_has_degamma;
3662         state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
3663
3664         /* TODO Duplicate dc_stream after objects are stream object is flattened */
3665
3666         return &state->base;
3667 }
3668
3669 static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
3670 {
3671         enum dc_irq_source irq_source;
3672         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3673         struct amdgpu_device *adev = crtc->dev->dev_private;
3674         int rc;
3675
3676         irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
3677
3678         rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
3679
3680         DRM_DEBUG_DRIVER("crtc %d - vupdate irq %sabling: r=%d\n",
3681                          acrtc->crtc_id, enable ? "en" : "dis", rc);
3682         return rc;
3683 }
3684
3685 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
3686 {
3687         enum dc_irq_source irq_source;
3688         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3689         struct amdgpu_device *adev = crtc->dev->dev_private;
3690         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
3691         int rc = 0;
3692
3693         if (enable) {
3694                 /* vblank irq on -> Only need vupdate irq in vrr mode */
3695                 if (amdgpu_dm_vrr_active(acrtc_state))
3696                         rc = dm_set_vupdate_irq(crtc, true);
3697         } else {
3698                 /* vblank irq off -> vupdate irq off */
3699                 rc = dm_set_vupdate_irq(crtc, false);
3700         }
3701
3702         if (rc)
3703                 return rc;
3704
3705         irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
3706         return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
3707 }
3708
3709 static int dm_enable_vblank(struct drm_crtc *crtc)
3710 {
3711         return dm_set_vblank(crtc, true);
3712 }
3713
3714 static void dm_disable_vblank(struct drm_crtc *crtc)
3715 {
3716         dm_set_vblank(crtc, false);
3717 }
3718
3719 /* Implemented only the options currently availible for the driver */
3720 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
3721         .reset = dm_crtc_reset_state,
3722         .destroy = amdgpu_dm_crtc_destroy,
3723         .gamma_set = drm_atomic_helper_legacy_gamma_set,
3724         .set_config = drm_atomic_helper_set_config,
3725         .page_flip = drm_atomic_helper_page_flip,
3726         .atomic_duplicate_state = dm_crtc_duplicate_state,
3727         .atomic_destroy_state = dm_crtc_destroy_state,
3728         .set_crc_source = amdgpu_dm_crtc_set_crc_source,
3729         .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
3730         .enable_vblank = dm_enable_vblank,
3731         .disable_vblank = dm_disable_vblank,
3732 };
3733
3734 static enum drm_connector_status
3735 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
3736 {
3737         bool connected;
3738         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
3739
3740         /*
3741          * Notes:
3742          * 1. This interface is NOT called in context of HPD irq.
3743          * 2. This interface *is called* in context of user-mode ioctl. Which
3744          * makes it a bad place for *any* MST-related activity.
3745          */
3746
3747         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
3748             !aconnector->fake_enable)
3749                 connected = (aconnector->dc_sink != NULL);
3750         else
3751                 connected = (aconnector->base.force == DRM_FORCE_ON);
3752
3753         return (connected ? connector_status_connected :
3754                         connector_status_disconnected);
3755 }
3756
3757 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
3758                                             struct drm_connector_state *connector_state,
3759                                             struct drm_property *property,
3760                                             uint64_t val)
3761 {
3762         struct drm_device *dev = connector->dev;
3763         struct amdgpu_device *adev = dev->dev_private;
3764         struct dm_connector_state *dm_old_state =
3765                 to_dm_connector_state(connector->state);
3766         struct dm_connector_state *dm_new_state =
3767                 to_dm_connector_state(connector_state);
3768
3769         int ret = -EINVAL;
3770
3771         if (property == dev->mode_config.scaling_mode_property) {
3772                 enum amdgpu_rmx_type rmx_type;
3773
3774                 switch (val) {
3775                 case DRM_MODE_SCALE_CENTER:
3776                         rmx_type = RMX_CENTER;
3777                         break;
3778                 case DRM_MODE_SCALE_ASPECT:
3779                         rmx_type = RMX_ASPECT;
3780                         break;
3781                 case DRM_MODE_SCALE_FULLSCREEN:
3782                         rmx_type = RMX_FULL;
3783                         break;
3784                 case DRM_MODE_SCALE_NONE:
3785                 default:
3786                         rmx_type = RMX_OFF;
3787                         break;
3788                 }
3789
3790                 if (dm_old_state->scaling == rmx_type)
3791                         return 0;
3792
3793                 dm_new_state->scaling = rmx_type;
3794                 ret = 0;
3795         } else if (property == adev->mode_info.underscan_hborder_property) {
3796                 dm_new_state->underscan_hborder = val;
3797                 ret = 0;
3798         } else if (property == adev->mode_info.underscan_vborder_property) {
3799                 dm_new_state->underscan_vborder = val;
3800                 ret = 0;
3801         } else if (property == adev->mode_info.underscan_property) {
3802                 dm_new_state->underscan_enable = val;
3803                 ret = 0;
3804         } else if (property == adev->mode_info.abm_level_property) {
3805                 dm_new_state->abm_level = val;
3806                 ret = 0;
3807         }
3808
3809         return ret;
3810 }
3811
3812 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
3813                                             const struct drm_connector_state *state,
3814                                             struct drm_property *property,
3815                                             uint64_t *val)
3816 {
3817         struct drm_device *dev = connector->dev;
3818         struct amdgpu_device *adev = dev->dev_private;
3819         struct dm_connector_state *dm_state =
3820                 to_dm_connector_state(state);
3821         int ret = -EINVAL;
3822
3823         if (property == dev->mode_config.scaling_mode_property) {
3824                 switch (dm_state->scaling) {
3825                 case RMX_CENTER:
3826                         *val = DRM_MODE_SCALE_CENTER;
3827                         break;
3828                 case RMX_ASPECT:
3829                         *val = DRM_MODE_SCALE_ASPECT;
3830                         break;
3831                 case RMX_FULL:
3832                         *val = DRM_MODE_SCALE_FULLSCREEN;
3833                         break;
3834                 case RMX_OFF:
3835                 default:
3836                         *val = DRM_MODE_SCALE_NONE;
3837                         break;
3838                 }
3839                 ret = 0;
3840         } else if (property == adev->mode_info.underscan_hborder_property) {
3841                 *val = dm_state->underscan_hborder;
3842                 ret = 0;
3843         } else if (property == adev->mode_info.underscan_vborder_property) {
3844                 *val = dm_state->underscan_vborder;
3845                 ret = 0;
3846         } else if (property == adev->mode_info.underscan_property) {
3847                 *val = dm_state->underscan_enable;
3848                 ret = 0;
3849         } else if (property == adev->mode_info.abm_level_property) {
3850                 *val = dm_state->abm_level;
3851                 ret = 0;
3852         }
3853
3854         return ret;
3855 }
3856
3857 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
3858 {
3859         struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
3860
3861         drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
3862 }
3863
3864 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
3865 {
3866         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
3867         const struct dc_link *link = aconnector->dc_link;
3868         struct amdgpu_device *adev = connector->dev->dev_private;
3869         struct amdgpu_display_manager *dm = &adev->dm;
3870
3871 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3872         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3873
3874         if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
3875             link->type != dc_connection_none &&
3876             dm->backlight_dev) {
3877                 backlight_device_unregister(dm->backlight_dev);
3878                 dm->backlight_dev = NULL;
3879         }
3880 #endif
3881
3882         if (aconnector->dc_em_sink)
3883                 dc_sink_release(aconnector->dc_em_sink);
3884         aconnector->dc_em_sink = NULL;
3885         if (aconnector->dc_sink)
3886                 dc_sink_release(aconnector->dc_sink);
3887         aconnector->dc_sink = NULL;
3888
3889         drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
3890         drm_connector_unregister(connector);
3891         drm_connector_cleanup(connector);
3892         if (aconnector->i2c) {
3893                 i2c_del_adapter(&aconnector->i2c->base);
3894                 kfree(aconnector->i2c);
3895         }
3896
3897         kfree(connector);
3898 }
3899
3900 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
3901 {
3902         struct dm_connector_state *state =
3903                 to_dm_connector_state(connector->state);
3904
3905         if (connector->state)
3906                 __drm_atomic_helper_connector_destroy_state(connector->state);
3907
3908         kfree(state);
3909
3910         state = kzalloc(sizeof(*state), GFP_KERNEL);
3911
3912         if (state) {
3913                 state->scaling = RMX_OFF;
3914                 state->underscan_enable = false;
3915                 state->underscan_hborder = 0;
3916                 state->underscan_vborder = 0;
3917                 state->base.max_requested_bpc = 8;
3918
3919                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3920                         state->abm_level = amdgpu_dm_abm_level;
3921
3922                 __drm_atomic_helper_connector_reset(connector, &state->base);
3923         }
3924 }
3925
3926 struct drm_connector_state *
3927 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
3928 {
3929         struct dm_connector_state *state =
3930                 to_dm_connector_state(connector->state);
3931
3932         struct dm_connector_state *new_state =
3933                         kmemdup(state, sizeof(*state), GFP_KERNEL);
3934
3935         if (!new_state)
3936                 return NULL;
3937
3938         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
3939
3940         new_state->freesync_capable = state->freesync_capable;
3941         new_state->abm_level = state->abm_level;
3942         new_state->scaling = state->scaling;
3943         new_state->underscan_enable = state->underscan_enable;
3944         new_state->underscan_hborder = state->underscan_hborder;
3945         new_state->underscan_vborder = state->underscan_vborder;
3946
3947         return &new_state->base;
3948 }
3949
3950 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
3951         .reset = amdgpu_dm_connector_funcs_reset,
3952         .detect = amdgpu_dm_connector_detect,
3953         .fill_modes = drm_helper_probe_single_connector_modes,
3954         .destroy = amdgpu_dm_connector_destroy,
3955         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
3956         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
3957         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
3958         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
3959         .early_unregister = amdgpu_dm_connector_unregister
3960 };
3961
3962 static int get_modes(struct drm_connector *connector)
3963 {
3964         return amdgpu_dm_connector_get_modes(connector);
3965 }
3966
3967 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
3968 {
3969         struct dc_sink_init_data init_params = {
3970                         .link = aconnector->dc_link,
3971                         .sink_signal = SIGNAL_TYPE_VIRTUAL
3972         };
3973         struct edid *edid;
3974
3975         if (!aconnector->base.edid_blob_ptr) {
3976                 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
3977                                 aconnector->base.name);
3978
3979                 aconnector->base.force = DRM_FORCE_OFF;
3980                 aconnector->base.override_edid = false;
3981                 return;
3982         }
3983
3984         edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
3985
3986         aconnector->edid = edid;
3987
3988         aconnector->dc_em_sink = dc_link_add_remote_sink(
3989                 aconnector->dc_link,
3990                 (uint8_t *)edid,
3991                 (edid->extensions + 1) * EDID_LENGTH,
3992                 &init_params);
3993
3994         if (aconnector->base.force == DRM_FORCE_ON) {
3995                 aconnector->dc_sink = aconnector->dc_link->local_sink ?
3996                 aconnector->dc_link->local_sink :
3997                 aconnector->dc_em_sink;
3998                 dc_sink_retain(aconnector->dc_sink);
3999         }
4000 }
4001
4002 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
4003 {
4004         struct dc_link *link = (struct dc_link *)aconnector->dc_link;
4005
4006         /*
4007          * In case of headless boot with force on for DP managed connector
4008          * Those settings have to be != 0 to get initial modeset
4009          */
4010         if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
4011                 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
4012                 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
4013         }
4014
4015
4016         aconnector->base.override_edid = true;
4017         create_eml_sink(aconnector);
4018 }
4019
4020 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
4021                                    struct drm_display_mode *mode)
4022 {
4023         int result = MODE_ERROR;
4024         struct dc_sink *dc_sink;
4025         struct amdgpu_device *adev = connector->dev->dev_private;
4026         /* TODO: Unhardcode stream count */
4027         struct dc_stream_state *stream;
4028         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
4029         enum dc_status dc_result = DC_OK;
4030
4031         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
4032                         (mode->flags & DRM_MODE_FLAG_DBLSCAN))
4033                 return result;
4034
4035         /*
4036          * Only run this the first time mode_valid is called to initilialize
4037          * EDID mgmt
4038          */
4039         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
4040                 !aconnector->dc_em_sink)
4041                 handle_edid_mgmt(aconnector);
4042
4043         dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
4044
4045         if (dc_sink == NULL) {
4046                 DRM_ERROR("dc_sink is NULL!\n");
4047                 goto fail;
4048         }
4049
4050         stream = create_stream_for_sink(aconnector, mode, NULL, NULL);
4051         if (stream == NULL) {
4052                 DRM_ERROR("Failed to create stream for sink!\n");
4053                 goto fail;
4054         }
4055
4056         dc_result = dc_validate_stream(adev->dm.dc, stream);
4057
4058         if (dc_result == DC_OK)
4059                 result = MODE_OK;
4060         else
4061                 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
4062                               mode->vdisplay,
4063                               mode->hdisplay,
4064                               mode->clock,
4065                               dc_result);
4066
4067         dc_stream_release(stream);
4068
4069 fail:
4070         /* TODO: error handling*/
4071         return result;
4072 }
4073
4074 static int fill_hdr_info_packet(const struct drm_connector_state *state,
4075                                 struct dc_info_packet *out)
4076 {
4077         struct hdmi_drm_infoframe frame;
4078         unsigned char buf[30]; /* 26 + 4 */
4079         ssize_t len;
4080         int ret, i;
4081
4082         memset(out, 0, sizeof(*out));
4083
4084         if (!state->hdr_output_metadata)
4085                 return 0;
4086
4087         ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
4088         if (ret)
4089                 return ret;
4090
4091         len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
4092         if (len < 0)
4093                 return (int)len;
4094
4095         /* Static metadata is a fixed 26 bytes + 4 byte header. */
4096         if (len != 30)
4097                 return -EINVAL;
4098
4099         /* Prepare the infopacket for DC. */
4100         switch (state->connector->connector_type) {
4101         case DRM_MODE_CONNECTOR_HDMIA:
4102                 out->hb0 = 0x87; /* type */
4103                 out->hb1 = 0x01; /* version */
4104                 out->hb2 = 0x1A; /* length */
4105                 out->sb[0] = buf[3]; /* checksum */
4106                 i = 1;
4107                 break;
4108
4109         case DRM_MODE_CONNECTOR_DisplayPort:
4110         case DRM_MODE_CONNECTOR_eDP:
4111                 out->hb0 = 0x00; /* sdp id, zero */
4112                 out->hb1 = 0x87; /* type */
4113                 out->hb2 = 0x1D; /* payload len - 1 */
4114                 out->hb3 = (0x13 << 2); /* sdp version */
4115                 out->sb[0] = 0x01; /* version */
4116                 out->sb[1] = 0x1A; /* length */
4117                 i = 2;
4118                 break;
4119
4120         default:
4121                 return -EINVAL;
4122         }
4123
4124         memcpy(&out->sb[i], &buf[4], 26);
4125         out->valid = true;
4126
4127         print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
4128                        sizeof(out->sb), false);
4129
4130         return 0;
4131 }
4132
4133 static bool
4134 is_hdr_metadata_different(const struct drm_connector_state *old_state,
4135                           const struct drm_connector_state *new_state)
4136 {
4137         struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
4138         struct drm_property_blob *new_blob = new_state->hdr_output_metadata;
4139
4140         if (old_blob != new_blob) {
4141                 if (old_blob && new_blob &&
4142                     old_blob->length == new_blob->length)
4143                         return memcmp(old_blob->data, new_blob->data,
4144                                       old_blob->length);
4145
4146                 return true;
4147         }
4148
4149         return false;
4150 }
4151
4152 static int
4153 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
4154                                  struct drm_atomic_state *state)
4155 {
4156         struct drm_connector_state *new_con_state =
4157                 drm_atomic_get_new_connector_state(state, conn);
4158         struct drm_connector_state *old_con_state =
4159                 drm_atomic_get_old_connector_state(state, conn);
4160         struct drm_crtc *crtc = new_con_state->crtc;
4161         struct drm_crtc_state *new_crtc_state;
4162         int ret;
4163
4164         if (!crtc)
4165                 return 0;
4166
4167         if (is_hdr_metadata_different(old_con_state, new_con_state)) {
4168                 struct dc_info_packet hdr_infopacket;
4169
4170                 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
4171                 if (ret)
4172                         return ret;
4173
4174                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
4175                 if (IS_ERR(new_crtc_state))
4176                         return PTR_ERR(new_crtc_state);
4177
4178                 /*
4179                  * DC considers the stream backends changed if the
4180                  * static metadata changes. Forcing the modeset also
4181                  * gives a simple way for userspace to switch from
4182                  * 8bpc to 10bpc when setting the metadata to enter
4183                  * or exit HDR.
4184                  *
4185                  * Changing the static metadata after it's been
4186                  * set is permissible, however. So only force a
4187                  * modeset if we're entering or exiting HDR.
4188                  */
4189                 new_crtc_state->mode_changed =
4190                         !old_con_state->hdr_output_metadata ||
4191                         !new_con_state->hdr_output_metadata;
4192         }
4193
4194         return 0;
4195 }
4196
4197 static const struct drm_connector_helper_funcs
4198 amdgpu_dm_connector_helper_funcs = {
4199         /*
4200          * If hotplugging a second bigger display in FB Con mode, bigger resolution
4201          * modes will be filtered by drm_mode_validate_size(), and those modes
4202          * are missing after user start lightdm. So we need to renew modes list.
4203          * in get_modes call back, not just return the modes count
4204          */
4205         .get_modes = get_modes,
4206         .mode_valid = amdgpu_dm_connector_mode_valid,
4207         .atomic_check = amdgpu_dm_connector_atomic_check,
4208 };
4209
4210 static void dm_crtc_helper_disable(struct drm_crtc *crtc)
4211 {
4212 }
4213
4214 static bool does_crtc_have_active_cursor(struct drm_crtc_state *new_crtc_state)
4215 {
4216         struct drm_device *dev = new_crtc_state->crtc->dev;
4217         struct drm_plane *plane;
4218
4219         drm_for_each_plane_mask(plane, dev, new_crtc_state->plane_mask) {
4220                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4221                         return true;
4222         }
4223
4224         return false;
4225 }
4226
4227 static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
4228 {
4229         struct drm_atomic_state *state = new_crtc_state->state;
4230         struct drm_plane *plane;
4231         int num_active = 0;
4232
4233         drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) {
4234                 struct drm_plane_state *new_plane_state;
4235
4236                 /* Cursor planes are "fake". */
4237                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4238                         continue;
4239
4240                 new_plane_state = drm_atomic_get_new_plane_state(state, plane);
4241
4242                 if (!new_plane_state) {
4243                         /*
4244                          * The plane is enable on the CRTC and hasn't changed
4245                          * state. This means that it previously passed
4246                          * validation and is therefore enabled.
4247                          */
4248                         num_active += 1;
4249                         continue;
4250                 }
4251
4252                 /* We need a framebuffer to be considered enabled. */
4253                 num_active += (new_plane_state->fb != NULL);
4254         }
4255
4256         return num_active;
4257 }
4258
4259 /*
4260  * Sets whether interrupts should be enabled on a specific CRTC.
4261  * We require that the stream be enabled and that there exist active
4262  * DC planes on the stream.
4263  */
4264 static void
4265 dm_update_crtc_interrupt_state(struct drm_crtc *crtc,
4266                                struct drm_crtc_state *new_crtc_state)
4267 {
4268         struct dm_crtc_state *dm_new_crtc_state =
4269                 to_dm_crtc_state(new_crtc_state);
4270
4271         dm_new_crtc_state->active_planes = 0;
4272         dm_new_crtc_state->interrupts_enabled = false;
4273
4274         if (!dm_new_crtc_state->stream)
4275                 return;
4276
4277         dm_new_crtc_state->active_planes =
4278                 count_crtc_active_planes(new_crtc_state);
4279
4280         dm_new_crtc_state->interrupts_enabled =
4281                 dm_new_crtc_state->active_planes > 0;
4282 }
4283
4284 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
4285                                        struct drm_crtc_state *state)
4286 {
4287         struct amdgpu_device *adev = crtc->dev->dev_private;
4288         struct dc *dc = adev->dm.dc;
4289         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
4290         int ret = -EINVAL;
4291
4292         /*
4293          * Update interrupt state for the CRTC. This needs to happen whenever
4294          * the CRTC has changed or whenever any of its planes have changed.
4295          * Atomic check satisfies both of these requirements since the CRTC
4296          * is added to the state by DRM during drm_atomic_helper_check_planes.
4297          */
4298         dm_update_crtc_interrupt_state(crtc, state);
4299
4300         if (unlikely(!dm_crtc_state->stream &&
4301                      modeset_required(state, NULL, dm_crtc_state->stream))) {
4302                 WARN_ON(1);
4303                 return ret;
4304         }
4305
4306         /* In some use cases, like reset, no stream is attached */
4307         if (!dm_crtc_state->stream)
4308                 return 0;
4309
4310         /*
4311          * We want at least one hardware plane enabled to use
4312          * the stream with a cursor enabled.
4313          */
4314         if (state->enable && state->active &&
4315             does_crtc_have_active_cursor(state) &&
4316             dm_crtc_state->active_planes == 0)
4317                 return -EINVAL;
4318
4319         if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
4320                 return 0;
4321
4322         return ret;
4323 }
4324
4325 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
4326                                       const struct drm_display_mode *mode,
4327                                       struct drm_display_mode *adjusted_mode)
4328 {
4329         return true;
4330 }
4331
4332 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
4333         .disable = dm_crtc_helper_disable,
4334         .atomic_check = dm_crtc_helper_atomic_check,
4335         .mode_fixup = dm_crtc_helper_mode_fixup
4336 };
4337
4338 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
4339 {
4340
4341 }
4342
4343 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
4344                                           struct drm_crtc_state *crtc_state,
4345                                           struct drm_connector_state *conn_state)
4346 {
4347         return 0;
4348 }
4349
4350 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
4351         .disable = dm_encoder_helper_disable,
4352         .atomic_check = dm_encoder_helper_atomic_check
4353 };
4354
4355 static void dm_drm_plane_reset(struct drm_plane *plane)
4356 {
4357         struct dm_plane_state *amdgpu_state = NULL;
4358
4359         if (plane->state)
4360                 plane->funcs->atomic_destroy_state(plane, plane->state);
4361
4362         amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
4363         WARN_ON(amdgpu_state == NULL);
4364
4365         if (amdgpu_state)
4366                 __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base);
4367 }
4368
4369 static struct drm_plane_state *
4370 dm_drm_plane_duplicate_state(struct drm_plane *plane)
4371 {
4372         struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
4373
4374         old_dm_plane_state = to_dm_plane_state(plane->state);
4375         dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
4376         if (!dm_plane_state)
4377                 return NULL;
4378
4379         __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
4380
4381         if (old_dm_plane_state->dc_state) {
4382                 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
4383                 dc_plane_state_retain(dm_plane_state->dc_state);
4384         }
4385
4386         return &dm_plane_state->base;
4387 }
4388
4389 void dm_drm_plane_destroy_state(struct drm_plane *plane,
4390                                 struct drm_plane_state *state)
4391 {
4392         struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
4393
4394         if (dm_plane_state->dc_state)
4395                 dc_plane_state_release(dm_plane_state->dc_state);
4396
4397         drm_atomic_helper_plane_destroy_state(plane, state);
4398 }
4399
4400 static const struct drm_plane_funcs dm_plane_funcs = {
4401         .update_plane   = drm_atomic_helper_update_plane,
4402         .disable_plane  = drm_atomic_helper_disable_plane,
4403         .destroy        = drm_primary_helper_destroy,
4404         .reset = dm_drm_plane_reset,
4405         .atomic_duplicate_state = dm_drm_plane_duplicate_state,
4406         .atomic_destroy_state = dm_drm_plane_destroy_state,
4407 };
4408
4409 static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
4410                                       struct drm_plane_state *new_state)
4411 {
4412         struct amdgpu_framebuffer *afb;
4413         struct drm_gem_object *obj;
4414         struct amdgpu_device *adev;
4415         struct amdgpu_bo *rbo;
4416         struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
4417         struct list_head list;
4418         struct ttm_validate_buffer tv;
4419         struct ww_acquire_ctx ticket;
4420         uint64_t tiling_flags;
4421         uint32_t domain;
4422         int r;
4423
4424         dm_plane_state_old = to_dm_plane_state(plane->state);
4425         dm_plane_state_new = to_dm_plane_state(new_state);
4426
4427         if (!new_state->fb) {
4428                 DRM_DEBUG_DRIVER("No FB bound\n");
4429                 return 0;
4430         }
4431
4432         afb = to_amdgpu_framebuffer(new_state->fb);
4433         obj = new_state->fb->obj[0];
4434         rbo = gem_to_amdgpu_bo(obj);
4435         adev = amdgpu_ttm_adev(rbo->tbo.bdev);
4436         INIT_LIST_HEAD(&list);
4437
4438         tv.bo = &rbo->tbo;
4439         tv.num_shared = 1;
4440         list_add(&tv.head, &list);
4441
4442         r = ttm_eu_reserve_buffers(&ticket, &list, false, NULL, true);
4443         if (r) {
4444                 dev_err(adev->dev, "fail to reserve bo (%d)\n", r);
4445                 return r;
4446         }
4447
4448         if (plane->type != DRM_PLANE_TYPE_CURSOR)
4449                 domain = amdgpu_display_supported_domains(adev);
4450         else
4451                 domain = AMDGPU_GEM_DOMAIN_VRAM;
4452
4453         r = amdgpu_bo_pin(rbo, domain);
4454         if (unlikely(r != 0)) {
4455                 if (r != -ERESTARTSYS)
4456                         DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
4457                 ttm_eu_backoff_reservation(&ticket, &list);
4458                 return r;
4459         }
4460
4461         r = amdgpu_ttm_alloc_gart(&rbo->tbo);
4462         if (unlikely(r != 0)) {
4463                 amdgpu_bo_unpin(rbo);
4464                 ttm_eu_backoff_reservation(&ticket, &list);
4465                 DRM_ERROR("%p bind failed\n", rbo);
4466                 return r;
4467         }
4468
4469         amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
4470
4471         ttm_eu_backoff_reservation(&ticket, &list);
4472
4473         afb->address = amdgpu_bo_gpu_offset(rbo);
4474
4475         amdgpu_bo_ref(rbo);
4476
4477         if (dm_plane_state_new->dc_state &&
4478                         dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
4479                 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
4480
4481                 fill_plane_buffer_attributes(
4482                         adev, afb, plane_state->format, plane_state->rotation,
4483                         tiling_flags, &plane_state->tiling_info,
4484                         &plane_state->plane_size, &plane_state->dcc,
4485                         &plane_state->address);
4486         }
4487
4488         return 0;
4489 }
4490
4491 static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
4492                                        struct drm_plane_state *old_state)
4493 {
4494         struct amdgpu_bo *rbo;
4495         int r;
4496
4497         if (!old_state->fb)
4498                 return;
4499
4500         rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
4501         r = amdgpu_bo_reserve(rbo, false);
4502         if (unlikely(r)) {
4503                 DRM_ERROR("failed to reserve rbo before unpin\n");
4504                 return;
4505         }
4506
4507         amdgpu_bo_unpin(rbo);
4508         amdgpu_bo_unreserve(rbo);
4509         amdgpu_bo_unref(&rbo);
4510 }
4511
4512 static int dm_plane_atomic_check(struct drm_plane *plane,
4513                                  struct drm_plane_state *state)
4514 {
4515         struct amdgpu_device *adev = plane->dev->dev_private;
4516         struct dc *dc = adev->dm.dc;
4517         struct dm_plane_state *dm_plane_state;
4518         struct dc_scaling_info scaling_info;
4519         int ret;
4520
4521         dm_plane_state = to_dm_plane_state(state);
4522
4523         if (!dm_plane_state->dc_state)
4524                 return 0;
4525
4526         ret = fill_dc_scaling_info(state, &scaling_info);
4527         if (ret)
4528                 return ret;
4529
4530         if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
4531                 return 0;
4532
4533         return -EINVAL;
4534 }
4535
4536 static int dm_plane_atomic_async_check(struct drm_plane *plane,
4537                                        struct drm_plane_state *new_plane_state)
4538 {
4539         struct drm_plane_state *old_plane_state =
4540                 drm_atomic_get_old_plane_state(new_plane_state->state, plane);
4541
4542         /* Only support async updates on cursor planes. */
4543         if (plane->type != DRM_PLANE_TYPE_CURSOR)
4544                 return -EINVAL;
4545
4546         /*
4547          * DRM calls prepare_fb and cleanup_fb on new_plane_state for
4548          * async commits so don't allow fb changes.
4549          */
4550         if (old_plane_state->fb != new_plane_state->fb)
4551                 return -EINVAL;
4552
4553         return 0;
4554 }
4555
4556 static void dm_plane_atomic_async_update(struct drm_plane *plane,
4557                                          struct drm_plane_state *new_state)
4558 {
4559         struct drm_plane_state *old_state =
4560                 drm_atomic_get_old_plane_state(new_state->state, plane);
4561
4562         swap(plane->state->fb, new_state->fb);
4563
4564         plane->state->src_x = new_state->src_x;
4565         plane->state->src_y = new_state->src_y;
4566         plane->state->src_w = new_state->src_w;
4567         plane->state->src_h = new_state->src_h;
4568         plane->state->crtc_x = new_state->crtc_x;
4569         plane->state->crtc_y = new_state->crtc_y;
4570         plane->state->crtc_w = new_state->crtc_w;
4571         plane->state->crtc_h = new_state->crtc_h;
4572
4573         handle_cursor_update(plane, old_state);
4574 }
4575
4576 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
4577         .prepare_fb = dm_plane_helper_prepare_fb,
4578         .cleanup_fb = dm_plane_helper_cleanup_fb,
4579         .atomic_check = dm_plane_atomic_check,
4580         .atomic_async_check = dm_plane_atomic_async_check,
4581         .atomic_async_update = dm_plane_atomic_async_update
4582 };
4583
4584 /*
4585  * TODO: these are currently initialized to rgb formats only.
4586  * For future use cases we should either initialize them dynamically based on
4587  * plane capabilities, or initialize this array to all formats, so internal drm
4588  * check will succeed, and let DC implement proper check
4589  */
4590 static const uint32_t rgb_formats[] = {
4591         DRM_FORMAT_XRGB8888,
4592         DRM_FORMAT_ARGB8888,
4593         DRM_FORMAT_RGBA8888,
4594         DRM_FORMAT_XRGB2101010,
4595         DRM_FORMAT_XBGR2101010,
4596         DRM_FORMAT_ARGB2101010,
4597         DRM_FORMAT_ABGR2101010,
4598         DRM_FORMAT_XBGR8888,
4599         DRM_FORMAT_ABGR8888,
4600         DRM_FORMAT_RGB565,
4601 };
4602
4603 static const uint32_t overlay_formats[] = {
4604         DRM_FORMAT_XRGB8888,
4605         DRM_FORMAT_ARGB8888,
4606         DRM_FORMAT_RGBA8888,
4607         DRM_FORMAT_XBGR8888,
4608         DRM_FORMAT_ABGR8888,
4609         DRM_FORMAT_RGB565
4610 };
4611
4612 static const u32 cursor_formats[] = {
4613         DRM_FORMAT_ARGB8888
4614 };
4615
4616 static int get_plane_formats(const struct drm_plane *plane,
4617                              const struct dc_plane_cap *plane_cap,
4618                              uint32_t *formats, int max_formats)
4619 {
4620         int i, num_formats = 0;
4621
4622         /*
4623          * TODO: Query support for each group of formats directly from
4624          * DC plane caps. This will require adding more formats to the
4625          * caps list.
4626          */
4627
4628         switch (plane->type) {
4629         case DRM_PLANE_TYPE_PRIMARY:
4630                 for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) {
4631                         if (num_formats >= max_formats)
4632                                 break;
4633
4634                         formats[num_formats++] = rgb_formats[i];
4635                 }
4636
4637                 if (plane_cap && plane_cap->pixel_format_support.nv12)
4638                         formats[num_formats++] = DRM_FORMAT_NV12;
4639                 break;
4640
4641         case DRM_PLANE_TYPE_OVERLAY:
4642                 for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) {
4643                         if (num_formats >= max_formats)
4644                                 break;
4645
4646                         formats[num_formats++] = overlay_formats[i];
4647                 }
4648                 break;
4649
4650         case DRM_PLANE_TYPE_CURSOR:
4651                 for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) {
4652                         if (num_formats >= max_formats)
4653                                 break;
4654
4655                         formats[num_formats++] = cursor_formats[i];
4656                 }
4657                 break;
4658         }
4659
4660         return num_formats;
4661 }
4662
4663 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
4664                                 struct drm_plane *plane,
4665                                 unsigned long possible_crtcs,
4666                                 const struct dc_plane_cap *plane_cap)
4667 {
4668         uint32_t formats[32];
4669         int num_formats;
4670         int res = -EPERM;
4671
4672         num_formats = get_plane_formats(plane, plane_cap, formats,
4673                                         ARRAY_SIZE(formats));
4674
4675         res = drm_universal_plane_init(dm->adev->ddev, plane, possible_crtcs,
4676                                        &dm_plane_funcs, formats, num_formats,
4677                                        NULL, plane->type, NULL);
4678         if (res)
4679                 return res;
4680
4681         if (plane->type == DRM_PLANE_TYPE_OVERLAY &&
4682             plane_cap && plane_cap->per_pixel_alpha) {
4683                 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
4684                                           BIT(DRM_MODE_BLEND_PREMULTI);
4685
4686                 drm_plane_create_alpha_property(plane);
4687                 drm_plane_create_blend_mode_property(plane, blend_caps);
4688         }
4689
4690         if (plane->type == DRM_PLANE_TYPE_PRIMARY &&
4691             plane_cap && plane_cap->pixel_format_support.nv12) {
4692                 /* This only affects YUV formats. */
4693                 drm_plane_create_color_properties(
4694                         plane,
4695                         BIT(DRM_COLOR_YCBCR_BT601) |
4696                         BIT(DRM_COLOR_YCBCR_BT709),
4697                         BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
4698                         BIT(DRM_COLOR_YCBCR_FULL_RANGE),
4699                         DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE);
4700         }
4701
4702         drm_plane_helper_add(plane, &dm_plane_helper_funcs);
4703
4704         /* Create (reset) the plane state */
4705         if (plane->funcs->reset)
4706                 plane->funcs->reset(plane);
4707
4708         return 0;
4709 }
4710
4711 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
4712                                struct drm_plane *plane,
4713                                uint32_t crtc_index)
4714 {
4715         struct amdgpu_crtc *acrtc = NULL;
4716         struct drm_plane *cursor_plane;
4717
4718         int res = -ENOMEM;
4719
4720         cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
4721         if (!cursor_plane)
4722                 goto fail;
4723
4724         cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
4725         res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL);
4726
4727         acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
4728         if (!acrtc)
4729                 goto fail;
4730
4731         res = drm_crtc_init_with_planes(
4732                         dm->ddev,
4733                         &acrtc->base,
4734                         plane,
4735                         cursor_plane,
4736                         &amdgpu_dm_crtc_funcs, NULL);
4737
4738         if (res)
4739                 goto fail;
4740
4741         drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
4742
4743         /* Create (reset) the plane state */
4744         if (acrtc->base.funcs->reset)
4745                 acrtc->base.funcs->reset(&acrtc->base);
4746
4747         acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
4748         acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
4749
4750         acrtc->crtc_id = crtc_index;
4751         acrtc->base.enabled = false;
4752         acrtc->otg_inst = -1;
4753
4754         dm->adev->mode_info.crtcs[crtc_index] = acrtc;
4755         drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
4756                                    true, MAX_COLOR_LUT_ENTRIES);
4757         drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
4758
4759         return 0;
4760
4761 fail:
4762         kfree(acrtc);
4763         kfree(cursor_plane);
4764         return res;
4765 }
4766
4767
4768 static int to_drm_connector_type(enum signal_type st)
4769 {
4770         switch (st) {
4771         case SIGNAL_TYPE_HDMI_TYPE_A:
4772                 return DRM_MODE_CONNECTOR_HDMIA;
4773         case SIGNAL_TYPE_EDP:
4774                 return DRM_MODE_CONNECTOR_eDP;
4775         case SIGNAL_TYPE_LVDS:
4776                 return DRM_MODE_CONNECTOR_LVDS;
4777         case SIGNAL_TYPE_RGB:
4778                 return DRM_MODE_CONNECTOR_VGA;
4779         case SIGNAL_TYPE_DISPLAY_PORT:
4780         case SIGNAL_TYPE_DISPLAY_PORT_MST:
4781                 return DRM_MODE_CONNECTOR_DisplayPort;
4782         case SIGNAL_TYPE_DVI_DUAL_LINK:
4783         case SIGNAL_TYPE_DVI_SINGLE_LINK:
4784                 return DRM_MODE_CONNECTOR_DVID;
4785         case SIGNAL_TYPE_VIRTUAL:
4786                 return DRM_MODE_CONNECTOR_VIRTUAL;
4787
4788         default:
4789                 return DRM_MODE_CONNECTOR_Unknown;
4790         }
4791 }
4792
4793 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
4794 {
4795         return drm_encoder_find(connector->dev, NULL, connector->encoder_ids[0]);
4796 }
4797
4798 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
4799 {
4800         struct drm_encoder *encoder;
4801         struct amdgpu_encoder *amdgpu_encoder;
4802
4803         encoder = amdgpu_dm_connector_to_encoder(connector);
4804
4805         if (encoder == NULL)
4806                 return;
4807
4808         amdgpu_encoder = to_amdgpu_encoder(encoder);
4809
4810         amdgpu_encoder->native_mode.clock = 0;
4811
4812         if (!list_empty(&connector->probed_modes)) {
4813                 struct drm_display_mode *preferred_mode = NULL;
4814
4815                 list_for_each_entry(preferred_mode,
4816                                     &connector->probed_modes,
4817                                     head) {
4818                         if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
4819                                 amdgpu_encoder->native_mode = *preferred_mode;
4820
4821                         break;
4822                 }
4823
4824         }
4825 }
4826
4827 static struct drm_display_mode *
4828 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
4829                              char *name,
4830                              int hdisplay, int vdisplay)
4831 {
4832         struct drm_device *dev = encoder->dev;
4833         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
4834         struct drm_display_mode *mode = NULL;
4835         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
4836
4837         mode = drm_mode_duplicate(dev, native_mode);
4838
4839         if (mode == NULL)
4840                 return NULL;
4841
4842         mode->hdisplay = hdisplay;
4843         mode->vdisplay = vdisplay;
4844         mode->type &= ~DRM_MODE_TYPE_PREFERRED;
4845         strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
4846
4847         return mode;
4848
4849 }
4850
4851 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
4852                                                  struct drm_connector *connector)
4853 {
4854         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
4855         struct drm_display_mode *mode = NULL;
4856         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
4857         struct amdgpu_dm_connector *amdgpu_dm_connector =
4858                                 to_amdgpu_dm_connector(connector);
4859         int i;
4860         int n;
4861         struct mode_size {
4862                 char name[DRM_DISPLAY_MODE_LEN];
4863                 int w;
4864                 int h;
4865         } common_modes[] = {
4866                 {  "640x480",  640,  480},
4867                 {  "800x600",  800,  600},
4868                 { "1024x768", 1024,  768},
4869                 { "1280x720", 1280,  720},
4870                 { "1280x800", 1280,  800},
4871                 {"1280x1024", 1280, 1024},
4872                 { "1440x900", 1440,  900},
4873                 {"1680x1050", 1680, 1050},
4874                 {"1600x1200", 1600, 1200},
4875                 {"1920x1080", 1920, 1080},
4876                 {"1920x1200", 1920, 1200}
4877         };
4878
4879         n = ARRAY_SIZE(common_modes);
4880
4881         for (i = 0; i < n; i++) {
4882                 struct drm_display_mode *curmode = NULL;
4883                 bool mode_existed = false;
4884
4885                 if (common_modes[i].w > native_mode->hdisplay ||
4886                     common_modes[i].h > native_mode->vdisplay ||
4887                    (common_modes[i].w == native_mode->hdisplay &&
4888                     common_modes[i].h == native_mode->vdisplay))
4889                         continue;
4890
4891                 list_for_each_entry(curmode, &connector->probed_modes, head) {
4892                         if (common_modes[i].w == curmode->hdisplay &&
4893                             common_modes[i].h == curmode->vdisplay) {
4894                                 mode_existed = true;
4895                                 break;
4896                         }
4897                 }
4898
4899                 if (mode_existed)
4900                         continue;
4901
4902                 mode = amdgpu_dm_create_common_mode(encoder,
4903                                 common_modes[i].name, common_modes[i].w,
4904                                 common_modes[i].h);
4905                 drm_mode_probed_add(connector, mode);
4906                 amdgpu_dm_connector->num_modes++;
4907         }
4908 }
4909
4910 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
4911                                               struct edid *edid)
4912 {
4913         struct amdgpu_dm_connector *amdgpu_dm_connector =
4914                         to_amdgpu_dm_connector(connector);
4915
4916         if (edid) {
4917                 /* empty probed_modes */
4918                 INIT_LIST_HEAD(&connector->probed_modes);
4919                 amdgpu_dm_connector->num_modes =
4920                                 drm_add_edid_modes(connector, edid);
4921
4922                 /* sorting the probed modes before calling function
4923                  * amdgpu_dm_get_native_mode() since EDID can have
4924                  * more than one preferred mode. The modes that are
4925                  * later in the probed mode list could be of higher
4926                  * and preferred resolution. For example, 3840x2160
4927                  * resolution in base EDID preferred timing and 4096x2160
4928                  * preferred resolution in DID extension block later.
4929                  */
4930                 drm_mode_sort(&connector->probed_modes);
4931                 amdgpu_dm_get_native_mode(connector);
4932         } else {
4933                 amdgpu_dm_connector->num_modes = 0;
4934         }
4935 }
4936
4937 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
4938 {
4939         struct amdgpu_dm_connector *amdgpu_dm_connector =
4940                         to_amdgpu_dm_connector(connector);
4941         struct drm_encoder *encoder;
4942         struct edid *edid = amdgpu_dm_connector->edid;
4943
4944         encoder = amdgpu_dm_connector_to_encoder(connector);
4945
4946         if (!edid || !drm_edid_is_valid(edid)) {
4947                 amdgpu_dm_connector->num_modes =
4948                                 drm_add_modes_noedid(connector, 640, 480);
4949         } else {
4950                 amdgpu_dm_connector_ddc_get_modes(connector, edid);
4951                 amdgpu_dm_connector_add_common_modes(encoder, connector);
4952         }
4953         amdgpu_dm_fbc_init(connector);
4954
4955         return amdgpu_dm_connector->num_modes;
4956 }
4957
4958 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
4959                                      struct amdgpu_dm_connector *aconnector,
4960                                      int connector_type,
4961                                      struct dc_link *link,
4962                                      int link_index)
4963 {
4964         struct amdgpu_device *adev = dm->ddev->dev_private;
4965
4966         /*
4967          * Some of the properties below require access to state, like bpc.
4968          * Allocate some default initial connector state with our reset helper.
4969          */
4970         if (aconnector->base.funcs->reset)
4971                 aconnector->base.funcs->reset(&aconnector->base);
4972
4973         aconnector->connector_id = link_index;
4974         aconnector->dc_link = link;
4975         aconnector->base.interlace_allowed = false;
4976         aconnector->base.doublescan_allowed = false;
4977         aconnector->base.stereo_allowed = false;
4978         aconnector->base.dpms = DRM_MODE_DPMS_OFF;
4979         aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
4980         aconnector->audio_inst = -1;
4981         mutex_init(&aconnector->hpd_lock);
4982
4983         /*
4984          * configure support HPD hot plug connector_>polled default value is 0
4985          * which means HPD hot plug not supported
4986          */
4987         switch (connector_type) {
4988         case DRM_MODE_CONNECTOR_HDMIA:
4989                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
4990                 aconnector->base.ycbcr_420_allowed =
4991                         link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
4992                 break;
4993         case DRM_MODE_CONNECTOR_DisplayPort:
4994                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
4995                 aconnector->base.ycbcr_420_allowed =
4996                         link->link_enc->features.dp_ycbcr420_supported ? true : false;
4997                 break;
4998         case DRM_MODE_CONNECTOR_DVID:
4999                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
5000                 break;
5001         default:
5002                 break;
5003         }
5004
5005         drm_object_attach_property(&aconnector->base.base,
5006                                 dm->ddev->mode_config.scaling_mode_property,
5007                                 DRM_MODE_SCALE_NONE);
5008
5009         drm_object_attach_property(&aconnector->base.base,
5010                                 adev->mode_info.underscan_property,
5011                                 UNDERSCAN_OFF);
5012         drm_object_attach_property(&aconnector->base.base,
5013                                 adev->mode_info.underscan_hborder_property,
5014                                 0);
5015         drm_object_attach_property(&aconnector->base.base,
5016                                 adev->mode_info.underscan_vborder_property,
5017                                 0);
5018
5019         drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
5020
5021         /* This defaults to the max in the range, but we want 8bpc. */
5022         aconnector->base.state->max_bpc = 8;
5023         aconnector->base.state->max_requested_bpc = 8;
5024
5025         if (connector_type == DRM_MODE_CONNECTOR_eDP &&
5026             dc_is_dmcu_initialized(adev->dm.dc)) {
5027                 drm_object_attach_property(&aconnector->base.base,
5028                                 adev->mode_info.abm_level_property, 0);
5029         }
5030
5031         if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
5032             connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5033             connector_type == DRM_MODE_CONNECTOR_eDP) {
5034                 drm_object_attach_property(
5035                         &aconnector->base.base,
5036                         dm->ddev->mode_config.hdr_output_metadata_property, 0);
5037
5038                 drm_connector_attach_vrr_capable_property(
5039                         &aconnector->base);
5040         }
5041 }
5042
5043 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
5044                               struct i2c_msg *msgs, int num)
5045 {
5046         struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
5047         struct ddc_service *ddc_service = i2c->ddc_service;
5048         struct i2c_command cmd;
5049         int i;
5050         int result = -EIO;
5051
5052         cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
5053
5054         if (!cmd.payloads)
5055                 return result;
5056
5057         cmd.number_of_payloads = num;
5058         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
5059         cmd.speed = 100;
5060
5061         for (i = 0; i < num; i++) {
5062                 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
5063                 cmd.payloads[i].address = msgs[i].addr;
5064                 cmd.payloads[i].length = msgs[i].len;
5065                 cmd.payloads[i].data = msgs[i].buf;
5066         }
5067
5068         if (dc_submit_i2c(
5069                         ddc_service->ctx->dc,
5070                         ddc_service->ddc_pin->hw_info.ddc_channel,
5071                         &cmd))
5072                 result = num;
5073
5074         kfree(cmd.payloads);
5075         return result;
5076 }
5077
5078 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
5079 {
5080         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
5081 }
5082
5083 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
5084         .master_xfer = amdgpu_dm_i2c_xfer,
5085         .functionality = amdgpu_dm_i2c_func,
5086 };
5087
5088 static struct amdgpu_i2c_adapter *
5089 create_i2c(struct ddc_service *ddc_service,
5090            int link_index,
5091            int *res)
5092 {
5093         struct amdgpu_device *adev = ddc_service->ctx->driver_context;
5094         struct amdgpu_i2c_adapter *i2c;
5095
5096         i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
5097         if (!i2c)
5098                 return NULL;
5099         i2c->base.owner = THIS_MODULE;
5100         i2c->base.class = I2C_CLASS_DDC;
5101         i2c->base.dev.parent = &adev->pdev->dev;
5102         i2c->base.algo = &amdgpu_dm_i2c_algo;
5103         snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
5104         i2c_set_adapdata(&i2c->base, i2c);
5105         i2c->ddc_service = ddc_service;
5106         i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index;
5107
5108         return i2c;
5109 }
5110
5111
5112 /*
5113  * Note: this function assumes that dc_link_detect() was called for the
5114  * dc_link which will be represented by this aconnector.
5115  */
5116 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
5117                                     struct amdgpu_dm_connector *aconnector,
5118                                     uint32_t link_index,
5119                                     struct amdgpu_encoder *aencoder)
5120 {
5121         int res = 0;
5122         int connector_type;
5123         struct dc *dc = dm->dc;
5124         struct dc_link *link = dc_get_link_at_index(dc, link_index);
5125         struct amdgpu_i2c_adapter *i2c;
5126
5127         link->priv = aconnector;
5128
5129         DRM_DEBUG_DRIVER("%s()\n", __func__);
5130
5131         i2c = create_i2c(link->ddc, link->link_index, &res);
5132         if (!i2c) {
5133                 DRM_ERROR("Failed to create i2c adapter data\n");
5134                 return -ENOMEM;
5135         }
5136
5137         aconnector->i2c = i2c;
5138         res = i2c_add_adapter(&i2c->base);
5139
5140         if (res) {
5141                 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
5142                 goto out_free;
5143         }
5144
5145         connector_type = to_drm_connector_type(link->connector_signal);
5146
5147         res = drm_connector_init(
5148                         dm->ddev,
5149                         &aconnector->base,
5150                         &amdgpu_dm_connector_funcs,
5151                         connector_type);
5152
5153         if (res) {
5154                 DRM_ERROR("connector_init failed\n");
5155                 aconnector->connector_id = -1;
5156                 goto out_free;
5157         }
5158
5159         drm_connector_helper_add(
5160                         &aconnector->base,
5161                         &amdgpu_dm_connector_helper_funcs);
5162
5163         amdgpu_dm_connector_init_helper(
5164                 dm,
5165                 aconnector,
5166                 connector_type,
5167                 link,
5168                 link_index);
5169
5170         drm_connector_attach_encoder(
5171                 &aconnector->base, &aencoder->base);
5172
5173         drm_connector_register(&aconnector->base);
5174 #if defined(CONFIG_DEBUG_FS)
5175         connector_debugfs_init(aconnector);
5176         aconnector->debugfs_dpcd_address = 0;
5177         aconnector->debugfs_dpcd_size = 0;
5178 #endif
5179
5180         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
5181                 || connector_type == DRM_MODE_CONNECTOR_eDP)
5182                 amdgpu_dm_initialize_dp_connector(dm, aconnector);
5183
5184 out_free:
5185         if (res) {
5186                 kfree(i2c);
5187                 aconnector->i2c = NULL;
5188         }
5189         return res;
5190 }
5191
5192 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
5193 {
5194         switch (adev->mode_info.num_crtc) {
5195         case 1:
5196                 return 0x1;
5197         case 2:
5198                 return 0x3;
5199         case 3:
5200                 return 0x7;
5201         case 4:
5202                 return 0xf;
5203         case 5:
5204                 return 0x1f;
5205         case 6:
5206         default:
5207                 return 0x3f;
5208         }
5209 }
5210
5211 static int amdgpu_dm_encoder_init(struct drm_device *dev,
5212                                   struct amdgpu_encoder *aencoder,
5213                                   uint32_t link_index)
5214 {
5215         struct amdgpu_device *adev = dev->dev_private;
5216
5217         int res = drm_encoder_init(dev,
5218                                    &aencoder->base,
5219                                    &amdgpu_dm_encoder_funcs,
5220                                    DRM_MODE_ENCODER_TMDS,
5221                                    NULL);
5222
5223         aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
5224
5225         if (!res)
5226                 aencoder->encoder_id = link_index;
5227         else
5228                 aencoder->encoder_id = -1;
5229
5230         drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
5231
5232         return res;
5233 }
5234
5235 static void manage_dm_interrupts(struct amdgpu_device *adev,
5236                                  struct amdgpu_crtc *acrtc,
5237                                  bool enable)
5238 {
5239         /*
5240          * this is not correct translation but will work as soon as VBLANK
5241          * constant is the same as PFLIP
5242          */
5243         int irq_type =
5244                 amdgpu_display_crtc_idx_to_irq_type(
5245                         adev,
5246                         acrtc->crtc_id);
5247
5248         if (enable) {
5249                 drm_crtc_vblank_on(&acrtc->base);
5250                 amdgpu_irq_get(
5251                         adev,
5252                         &adev->pageflip_irq,
5253                         irq_type);
5254         } else {
5255
5256                 amdgpu_irq_put(
5257                         adev,
5258                         &adev->pageflip_irq,
5259                         irq_type);
5260                 drm_crtc_vblank_off(&acrtc->base);
5261         }
5262 }
5263
5264 static bool
5265 is_scaling_state_different(const struct dm_connector_state *dm_state,
5266                            const struct dm_connector_state *old_dm_state)
5267 {
5268         if (dm_state->scaling != old_dm_state->scaling)
5269                 return true;
5270         if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
5271                 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
5272                         return true;
5273         } else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
5274                 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
5275                         return true;
5276         } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
5277                    dm_state->underscan_vborder != old_dm_state->underscan_vborder)
5278                 return true;
5279         return false;
5280 }
5281
5282 static void remove_stream(struct amdgpu_device *adev,
5283                           struct amdgpu_crtc *acrtc,
5284                           struct dc_stream_state *stream)
5285 {
5286         /* this is the update mode case */
5287
5288         acrtc->otg_inst = -1;
5289         acrtc->enabled = false;
5290 }
5291
5292 static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
5293                                struct dc_cursor_position *position)
5294 {
5295         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
5296         int x, y;
5297         int xorigin = 0, yorigin = 0;
5298
5299         position->enable = false;
5300         position->x = 0;
5301         position->y = 0;
5302
5303         if (!crtc || !plane->state->fb)
5304                 return 0;
5305
5306         if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
5307             (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
5308                 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
5309                           __func__,
5310                           plane->state->crtc_w,
5311                           plane->state->crtc_h);
5312                 return -EINVAL;
5313         }
5314
5315         x = plane->state->crtc_x;
5316         y = plane->state->crtc_y;
5317
5318         if (x <= -amdgpu_crtc->max_cursor_width ||
5319             y <= -amdgpu_crtc->max_cursor_height)
5320                 return 0;
5321
5322         if (crtc->primary->state) {
5323                 /* avivo cursor are offset into the total surface */
5324                 x += crtc->primary->state->src_x >> 16;
5325                 y += crtc->primary->state->src_y >> 16;
5326         }
5327
5328         if (x < 0) {
5329                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
5330                 x = 0;
5331         }
5332         if (y < 0) {
5333                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
5334                 y = 0;
5335         }
5336         position->enable = true;
5337         position->x = x;
5338         position->y = y;
5339         position->x_hotspot = xorigin;
5340         position->y_hotspot = yorigin;
5341
5342         return 0;
5343 }
5344
5345 static void handle_cursor_update(struct drm_plane *plane,
5346                                  struct drm_plane_state *old_plane_state)
5347 {
5348         struct amdgpu_device *adev = plane->dev->dev_private;
5349         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
5350         struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
5351         struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
5352         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
5353         uint64_t address = afb ? afb->address : 0;
5354         struct dc_cursor_position position;
5355         struct dc_cursor_attributes attributes;
5356         int ret;
5357
5358         if (!plane->state->fb && !old_plane_state->fb)
5359                 return;
5360
5361         DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
5362                          __func__,
5363                          amdgpu_crtc->crtc_id,
5364                          plane->state->crtc_w,
5365                          plane->state->crtc_h);
5366
5367         ret = get_cursor_position(plane, crtc, &position);
5368         if (ret)
5369                 return;
5370
5371         if (!position.enable) {
5372                 /* turn off cursor */
5373                 if (crtc_state && crtc_state->stream) {
5374                         mutex_lock(&adev->dm.dc_lock);
5375                         dc_stream_set_cursor_position(crtc_state->stream,
5376                                                       &position);
5377                         mutex_unlock(&adev->dm.dc_lock);
5378                 }
5379                 return;
5380         }
5381
5382         amdgpu_crtc->cursor_width = plane->state->crtc_w;
5383         amdgpu_crtc->cursor_height = plane->state->crtc_h;
5384
5385         memset(&attributes, 0, sizeof(attributes));
5386         attributes.address.high_part = upper_32_bits(address);
5387         attributes.address.low_part  = lower_32_bits(address);
5388         attributes.width             = plane->state->crtc_w;
5389         attributes.height            = plane->state->crtc_h;
5390         attributes.color_format      = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
5391         attributes.rotation_angle    = 0;
5392         attributes.attribute_flags.value = 0;
5393
5394         attributes.pitch = attributes.width;
5395
5396         if (crtc_state->stream) {
5397                 mutex_lock(&adev->dm.dc_lock);
5398                 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
5399                                                          &attributes))
5400                         DRM_ERROR("DC failed to set cursor attributes\n");
5401
5402                 if (!dc_stream_set_cursor_position(crtc_state->stream,
5403                                                    &position))
5404                         DRM_ERROR("DC failed to set cursor position\n");
5405                 mutex_unlock(&adev->dm.dc_lock);
5406         }
5407 }
5408
5409 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
5410 {
5411
5412         assert_spin_locked(&acrtc->base.dev->event_lock);
5413         WARN_ON(acrtc->event);
5414
5415         acrtc->event = acrtc->base.state->event;
5416
5417         /* Set the flip status */
5418         acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
5419
5420         /* Mark this event as consumed */
5421         acrtc->base.state->event = NULL;
5422
5423         DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
5424                                                  acrtc->crtc_id);
5425 }
5426
5427 static void update_freesync_state_on_stream(
5428         struct amdgpu_display_manager *dm,
5429         struct dm_crtc_state *new_crtc_state,
5430         struct dc_stream_state *new_stream,
5431         struct dc_plane_state *surface,
5432         u32 flip_timestamp_in_us)
5433 {
5434         struct mod_vrr_params vrr_params;
5435         struct dc_info_packet vrr_infopacket = {0};
5436         struct amdgpu_device *adev = dm->adev;
5437         unsigned long flags;
5438
5439         if (!new_stream)
5440                 return;
5441
5442         /*
5443          * TODO: Determine why min/max totals and vrefresh can be 0 here.
5444          * For now it's sufficient to just guard against these conditions.
5445          */
5446
5447         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
5448                 return;
5449
5450         spin_lock_irqsave(&adev->ddev->event_lock, flags);
5451         vrr_params = new_crtc_state->vrr_params;
5452
5453         if (surface) {
5454                 mod_freesync_handle_preflip(
5455                         dm->freesync_module,
5456                         surface,
5457                         new_stream,
5458                         flip_timestamp_in_us,
5459                         &vrr_params);
5460
5461                 if (adev->family < AMDGPU_FAMILY_AI &&
5462                     amdgpu_dm_vrr_active(new_crtc_state)) {
5463                         mod_freesync_handle_v_update(dm->freesync_module,
5464                                                      new_stream, &vrr_params);
5465
5466                         /* Need to call this before the frame ends. */
5467                         dc_stream_adjust_vmin_vmax(dm->dc,
5468                                                    new_crtc_state->stream,
5469                                                    &vrr_params.adjust);
5470                 }
5471         }
5472
5473         mod_freesync_build_vrr_infopacket(
5474                 dm->freesync_module,
5475                 new_stream,
5476                 &vrr_params,
5477                 PACKET_TYPE_VRR,
5478                 TRANSFER_FUNC_UNKNOWN,
5479                 &vrr_infopacket);
5480
5481         new_crtc_state->freesync_timing_changed |=
5482                 (memcmp(&new_crtc_state->vrr_params.adjust,
5483                         &vrr_params.adjust,
5484                         sizeof(vrr_params.adjust)) != 0);
5485
5486         new_crtc_state->freesync_vrr_info_changed |=
5487                 (memcmp(&new_crtc_state->vrr_infopacket,
5488                         &vrr_infopacket,
5489                         sizeof(vrr_infopacket)) != 0);
5490
5491         new_crtc_state->vrr_params = vrr_params;
5492         new_crtc_state->vrr_infopacket = vrr_infopacket;
5493
5494         new_stream->adjust = new_crtc_state->vrr_params.adjust;
5495         new_stream->vrr_infopacket = vrr_infopacket;
5496
5497         if (new_crtc_state->freesync_vrr_info_changed)
5498                 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
5499                               new_crtc_state->base.crtc->base.id,
5500                               (int)new_crtc_state->base.vrr_enabled,
5501                               (int)vrr_params.state);
5502
5503         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
5504 }
5505
5506 static void pre_update_freesync_state_on_stream(
5507         struct amdgpu_display_manager *dm,
5508         struct dm_crtc_state *new_crtc_state)
5509 {
5510         struct dc_stream_state *new_stream = new_crtc_state->stream;
5511         struct mod_vrr_params vrr_params;
5512         struct mod_freesync_config config = new_crtc_state->freesync_config;
5513         struct amdgpu_device *adev = dm->adev;
5514         unsigned long flags;
5515
5516         if (!new_stream)
5517                 return;
5518
5519         /*
5520          * TODO: Determine why min/max totals and vrefresh can be 0 here.
5521          * For now it's sufficient to just guard against these conditions.
5522          */
5523         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
5524                 return;
5525
5526         spin_lock_irqsave(&adev->ddev->event_lock, flags);
5527         vrr_params = new_crtc_state->vrr_params;
5528
5529         if (new_crtc_state->vrr_supported &&
5530             config.min_refresh_in_uhz &&
5531             config.max_refresh_in_uhz) {
5532                 config.state = new_crtc_state->base.vrr_enabled ?
5533                         VRR_STATE_ACTIVE_VARIABLE :
5534                         VRR_STATE_INACTIVE;
5535         } else {
5536                 config.state = VRR_STATE_UNSUPPORTED;
5537         }
5538
5539         mod_freesync_build_vrr_params(dm->freesync_module,
5540                                       new_stream,
5541                                       &config, &vrr_params);
5542
5543         new_crtc_state->freesync_timing_changed |=
5544                 (memcmp(&new_crtc_state->vrr_params.adjust,
5545                         &vrr_params.adjust,
5546                         sizeof(vrr_params.adjust)) != 0);
5547
5548         new_crtc_state->vrr_params = vrr_params;
5549         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
5550 }
5551
5552 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
5553                                             struct dm_crtc_state *new_state)
5554 {
5555         bool old_vrr_active = amdgpu_dm_vrr_active(old_state);
5556         bool new_vrr_active = amdgpu_dm_vrr_active(new_state);
5557
5558         if (!old_vrr_active && new_vrr_active) {
5559                 /* Transition VRR inactive -> active:
5560                  * While VRR is active, we must not disable vblank irq, as a
5561                  * reenable after disable would compute bogus vblank/pflip
5562                  * timestamps if it likely happened inside display front-porch.
5563                  *
5564                  * We also need vupdate irq for the actual core vblank handling
5565                  * at end of vblank.
5566                  */
5567                 dm_set_vupdate_irq(new_state->base.crtc, true);
5568                 drm_crtc_vblank_get(new_state->base.crtc);
5569                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
5570                                  __func__, new_state->base.crtc->base.id);
5571         } else if (old_vrr_active && !new_vrr_active) {
5572                 /* Transition VRR active -> inactive:
5573                  * Allow vblank irq disable again for fixed refresh rate.
5574                  */
5575                 dm_set_vupdate_irq(new_state->base.crtc, false);
5576                 drm_crtc_vblank_put(new_state->base.crtc);
5577                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
5578                                  __func__, new_state->base.crtc->base.id);
5579         }
5580 }
5581
5582 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
5583 {
5584         struct drm_plane *plane;
5585         struct drm_plane_state *old_plane_state, *new_plane_state;
5586         int i;
5587
5588         /*
5589          * TODO: Make this per-stream so we don't issue redundant updates for
5590          * commits with multiple streams.
5591          */
5592         for_each_oldnew_plane_in_state(state, plane, old_plane_state,
5593                                        new_plane_state, i)
5594                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5595                         handle_cursor_update(plane, old_plane_state);
5596 }
5597
5598 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
5599                                     struct dc_state *dc_state,
5600                                     struct drm_device *dev,
5601                                     struct amdgpu_display_manager *dm,
5602                                     struct drm_crtc *pcrtc,
5603                                     bool wait_for_vblank)
5604 {
5605         uint32_t i;
5606         uint64_t timestamp_ns;
5607         struct drm_plane *plane;
5608         struct drm_plane_state *old_plane_state, *new_plane_state;
5609         struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
5610         struct drm_crtc_state *new_pcrtc_state =
5611                         drm_atomic_get_new_crtc_state(state, pcrtc);
5612         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
5613         struct dm_crtc_state *dm_old_crtc_state =
5614                         to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
5615         int planes_count = 0, vpos, hpos;
5616         long r;
5617         unsigned long flags;
5618         struct amdgpu_bo *abo;
5619         uint64_t tiling_flags;
5620         uint32_t target_vblank, last_flip_vblank;
5621         bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
5622         bool pflip_present = false;
5623         struct {
5624                 struct dc_surface_update surface_updates[MAX_SURFACES];
5625                 struct dc_plane_info plane_infos[MAX_SURFACES];
5626                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
5627                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
5628                 struct dc_stream_update stream_update;
5629         } *bundle;
5630
5631         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
5632
5633         if (!bundle) {
5634                 dm_error("Failed to allocate update bundle\n");
5635                 goto cleanup;
5636         }
5637
5638         /*
5639          * Disable the cursor first if we're disabling all the planes.
5640          * It'll remain on the screen after the planes are re-enabled
5641          * if we don't.
5642          */
5643         if (acrtc_state->active_planes == 0)
5644                 amdgpu_dm_commit_cursors(state);
5645
5646         /* update planes when needed */
5647         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
5648                 struct drm_crtc *crtc = new_plane_state->crtc;
5649                 struct drm_crtc_state *new_crtc_state;
5650                 struct drm_framebuffer *fb = new_plane_state->fb;
5651                 bool plane_needs_flip;
5652                 struct dc_plane_state *dc_plane;
5653                 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
5654
5655                 /* Cursor plane is handled after stream updates */
5656                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5657                         continue;
5658
5659                 if (!fb || !crtc || pcrtc != crtc)
5660                         continue;
5661
5662                 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
5663                 if (!new_crtc_state->active)
5664                         continue;
5665
5666                 dc_plane = dm_new_plane_state->dc_state;
5667
5668                 bundle->surface_updates[planes_count].surface = dc_plane;
5669                 if (new_pcrtc_state->color_mgmt_changed) {
5670                         bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
5671                         bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
5672                 }
5673
5674                 fill_dc_scaling_info(new_plane_state,
5675                                      &bundle->scaling_infos[planes_count]);
5676
5677                 bundle->surface_updates[planes_count].scaling_info =
5678                         &bundle->scaling_infos[planes_count];
5679
5680                 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
5681
5682                 pflip_present = pflip_present || plane_needs_flip;
5683
5684                 if (!plane_needs_flip) {
5685                         planes_count += 1;
5686                         continue;
5687                 }
5688
5689                 abo = gem_to_amdgpu_bo(fb->obj[0]);
5690
5691                 /*
5692                  * Wait for all fences on this FB. Do limited wait to avoid
5693                  * deadlock during GPU reset when this fence will not signal
5694                  * but we hold reservation lock for the BO.
5695                  */
5696                 r = reservation_object_wait_timeout_rcu(abo->tbo.resv, true,
5697                                                         false,
5698                                                         msecs_to_jiffies(5000));
5699                 if (unlikely(r <= 0))
5700                         DRM_ERROR("Waiting for fences timed out or interrupted!");
5701
5702                 /*
5703                  * TODO This might fail and hence better not used, wait
5704                  * explicitly on fences instead
5705                  * and in general should be called for
5706                  * blocking commit to as per framework helpers
5707                  */
5708                 r = amdgpu_bo_reserve(abo, true);
5709                 if (unlikely(r != 0))
5710                         DRM_ERROR("failed to reserve buffer before flip\n");
5711
5712                 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
5713
5714                 amdgpu_bo_unreserve(abo);
5715
5716                 fill_dc_plane_info_and_addr(
5717                         dm->adev, new_plane_state, tiling_flags,
5718                         &bundle->plane_infos[planes_count],
5719                         &bundle->flip_addrs[planes_count].address);
5720
5721                 bundle->surface_updates[planes_count].plane_info =
5722                         &bundle->plane_infos[planes_count];
5723
5724                 bundle->flip_addrs[planes_count].flip_immediate =
5725                                 (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
5726
5727                 timestamp_ns = ktime_get_ns();
5728                 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
5729                 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
5730                 bundle->surface_updates[planes_count].surface = dc_plane;
5731
5732                 if (!bundle->surface_updates[planes_count].surface) {
5733                         DRM_ERROR("No surface for CRTC: id=%d\n",
5734                                         acrtc_attach->crtc_id);
5735                         continue;
5736                 }
5737
5738                 if (plane == pcrtc->primary)
5739                         update_freesync_state_on_stream(
5740                                 dm,
5741                                 acrtc_state,
5742                                 acrtc_state->stream,
5743                                 dc_plane,
5744                                 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
5745
5746                 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x\n",
5747                                  __func__,
5748                                  bundle->flip_addrs[planes_count].address.grph.addr.high_part,
5749                                  bundle->flip_addrs[planes_count].address.grph.addr.low_part);
5750
5751                 planes_count += 1;
5752
5753         }
5754
5755         if (pflip_present) {
5756                 if (!vrr_active) {
5757                         /* Use old throttling in non-vrr fixed refresh rate mode
5758                          * to keep flip scheduling based on target vblank counts
5759                          * working in a backwards compatible way, e.g., for
5760                          * clients using the GLX_OML_sync_control extension or
5761                          * DRI3/Present extension with defined target_msc.
5762                          */
5763                         last_flip_vblank = amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id);
5764                 }
5765                 else {
5766                         /* For variable refresh rate mode only:
5767                          * Get vblank of last completed flip to avoid > 1 vrr
5768                          * flips per video frame by use of throttling, but allow
5769                          * flip programming anywhere in the possibly large
5770                          * variable vrr vblank interval for fine-grained flip
5771                          * timing control and more opportunity to avoid stutter
5772                          * on late submission of flips.
5773                          */
5774                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
5775                         last_flip_vblank = acrtc_attach->last_flip_vblank;
5776                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
5777                 }
5778
5779                 target_vblank = last_flip_vblank + wait_for_vblank;
5780
5781                 /*
5782                  * Wait until we're out of the vertical blank period before the one
5783                  * targeted by the flip
5784                  */
5785                 while ((acrtc_attach->enabled &&
5786                         (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
5787                                                             0, &vpos, &hpos, NULL,
5788                                                             NULL, &pcrtc->hwmode)
5789                          & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
5790                         (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
5791                         (int)(target_vblank -
5792                           amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id)) > 0)) {
5793                         usleep_range(1000, 1100);
5794                 }
5795
5796                 if (acrtc_attach->base.state->event) {
5797                         drm_crtc_vblank_get(pcrtc);
5798
5799                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
5800
5801                         WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
5802                         prepare_flip_isr(acrtc_attach);
5803
5804                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
5805                 }
5806
5807                 if (acrtc_state->stream) {
5808                         if (acrtc_state->freesync_vrr_info_changed)
5809                                 bundle->stream_update.vrr_infopacket =
5810                                         &acrtc_state->stream->vrr_infopacket;
5811                 }
5812         }
5813
5814         /* Update the planes if changed or disable if we don't have any. */
5815         if ((planes_count || acrtc_state->active_planes == 0) &&
5816                 acrtc_state->stream) {
5817                 if (new_pcrtc_state->mode_changed) {
5818                         bundle->stream_update.src = acrtc_state->stream->src;
5819                         bundle->stream_update.dst = acrtc_state->stream->dst;
5820                 }
5821
5822                 if (new_pcrtc_state->color_mgmt_changed) {
5823                         /*
5824                          * TODO: This isn't fully correct since we've actually
5825                          * already modified the stream in place.
5826                          */
5827                         bundle->stream_update.gamut_remap =
5828                                 &acrtc_state->stream->gamut_remap_matrix;
5829                         bundle->stream_update.output_csc_transform =
5830                                 &acrtc_state->stream->csc_color_matrix;
5831                         bundle->stream_update.out_transfer_func =
5832                                 acrtc_state->stream->out_transfer_func;
5833                 }
5834
5835                 acrtc_state->stream->abm_level = acrtc_state->abm_level;
5836                 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
5837                         bundle->stream_update.abm_level = &acrtc_state->abm_level;
5838
5839                 /*
5840                  * If FreeSync state on the stream has changed then we need to
5841                  * re-adjust the min/max bounds now that DC doesn't handle this
5842                  * as part of commit.
5843                  */
5844                 if (amdgpu_dm_vrr_active(dm_old_crtc_state) !=
5845                     amdgpu_dm_vrr_active(acrtc_state)) {
5846                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
5847                         dc_stream_adjust_vmin_vmax(
5848                                 dm->dc, acrtc_state->stream,
5849                                 &acrtc_state->vrr_params.adjust);
5850                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
5851                 }
5852
5853                 mutex_lock(&dm->dc_lock);
5854                 dc_commit_updates_for_stream(dm->dc,
5855                                                      bundle->surface_updates,
5856                                                      planes_count,
5857                                                      acrtc_state->stream,
5858                                                      &bundle->stream_update,
5859                                                      dc_state);
5860                 mutex_unlock(&dm->dc_lock);
5861         }
5862
5863         /*
5864          * Update cursor state *after* programming all the planes.
5865          * This avoids redundant programming in the case where we're going
5866          * to be disabling a single plane - those pipes are being disabled.
5867          */
5868         if (acrtc_state->active_planes)
5869                 amdgpu_dm_commit_cursors(state);
5870
5871 cleanup:
5872         kfree(bundle);
5873 }
5874
5875 static void amdgpu_dm_commit_audio(struct drm_device *dev,
5876                                    struct drm_atomic_state *state)
5877 {
5878         struct amdgpu_device *adev = dev->dev_private;
5879         struct amdgpu_dm_connector *aconnector;
5880         struct drm_connector *connector;
5881         struct drm_connector_state *old_con_state, *new_con_state;
5882         struct drm_crtc_state *new_crtc_state;
5883         struct dm_crtc_state *new_dm_crtc_state;
5884         const struct dc_stream_status *status;
5885         int i, inst;
5886
5887         /* Notify device removals. */
5888         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
5889                 if (old_con_state->crtc != new_con_state->crtc) {
5890                         /* CRTC changes require notification. */
5891                         goto notify;
5892                 }
5893
5894                 if (!new_con_state->crtc)
5895                         continue;
5896
5897                 new_crtc_state = drm_atomic_get_new_crtc_state(
5898                         state, new_con_state->crtc);
5899
5900                 if (!new_crtc_state)
5901                         continue;
5902
5903                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
5904                         continue;
5905
5906         notify:
5907                 aconnector = to_amdgpu_dm_connector(connector);
5908
5909                 mutex_lock(&adev->dm.audio_lock);
5910                 inst = aconnector->audio_inst;
5911                 aconnector->audio_inst = -1;
5912                 mutex_unlock(&adev->dm.audio_lock);
5913
5914                 amdgpu_dm_audio_eld_notify(adev, inst);
5915         }
5916
5917         /* Notify audio device additions. */
5918         for_each_new_connector_in_state(state, connector, new_con_state, i) {
5919                 if (!new_con_state->crtc)
5920                         continue;
5921
5922                 new_crtc_state = drm_atomic_get_new_crtc_state(
5923                         state, new_con_state->crtc);
5924
5925                 if (!new_crtc_state)
5926                         continue;
5927
5928                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
5929                         continue;
5930
5931                 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
5932                 if (!new_dm_crtc_state->stream)
5933                         continue;
5934
5935                 status = dc_stream_get_status(new_dm_crtc_state->stream);
5936                 if (!status)
5937                         continue;
5938
5939                 aconnector = to_amdgpu_dm_connector(connector);
5940
5941                 mutex_lock(&adev->dm.audio_lock);
5942                 inst = status->audio_inst;
5943                 aconnector->audio_inst = inst;
5944                 mutex_unlock(&adev->dm.audio_lock);
5945
5946                 amdgpu_dm_audio_eld_notify(adev, inst);
5947         }
5948 }
5949
5950 /*
5951  * Enable interrupts on CRTCs that are newly active, undergone
5952  * a modeset, or have active planes again.
5953  *
5954  * Done in two passes, based on the for_modeset flag:
5955  * Pass 1: For CRTCs going through modeset
5956  * Pass 2: For CRTCs going from 0 to n active planes
5957  *
5958  * Interrupts can only be enabled after the planes are programmed,
5959  * so this requires a two-pass approach since we don't want to
5960  * just defer the interrupts until after commit planes every time.
5961  */
5962 static void amdgpu_dm_enable_crtc_interrupts(struct drm_device *dev,
5963                                              struct drm_atomic_state *state,
5964                                              bool for_modeset)
5965 {
5966         struct amdgpu_device *adev = dev->dev_private;
5967         struct drm_crtc *crtc;
5968         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
5969         int i;
5970
5971         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
5972                                       new_crtc_state, i) {
5973                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
5974                 struct dm_crtc_state *dm_new_crtc_state =
5975                         to_dm_crtc_state(new_crtc_state);
5976                 struct dm_crtc_state *dm_old_crtc_state =
5977                         to_dm_crtc_state(old_crtc_state);
5978                 bool modeset = drm_atomic_crtc_needs_modeset(new_crtc_state);
5979                 bool run_pass;
5980
5981                 run_pass = (for_modeset && modeset) ||
5982                            (!for_modeset && !modeset &&
5983                             !dm_old_crtc_state->interrupts_enabled);
5984
5985                 if (!run_pass)
5986                         continue;
5987
5988                 if (!dm_new_crtc_state->interrupts_enabled)
5989                         continue;
5990
5991                 manage_dm_interrupts(adev, acrtc, true);
5992
5993 #ifdef CONFIG_DEBUG_FS
5994                 /* The stream has changed so CRC capture needs to re-enabled. */
5995                 if (dm_new_crtc_state->crc_enabled) {
5996                         dm_new_crtc_state->crc_enabled = false;
5997                         amdgpu_dm_crtc_set_crc_source(crtc, "auto");
5998                 }
5999 #endif
6000         }
6001 }
6002
6003 /*
6004  * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
6005  * @crtc_state: the DRM CRTC state
6006  * @stream_state: the DC stream state.
6007  *
6008  * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
6009  * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
6010  */
6011 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
6012                                                 struct dc_stream_state *stream_state)
6013 {
6014         stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
6015 }
6016
6017 static int amdgpu_dm_atomic_commit(struct drm_device *dev,
6018                                    struct drm_atomic_state *state,
6019                                    bool nonblock)
6020 {
6021         struct drm_crtc *crtc;
6022         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
6023         struct amdgpu_device *adev = dev->dev_private;
6024         int i;
6025
6026         /*
6027          * We evade vblank and pflip interrupts on CRTCs that are undergoing
6028          * a modeset, being disabled, or have no active planes.
6029          *
6030          * It's done in atomic commit rather than commit tail for now since
6031          * some of these interrupt handlers access the current CRTC state and
6032          * potentially the stream pointer itself.
6033          *
6034          * Since the atomic state is swapped within atomic commit and not within
6035          * commit tail this would leave to new state (that hasn't been committed yet)
6036          * being accesssed from within the handlers.
6037          *
6038          * TODO: Fix this so we can do this in commit tail and not have to block
6039          * in atomic check.
6040          */
6041         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6042                 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
6043                 struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6044                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
6045
6046                 if (dm_old_crtc_state->interrupts_enabled &&
6047                     (!dm_new_crtc_state->interrupts_enabled ||
6048                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
6049                         /*
6050                          * Drop the extra vblank reference added by CRC
6051                          * capture if applicable.
6052                          */
6053                         if (dm_new_crtc_state->crc_enabled)
6054                                 drm_crtc_vblank_put(crtc);
6055
6056                         /*
6057                          * Only keep CRC capture enabled if there's
6058                          * still a stream for the CRTC.
6059                          */
6060                         if (!dm_new_crtc_state->stream)
6061                                 dm_new_crtc_state->crc_enabled = false;
6062
6063                         manage_dm_interrupts(adev, acrtc, false);
6064                 }
6065         }
6066         /*
6067          * Add check here for SoC's that support hardware cursor plane, to
6068          * unset legacy_cursor_update
6069          */
6070
6071         return drm_atomic_helper_commit(dev, state, nonblock);
6072
6073         /*TODO Handle EINTR, reenable IRQ*/
6074 }
6075
6076 /**
6077  * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
6078  * @state: The atomic state to commit
6079  *
6080  * This will tell DC to commit the constructed DC state from atomic_check,
6081  * programming the hardware. Any failures here implies a hardware failure, since
6082  * atomic check should have filtered anything non-kosher.
6083  */
6084 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
6085 {
6086         struct drm_device *dev = state->dev;
6087         struct amdgpu_device *adev = dev->dev_private;
6088         struct amdgpu_display_manager *dm = &adev->dm;
6089         struct dm_atomic_state *dm_state;
6090         struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
6091         uint32_t i, j;
6092         struct drm_crtc *crtc;
6093         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
6094         unsigned long flags;
6095         bool wait_for_vblank = true;
6096         struct drm_connector *connector;
6097         struct drm_connector_state *old_con_state, *new_con_state;
6098         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
6099         int crtc_disable_count = 0;
6100
6101         drm_atomic_helper_update_legacy_modeset_state(dev, state);
6102
6103         dm_state = dm_atomic_get_new_state(state);
6104         if (dm_state && dm_state->context) {
6105                 dc_state = dm_state->context;
6106         } else {
6107                 /* No state changes, retain current state. */
6108                 dc_state_temp = dc_create_state(dm->dc);
6109                 ASSERT(dc_state_temp);
6110                 dc_state = dc_state_temp;
6111                 dc_resource_state_copy_construct_current(dm->dc, dc_state);
6112         }
6113
6114         /* update changed items */
6115         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6116                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
6117
6118                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6119                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
6120
6121                 DRM_DEBUG_DRIVER(
6122                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
6123                         "planes_changed:%d, mode_changed:%d,active_changed:%d,"
6124                         "connectors_changed:%d\n",
6125                         acrtc->crtc_id,
6126                         new_crtc_state->enable,
6127                         new_crtc_state->active,
6128                         new_crtc_state->planes_changed,
6129                         new_crtc_state->mode_changed,
6130                         new_crtc_state->active_changed,
6131                         new_crtc_state->connectors_changed);
6132
6133                 /* Copy all transient state flags into dc state */
6134                 if (dm_new_crtc_state->stream) {
6135                         amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
6136                                                             dm_new_crtc_state->stream);
6137                 }
6138
6139                 /* handles headless hotplug case, updating new_state and
6140                  * aconnector as needed
6141                  */
6142
6143                 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
6144
6145                         DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
6146
6147                         if (!dm_new_crtc_state->stream) {
6148                                 /*
6149                                  * this could happen because of issues with
6150                                  * userspace notifications delivery.
6151                                  * In this case userspace tries to set mode on
6152                                  * display which is disconnected in fact.
6153                                  * dc_sink is NULL in this case on aconnector.
6154                                  * We expect reset mode will come soon.
6155                                  *
6156                                  * This can also happen when unplug is done
6157                                  * during resume sequence ended
6158                                  *
6159                                  * In this case, we want to pretend we still
6160                                  * have a sink to keep the pipe running so that
6161                                  * hw state is consistent with the sw state
6162                                  */
6163                                 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
6164                                                 __func__, acrtc->base.base.id);
6165                                 continue;
6166                         }
6167
6168                         if (dm_old_crtc_state->stream)
6169                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
6170
6171                         pm_runtime_get_noresume(dev->dev);
6172
6173                         acrtc->enabled = true;
6174                         acrtc->hw_mode = new_crtc_state->mode;
6175                         crtc->hwmode = new_crtc_state->mode;
6176                 } else if (modereset_required(new_crtc_state)) {
6177                         DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
6178
6179                         /* i.e. reset mode */
6180                         if (dm_old_crtc_state->stream)
6181                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
6182                 }
6183         } /* for_each_crtc_in_state() */
6184
6185         if (dc_state) {
6186                 dm_enable_per_frame_crtc_master_sync(dc_state);
6187                 mutex_lock(&dm->dc_lock);
6188                 WARN_ON(!dc_commit_state(dm->dc, dc_state));
6189                 mutex_unlock(&dm->dc_lock);
6190         }
6191
6192         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
6193                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
6194
6195                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6196
6197                 if (dm_new_crtc_state->stream != NULL) {
6198                         const struct dc_stream_status *status =
6199                                         dc_stream_get_status(dm_new_crtc_state->stream);
6200
6201                         if (!status)
6202                                 status = dc_stream_get_status_from_state(dc_state,
6203                                                                          dm_new_crtc_state->stream);
6204
6205                         if (!status)
6206                                 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
6207                         else
6208                                 acrtc->otg_inst = status->primary_otg_inst;
6209                 }
6210         }
6211
6212         /* Handle connector state changes */
6213         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
6214                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
6215                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
6216                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
6217                 struct dc_surface_update dummy_updates[MAX_SURFACES];
6218                 struct dc_stream_update stream_update;
6219                 struct dc_info_packet hdr_packet;
6220                 struct dc_stream_status *status = NULL;
6221                 bool abm_changed, hdr_changed, scaling_changed;
6222
6223                 memset(&dummy_updates, 0, sizeof(dummy_updates));
6224                 memset(&stream_update, 0, sizeof(stream_update));
6225
6226                 if (acrtc) {
6227                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
6228                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
6229                 }
6230
6231                 /* Skip any modesets/resets */
6232                 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
6233                         continue;
6234
6235                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6236                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
6237
6238                 scaling_changed = is_scaling_state_different(dm_new_con_state,
6239                                                              dm_old_con_state);
6240
6241                 abm_changed = dm_new_crtc_state->abm_level !=
6242                               dm_old_crtc_state->abm_level;
6243
6244                 hdr_changed =
6245                         is_hdr_metadata_different(old_con_state, new_con_state);
6246
6247                 if (!scaling_changed && !abm_changed && !hdr_changed)
6248                         continue;
6249
6250                 if (scaling_changed) {
6251                         update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
6252                                         dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
6253
6254                         stream_update.src = dm_new_crtc_state->stream->src;
6255                         stream_update.dst = dm_new_crtc_state->stream->dst;
6256                 }
6257
6258                 if (abm_changed) {
6259                         dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
6260
6261                         stream_update.abm_level = &dm_new_crtc_state->abm_level;
6262                 }
6263
6264                 if (hdr_changed) {
6265                         fill_hdr_info_packet(new_con_state, &hdr_packet);
6266                         stream_update.hdr_static_metadata = &hdr_packet;
6267                 }
6268
6269                 status = dc_stream_get_status(dm_new_crtc_state->stream);
6270                 WARN_ON(!status);
6271                 WARN_ON(!status->plane_count);
6272
6273                 /*
6274                  * TODO: DC refuses to perform stream updates without a dc_surface_update.
6275                  * Here we create an empty update on each plane.
6276                  * To fix this, DC should permit updating only stream properties.
6277                  */
6278                 for (j = 0; j < status->plane_count; j++)
6279                         dummy_updates[j].surface = status->plane_states[0];
6280
6281
6282                 mutex_lock(&dm->dc_lock);
6283                 dc_commit_updates_for_stream(dm->dc,
6284                                                      dummy_updates,
6285                                                      status->plane_count,
6286                                                      dm_new_crtc_state->stream,
6287                                                      &stream_update,
6288                                                      dc_state);
6289                 mutex_unlock(&dm->dc_lock);
6290         }
6291
6292         /* Count number of newly disabled CRTCs for dropping PM refs later. */
6293         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
6294                                       new_crtc_state, i) {
6295                 if (old_crtc_state->active && !new_crtc_state->active)
6296                         crtc_disable_count++;
6297
6298                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6299                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
6300
6301                 /* Update freesync active state. */
6302                 pre_update_freesync_state_on_stream(dm, dm_new_crtc_state);
6303
6304                 /* Handle vrr on->off / off->on transitions */
6305                 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state,
6306                                                 dm_new_crtc_state);
6307         }
6308
6309         /* Enable interrupts for CRTCs going through a modeset. */
6310         amdgpu_dm_enable_crtc_interrupts(dev, state, true);
6311
6312         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
6313                 if (new_crtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC)
6314                         wait_for_vblank = false;
6315
6316         /* update planes when needed per crtc*/
6317         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
6318                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6319
6320                 if (dm_new_crtc_state->stream)
6321                         amdgpu_dm_commit_planes(state, dc_state, dev,
6322                                                 dm, crtc, wait_for_vblank);
6323         }
6324
6325         /* Enable interrupts for CRTCs going from 0 to n active planes. */
6326         amdgpu_dm_enable_crtc_interrupts(dev, state, false);
6327
6328         /* Update audio instances for each connector. */
6329         amdgpu_dm_commit_audio(dev, state);
6330
6331         /*
6332          * send vblank event on all events not handled in flip and
6333          * mark consumed event for drm_atomic_helper_commit_hw_done
6334          */
6335         spin_lock_irqsave(&adev->ddev->event_lock, flags);
6336         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
6337
6338                 if (new_crtc_state->event)
6339                         drm_send_event_locked(dev, &new_crtc_state->event->base);
6340
6341                 new_crtc_state->event = NULL;
6342         }
6343         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
6344
6345         /* Signal HW programming completion */
6346         drm_atomic_helper_commit_hw_done(state);
6347
6348         if (wait_for_vblank)
6349                 drm_atomic_helper_wait_for_flip_done(dev, state);
6350
6351         drm_atomic_helper_cleanup_planes(dev, state);
6352
6353         /*
6354          * Finally, drop a runtime PM reference for each newly disabled CRTC,
6355          * so we can put the GPU into runtime suspend if we're not driving any
6356          * displays anymore
6357          */
6358         for (i = 0; i < crtc_disable_count; i++)
6359                 pm_runtime_put_autosuspend(dev->dev);
6360         pm_runtime_mark_last_busy(dev->dev);
6361
6362         if (dc_state_temp)
6363                 dc_release_state(dc_state_temp);
6364 }
6365
6366
6367 static int dm_force_atomic_commit(struct drm_connector *connector)
6368 {
6369         int ret = 0;
6370         struct drm_device *ddev = connector->dev;
6371         struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
6372         struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
6373         struct drm_plane *plane = disconnected_acrtc->base.primary;
6374         struct drm_connector_state *conn_state;
6375         struct drm_crtc_state *crtc_state;
6376         struct drm_plane_state *plane_state;
6377
6378         if (!state)
6379                 return -ENOMEM;
6380
6381         state->acquire_ctx = ddev->mode_config.acquire_ctx;
6382
6383         /* Construct an atomic state to restore previous display setting */
6384
6385         /*
6386          * Attach connectors to drm_atomic_state
6387          */
6388         conn_state = drm_atomic_get_connector_state(state, connector);
6389
6390         ret = PTR_ERR_OR_ZERO(conn_state);
6391         if (ret)
6392                 goto err;
6393
6394         /* Attach crtc to drm_atomic_state*/
6395         crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
6396
6397         ret = PTR_ERR_OR_ZERO(crtc_state);
6398         if (ret)
6399                 goto err;
6400
6401         /* force a restore */
6402         crtc_state->mode_changed = true;
6403
6404         /* Attach plane to drm_atomic_state */
6405         plane_state = drm_atomic_get_plane_state(state, plane);
6406
6407         ret = PTR_ERR_OR_ZERO(plane_state);
6408         if (ret)
6409                 goto err;
6410
6411
6412         /* Call commit internally with the state we just constructed */
6413         ret = drm_atomic_commit(state);
6414         if (!ret)
6415                 return 0;
6416
6417 err:
6418         DRM_ERROR("Restoring old state failed with %i\n", ret);
6419         drm_atomic_state_put(state);
6420
6421         return ret;
6422 }
6423
6424 /*
6425  * This function handles all cases when set mode does not come upon hotplug.
6426  * This includes when a display is unplugged then plugged back into the
6427  * same port and when running without usermode desktop manager supprot
6428  */
6429 void dm_restore_drm_connector_state(struct drm_device *dev,
6430                                     struct drm_connector *connector)
6431 {
6432         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6433         struct amdgpu_crtc *disconnected_acrtc;
6434         struct dm_crtc_state *acrtc_state;
6435
6436         if (!aconnector->dc_sink || !connector->state || !connector->encoder)
6437                 return;
6438
6439         disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
6440         if (!disconnected_acrtc)
6441                 return;
6442
6443         acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
6444         if (!acrtc_state->stream)
6445                 return;
6446
6447         /*
6448          * If the previous sink is not released and different from the current,
6449          * we deduce we are in a state where we can not rely on usermode call
6450          * to turn on the display, so we do it here
6451          */
6452         if (acrtc_state->stream->sink != aconnector->dc_sink)
6453                 dm_force_atomic_commit(&aconnector->base);
6454 }
6455
6456 /*
6457  * Grabs all modesetting locks to serialize against any blocking commits,
6458  * Waits for completion of all non blocking commits.
6459  */
6460 static int do_aquire_global_lock(struct drm_device *dev,
6461                                  struct drm_atomic_state *state)
6462 {
6463         struct drm_crtc *crtc;
6464         struct drm_crtc_commit *commit;
6465         long ret;
6466
6467         /*
6468          * Adding all modeset locks to aquire_ctx will
6469          * ensure that when the framework release it the
6470          * extra locks we are locking here will get released to
6471          */
6472         ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
6473         if (ret)
6474                 return ret;
6475
6476         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6477                 spin_lock(&crtc->commit_lock);
6478                 commit = list_first_entry_or_null(&crtc->commit_list,
6479                                 struct drm_crtc_commit, commit_entry);
6480                 if (commit)
6481                         drm_crtc_commit_get(commit);
6482                 spin_unlock(&crtc->commit_lock);
6483
6484                 if (!commit)
6485                         continue;
6486
6487                 /*
6488                  * Make sure all pending HW programming completed and
6489                  * page flips done
6490                  */
6491                 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
6492
6493                 if (ret > 0)
6494                         ret = wait_for_completion_interruptible_timeout(
6495                                         &commit->flip_done, 10*HZ);
6496
6497                 if (ret == 0)
6498                         DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
6499                                   "timed out\n", crtc->base.id, crtc->name);
6500
6501                 drm_crtc_commit_put(commit);
6502         }
6503
6504         return ret < 0 ? ret : 0;
6505 }
6506
6507 static void get_freesync_config_for_crtc(
6508         struct dm_crtc_state *new_crtc_state,
6509         struct dm_connector_state *new_con_state)
6510 {
6511         struct mod_freesync_config config = {0};
6512         struct amdgpu_dm_connector *aconnector =
6513                         to_amdgpu_dm_connector(new_con_state->base.connector);
6514         struct drm_display_mode *mode = &new_crtc_state->base.mode;
6515         int vrefresh = drm_mode_vrefresh(mode);
6516
6517         new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
6518                                         vrefresh >= aconnector->min_vfreq &&
6519                                         vrefresh <= aconnector->max_vfreq;
6520
6521         if (new_crtc_state->vrr_supported) {
6522                 new_crtc_state->stream->ignore_msa_timing_param = true;
6523                 config.state = new_crtc_state->base.vrr_enabled ?
6524                                 VRR_STATE_ACTIVE_VARIABLE :
6525                                 VRR_STATE_INACTIVE;
6526                 config.min_refresh_in_uhz =
6527                                 aconnector->min_vfreq * 1000000;
6528                 config.max_refresh_in_uhz =
6529                                 aconnector->max_vfreq * 1000000;
6530                 config.vsif_supported = true;
6531                 config.btr = true;
6532         }
6533
6534         new_crtc_state->freesync_config = config;
6535 }
6536
6537 static void reset_freesync_config_for_crtc(
6538         struct dm_crtc_state *new_crtc_state)
6539 {
6540         new_crtc_state->vrr_supported = false;
6541
6542         memset(&new_crtc_state->vrr_params, 0,
6543                sizeof(new_crtc_state->vrr_params));
6544         memset(&new_crtc_state->vrr_infopacket, 0,
6545                sizeof(new_crtc_state->vrr_infopacket));
6546 }
6547
6548 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
6549                                 struct drm_atomic_state *state,
6550                                 struct drm_crtc *crtc,
6551                                 struct drm_crtc_state *old_crtc_state,
6552                                 struct drm_crtc_state *new_crtc_state,
6553                                 bool enable,
6554                                 bool *lock_and_validation_needed)
6555 {
6556         struct dm_atomic_state *dm_state = NULL;
6557         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
6558         struct dc_stream_state *new_stream;
6559         int ret = 0;
6560
6561         /*
6562          * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
6563          * update changed items
6564          */
6565         struct amdgpu_crtc *acrtc = NULL;
6566         struct amdgpu_dm_connector *aconnector = NULL;
6567         struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
6568         struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
6569
6570         new_stream = NULL;
6571
6572         dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
6573         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6574         acrtc = to_amdgpu_crtc(crtc);
6575         aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
6576
6577         /* TODO This hack should go away */
6578         if (aconnector && enable) {
6579                 /* Make sure fake sink is created in plug-in scenario */
6580                 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
6581                                                             &aconnector->base);
6582                 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
6583                                                             &aconnector->base);
6584
6585                 if (IS_ERR(drm_new_conn_state)) {
6586                         ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
6587                         goto fail;
6588                 }
6589
6590                 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
6591                 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
6592
6593                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
6594                         goto skip_modeset;
6595
6596                 new_stream = create_stream_for_sink(aconnector,
6597                                                      &new_crtc_state->mode,
6598                                                     dm_new_conn_state,
6599                                                     dm_old_crtc_state->stream);
6600
6601                 /*
6602                  * we can have no stream on ACTION_SET if a display
6603                  * was disconnected during S3, in this case it is not an
6604                  * error, the OS will be updated after detection, and
6605                  * will do the right thing on next atomic commit
6606                  */
6607
6608                 if (!new_stream) {
6609                         DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
6610                                         __func__, acrtc->base.base.id);
6611                         ret = -ENOMEM;
6612                         goto fail;
6613                 }
6614
6615                 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
6616
6617                 ret = fill_hdr_info_packet(drm_new_conn_state,
6618                                            &new_stream->hdr_static_metadata);
6619                 if (ret)
6620                         goto fail;
6621
6622                 /*
6623                  * If we already removed the old stream from the context
6624                  * (and set the new stream to NULL) then we can't reuse
6625                  * the old stream even if the stream and scaling are unchanged.
6626                  * We'll hit the BUG_ON and black screen.
6627                  *
6628                  * TODO: Refactor this function to allow this check to work
6629                  * in all conditions.
6630                  */
6631                 if (dm_new_crtc_state->stream &&
6632                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
6633                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
6634                         new_crtc_state->mode_changed = false;
6635                         DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
6636                                          new_crtc_state->mode_changed);
6637                 }
6638         }
6639
6640         /* mode_changed flag may get updated above, need to check again */
6641         if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
6642                 goto skip_modeset;
6643
6644         DRM_DEBUG_DRIVER(
6645                 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
6646                 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
6647                 "connectors_changed:%d\n",
6648                 acrtc->crtc_id,
6649                 new_crtc_state->enable,
6650                 new_crtc_state->active,
6651                 new_crtc_state->planes_changed,
6652                 new_crtc_state->mode_changed,
6653                 new_crtc_state->active_changed,
6654                 new_crtc_state->connectors_changed);
6655
6656         /* Remove stream for any changed/disabled CRTC */
6657         if (!enable) {
6658
6659                 if (!dm_old_crtc_state->stream)
6660                         goto skip_modeset;
6661
6662                 ret = dm_atomic_get_state(state, &dm_state);
6663                 if (ret)
6664                         goto fail;
6665
6666                 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
6667                                 crtc->base.id);
6668
6669                 /* i.e. reset mode */
6670                 if (dc_remove_stream_from_ctx(
6671                                 dm->dc,
6672                                 dm_state->context,
6673                                 dm_old_crtc_state->stream) != DC_OK) {
6674                         ret = -EINVAL;
6675                         goto fail;
6676                 }
6677
6678                 dc_stream_release(dm_old_crtc_state->stream);
6679                 dm_new_crtc_state->stream = NULL;
6680
6681                 reset_freesync_config_for_crtc(dm_new_crtc_state);
6682
6683                 *lock_and_validation_needed = true;
6684
6685         } else {/* Add stream for any updated/enabled CRTC */
6686                 /*
6687                  * Quick fix to prevent NULL pointer on new_stream when
6688                  * added MST connectors not found in existing crtc_state in the chained mode
6689                  * TODO: need to dig out the root cause of that
6690                  */
6691                 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
6692                         goto skip_modeset;
6693
6694                 if (modereset_required(new_crtc_state))
6695                         goto skip_modeset;
6696
6697                 if (modeset_required(new_crtc_state, new_stream,
6698                                      dm_old_crtc_state->stream)) {
6699
6700                         WARN_ON(dm_new_crtc_state->stream);
6701
6702                         ret = dm_atomic_get_state(state, &dm_state);
6703                         if (ret)
6704                                 goto fail;
6705
6706                         dm_new_crtc_state->stream = new_stream;
6707
6708                         dc_stream_retain(new_stream);
6709
6710                         DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
6711                                                 crtc->base.id);
6712
6713                         if (dc_add_stream_to_ctx(
6714                                         dm->dc,
6715                                         dm_state->context,
6716                                         dm_new_crtc_state->stream) != DC_OK) {
6717                                 ret = -EINVAL;
6718                                 goto fail;
6719                         }
6720
6721                         *lock_and_validation_needed = true;
6722                 }
6723         }
6724
6725 skip_modeset:
6726         /* Release extra reference */
6727         if (new_stream)
6728                  dc_stream_release(new_stream);
6729
6730         /*
6731          * We want to do dc stream updates that do not require a
6732          * full modeset below.
6733          */
6734         if (!(enable && aconnector && new_crtc_state->enable &&
6735               new_crtc_state->active))
6736                 return 0;
6737         /*
6738          * Given above conditions, the dc state cannot be NULL because:
6739          * 1. We're in the process of enabling CRTCs (just been added
6740          *    to the dc context, or already is on the context)
6741          * 2. Has a valid connector attached, and
6742          * 3. Is currently active and enabled.
6743          * => The dc stream state currently exists.
6744          */
6745         BUG_ON(dm_new_crtc_state->stream == NULL);
6746
6747         /* Scaling or underscan settings */
6748         if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
6749                 update_stream_scaling_settings(
6750                         &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
6751
6752         /* ABM settings */
6753         dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
6754
6755         /*
6756          * Color management settings. We also update color properties
6757          * when a modeset is needed, to ensure it gets reprogrammed.
6758          */
6759         if (dm_new_crtc_state->base.color_mgmt_changed ||
6760             drm_atomic_crtc_needs_modeset(new_crtc_state)) {
6761                 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
6762                 if (ret)
6763                         goto fail;
6764         }
6765
6766         /* Update Freesync settings. */
6767         get_freesync_config_for_crtc(dm_new_crtc_state,
6768                                      dm_new_conn_state);
6769
6770         return ret;
6771
6772 fail:
6773         if (new_stream)
6774                 dc_stream_release(new_stream);
6775         return ret;
6776 }
6777
6778 static bool should_reset_plane(struct drm_atomic_state *state,
6779                                struct drm_plane *plane,
6780                                struct drm_plane_state *old_plane_state,
6781                                struct drm_plane_state *new_plane_state)
6782 {
6783         struct drm_plane *other;
6784         struct drm_plane_state *old_other_state, *new_other_state;
6785         struct drm_crtc_state *new_crtc_state;
6786         int i;
6787
6788         /*
6789          * TODO: Remove this hack once the checks below are sufficient
6790          * enough to determine when we need to reset all the planes on
6791          * the stream.
6792          */
6793         if (state->allow_modeset)
6794                 return true;
6795
6796         /* Exit early if we know that we're adding or removing the plane. */
6797         if (old_plane_state->crtc != new_plane_state->crtc)
6798                 return true;
6799
6800         /* old crtc == new_crtc == NULL, plane not in context. */
6801         if (!new_plane_state->crtc)
6802                 return false;
6803
6804         new_crtc_state =
6805                 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
6806
6807         if (!new_crtc_state)
6808                 return true;
6809
6810         /* CRTC Degamma changes currently require us to recreate planes. */
6811         if (new_crtc_state->color_mgmt_changed)
6812                 return true;
6813
6814         if (drm_atomic_crtc_needs_modeset(new_crtc_state))
6815                 return true;
6816
6817         /*
6818          * If there are any new primary or overlay planes being added or
6819          * removed then the z-order can potentially change. To ensure
6820          * correct z-order and pipe acquisition the current DC architecture
6821          * requires us to remove and recreate all existing planes.
6822          *
6823          * TODO: Come up with a more elegant solution for this.
6824          */
6825         for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
6826                 if (other->type == DRM_PLANE_TYPE_CURSOR)
6827                         continue;
6828
6829                 if (old_other_state->crtc != new_plane_state->crtc &&
6830                     new_other_state->crtc != new_plane_state->crtc)
6831                         continue;
6832
6833                 if (old_other_state->crtc != new_other_state->crtc)
6834                         return true;
6835
6836                 /* TODO: Remove this once we can handle fast format changes. */
6837                 if (old_other_state->fb && new_other_state->fb &&
6838                     old_other_state->fb->format != new_other_state->fb->format)
6839                         return true;
6840         }
6841
6842         return false;
6843 }
6844
6845 static int dm_update_plane_state(struct dc *dc,
6846                                  struct drm_atomic_state *state,
6847                                  struct drm_plane *plane,
6848                                  struct drm_plane_state *old_plane_state,
6849                                  struct drm_plane_state *new_plane_state,
6850                                  bool enable,
6851                                  bool *lock_and_validation_needed)
6852 {
6853
6854         struct dm_atomic_state *dm_state = NULL;
6855         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
6856         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
6857         struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
6858         struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
6859         bool needs_reset;
6860         int ret = 0;
6861
6862
6863         new_plane_crtc = new_plane_state->crtc;
6864         old_plane_crtc = old_plane_state->crtc;
6865         dm_new_plane_state = to_dm_plane_state(new_plane_state);
6866         dm_old_plane_state = to_dm_plane_state(old_plane_state);
6867
6868         /*TODO Implement atomic check for cursor plane */
6869         if (plane->type == DRM_PLANE_TYPE_CURSOR)
6870                 return 0;
6871
6872         needs_reset = should_reset_plane(state, plane, old_plane_state,
6873                                          new_plane_state);
6874
6875         /* Remove any changed/removed planes */
6876         if (!enable) {
6877                 if (!needs_reset)
6878                         return 0;
6879
6880                 if (!old_plane_crtc)
6881                         return 0;
6882
6883                 old_crtc_state = drm_atomic_get_old_crtc_state(
6884                                 state, old_plane_crtc);
6885                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
6886
6887                 if (!dm_old_crtc_state->stream)
6888                         return 0;
6889
6890                 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
6891                                 plane->base.id, old_plane_crtc->base.id);
6892
6893                 ret = dm_atomic_get_state(state, &dm_state);
6894                 if (ret)
6895                         return ret;
6896
6897                 if (!dc_remove_plane_from_context(
6898                                 dc,
6899                                 dm_old_crtc_state->stream,
6900                                 dm_old_plane_state->dc_state,
6901                                 dm_state->context)) {
6902
6903                         ret = EINVAL;
6904                         return ret;
6905                 }
6906
6907
6908                 dc_plane_state_release(dm_old_plane_state->dc_state);
6909                 dm_new_plane_state->dc_state = NULL;
6910
6911                 *lock_and_validation_needed = true;
6912
6913         } else { /* Add new planes */
6914                 struct dc_plane_state *dc_new_plane_state;
6915
6916                 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
6917                         return 0;
6918
6919                 if (!new_plane_crtc)
6920                         return 0;
6921
6922                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
6923                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6924
6925                 if (!dm_new_crtc_state->stream)
6926                         return 0;
6927
6928                 if (!needs_reset)
6929                         return 0;
6930
6931                 WARN_ON(dm_new_plane_state->dc_state);
6932
6933                 dc_new_plane_state = dc_create_plane_state(dc);
6934                 if (!dc_new_plane_state)
6935                         return -ENOMEM;
6936
6937                 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
6938                                 plane->base.id, new_plane_crtc->base.id);
6939
6940                 ret = fill_dc_plane_attributes(
6941                         new_plane_crtc->dev->dev_private,
6942                         dc_new_plane_state,
6943                         new_plane_state,
6944                         new_crtc_state);
6945                 if (ret) {
6946                         dc_plane_state_release(dc_new_plane_state);
6947                         return ret;
6948                 }
6949
6950                 ret = dm_atomic_get_state(state, &dm_state);
6951                 if (ret) {
6952                         dc_plane_state_release(dc_new_plane_state);
6953                         return ret;
6954                 }
6955
6956                 /*
6957                  * Any atomic check errors that occur after this will
6958                  * not need a release. The plane state will be attached
6959                  * to the stream, and therefore part of the atomic
6960                  * state. It'll be released when the atomic state is
6961                  * cleaned.
6962                  */
6963                 if (!dc_add_plane_to_context(
6964                                 dc,
6965                                 dm_new_crtc_state->stream,
6966                                 dc_new_plane_state,
6967                                 dm_state->context)) {
6968
6969                         dc_plane_state_release(dc_new_plane_state);
6970                         return -EINVAL;
6971                 }
6972
6973                 dm_new_plane_state->dc_state = dc_new_plane_state;
6974
6975                 /* Tell DC to do a full surface update every time there
6976                  * is a plane change. Inefficient, but works for now.
6977                  */
6978                 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
6979
6980                 *lock_and_validation_needed = true;
6981         }
6982
6983
6984         return ret;
6985 }
6986
6987 static int
6988 dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm,
6989                                     struct drm_atomic_state *state,
6990                                     enum surface_update_type *out_type)
6991 {
6992         struct dc *dc = dm->dc;
6993         struct dm_atomic_state *dm_state = NULL, *old_dm_state = NULL;
6994         int i, j, num_plane, ret = 0;
6995         struct drm_plane_state *old_plane_state, *new_plane_state;
6996         struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state;
6997         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
6998         struct drm_plane *plane;
6999
7000         struct drm_crtc *crtc;
7001         struct drm_crtc_state *new_crtc_state, *old_crtc_state;
7002         struct dm_crtc_state *new_dm_crtc_state, *old_dm_crtc_state;
7003         struct dc_stream_status *status = NULL;
7004
7005         struct dc_surface_update *updates;
7006         enum surface_update_type update_type = UPDATE_TYPE_FAST;
7007
7008         updates = kcalloc(MAX_SURFACES, sizeof(*updates), GFP_KERNEL);
7009
7010         if (!updates) {
7011                 DRM_ERROR("Failed to allocate plane updates\n");
7012                 /* Set type to FULL to avoid crashing in DC*/
7013                 update_type = UPDATE_TYPE_FULL;
7014                 goto cleanup;
7015         }
7016
7017         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7018                 struct dc_scaling_info scaling_info;
7019                 struct dc_stream_update stream_update;
7020
7021                 memset(&stream_update, 0, sizeof(stream_update));
7022
7023                 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
7024                 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state);
7025                 num_plane = 0;
7026
7027                 if (new_dm_crtc_state->stream != old_dm_crtc_state->stream) {
7028                         update_type = UPDATE_TYPE_FULL;
7029                         goto cleanup;
7030                 }
7031
7032                 if (!new_dm_crtc_state->stream)
7033                         continue;
7034
7035                 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) {
7036                         new_plane_crtc = new_plane_state->crtc;
7037                         old_plane_crtc = old_plane_state->crtc;
7038                         new_dm_plane_state = to_dm_plane_state(new_plane_state);
7039                         old_dm_plane_state = to_dm_plane_state(old_plane_state);
7040
7041                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
7042                                 continue;
7043
7044                         if (new_dm_plane_state->dc_state != old_dm_plane_state->dc_state) {
7045                                 update_type = UPDATE_TYPE_FULL;
7046                                 goto cleanup;
7047                         }
7048
7049                         if (crtc != new_plane_crtc)
7050                                 continue;
7051
7052                         updates[num_plane].surface = new_dm_plane_state->dc_state;
7053
7054                         if (new_crtc_state->mode_changed) {
7055                                 stream_update.dst = new_dm_crtc_state->stream->dst;
7056                                 stream_update.src = new_dm_crtc_state->stream->src;
7057                         }
7058
7059                         if (new_crtc_state->color_mgmt_changed) {
7060                                 updates[num_plane].gamma =
7061                                                 new_dm_plane_state->dc_state->gamma_correction;
7062                                 updates[num_plane].in_transfer_func =
7063                                                 new_dm_plane_state->dc_state->in_transfer_func;
7064                                 stream_update.gamut_remap =
7065                                                 &new_dm_crtc_state->stream->gamut_remap_matrix;
7066                                 stream_update.output_csc_transform =
7067                                                 &new_dm_crtc_state->stream->csc_color_matrix;
7068                                 stream_update.out_transfer_func =
7069                                                 new_dm_crtc_state->stream->out_transfer_func;
7070                         }
7071
7072                         ret = fill_dc_scaling_info(new_plane_state,
7073                                                    &scaling_info);
7074                         if (ret)
7075                                 goto cleanup;
7076
7077                         updates[num_plane].scaling_info = &scaling_info;
7078
7079                         num_plane++;
7080                 }
7081
7082                 if (num_plane == 0)
7083                         continue;
7084
7085                 ret = dm_atomic_get_state(state, &dm_state);
7086                 if (ret)
7087                         goto cleanup;
7088
7089                 old_dm_state = dm_atomic_get_old_state(state);
7090                 if (!old_dm_state) {
7091                         ret = -EINVAL;
7092                         goto cleanup;
7093                 }
7094
7095                 status = dc_stream_get_status_from_state(old_dm_state->context,
7096                                                          new_dm_crtc_state->stream);
7097
7098                 /*
7099                  * TODO: DC modifies the surface during this call so we need
7100                  * to lock here - find a way to do this without locking.
7101                  */
7102                 mutex_lock(&dm->dc_lock);
7103                 update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane,
7104                                                                   &stream_update, status);
7105                 mutex_unlock(&dm->dc_lock);
7106
7107                 if (update_type > UPDATE_TYPE_MED) {
7108                         update_type = UPDATE_TYPE_FULL;
7109                         goto cleanup;
7110                 }
7111         }
7112
7113 cleanup:
7114         kfree(updates);
7115
7116         *out_type = update_type;
7117         return ret;
7118 }
7119
7120 /**
7121  * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
7122  * @dev: The DRM device
7123  * @state: The atomic state to commit
7124  *
7125  * Validate that the given atomic state is programmable by DC into hardware.
7126  * This involves constructing a &struct dc_state reflecting the new hardware
7127  * state we wish to commit, then querying DC to see if it is programmable. It's
7128  * important not to modify the existing DC state. Otherwise, atomic_check
7129  * may unexpectedly commit hardware changes.
7130  *
7131  * When validating the DC state, it's important that the right locks are
7132  * acquired. For full updates case which removes/adds/updates streams on one
7133  * CRTC while flipping on another CRTC, acquiring global lock will guarantee
7134  * that any such full update commit will wait for completion of any outstanding
7135  * flip using DRMs synchronization events. See
7136  * dm_determine_update_type_for_commit()
7137  *
7138  * Note that DM adds the affected connectors for all CRTCs in state, when that
7139  * might not seem necessary. This is because DC stream creation requires the
7140  * DC sink, which is tied to the DRM connector state. Cleaning this up should
7141  * be possible but non-trivial - a possible TODO item.
7142  *
7143  * Return: -Error code if validation failed.
7144  */
7145 static int amdgpu_dm_atomic_check(struct drm_device *dev,
7146                                   struct drm_atomic_state *state)
7147 {
7148         struct amdgpu_device *adev = dev->dev_private;
7149         struct dm_atomic_state *dm_state = NULL;
7150         struct dc *dc = adev->dm.dc;
7151         struct drm_connector *connector;
7152         struct drm_connector_state *old_con_state, *new_con_state;
7153         struct drm_crtc *crtc;
7154         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
7155         struct drm_plane *plane;
7156         struct drm_plane_state *old_plane_state, *new_plane_state;
7157         enum surface_update_type update_type = UPDATE_TYPE_FAST;
7158         enum surface_update_type overall_update_type = UPDATE_TYPE_FAST;
7159
7160         int ret, i;
7161
7162         /*
7163          * This bool will be set for true for any modeset/reset
7164          * or plane update which implies non fast surface update.
7165          */
7166         bool lock_and_validation_needed = false;
7167
7168         ret = drm_atomic_helper_check_modeset(dev, state);
7169         if (ret)
7170                 goto fail;
7171
7172         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7173                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
7174                     !new_crtc_state->color_mgmt_changed &&
7175                     old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled)
7176                         continue;
7177
7178                 if (!new_crtc_state->enable)
7179                         continue;
7180
7181                 ret = drm_atomic_add_affected_connectors(state, crtc);
7182                 if (ret)
7183                         return ret;
7184
7185                 ret = drm_atomic_add_affected_planes(state, crtc);
7186                 if (ret)
7187                         goto fail;
7188         }
7189
7190         /*
7191          * Add all primary and overlay planes on the CRTC to the state
7192          * whenever a plane is enabled to maintain correct z-ordering
7193          * and to enable fast surface updates.
7194          */
7195         drm_for_each_crtc(crtc, dev) {
7196                 bool modified = false;
7197
7198                 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
7199                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
7200                                 continue;
7201
7202                         if (new_plane_state->crtc == crtc ||
7203                             old_plane_state->crtc == crtc) {
7204                                 modified = true;
7205                                 break;
7206                         }
7207                 }
7208
7209                 if (!modified)
7210                         continue;
7211
7212                 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
7213                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
7214                                 continue;
7215
7216                         new_plane_state =
7217                                 drm_atomic_get_plane_state(state, plane);
7218
7219                         if (IS_ERR(new_plane_state)) {
7220                                 ret = PTR_ERR(new_plane_state);
7221                                 goto fail;
7222                         }
7223                 }
7224         }
7225
7226         /* Remove exiting planes if they are modified */
7227         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
7228                 ret = dm_update_plane_state(dc, state, plane,
7229                                             old_plane_state,
7230                                             new_plane_state,
7231                                             false,
7232                                             &lock_and_validation_needed);
7233                 if (ret)
7234                         goto fail;
7235         }
7236
7237         /* Disable all crtcs which require disable */
7238         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7239                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
7240                                            old_crtc_state,
7241                                            new_crtc_state,
7242                                            false,
7243                                            &lock_and_validation_needed);
7244                 if (ret)
7245                         goto fail;
7246         }
7247
7248         /* Enable all crtcs which require enable */
7249         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7250                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
7251                                            old_crtc_state,
7252                                            new_crtc_state,
7253                                            true,
7254                                            &lock_and_validation_needed);
7255                 if (ret)
7256                         goto fail;
7257         }
7258
7259         /* Add new/modified planes */
7260         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
7261                 ret = dm_update_plane_state(dc, state, plane,
7262                                             old_plane_state,
7263                                             new_plane_state,
7264                                             true,
7265                                             &lock_and_validation_needed);
7266                 if (ret)
7267                         goto fail;
7268         }
7269
7270         /* Run this here since we want to validate the streams we created */
7271         ret = drm_atomic_helper_check_planes(dev, state);
7272         if (ret)
7273                 goto fail;
7274
7275         /* Check scaling and underscan changes*/
7276         /* TODO Removed scaling changes validation due to inability to commit
7277          * new stream into context w\o causing full reset. Need to
7278          * decide how to handle.
7279          */
7280         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
7281                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
7282                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
7283                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
7284
7285                 /* Skip any modesets/resets */
7286                 if (!acrtc || drm_atomic_crtc_needs_modeset(
7287                                 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
7288                         continue;
7289
7290                 /* Skip any thing not scale or underscan changes */
7291                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
7292                         continue;
7293
7294                 overall_update_type = UPDATE_TYPE_FULL;
7295                 lock_and_validation_needed = true;
7296         }
7297
7298         ret = dm_determine_update_type_for_commit(&adev->dm, state, &update_type);
7299         if (ret)
7300                 goto fail;
7301
7302         if (overall_update_type < update_type)
7303                 overall_update_type = update_type;
7304
7305         /*
7306          * lock_and_validation_needed was an old way to determine if we need to set
7307          * the global lock. Leaving it in to check if we broke any corner cases
7308          * lock_and_validation_needed true = UPDATE_TYPE_FULL or UPDATE_TYPE_MED
7309          * lock_and_validation_needed false = UPDATE_TYPE_FAST
7310          */
7311         if (lock_and_validation_needed && overall_update_type <= UPDATE_TYPE_FAST)
7312                 WARN(1, "Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL");
7313
7314         if (overall_update_type > UPDATE_TYPE_FAST) {
7315                 ret = dm_atomic_get_state(state, &dm_state);
7316                 if (ret)
7317                         goto fail;
7318
7319                 ret = do_aquire_global_lock(dev, state);
7320                 if (ret)
7321                         goto fail;
7322
7323                 if (dc_validate_global_state(dc, dm_state->context, false) != DC_OK) {
7324                         ret = -EINVAL;
7325                         goto fail;
7326                 }
7327         } else if (state->legacy_cursor_update) {
7328                 /*
7329                  * This is a fast cursor update coming from the plane update
7330                  * helper, check if it can be done asynchronously for better
7331                  * performance.
7332                  */
7333                 state->async_update = !drm_atomic_helper_async_check(dev, state);
7334         }
7335
7336         /* Must be success */
7337         WARN_ON(ret);
7338         return ret;
7339
7340 fail:
7341         if (ret == -EDEADLK)
7342                 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
7343         else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
7344                 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
7345         else
7346                 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
7347
7348         return ret;
7349 }
7350
7351 static bool is_dp_capable_without_timing_msa(struct dc *dc,
7352                                              struct amdgpu_dm_connector *amdgpu_dm_connector)
7353 {
7354         uint8_t dpcd_data;
7355         bool capable = false;
7356
7357         if (amdgpu_dm_connector->dc_link &&
7358                 dm_helpers_dp_read_dpcd(
7359                                 NULL,
7360                                 amdgpu_dm_connector->dc_link,
7361                                 DP_DOWN_STREAM_PORT_COUNT,
7362                                 &dpcd_data,
7363                                 sizeof(dpcd_data))) {
7364                 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
7365         }
7366
7367         return capable;
7368 }
7369 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
7370                                         struct edid *edid)
7371 {
7372         int i;
7373         bool edid_check_required;
7374         struct detailed_timing *timing;
7375         struct detailed_non_pixel *data;
7376         struct detailed_data_monitor_range *range;
7377         struct amdgpu_dm_connector *amdgpu_dm_connector =
7378                         to_amdgpu_dm_connector(connector);
7379         struct dm_connector_state *dm_con_state = NULL;
7380
7381         struct drm_device *dev = connector->dev;
7382         struct amdgpu_device *adev = dev->dev_private;
7383         bool freesync_capable = false;
7384
7385         if (!connector->state) {
7386                 DRM_ERROR("%s - Connector has no state", __func__);
7387                 goto update;
7388         }
7389
7390         if (!edid) {
7391                 dm_con_state = to_dm_connector_state(connector->state);
7392
7393                 amdgpu_dm_connector->min_vfreq = 0;
7394                 amdgpu_dm_connector->max_vfreq = 0;
7395                 amdgpu_dm_connector->pixel_clock_mhz = 0;
7396
7397                 goto update;
7398         }
7399
7400         dm_con_state = to_dm_connector_state(connector->state);
7401
7402         edid_check_required = false;
7403         if (!amdgpu_dm_connector->dc_sink) {
7404                 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
7405                 goto update;
7406         }
7407         if (!adev->dm.freesync_module)
7408                 goto update;
7409         /*
7410          * if edid non zero restrict freesync only for dp and edp
7411          */
7412         if (edid) {
7413                 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
7414                         || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
7415                         edid_check_required = is_dp_capable_without_timing_msa(
7416                                                 adev->dm.dc,
7417                                                 amdgpu_dm_connector);
7418                 }
7419         }
7420         if (edid_check_required == true && (edid->version > 1 ||
7421            (edid->version == 1 && edid->revision > 1))) {
7422                 for (i = 0; i < 4; i++) {
7423
7424                         timing  = &edid->detailed_timings[i];
7425                         data    = &timing->data.other_data;
7426                         range   = &data->data.range;
7427                         /*
7428                          * Check if monitor has continuous frequency mode
7429                          */
7430                         if (data->type != EDID_DETAIL_MONITOR_RANGE)
7431                                 continue;
7432                         /*
7433                          * Check for flag range limits only. If flag == 1 then
7434                          * no additional timing information provided.
7435                          * Default GTF, GTF Secondary curve and CVT are not
7436                          * supported
7437                          */
7438                         if (range->flags != 1)
7439                                 continue;
7440
7441                         amdgpu_dm_connector->min_vfreq = range->min_vfreq;
7442                         amdgpu_dm_connector->max_vfreq = range->max_vfreq;
7443                         amdgpu_dm_connector->pixel_clock_mhz =
7444                                 range->pixel_clock_mhz * 10;
7445                         break;
7446                 }
7447
7448                 if (amdgpu_dm_connector->max_vfreq -
7449                     amdgpu_dm_connector->min_vfreq > 10) {
7450
7451                         freesync_capable = true;
7452                 }
7453         }
7454
7455 update:
7456         if (dm_con_state)
7457                 dm_con_state->freesync_capable = freesync_capable;
7458
7459         if (connector->vrr_capable_property)
7460                 drm_connector_set_vrr_capable_property(connector,
7461                                                        freesync_capable);
7462 }
7463