drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services_types.h"
  27 #include "dc.h"
  28 #include "dc/inc/core_types.h"
  29
  30 #include "vid.h"
  31 #include "amdgpu.h"
  32 #include "amdgpu_display.h"
  33 #include "atom.h"
  34 #include "amdgpu_dm.h"
  35 #include "amdgpu_pm.h"
  36
  37 #include "amd_shared.h"
  38 #include "amdgpu_dm_irq.h"
  39 #include "dm_helpers.h"
  40 #include "dm_services_types.h"
  41 #include "amdgpu_dm_mst_types.h"
  42
  43 #include "ivsrcid/ivsrcid_vislands30.h"
  44
  45 #include <linux/module.h>
  46 #include <linux/moduleparam.h>
  47 #include <linux/version.h>
  48 #include <linux/types.h>
  49
  50 #include <drm/drmP.h>
  51 #include <drm/drm_atomic.h>
  52 #include <drm/drm_atomic_helper.h>
  53 #include <drm/drm_dp_mst_helper.h>
  54 #include <drm/drm_fb_helper.h>
  55 #include <drm/drm_edid.h>
  56
  57 #include "modules/inc/mod_freesync.h"
  58
  59 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
  60 #include "ivsrcid/irqsrcs_dcn_1_0.h"
  61
  62 #include "dcn/dcn_1_0_offset.h"
  63 #include "dcn/dcn_1_0_sh_mask.h"
  64 #include "soc15_hw_ip.h"
  65 #include "vega10_ip_offset.h"
  66
  67 #include "soc15_common.h"
  68 #endif
  69
  70 #include "modules/inc/mod_freesync.h"
  71
  72 #include "i2caux_interface.h"
  73
  74 /* basic init/fini API */
  75 static int amdgpu_dm_init(struct amdgpu_device *adev);
  76 static void amdgpu_dm_fini(struct amdgpu_device *adev);
  77
  78 /* initializes drm_device display related structures, based on the information
  79  * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
  80  * drm_encoder, drm_mode_config
  81  *
  82  * Returns 0 on success
  83  */
  84 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
  85 /* removes and deallocates the drm structures, created by the above function */
  86 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
  87
  88 static void
  89 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
  90
  91 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
  92                                 struct amdgpu_plane *aplane,
  93                                 unsigned long possible_crtcs);
  94 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
  95                                struct drm_plane *plane,
  96                                uint32_t link_index);
  97 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
  98                                     struct amdgpu_dm_connector *amdgpu_dm_connector,
  99                                     uint32_t link_index,
 100                                     struct amdgpu_encoder *amdgpu_encoder);
 101 static int amdgpu_dm_encoder_init(struct drm_device *dev,
 102                                   struct amdgpu_encoder *aencoder,
 103                                   uint32_t link_index);
 104
 105 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
 106
 107 static int amdgpu_dm_atomic_commit(struct drm_device *dev,
 108                                    struct drm_atomic_state *state,
 109                                    bool nonblock);
 110
 111 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
 112
 113 static int amdgpu_dm_atomic_check(struct drm_device *dev,
 114                                   struct drm_atomic_state *state);
 115
 116
 117
 118
 119 static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
 120         DRM_PLANE_TYPE_PRIMARY,
 121         DRM_PLANE_TYPE_PRIMARY,
 122         DRM_PLANE_TYPE_PRIMARY,
 123         DRM_PLANE_TYPE_PRIMARY,
 124         DRM_PLANE_TYPE_PRIMARY,
 125         DRM_PLANE_TYPE_PRIMARY,
 126 };
 127
 128 static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
 129         DRM_PLANE_TYPE_PRIMARY,
 130         DRM_PLANE_TYPE_PRIMARY,
 131         DRM_PLANE_TYPE_PRIMARY,
 132         DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */
 133 };
 134
 135 static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
 136         DRM_PLANE_TYPE_PRIMARY,
 137         DRM_PLANE_TYPE_PRIMARY,
 138         DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
 139 };
 140
 141 /*
 142  * dm_vblank_get_counter
 143  *
 144  * @brief
 145  * Get counter for number of vertical blanks
 146  *
 147  * @param
 148  * struct amdgpu_device *adev - [in] desired amdgpu device
 149  * int disp_idx - [in] which CRTC to get the counter from
 150  *
 151  * @return
 152  * Counter for vertical blanks
 153  */
 154 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 155 {
 156         if (crtc >= adev->mode_info.num_crtc)
 157                 return 0;
 158         else {
 159                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 160                 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
 161                                 acrtc->base.state);
 162
 163
 164                 if (acrtc_state->stream == NULL) {
 165                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 166                                   crtc);
 167                         return 0;
 168                 }
 169
 170                 return dc_stream_get_vblank_counter(acrtc_state->stream);
 171         }
 172 }
 173
 174 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 175                                   u32 *vbl, u32 *position)
 176 {
 177         uint32_t v_blank_start, v_blank_end, h_position, v_position;
 178
 179         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 180                 return -EINVAL;
 181         else {
 182                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 183                 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
 184                                                 acrtc->base.state);
 185
 186                 if (acrtc_state->stream ==  NULL) {
 187                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 188                                   crtc);
 189                         return 0;
 190                 }
 191
 192                 /*
 193                  * TODO rework base driver to use values directly.
 194                  * for now parse it back into reg-format
 195                  */
 196                 dc_stream_get_scanoutpos(acrtc_state->stream,
 197                                          &v_blank_start,
 198                                          &v_blank_end,
 199                                          &h_position,
 200                                          &v_position);
 201
 202                 *position = v_position | (h_position << 16);
 203                 *vbl = v_blank_start | (v_blank_end << 16);
 204         }
 205
 206         return 0;
 207 }
 208
 209 static bool dm_is_idle(void *handle)
 210 {
 211         /* XXX todo */
 212         return true;
 213 }
 214
 215 static int dm_wait_for_idle(void *handle)
 216 {
 217         /* XXX todo */
 218         return 0;
 219 }
 220
 221 static bool dm_check_soft_reset(void *handle)
 222 {
 223         return false;
 224 }
 225
 226 static int dm_soft_reset(void *handle)
 227 {
 228         /* XXX todo */
 229         return 0;
 230 }
 231
 232 static struct amdgpu_crtc *
 233 get_crtc_by_otg_inst(struct amdgpu_device *adev,
 234                      int otg_inst)
 235 {
 236         struct drm_device *dev = adev->ddev;
 237         struct drm_crtc *crtc;
 238         struct amdgpu_crtc *amdgpu_crtc;
 239
 240         /*
 241          * following if is check inherited from both functions where this one is
 242          * used now. Need to be checked why it could happen.
 243          */
 244         if (otg_inst == -1) {
 245                 WARN_ON(1);
 246                 return adev->mode_info.crtcs[0];
 247         }
 248
 249         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 250                 amdgpu_crtc = to_amdgpu_crtc(crtc);
 251
 252                 if (amdgpu_crtc->otg_inst == otg_inst)
 253                         return amdgpu_crtc;
 254         }
 255
 256         return NULL;
 257 }
 258
 259 static void dm_pflip_high_irq(void *interrupt_params)
 260 {
 261         struct amdgpu_crtc *amdgpu_crtc;
 262         struct common_irq_params *irq_params = interrupt_params;
 263         struct amdgpu_device *adev = irq_params->adev;
 264         unsigned long flags;
 265
 266         amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
 267
 268         /* IRQ could occur when in initial stage */
 269         /*TODO work and BO cleanup */
 270         if (amdgpu_crtc == NULL) {
 271                 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
 272                 return;
 273         }
 274
 275         spin_lock_irqsave(&adev->ddev->event_lock, flags);
 276
 277         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
 278                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
 279                                                  amdgpu_crtc->pflip_status,
 280                                                  AMDGPU_FLIP_SUBMITTED,
 281                                                  amdgpu_crtc->crtc_id,
 282                                                  amdgpu_crtc);
 283                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 284                 return;
 285         }
 286
 287
 288         /* wakeup usersapce */
 289         if (amdgpu_crtc->event) {
 290                 /* Update to correct count/ts if racing with vblank irq */
 291                 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
 292
 293                 drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
 294
 295                 /* page flip completed. clean up */
 296                 amdgpu_crtc->event = NULL;
 297
 298         } else
 299                 WARN_ON(1);
 300
 301         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 302         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 303
 304         DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n",
 305                                         __func__, amdgpu_crtc->crtc_id, amdgpu_crtc);
 306
 307         drm_crtc_vblank_put(&amdgpu_crtc->base);
 308 }
 309
 310 static void dm_crtc_high_irq(void *interrupt_params)
 311 {
 312         struct common_irq_params *irq_params = interrupt_params;
 313         struct amdgpu_device *adev = irq_params->adev;
 314         uint8_t crtc_index = 0;
 315         struct amdgpu_crtc *acrtc;
 316
 317         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
 318
 319         if (acrtc)
 320                 crtc_index = acrtc->crtc_id;
 321
 322         drm_handle_vblank(adev->ddev, crtc_index);
 323         amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
 324 }
 325
 326 static int dm_set_clockgating_state(void *handle,
 327                   enum amd_clockgating_state state)
 328 {
 329         return 0;
 330 }
 331
 332 static int dm_set_powergating_state(void *handle,
 333                   enum amd_powergating_state state)
 334 {
 335         return 0;
 336 }
 337
 338 /* Prototypes of private functions */
 339 static int dm_early_init(void* handle);
 340
 341 static void hotplug_notify_work_func(struct work_struct *work)
 342 {
 343         struct amdgpu_display_manager *dm = container_of(work, struct amdgpu_display_manager, mst_hotplug_work);
 344         struct drm_device *dev = dm->ddev;
 345
 346         drm_kms_helper_hotplug_event(dev);
 347 }
 348
 349 #if defined(CONFIG_DRM_AMD_DC_FBC)
 350 /* Allocate memory for FBC compressed data  */
 351 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 352 {
 353         struct drm_device *dev = connector->dev;
 354         struct amdgpu_device *adev = dev->dev_private;
 355         struct dm_comressor_info *compressor = &adev->dm.compressor;
 356         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
 357         struct drm_display_mode *mode;
 358         unsigned long max_size = 0;
 359
 360         if (adev->dm.dc->fbc_compressor == NULL)
 361                 return;
 362
 363         if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
 364                 return;
 365
 366         if (compressor->bo_ptr)
 367                 return;
 368
 369
 370         list_for_each_entry(mode, &connector->modes, head) {
 371                 if (max_size < mode->htotal * mode->vtotal)
 372                         max_size = mode->htotal * mode->vtotal;
 373         }
 374
 375         if (max_size) {
 376                 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
 377                             AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
 378                             &compressor->gpu_addr, &compressor->cpu_addr);
 379
 380                 if (r)
 381                         DRM_ERROR("DM: Failed to initialize FBC\n");
 382                 else {
 383                         adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
 384                         DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
 385                 }
 386
 387         }
 388
 389 }
 390 #endif
 391
 392
 393 /* Init display KMS
 394  *
 395  * Returns 0 on success
 396  */
 397 static int amdgpu_dm_init(struct amdgpu_device *adev)
 398 {
 399         struct dc_init_data init_data;
 400         adev->dm.ddev = adev->ddev;
 401         adev->dm.adev = adev;
 402
 403         /* Zero all the fields */
 404         memset(&init_data, 0, sizeof(init_data));
 405
 406         if(amdgpu_dm_irq_init(adev)) {
 407                 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
 408                 goto error;
 409         }
 410
 411         init_data.asic_id.chip_family = adev->family;
 412
 413         init_data.asic_id.pci_revision_id = adev->rev_id;
 414         init_data.asic_id.hw_internal_rev = adev->external_rev_id;
 415
 416         init_data.asic_id.vram_width = adev->gmc.vram_width;
 417         /* TODO: initialize init_data.asic_id.vram_type here!!!! */
 418         init_data.asic_id.atombios_base_address =
 419                 adev->mode_info.atom_context->bios;
 420
 421         init_data.driver = adev;
 422
 423         adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
 424
 425         if (!adev->dm.cgs_device) {
 426                 DRM_ERROR("amdgpu: failed to create cgs device.\n");
 427                 goto error;
 428         }
 429
 430         init_data.cgs_device = adev->dm.cgs_device;
 431
 432         adev->dm.dal = NULL;
 433
 434         init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
 435
 436         if (amdgpu_dc_log)
 437                 init_data.log_mask = DC_DEFAULT_LOG_MASK;
 438         else
 439                 init_data.log_mask = DC_MIN_LOG_MASK;
 440
 441         /*
 442          * TODO debug why this doesn't work on Raven
 443          */
 444         if (adev->flags & AMD_IS_APU &&
 445             adev->asic_type >= CHIP_CARRIZO &&
 446             adev->asic_type < CHIP_RAVEN)
 447                 init_data.flags.gpu_vm_support = true;
 448
 449         /* Display Core create. */
 450         adev->dm.dc = dc_create(&init_data);
 451
 452         if (adev->dm.dc) {
 453                 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
 454         } else {
 455                 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
 456                 goto error;
 457         }
 458
 459         INIT_WORK(&adev->dm.mst_hotplug_work, hotplug_notify_work_func);
 460
 461         adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
 462         if (!adev->dm.freesync_module) {
 463                 DRM_ERROR(
 464                 "amdgpu: failed to initialize freesync_module.\n");
 465         } else
 466                 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
 467                                 adev->dm.freesync_module);
 468
 469         amdgpu_dm_init_color_mod();
 470
 471         if (amdgpu_dm_initialize_drm_device(adev)) {
 472                 DRM_ERROR(
 473                 "amdgpu: failed to initialize sw for display support.\n");
 474                 goto error;
 475         }
 476
 477         /* Update the actual used number of crtc */
 478         adev->mode_info.num_crtc = adev->dm.display_indexes_num;
 479
 480         /* TODO: Add_display_info? */
 481
 482         /* TODO use dynamic cursor width */
 483         adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
 484         adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
 485
 486         if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
 487                 DRM_ERROR(
 488                 "amdgpu: failed to initialize sw for display support.\n");
 489                 goto error;
 490         }
 491
 492         DRM_DEBUG_DRIVER("KMS initialized.\n");
 493
 494         return 0;
 495 error:
 496         amdgpu_dm_fini(adev);
 497
 498         return -1;
 499 }
 500
 501 static void amdgpu_dm_fini(struct amdgpu_device *adev)
 502 {
 503         amdgpu_dm_destroy_drm_device(&adev->dm);
 504         /*
 505          * TODO: pageflip, vlank interrupt
 506          *
 507          * amdgpu_dm_irq_fini(adev);
 508          */
 509
 510         if (adev->dm.cgs_device) {
 511                 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
 512                 adev->dm.cgs_device = NULL;
 513         }
 514         if (adev->dm.freesync_module) {
 515                 mod_freesync_destroy(adev->dm.freesync_module);
 516                 adev->dm.freesync_module = NULL;
 517         }
 518         /* DC Destroy TODO: Replace destroy DAL */
 519         if (adev->dm.dc)
 520                 dc_destroy(&adev->dm.dc);
 521         return;
 522 }
 523
 524 static int dm_sw_init(void *handle)
 525 {
 526         return 0;
 527 }
 528
 529 static int dm_sw_fini(void *handle)
 530 {
 531         return 0;
 532 }
 533
 534 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
 535 {
 536         struct amdgpu_dm_connector *aconnector;
 537         struct drm_connector *connector;
 538         int ret = 0;
 539
 540         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
 541
 542         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 543                 aconnector = to_amdgpu_dm_connector(connector);
 544                 if (aconnector->dc_link->type == dc_connection_mst_branch &&
 545                     aconnector->mst_mgr.aux) {
 546                         DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
 547                                         aconnector, aconnector->base.base.id);
 548
 549                         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
 550                         if (ret < 0) {
 551                                 DRM_ERROR("DM_MST: Failed to start MST\n");
 552                                 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
 553                                 return ret;
 554                                 }
 555                         }
 556         }
 557
 558         drm_modeset_unlock(&dev->mode_config.connection_mutex);
 559         return ret;
 560 }
 561
 562 static int dm_late_init(void *handle)
 563 {
 564         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 565
 566         return detect_mst_link_for_all_connectors(adev->ddev);
 567 }
 568
 569 static void s3_handle_mst(struct drm_device *dev, bool suspend)
 570 {
 571         struct amdgpu_dm_connector *aconnector;
 572         struct drm_connector *connector;
 573
 574         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
 575
 576         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 577                    aconnector = to_amdgpu_dm_connector(connector);
 578                    if (aconnector->dc_link->type == dc_connection_mst_branch &&
 579                                    !aconnector->mst_port) {
 580
 581                            if (suspend)
 582                                    drm_dp_mst_topology_mgr_suspend(&aconnector->mst_mgr);
 583                            else
 584                                    drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr);
 585                    }
 586         }
 587
 588         drm_modeset_unlock(&dev->mode_config.connection_mutex);
 589 }
 590
 591 static int dm_hw_init(void *handle)
 592 {
 593         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 594         /* Create DAL display manager */
 595         amdgpu_dm_init(adev);
 596         amdgpu_dm_hpd_init(adev);
 597
 598         return 0;
 599 }
 600
 601 static int dm_hw_fini(void *handle)
 602 {
 603         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 604
 605         amdgpu_dm_hpd_fini(adev);
 606
 607         amdgpu_dm_irq_fini(adev);
 608         amdgpu_dm_fini(adev);
 609         return 0;
 610 }
 611
 612 static int dm_suspend(void *handle)
 613 {
 614         struct amdgpu_device *adev = handle;
 615         struct amdgpu_display_manager *dm = &adev->dm;
 616         int ret = 0;
 617
 618         s3_handle_mst(adev->ddev, true);
 619
 620         amdgpu_dm_irq_suspend(adev);
 621
 622         WARN_ON(adev->dm.cached_state);
 623         adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
 624
 625         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
 626
 627         return ret;
 628 }
 629
 630 static struct amdgpu_dm_connector *
 631 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
 632                                              struct drm_crtc *crtc)
 633 {
 634         uint32_t i;
 635         struct drm_connector_state *new_con_state;
 636         struct drm_connector *connector;
 637         struct drm_crtc *crtc_from_state;
 638
 639         for_each_new_connector_in_state(state, connector, new_con_state, i) {
 640                 crtc_from_state = new_con_state->crtc;
 641
 642                 if (crtc_from_state == crtc)
 643                         return to_amdgpu_dm_connector(connector);
 644         }
 645
 646         return NULL;
 647 }
 648
 649 static int dm_resume(void *handle)
 650 {
 651         struct amdgpu_device *adev = handle;
 652         struct amdgpu_display_manager *dm = &adev->dm;
 653         int ret = 0;
 654
 655         /* power on hardware */
 656         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
 657
 658         ret = amdgpu_dm_display_resume(adev);
 659         return ret;
 660 }
 661
 662 int amdgpu_dm_display_resume(struct amdgpu_device *adev)
 663 {
 664         struct drm_device *ddev = adev->ddev;
 665         struct amdgpu_display_manager *dm = &adev->dm;
 666         struct amdgpu_dm_connector *aconnector;
 667         struct drm_connector *connector;
 668         struct drm_crtc *crtc;
 669         struct drm_crtc_state *new_crtc_state;
 670         struct dm_crtc_state *dm_new_crtc_state;
 671         struct drm_plane *plane;
 672         struct drm_plane_state *new_plane_state;
 673         struct dm_plane_state *dm_new_plane_state;
 674
 675         int ret = 0;
 676         int i;
 677
 678         /* program HPD filter */
 679         dc_resume(dm->dc);
 680
 681         /* On resume we need to  rewrite the MSTM control bits to enamble MST*/
 682         s3_handle_mst(ddev, false);
 683
 684         /*
 685          * early enable HPD Rx IRQ, should be done before set mode as short
 686          * pulse interrupts are used for MST
 687          */
 688         amdgpu_dm_irq_resume_early(adev);
 689
 690         /* Do detection*/
 691         list_for_each_entry(connector,
 692                         &ddev->mode_config.connector_list, head) {
 693                 aconnector = to_amdgpu_dm_connector(connector);
 694
 695                 /*
 696                  * this is the case when traversing through already created
 697                  * MST connectors, should be skipped
 698                  */
 699                 if (aconnector->mst_port)
 700                         continue;
 701
 702                 mutex_lock(&aconnector->hpd_lock);
 703                 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
 704
 705                 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
 706                         aconnector->fake_enable = false;
 707
 708                 aconnector->dc_sink = NULL;
 709                 amdgpu_dm_update_connector_after_detect(aconnector);
 710                 mutex_unlock(&aconnector->hpd_lock);
 711         }
 712
 713         /* Force mode set in atomic comit */
 714         for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i)
 715                 new_crtc_state->active_changed = true;
 716
 717         /*
 718          * atomic_check is expected to create the dc states. We need to release
 719          * them here, since they were duplicated as part of the suspend
 720          * procedure.
 721          */
 722         for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i) {
 723                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
 724                 if (dm_new_crtc_state->stream) {
 725                         WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
 726                         dc_stream_release(dm_new_crtc_state->stream);
 727                         dm_new_crtc_state->stream = NULL;
 728                 }
 729         }
 730
 731         for_each_new_plane_in_state(adev->dm.cached_state, plane, new_plane_state, i) {
 732                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
 733                 if (dm_new_plane_state->dc_state) {
 734                         WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
 735                         dc_plane_state_release(dm_new_plane_state->dc_state);
 736                         dm_new_plane_state->dc_state = NULL;
 737                 }
 738         }
 739
 740         ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state);
 741
 742         adev->dm.cached_state = NULL;
 743
 744         amdgpu_dm_irq_resume_late(adev);
 745
 746         return ret;
 747 }
 748
 749 static const struct amd_ip_funcs amdgpu_dm_funcs = {
 750         .name = "dm",
 751         .early_init = dm_early_init,
 752         .late_init = dm_late_init,
 753         .sw_init = dm_sw_init,
 754         .sw_fini = dm_sw_fini,
 755         .hw_init = dm_hw_init,
 756         .hw_fini = dm_hw_fini,
 757         .suspend = dm_suspend,
 758         .resume = dm_resume,
 759         .is_idle = dm_is_idle,
 760         .wait_for_idle = dm_wait_for_idle,
 761         .check_soft_reset = dm_check_soft_reset,
 762         .soft_reset = dm_soft_reset,
 763         .set_clockgating_state = dm_set_clockgating_state,
 764         .set_powergating_state = dm_set_powergating_state,
 765 };
 766
 767 const struct amdgpu_ip_block_version dm_ip_block =
 768 {
 769         .type = AMD_IP_BLOCK_TYPE_DCE,
 770         .major = 1,
 771         .minor = 0,
 772         .rev = 0,
 773         .funcs = &amdgpu_dm_funcs,
 774 };
 775
 776
 777 static struct drm_atomic_state *
 778 dm_atomic_state_alloc(struct drm_device *dev)
 779 {
 780         struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
 781
 782         if (!state)
 783                 return NULL;
 784
 785         if (drm_atomic_state_init(dev, &state->base) < 0)
 786                 goto fail;
 787
 788         return &state->base;
 789
 790 fail:
 791         kfree(state);
 792         return NULL;
 793 }
 794
 795 static void
 796 dm_atomic_state_clear(struct drm_atomic_state *state)
 797 {
 798         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
 799
 800         if (dm_state->context) {
 801                 dc_release_state(dm_state->context);
 802                 dm_state->context = NULL;
 803         }
 804
 805         drm_atomic_state_default_clear(state);
 806 }
 807
 808 static void
 809 dm_atomic_state_alloc_free(struct drm_atomic_state *state)
 810 {
 811         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
 812         drm_atomic_state_default_release(state);
 813         kfree(dm_state);
 814 }
 815
 816 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
 817         .fb_create = amdgpu_display_user_framebuffer_create,
 818         .output_poll_changed = drm_fb_helper_output_poll_changed,
 819         .atomic_check = amdgpu_dm_atomic_check,
 820         .atomic_commit = amdgpu_dm_atomic_commit,
 821         .atomic_state_alloc = dm_atomic_state_alloc,
 822         .atomic_state_clear = dm_atomic_state_clear,
 823         .atomic_state_free = dm_atomic_state_alloc_free
 824 };
 825
 826 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
 827         .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
 828 };
 829
 830 static void
 831 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
 832 {
 833         struct drm_connector *connector = &aconnector->base;
 834         struct drm_device *dev = connector->dev;
 835         struct dc_sink *sink;
 836
 837         /* MST handled by drm_mst framework */
 838         if (aconnector->mst_mgr.mst_state == true)
 839                 return;
 840
 841
 842         sink = aconnector->dc_link->local_sink;
 843
 844         /* Edid mgmt connector gets first update only in mode_valid hook and then
 845          * the connector sink is set to either fake or physical sink depends on link status.
 846          * don't do it here if u are during boot
 847          */
 848         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
 849                         && aconnector->dc_em_sink) {
 850
 851                 /* For S3 resume with headless use eml_sink to fake stream
 852                  * because on resume connecotr->sink is set ti NULL
 853                  */
 854                 mutex_lock(&dev->mode_config.mutex);
 855
 856                 if (sink) {
 857                         if (aconnector->dc_sink) {
 858                                 amdgpu_dm_remove_sink_from_freesync_module(
 859                                                                 connector);
 860                                 /* retain and release bellow are used for
 861                                  * bump up refcount for sink because the link don't point
 862                                  * to it anymore after disconnect so on next crtc to connector
 863                                  * reshuffle by UMD we will get into unwanted dc_sink release
 864                                  */
 865                                 if (aconnector->dc_sink != aconnector->dc_em_sink)
 866                                         dc_sink_release(aconnector->dc_sink);
 867                         }
 868                         aconnector->dc_sink = sink;
 869                         amdgpu_dm_add_sink_to_freesync_module(
 870                                                 connector, aconnector->edid);
 871                 } else {
 872                         amdgpu_dm_remove_sink_from_freesync_module(connector);
 873                         if (!aconnector->dc_sink)
 874                                 aconnector->dc_sink = aconnector->dc_em_sink;
 875                         else if (aconnector->dc_sink != aconnector->dc_em_sink)
 876                                 dc_sink_retain(aconnector->dc_sink);
 877                 }
 878
 879                 mutex_unlock(&dev->mode_config.mutex);
 880                 return;
 881         }
 882
 883         /*
 884          * TODO: temporary guard to look for proper fix
 885          * if this sink is MST sink, we should not do anything
 886          */
 887         if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
 888                 return;
 889
 890         if (aconnector->dc_sink == sink) {
 891                 /* We got a DP short pulse (Link Loss, DP CTS, etc...).
 892                  * Do nothing!! */
 893                 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
 894                                 aconnector->connector_id);
 895                 return;
 896         }
 897
 898         DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
 899                 aconnector->connector_id, aconnector->dc_sink, sink);
 900
 901         mutex_lock(&dev->mode_config.mutex);
 902
 903         /* 1. Update status of the drm connector
 904          * 2. Send an event and let userspace tell us what to do */
 905         if (sink) {
 906                 /* TODO: check if we still need the S3 mode update workaround.
 907                  * If yes, put it here. */
 908                 if (aconnector->dc_sink)
 909                         amdgpu_dm_remove_sink_from_freesync_module(
 910                                                         connector);
 911
 912                 aconnector->dc_sink = sink;
 913                 if (sink->dc_edid.length == 0) {
 914                         aconnector->edid = NULL;
 915                 } else {
 916                         aconnector->edid =
 917                                 (struct edid *) sink->dc_edid.raw_edid;
 918
 919
 920                         drm_mode_connector_update_edid_property(connector,
 921                                         aconnector->edid);
 922                 }
 923                 amdgpu_dm_add_sink_to_freesync_module(connector, aconnector->edid);
 924
 925         } else {
 926                 amdgpu_dm_remove_sink_from_freesync_module(connector);
 927                 drm_mode_connector_update_edid_property(connector, NULL);
 928                 aconnector->num_modes = 0;
 929                 aconnector->dc_sink = NULL;
 930         }
 931
 932         mutex_unlock(&dev->mode_config.mutex);
 933 }
 934
 935 static void handle_hpd_irq(void *param)
 936 {
 937         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
 938         struct drm_connector *connector = &aconnector->base;
 939         struct drm_device *dev = connector->dev;
 940
 941         /* In case of failure or MST no need to update connector status or notify the OS
 942          * since (for MST case) MST does this in it's own context.
 943          */
 944         mutex_lock(&aconnector->hpd_lock);
 945
 946         if (aconnector->fake_enable)
 947                 aconnector->fake_enable = false;
 948
 949         if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
 950                 amdgpu_dm_update_connector_after_detect(aconnector);
 951
 952
 953                 drm_modeset_lock_all(dev);
 954                 dm_restore_drm_connector_state(dev, connector);
 955                 drm_modeset_unlock_all(dev);
 956
 957                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
 958                         drm_kms_helper_hotplug_event(dev);
 959         }
 960         mutex_unlock(&aconnector->hpd_lock);
 961
 962 }
 963
 964 static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
 965 {
 966         uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
 967         uint8_t dret;
 968         bool new_irq_handled = false;
 969         int dpcd_addr;
 970         int dpcd_bytes_to_read;
 971
 972         const int max_process_count = 30;
 973         int process_count = 0;
 974
 975         const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
 976
 977         if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
 978                 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
 979                 /* DPCD 0x200 - 0x201 for downstream IRQ */
 980                 dpcd_addr = DP_SINK_COUNT;
 981         } else {
 982                 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
 983                 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
 984                 dpcd_addr = DP_SINK_COUNT_ESI;
 985         }
 986
 987         dret = drm_dp_dpcd_read(
 988                 &aconnector->dm_dp_aux.aux,
 989                 dpcd_addr,
 990                 esi,
 991                 dpcd_bytes_to_read);
 992
 993         while (dret == dpcd_bytes_to_read &&
 994                 process_count < max_process_count) {
 995                 uint8_t retry;
 996                 dret = 0;
 997
 998                 process_count++;
 999
1000                 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
1001                 /* handle HPD short pulse irq */
1002                 if (aconnector->mst_mgr.mst_state)
1003                         drm_dp_mst_hpd_irq(
1004                                 &aconnector->mst_mgr,
1005                                 esi,
1006                                 &new_irq_handled);
1007
1008                 if (new_irq_handled) {
1009                         /* ACK at DPCD to notify down stream */
1010                         const int ack_dpcd_bytes_to_write =
1011                                 dpcd_bytes_to_read - 1;
1012
1013                         for (retry = 0; retry < 3; retry++) {
1014                                 uint8_t wret;
1015
1016                                 wret = drm_dp_dpcd_write(
1017                                         &aconnector->dm_dp_aux.aux,
1018                                         dpcd_addr + 1,
1019                                         &esi[1],
1020                                         ack_dpcd_bytes_to_write);
1021                                 if (wret == ack_dpcd_bytes_to_write)
1022                                         break;
1023                         }
1024
1025                         /* check if there is new irq to be handle */
1026                         dret = drm_dp_dpcd_read(
1027                                 &aconnector->dm_dp_aux.aux,
1028                                 dpcd_addr,
1029                                 esi,
1030                                 dpcd_bytes_to_read);
1031
1032                         new_irq_handled = false;
1033                 } else {
1034                         break;
1035                 }
1036         }
1037
1038         if (process_count == max_process_count)
1039                 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
1040 }
1041
1042 static void handle_hpd_rx_irq(void *param)
1043 {
1044         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
1045         struct drm_connector *connector = &aconnector->base;
1046         struct drm_device *dev = connector->dev;
1047         struct dc_link *dc_link = aconnector->dc_link;
1048         bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
1049
1050         /* TODO:Temporary add mutex to protect hpd interrupt not have a gpio
1051          * conflict, after implement i2c helper, this mutex should be
1052          * retired.
1053          */
1054         if (dc_link->type != dc_connection_mst_branch)
1055                 mutex_lock(&aconnector->hpd_lock);
1056
1057         if (dc_link_handle_hpd_rx_irq(dc_link, NULL) &&
1058                         !is_mst_root_connector) {
1059                 /* Downstream Port status changed. */
1060                 if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
1061
1062                         if (aconnector->fake_enable)
1063                                 aconnector->fake_enable = false;
1064
1065                         amdgpu_dm_update_connector_after_detect(aconnector);
1066
1067
1068                         drm_modeset_lock_all(dev);
1069                         dm_restore_drm_connector_state(dev, connector);
1070                         drm_modeset_unlock_all(dev);
1071
1072                         drm_kms_helper_hotplug_event(dev);
1073                 }
1074         }
1075         if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
1076             (dc_link->type == dc_connection_mst_branch))
1077                 dm_handle_hpd_rx_irq(aconnector);
1078
1079         if (dc_link->type != dc_connection_mst_branch)
1080                 mutex_unlock(&aconnector->hpd_lock);
1081 }
1082
1083 static void register_hpd_handlers(struct amdgpu_device *adev)
1084 {
1085         struct drm_device *dev = adev->ddev;
1086         struct drm_connector *connector;
1087         struct amdgpu_dm_connector *aconnector;
1088         const struct dc_link *dc_link;
1089         struct dc_interrupt_params int_params = {0};
1090
1091         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1092         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1093
1094         list_for_each_entry(connector,
1095                         &dev->mode_config.connector_list, head) {
1096
1097                 aconnector = to_amdgpu_dm_connector(connector);
1098                 dc_link = aconnector->dc_link;
1099
1100                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1101                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1102                         int_params.irq_source = dc_link->irq_source_hpd;
1103
1104                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
1105                                         handle_hpd_irq,
1106                                         (void *) aconnector);
1107                 }
1108
1109                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1110
1111                         /* Also register for DP short pulse (hpd_rx). */
1112                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1113                         int_params.irq_source = dc_link->irq_source_hpd_rx;
1114
1115                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
1116                                         handle_hpd_rx_irq,
1117                                         (void *) aconnector);
1118                 }
1119         }
1120 }
1121
1122 /* Register IRQ sources and initialize IRQ callbacks */
1123 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1124 {
1125         struct dc *dc = adev->dm.dc;
1126         struct common_irq_params *c_irq_params;
1127         struct dc_interrupt_params int_params = {0};
1128         int r;
1129         int i;
1130         unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY;
1131
1132         if (adev->asic_type == CHIP_VEGA10 ||
1133             adev->asic_type == CHIP_VEGA12 ||
1134             adev->asic_type == CHIP_RAVEN)
1135                 client_id = SOC15_IH_CLIENTID_DCE;
1136
1137         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1138         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1139
1140         /* Actions of amdgpu_irq_add_id():
1141          * 1. Register a set() function with base driver.
1142          *    Base driver will call set() function to enable/disable an
1143          *    interrupt in DC hardware.
1144          * 2. Register amdgpu_dm_irq_handler().
1145          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1146          *    coming from DC hardware.
1147          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1148          *    for acknowledging and handling. */
1149
1150         /* Use VBLANK interrupt */
1151         for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
1152                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
1153                 if (r) {
1154                         DRM_ERROR("Failed to add crtc irq id!\n");
1155                         return r;
1156                 }
1157
1158                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1159                 int_params.irq_source =
1160                         dc_interrupt_to_irq_source(dc, i, 0);
1161
1162                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1163
1164                 c_irq_params->adev = adev;
1165                 c_irq_params->irq_src = int_params.irq_source;
1166
1167                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1168                                 dm_crtc_high_irq, c_irq_params);
1169         }
1170
1171         /* Use GRPH_PFLIP interrupt */
1172         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1173                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
1174                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
1175                 if (r) {
1176                         DRM_ERROR("Failed to add page flip irq id!\n");
1177                         return r;
1178                 }
1179
1180                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1181                 int_params.irq_source =
1182                         dc_interrupt_to_irq_source(dc, i, 0);
1183
1184                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1185
1186                 c_irq_params->adev = adev;
1187                 c_irq_params->irq_src = int_params.irq_source;
1188
1189                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1190                                 dm_pflip_high_irq, c_irq_params);
1191
1192         }
1193
1194         /* HPD */
1195         r = amdgpu_irq_add_id(adev, client_id,
1196                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
1197         if (r) {
1198                 DRM_ERROR("Failed to add hpd irq id!\n");
1199                 return r;
1200         }
1201
1202         register_hpd_handlers(adev);
1203
1204         return 0;
1205 }
1206
1207 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1208 /* Register IRQ sources and initialize IRQ callbacks */
1209 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1210 {
1211         struct dc *dc = adev->dm.dc;
1212         struct common_irq_params *c_irq_params;
1213         struct dc_interrupt_params int_params = {0};
1214         int r;
1215         int i;
1216
1217         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1218         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1219
1220         /* Actions of amdgpu_irq_add_id():
1221          * 1. Register a set() function with base driver.
1222          *    Base driver will call set() function to enable/disable an
1223          *    interrupt in DC hardware.
1224          * 2. Register amdgpu_dm_irq_handler().
1225          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1226          *    coming from DC hardware.
1227          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1228          *    for acknowledging and handling.
1229          * */
1230
1231         /* Use VSTARTUP interrupt */
1232         for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1233                         i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1234                         i++) {
1235                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
1236
1237                 if (r) {
1238                         DRM_ERROR("Failed to add crtc irq id!\n");
1239                         return r;
1240                 }
1241
1242                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1243                 int_params.irq_source =
1244                         dc_interrupt_to_irq_source(dc, i, 0);
1245
1246                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1247
1248                 c_irq_params->adev = adev;
1249                 c_irq_params->irq_src = int_params.irq_source;
1250
1251                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1252                                 dm_crtc_high_irq, c_irq_params);
1253         }
1254
1255         /* Use GRPH_PFLIP interrupt */
1256         for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1257                         i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1258                         i++) {
1259                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
1260                 if (r) {
1261                         DRM_ERROR("Failed to add page flip irq id!\n");
1262                         return r;
1263                 }
1264
1265                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1266                 int_params.irq_source =
1267                         dc_interrupt_to_irq_source(dc, i, 0);
1268
1269                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1270
1271                 c_irq_params->adev = adev;
1272                 c_irq_params->irq_src = int_params.irq_source;
1273
1274                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1275                                 dm_pflip_high_irq, c_irq_params);
1276
1277         }
1278
1279         /* HPD */
1280         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
1281                         &adev->hpd_irq);
1282         if (r) {
1283                 DRM_ERROR("Failed to add hpd irq id!\n");
1284                 return r;
1285         }
1286
1287         register_hpd_handlers(adev);
1288
1289         return 0;
1290 }
1291 #endif
1292
1293 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1294 {
1295         int r;
1296
1297         adev->mode_info.mode_config_initialized = true;
1298
1299         adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
1300         adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
1301
1302         adev->ddev->mode_config.max_width = 16384;
1303         adev->ddev->mode_config.max_height = 16384;
1304
1305         adev->ddev->mode_config.preferred_depth = 24;
1306         adev->ddev->mode_config.prefer_shadow = 1;
1307         /* indicate support of immediate flip */
1308         adev->ddev->mode_config.async_page_flip = true;
1309
1310         adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
1311
1312         r = amdgpu_display_modeset_create_props(adev);
1313         if (r)
1314                 return r;
1315
1316         return 0;
1317 }
1318
1319 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1320         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1321
1322 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
1323 {
1324         struct amdgpu_display_manager *dm = bl_get_data(bd);
1325
1326         if (dc_link_set_backlight_level(dm->backlight_link,
1327                         bd->props.brightness, 0, 0))
1328                 return 0;
1329         else
1330                 return 1;
1331 }
1332
1333 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
1334 {
1335         return bd->props.brightness;
1336 }
1337
1338 static const struct backlight_ops amdgpu_dm_backlight_ops = {
1339         .get_brightness = amdgpu_dm_backlight_get_brightness,
1340         .update_status  = amdgpu_dm_backlight_update_status,
1341 };
1342
1343 static void
1344 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
1345 {
1346         char bl_name[16];
1347         struct backlight_properties props = { 0 };
1348
1349         props.max_brightness = AMDGPU_MAX_BL_LEVEL;
1350         props.type = BACKLIGHT_RAW;
1351
1352         snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
1353                         dm->adev->ddev->primary->index);
1354
1355         dm->backlight_dev = backlight_device_register(bl_name,
1356                         dm->adev->ddev->dev,
1357                         dm,
1358                         &amdgpu_dm_backlight_ops,
1359                         &props);
1360
1361         if (IS_ERR(dm->backlight_dev))
1362                 DRM_ERROR("DM: Backlight registration failed!\n");
1363         else
1364                 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
1365 }
1366
1367 #endif
1368
1369 static int initialize_plane(struct amdgpu_display_manager *dm,
1370                              struct amdgpu_mode_info *mode_info,
1371                              int plane_id)
1372 {
1373         struct amdgpu_plane *plane;
1374         unsigned long possible_crtcs;
1375         int ret = 0;
1376
1377         plane = kzalloc(sizeof(struct amdgpu_plane), GFP_KERNEL);
1378         mode_info->planes[plane_id] = plane;
1379
1380         if (!plane) {
1381                 DRM_ERROR("KMS: Failed to allocate plane\n");
1382                 return -ENOMEM;
1383         }
1384         plane->base.type = mode_info->plane_type[plane_id];
1385
1386         /*
1387          * HACK: IGT tests expect that each plane can only have one
1388          * one possible CRTC. For now, set one CRTC for each
1389          * plane that is not an underlay, but still allow multiple
1390          * CRTCs for underlay planes.
1391          */
1392         possible_crtcs = 1 << plane_id;
1393         if (plane_id >= dm->dc->caps.max_streams)
1394                 possible_crtcs = 0xff;
1395
1396         ret = amdgpu_dm_plane_init(dm, mode_info->planes[plane_id], possible_crtcs);
1397
1398         if (ret) {
1399                 DRM_ERROR("KMS: Failed to initialize plane\n");
1400                 return ret;
1401         }
1402
1403         return ret;
1404 }
1405
1406
1407 static void register_backlight_device(struct amdgpu_display_manager *dm,
1408                                       struct dc_link *link)
1409 {
1410 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1411         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1412
1413         if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
1414             link->type != dc_connection_none) {
1415                 /* Event if registration failed, we should continue with
1416                  * DM initialization because not having a backlight control
1417                  * is better then a black screen.
1418                  */
1419                 amdgpu_dm_register_backlight_device(dm);
1420
1421                 if (dm->backlight_dev)
1422                         dm->backlight_link = link;
1423         }
1424 #endif
1425 }
1426
1427
1428 /* In this architecture, the association
1429  * connector -> encoder -> crtc
1430  * id not really requried. The crtc and connector will hold the
1431  * display_index as an abstraction to use with DAL component
1432  *
1433  * Returns 0 on success
1434  */
1435 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
1436 {
1437         struct amdgpu_display_manager *dm = &adev->dm;
1438         int32_t i;
1439         struct amdgpu_dm_connector *aconnector = NULL;
1440         struct amdgpu_encoder *aencoder = NULL;
1441         struct amdgpu_mode_info *mode_info = &adev->mode_info;
1442         uint32_t link_cnt;
1443         int32_t total_overlay_planes, total_primary_planes;
1444
1445         link_cnt = dm->dc->caps.max_links;
1446         if (amdgpu_dm_mode_config_init(dm->adev)) {
1447                 DRM_ERROR("DM: Failed to initialize mode config\n");
1448                 return -1;
1449         }
1450
1451         /* Identify the number of planes to be initialized */
1452         total_overlay_planes = dm->dc->caps.max_slave_planes;
1453         total_primary_planes = dm->dc->caps.max_planes - dm->dc->caps.max_slave_planes;
1454
1455         /* First initialize overlay planes, index starting after primary planes */
1456         for (i = (total_overlay_planes - 1); i >= 0; i--) {
1457                 if (initialize_plane(dm, mode_info, (total_primary_planes + i))) {
1458                         DRM_ERROR("KMS: Failed to initialize overlay plane\n");
1459                         goto fail;
1460                 }
1461         }
1462
1463         /* Initialize primary planes */
1464         for (i = (total_primary_planes - 1); i >= 0; i--) {
1465                 if (initialize_plane(dm, mode_info, i)) {
1466                         DRM_ERROR("KMS: Failed to initialize primary plane\n");
1467                         goto fail;
1468                 }
1469         }
1470
1471         for (i = 0; i < dm->dc->caps.max_streams; i++)
1472                 if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) {
1473                         DRM_ERROR("KMS: Failed to initialize crtc\n");
1474                         goto fail;
1475                 }
1476
1477         dm->display_indexes_num = dm->dc->caps.max_streams;
1478
1479         /* loops over all connectors on the board */
1480         for (i = 0; i < link_cnt; i++) {
1481                 struct dc_link *link = NULL;
1482
1483                 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
1484                         DRM_ERROR(
1485                                 "KMS: Cannot support more than %d display indexes\n",
1486                                         AMDGPU_DM_MAX_DISPLAY_INDEX);
1487                         continue;
1488                 }
1489
1490                 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
1491                 if (!aconnector)
1492                         goto fail;
1493
1494                 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
1495                 if (!aencoder)
1496                         goto fail;
1497
1498                 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
1499                         DRM_ERROR("KMS: Failed to initialize encoder\n");
1500                         goto fail;
1501                 }
1502
1503                 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
1504                         DRM_ERROR("KMS: Failed to initialize connector\n");
1505                         goto fail;
1506                 }
1507
1508                 link = dc_get_link_at_index(dm->dc, i);
1509
1510                 if (dc_link_detect(link, DETECT_REASON_BOOT)) {
1511                         amdgpu_dm_update_connector_after_detect(aconnector);
1512                         register_backlight_device(dm, link);
1513                 }
1514
1515
1516         }
1517
1518         /* Software is initialized. Now we can register interrupt handlers. */
1519         switch (adev->asic_type) {
1520         case CHIP_BONAIRE:
1521         case CHIP_HAWAII:
1522         case CHIP_KAVERI:
1523         case CHIP_KABINI:
1524         case CHIP_MULLINS:
1525         case CHIP_TONGA:
1526         case CHIP_FIJI:
1527         case CHIP_CARRIZO:
1528         case CHIP_STONEY:
1529         case CHIP_POLARIS11:
1530         case CHIP_POLARIS10:
1531         case CHIP_POLARIS12:
1532         case CHIP_VEGA10:
1533         case CHIP_VEGA12:
1534                 if (dce110_register_irq_handlers(dm->adev)) {
1535                         DRM_ERROR("DM: Failed to initialize IRQ\n");
1536                         goto fail;
1537                 }
1538                 break;
1539 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1540         case CHIP_RAVEN:
1541                 if (dcn10_register_irq_handlers(dm->adev)) {
1542                         DRM_ERROR("DM: Failed to initialize IRQ\n");
1543                         goto fail;
1544                 }
1545                 /*
1546                  * Temporary disable until pplib/smu interaction is implemented
1547                  */
1548                 dm->dc->debug.disable_stutter = true;
1549                 break;
1550 #endif
1551         default:
1552                 DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
1553                 goto fail;
1554         }
1555
1556         return 0;
1557 fail:
1558         kfree(aencoder);
1559         kfree(aconnector);
1560         for (i = 0; i < dm->dc->caps.max_planes; i++)
1561                 kfree(mode_info->planes[i]);
1562         return -1;
1563 }
1564
1565 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
1566 {
1567         drm_mode_config_cleanup(dm->ddev);
1568         return;
1569 }
1570
1571 /******************************************************************************
1572  * amdgpu_display_funcs functions
1573  *****************************************************************************/
1574
1575 /**
1576  * dm_bandwidth_update - program display watermarks
1577  *
1578  * @adev: amdgpu_device pointer
1579  *
1580  * Calculate and program the display watermarks and line buffer allocation.
1581  */
1582 static void dm_bandwidth_update(struct amdgpu_device *adev)
1583 {
1584         /* TODO: implement later */
1585 }
1586
1587 static void dm_set_backlight_level(struct amdgpu_encoder *amdgpu_encoder,
1588                                      u8 level)
1589 {
1590         /* TODO: translate amdgpu_encoder to display_index and call DAL */
1591 }
1592
1593 static u8 dm_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder)
1594 {
1595         /* TODO: translate amdgpu_encoder to display_index and call DAL */
1596         return 0;
1597 }
1598
1599 static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
1600                                 struct drm_file *filp)
1601 {
1602         struct mod_freesync_params freesync_params;
1603         uint8_t num_streams;
1604         uint8_t i;
1605
1606         struct amdgpu_device *adev = dev->dev_private;
1607         int r = 0;
1608
1609         /* Get freesync enable flag from DRM */
1610
1611         num_streams = dc_get_current_stream_count(adev->dm.dc);
1612
1613         for (i = 0; i < num_streams; i++) {
1614                 struct dc_stream_state *stream;
1615                 stream = dc_get_stream_at_index(adev->dm.dc, i);
1616
1617                 mod_freesync_update_state(adev->dm.freesync_module,
1618                                           &stream, 1, &freesync_params);
1619         }
1620
1621         return r;
1622 }
1623
1624 static const struct amdgpu_display_funcs dm_display_funcs = {
1625         .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
1626         .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
1627         .backlight_set_level =
1628                 dm_set_backlight_level,/* called unconditionally */
1629         .backlight_get_level =
1630                 dm_get_backlight_level,/* called unconditionally */
1631         .hpd_sense = NULL,/* called unconditionally */
1632         .hpd_set_polarity = NULL, /* called unconditionally */
1633         .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
1634         .page_flip_get_scanoutpos =
1635                 dm_crtc_get_scanoutpos,/* called unconditionally */
1636         .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
1637         .add_connector = NULL, /* VBIOS parsing. DAL does it. */
1638         .notify_freesync = amdgpu_notify_freesync,
1639
1640 };
1641
1642 #if defined(CONFIG_DEBUG_KERNEL_DC)
1643
1644 static ssize_t s3_debug_store(struct device *device,
1645                               struct device_attribute *attr,
1646                               const char *buf,
1647                               size_t count)
1648 {
1649         int ret;
1650         int s3_state;
1651         struct pci_dev *pdev = to_pci_dev(device);
1652         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1653         struct amdgpu_device *adev = drm_dev->dev_private;
1654
1655         ret = kstrtoint(buf, 0, &s3_state);
1656
1657         if (ret == 0) {
1658                 if (s3_state) {
1659                         dm_resume(adev);
1660                         amdgpu_dm_display_resume(adev);
1661                         drm_kms_helper_hotplug_event(adev->ddev);
1662                 } else
1663                         dm_suspend(adev);
1664         }
1665
1666         return ret == 0 ? count : 0;
1667 }
1668
1669 DEVICE_ATTR_WO(s3_debug);
1670
1671 #endif
1672
1673 static int dm_early_init(void *handle)
1674 {
1675         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1676
1677         switch (adev->asic_type) {
1678         case CHIP_BONAIRE:
1679         case CHIP_HAWAII:
1680                 adev->mode_info.num_crtc = 6;
1681                 adev->mode_info.num_hpd = 6;
1682                 adev->mode_info.num_dig = 6;
1683                 adev->mode_info.plane_type = dm_plane_type_default;
1684                 break;
1685         case CHIP_KAVERI:
1686                 adev->mode_info.num_crtc = 4;
1687                 adev->mode_info.num_hpd = 6;
1688                 adev->mode_info.num_dig = 7;
1689                 adev->mode_info.plane_type = dm_plane_type_default;
1690                 break;
1691         case CHIP_KABINI:
1692         case CHIP_MULLINS:
1693                 adev->mode_info.num_crtc = 2;
1694                 adev->mode_info.num_hpd = 6;
1695                 adev->mode_info.num_dig = 6;
1696                 adev->mode_info.plane_type = dm_plane_type_default;
1697                 break;
1698         case CHIP_FIJI:
1699         case CHIP_TONGA:
1700                 adev->mode_info.num_crtc = 6;
1701                 adev->mode_info.num_hpd = 6;
1702                 adev->mode_info.num_dig = 7;
1703                 adev->mode_info.plane_type = dm_plane_type_default;
1704                 break;
1705         case CHIP_CARRIZO:
1706                 adev->mode_info.num_crtc = 3;
1707                 adev->mode_info.num_hpd = 6;
1708                 adev->mode_info.num_dig = 9;
1709                 adev->mode_info.plane_type = dm_plane_type_carizzo;
1710                 break;
1711         case CHIP_STONEY:
1712                 adev->mode_info.num_crtc = 2;
1713                 adev->mode_info.num_hpd = 6;
1714                 adev->mode_info.num_dig = 9;
1715                 adev->mode_info.plane_type = dm_plane_type_stoney;
1716                 break;
1717         case CHIP_POLARIS11:
1718         case CHIP_POLARIS12:
1719                 adev->mode_info.num_crtc = 5;
1720                 adev->mode_info.num_hpd = 5;
1721                 adev->mode_info.num_dig = 5;
1722                 adev->mode_info.plane_type = dm_plane_type_default;
1723                 break;
1724         case CHIP_POLARIS10:
1725                 adev->mode_info.num_crtc = 6;
1726                 adev->mode_info.num_hpd = 6;
1727                 adev->mode_info.num_dig = 6;
1728                 adev->mode_info.plane_type = dm_plane_type_default;
1729                 break;
1730         case CHIP_VEGA10:
1731         case CHIP_VEGA12:
1732                 adev->mode_info.num_crtc = 6;
1733                 adev->mode_info.num_hpd = 6;
1734                 adev->mode_info.num_dig = 6;
1735                 adev->mode_info.plane_type = dm_plane_type_default;
1736                 break;
1737 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1738         case CHIP_RAVEN:
1739                 adev->mode_info.num_crtc = 4;
1740                 adev->mode_info.num_hpd = 4;
1741                 adev->mode_info.num_dig = 4;
1742                 adev->mode_info.plane_type = dm_plane_type_default;
1743                 break;
1744 #endif
1745         default:
1746                 DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
1747                 return -EINVAL;
1748         }
1749
1750         amdgpu_dm_set_irq_funcs(adev);
1751
1752         if (adev->mode_info.funcs == NULL)
1753                 adev->mode_info.funcs = &dm_display_funcs;
1754
1755         /* Note: Do NOT change adev->audio_endpt_rreg and
1756          * adev->audio_endpt_wreg because they are initialised in
1757          * amdgpu_device_init() */
1758 #if defined(CONFIG_DEBUG_KERNEL_DC)
1759         device_create_file(
1760                 adev->ddev->dev,
1761                 &dev_attr_s3_debug);
1762 #endif
1763
1764         return 0;
1765 }
1766
1767 static bool modeset_required(struct drm_crtc_state *crtc_state,
1768                              struct dc_stream_state *new_stream,
1769                              struct dc_stream_state *old_stream)
1770 {
1771         if (!drm_atomic_crtc_needs_modeset(crtc_state))
1772                 return false;
1773
1774         if (!crtc_state->enable)
1775                 return false;
1776
1777         return crtc_state->active;
1778 }
1779
1780 static bool modereset_required(struct drm_crtc_state *crtc_state)
1781 {
1782         if (!drm_atomic_crtc_needs_modeset(crtc_state))
1783                 return false;
1784
1785         return !crtc_state->enable || !crtc_state->active;
1786 }
1787
1788 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
1789 {
1790         drm_encoder_cleanup(encoder);
1791         kfree(encoder);
1792 }
1793
1794 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
1795         .destroy = amdgpu_dm_encoder_destroy,
1796 };
1797
1798 static bool fill_rects_from_plane_state(const struct drm_plane_state *state,
1799                                         struct dc_plane_state *plane_state)
1800 {
1801         plane_state->src_rect.x = state->src_x >> 16;
1802         plane_state->src_rect.y = state->src_y >> 16;
1803         /*we ignore for now mantissa and do not to deal with floating pixels :(*/
1804         plane_state->src_rect.width = state->src_w >> 16;
1805
1806         if (plane_state->src_rect.width == 0)
1807                 return false;
1808
1809         plane_state->src_rect.height = state->src_h >> 16;
1810         if (plane_state->src_rect.height == 0)
1811                 return false;
1812
1813         plane_state->dst_rect.x = state->crtc_x;
1814         plane_state->dst_rect.y = state->crtc_y;
1815
1816         if (state->crtc_w == 0)
1817                 return false;
1818
1819         plane_state->dst_rect.width = state->crtc_w;
1820
1821         if (state->crtc_h == 0)
1822                 return false;
1823
1824         plane_state->dst_rect.height = state->crtc_h;
1825
1826         plane_state->clip_rect = plane_state->dst_rect;
1827
1828         switch (state->rotation & DRM_MODE_ROTATE_MASK) {
1829         case DRM_MODE_ROTATE_0:
1830                 plane_state->rotation = ROTATION_ANGLE_0;
1831                 break;
1832         case DRM_MODE_ROTATE_90:
1833                 plane_state->rotation = ROTATION_ANGLE_90;
1834                 break;
1835         case DRM_MODE_ROTATE_180:
1836                 plane_state->rotation = ROTATION_ANGLE_180;
1837                 break;
1838         case DRM_MODE_ROTATE_270:
1839                 plane_state->rotation = ROTATION_ANGLE_270;
1840                 break;
1841         default:
1842                 plane_state->rotation = ROTATION_ANGLE_0;
1843                 break;
1844         }
1845
1846         return true;
1847 }
1848 static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
1849                        uint64_t *tiling_flags)
1850 {
1851         struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
1852         int r = amdgpu_bo_reserve(rbo, false);
1853
1854         if (unlikely(r)) {
1855                 // Don't show error msg. when return -ERESTARTSYS
1856                 if (r != -ERESTARTSYS)
1857                         DRM_ERROR("Unable to reserve buffer: %d\n", r);
1858                 return r;
1859         }
1860
1861         if (tiling_flags)
1862                 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
1863
1864         amdgpu_bo_unreserve(rbo);
1865
1866         return r;
1867 }
1868
1869 static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
1870                                          struct dc_plane_state *plane_state,
1871                                          const struct amdgpu_framebuffer *amdgpu_fb)
1872 {
1873         uint64_t tiling_flags;
1874         unsigned int awidth;
1875         const struct drm_framebuffer *fb = &amdgpu_fb->base;
1876         int ret = 0;
1877         struct drm_format_name_buf format_name;
1878
1879         ret = get_fb_info(
1880                 amdgpu_fb,
1881                 &tiling_flags);
1882
1883         if (ret)
1884                 return ret;
1885
1886         switch (fb->format->format) {
1887         case DRM_FORMAT_C8:
1888                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
1889                 break;
1890         case DRM_FORMAT_RGB565:
1891                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
1892                 break;
1893         case DRM_FORMAT_XRGB8888:
1894         case DRM_FORMAT_ARGB8888:
1895                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
1896                 break;
1897         case DRM_FORMAT_XRGB2101010:
1898         case DRM_FORMAT_ARGB2101010:
1899                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
1900                 break;
1901         case DRM_FORMAT_XBGR2101010:
1902         case DRM_FORMAT_ABGR2101010:
1903                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
1904                 break;
1905         case DRM_FORMAT_NV21:
1906                 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
1907                 break;
1908         case DRM_FORMAT_NV12:
1909                 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
1910                 break;
1911         default:
1912                 DRM_ERROR("Unsupported screen format %s\n",
1913                           drm_get_format_name(fb->format->format, &format_name));
1914                 return -EINVAL;
1915         }
1916
1917         if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1918                 plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;
1919                 plane_state->plane_size.grph.surface_size.x = 0;
1920                 plane_state->plane_size.grph.surface_size.y = 0;
1921                 plane_state->plane_size.grph.surface_size.width = fb->width;
1922                 plane_state->plane_size.grph.surface_size.height = fb->height;
1923                 plane_state->plane_size.grph.surface_pitch =
1924                                 fb->pitches[0] / fb->format->cpp[0];
1925                 /* TODO: unhardcode */
1926                 plane_state->color_space = COLOR_SPACE_SRGB;
1927
1928         } else {
1929                 awidth = ALIGN(fb->width, 64);
1930                 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
1931                 plane_state->plane_size.video.luma_size.x = 0;
1932                 plane_state->plane_size.video.luma_size.y = 0;
1933                 plane_state->plane_size.video.luma_size.width = awidth;
1934                 plane_state->plane_size.video.luma_size.height = fb->height;
1935                 /* TODO: unhardcode */
1936                 plane_state->plane_size.video.luma_pitch = awidth;
1937
1938                 plane_state->plane_size.video.chroma_size.x = 0;
1939                 plane_state->plane_size.video.chroma_size.y = 0;
1940                 plane_state->plane_size.video.chroma_size.width = awidth;
1941                 plane_state->plane_size.video.chroma_size.height = fb->height;
1942                 plane_state->plane_size.video.chroma_pitch = awidth / 2;
1943
1944                 /* TODO: unhardcode */
1945                 plane_state->color_space = COLOR_SPACE_YCBCR709;
1946         }
1947
1948         memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));
1949
1950         /* Fill GFX8 params */
1951         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
1952                 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
1953
1954                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1955                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1956                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1957                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1958                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1959
1960                 /* XXX fix me for VI */
1961                 plane_state->tiling_info.gfx8.num_banks = num_banks;
1962                 plane_state->tiling_info.gfx8.array_mode =
1963                                 DC_ARRAY_2D_TILED_THIN1;
1964                 plane_state->tiling_info.gfx8.tile_split = tile_split;
1965                 plane_state->tiling_info.gfx8.bank_width = bankw;
1966                 plane_state->tiling_info.gfx8.bank_height = bankh;
1967                 plane_state->tiling_info.gfx8.tile_aspect = mtaspect;
1968                 plane_state->tiling_info.gfx8.tile_mode =
1969                                 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
1970         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
1971                         == DC_ARRAY_1D_TILED_THIN1) {
1972                 plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
1973         }
1974
1975         plane_state->tiling_info.gfx8.pipe_config =
1976                         AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1977
1978         if (adev->asic_type == CHIP_VEGA10 ||
1979             adev->asic_type == CHIP_VEGA12 ||
1980             adev->asic_type == CHIP_RAVEN) {
1981                 /* Fill GFX9 params */
1982                 plane_state->tiling_info.gfx9.num_pipes =
1983                         adev->gfx.config.gb_addr_config_fields.num_pipes;
1984                 plane_state->tiling_info.gfx9.num_banks =
1985                         adev->gfx.config.gb_addr_config_fields.num_banks;
1986                 plane_state->tiling_info.gfx9.pipe_interleave =
1987                         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
1988                 plane_state->tiling_info.gfx9.num_shader_engines =
1989                         adev->gfx.config.gb_addr_config_fields.num_se;
1990                 plane_state->tiling_info.gfx9.max_compressed_frags =
1991                         adev->gfx.config.gb_addr_config_fields.max_compress_frags;
1992                 plane_state->tiling_info.gfx9.num_rb_per_se =
1993                         adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
1994                 plane_state->tiling_info.gfx9.swizzle =
1995                         AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
1996                 plane_state->tiling_info.gfx9.shaderEnable = 1;
1997         }
1998
1999         plane_state->visible = true;
2000         plane_state->scaling_quality.h_taps_c = 0;
2001         plane_state->scaling_quality.v_taps_c = 0;
2002
2003         /* is this needed? is plane_state zeroed at allocation? */
2004         plane_state->scaling_quality.h_taps = 0;
2005         plane_state->scaling_quality.v_taps = 0;
2006         plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE;
2007
2008         return ret;
2009
2010 }
2011
2012 static int fill_plane_attributes(struct amdgpu_device *adev,
2013                                  struct dc_plane_state *dc_plane_state,
2014                                  struct drm_plane_state *plane_state,
2015                                  struct drm_crtc_state *crtc_state)
2016 {
2017         const struct amdgpu_framebuffer *amdgpu_fb =
2018                 to_amdgpu_framebuffer(plane_state->fb);
2019         const struct drm_crtc *crtc = plane_state->crtc;
2020         struct dc_transfer_func *input_tf;
2021         int ret = 0;
2022
2023         if (!fill_rects_from_plane_state(plane_state, dc_plane_state))
2024                 return -EINVAL;
2025
2026         ret = fill_plane_attributes_from_fb(
2027                 crtc->dev->dev_private,
2028                 dc_plane_state,
2029                 amdgpu_fb);
2030
2031         if (ret)
2032                 return ret;
2033
2034         input_tf = dc_create_transfer_func();
2035
2036         if (input_tf == NULL)
2037                 return -ENOMEM;
2038
2039         dc_plane_state->in_transfer_func = input_tf;
2040
2041         /*
2042          * Always set input transfer function, since plane state is refreshed
2043          * every time.
2044          */
2045         ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state);
2046         if (ret) {
2047                 dc_transfer_func_release(dc_plane_state->in_transfer_func);
2048                 dc_plane_state->in_transfer_func = NULL;
2049         }
2050
2051         return ret;
2052 }
2053
2054 /*****************************************************************************/
2055
2056 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
2057                                            const struct dm_connector_state *dm_state,
2058                                            struct dc_stream_state *stream)
2059 {
2060         enum amdgpu_rmx_type rmx_type;
2061
2062         struct rect src = { 0 }; /* viewport in composition space*/
2063         struct rect dst = { 0 }; /* stream addressable area */
2064
2065         /* no mode. nothing to be done */
2066         if (!mode)
2067                 return;
2068
2069         /* Full screen scaling by default */
2070         src.width = mode->hdisplay;
2071         src.height = mode->vdisplay;
2072         dst.width = stream->timing.h_addressable;
2073         dst.height = stream->timing.v_addressable;
2074
2075         if (dm_state) {
2076                 rmx_type = dm_state->scaling;
2077                 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
2078                         if (src.width * dst.height <
2079                                         src.height * dst.width) {
2080                                 /* height needs less upscaling/more downscaling */
2081                                 dst.width = src.width *
2082                                                 dst.height / src.height;
2083                         } else {
2084                                 /* width needs less upscaling/more downscaling */
2085                                 dst.height = src.height *
2086                                                 dst.width / src.width;
2087                         }
2088                 } else if (rmx_type == RMX_CENTER) {
2089                         dst = src;
2090                 }
2091
2092                 dst.x = (stream->timing.h_addressable - dst.width) / 2;
2093                 dst.y = (stream->timing.v_addressable - dst.height) / 2;
2094
2095                 if (dm_state->underscan_enable) {
2096                         dst.x += dm_state->underscan_hborder / 2;
2097                         dst.y += dm_state->underscan_vborder / 2;
2098                         dst.width -= dm_state->underscan_hborder;
2099                         dst.height -= dm_state->underscan_vborder;
2100                 }
2101         }
2102
2103         stream->src = src;
2104         stream->dst = dst;
2105
2106         DRM_DEBUG_DRIVER("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
2107                         dst.x, dst.y, dst.width, dst.height);
2108
2109 }
2110
2111 static enum dc_color_depth
2112 convert_color_depth_from_display_info(const struct drm_connector *connector)
2113 {
2114         uint32_t bpc = connector->display_info.bpc;
2115
2116         /* Limited color depth to 8bit
2117          * TODO: Still need to handle deep color
2118          */
2119         if (bpc > 8)
2120                 bpc = 8;
2121
2122         switch (bpc) {
2123         case 0:
2124                 /* Temporary Work around, DRM don't parse color depth for
2125                  * EDID revision before 1.4
2126                  * TODO: Fix edid parsing
2127                  */
2128                 return COLOR_DEPTH_888;
2129         case 6:
2130                 return COLOR_DEPTH_666;
2131         case 8:
2132                 return COLOR_DEPTH_888;
2133         case 10:
2134                 return COLOR_DEPTH_101010;
2135         case 12:
2136                 return COLOR_DEPTH_121212;
2137         case 14:
2138                 return COLOR_DEPTH_141414;
2139         case 16:
2140                 return COLOR_DEPTH_161616;
2141         default:
2142                 return COLOR_DEPTH_UNDEFINED;
2143         }
2144 }
2145
2146 static enum dc_aspect_ratio
2147 get_aspect_ratio(const struct drm_display_mode *mode_in)
2148 {
2149         int32_t width = mode_in->crtc_hdisplay * 9;
2150         int32_t height = mode_in->crtc_vdisplay * 16;
2151
2152         if ((width - height) < 10 && (width - height) > -10)
2153                 return ASPECT_RATIO_16_9;
2154         else
2155                 return ASPECT_RATIO_4_3;
2156 }
2157
2158 static enum dc_color_space
2159 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
2160 {
2161         enum dc_color_space color_space = COLOR_SPACE_SRGB;
2162
2163         switch (dc_crtc_timing->pixel_encoding) {
2164         case PIXEL_ENCODING_YCBCR422:
2165         case PIXEL_ENCODING_YCBCR444:
2166         case PIXEL_ENCODING_YCBCR420:
2167         {
2168                 /*
2169                  * 27030khz is the separation point between HDTV and SDTV
2170                  * according to HDMI spec, we use YCbCr709 and YCbCr601
2171                  * respectively
2172                  */
2173                 if (dc_crtc_timing->pix_clk_khz > 27030) {
2174                         if (dc_crtc_timing->flags.Y_ONLY)
2175                                 color_space =
2176                                         COLOR_SPACE_YCBCR709_LIMITED;
2177                         else
2178                                 color_space = COLOR_SPACE_YCBCR709;
2179                 } else {
2180                         if (dc_crtc_timing->flags.Y_ONLY)
2181                                 color_space =
2182                                         COLOR_SPACE_YCBCR601_LIMITED;
2183                         else
2184                                 color_space = COLOR_SPACE_YCBCR601;
2185                 }
2186
2187         }
2188         break;
2189         case PIXEL_ENCODING_RGB:
2190                 color_space = COLOR_SPACE_SRGB;
2191                 break;
2192
2193         default:
2194                 WARN_ON(1);
2195                 break;
2196         }
2197
2198         return color_space;
2199 }
2200
2201 /*****************************************************************************/
2202
2203 static void
2204 fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
2205                                              const struct drm_display_mode *mode_in,
2206                                              const struct drm_connector *connector)
2207 {
2208         struct dc_crtc_timing *timing_out = &stream->timing;
2209         struct dc_transfer_func *tf = dc_create_transfer_func();
2210
2211         memset(timing_out, 0, sizeof(struct dc_crtc_timing));
2212
2213         timing_out->h_border_left = 0;
2214         timing_out->h_border_right = 0;
2215         timing_out->v_border_top = 0;
2216         timing_out->v_border_bottom = 0;
2217         /* TODO: un-hardcode */
2218
2219         if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
2220                         && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2221                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
2222         else
2223                 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
2224
2225         timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
2226         timing_out->display_color_depth = convert_color_depth_from_display_info(
2227                         connector);
2228         timing_out->scan_type = SCANNING_TYPE_NODATA;
2229         timing_out->hdmi_vic = 0;
2230         timing_out->vic = drm_match_cea_mode(mode_in);
2231
2232         timing_out->h_addressable = mode_in->crtc_hdisplay;
2233         timing_out->h_total = mode_in->crtc_htotal;
2234         timing_out->h_sync_width =
2235                 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
2236         timing_out->h_front_porch =
2237                 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
2238         timing_out->v_total = mode_in->crtc_vtotal;
2239         timing_out->v_addressable = mode_in->crtc_vdisplay;
2240         timing_out->v_front_porch =
2241                 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
2242         timing_out->v_sync_width =
2243                 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
2244         timing_out->pix_clk_khz = mode_in->crtc_clock;
2245         timing_out->aspect_ratio = get_aspect_ratio(mode_in);
2246         if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
2247                 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
2248         if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
2249                 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
2250
2251         stream->output_color_space = get_output_color_space(timing_out);
2252
2253         tf->type = TF_TYPE_PREDEFINED;
2254         tf->tf = TRANSFER_FUNCTION_SRGB;
2255         stream->out_transfer_func = tf;
2256 }
2257
2258 static void fill_audio_info(struct audio_info *audio_info,
2259                             const struct drm_connector *drm_connector,
2260                             const struct dc_sink *dc_sink)
2261 {
2262         int i = 0;
2263         int cea_revision = 0;
2264         const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
2265
2266         audio_info->manufacture_id = edid_caps->manufacturer_id;
2267         audio_info->product_id = edid_caps->product_id;
2268
2269         cea_revision = drm_connector->display_info.cea_rev;
2270
2271         strncpy(audio_info->display_name,
2272                 edid_caps->display_name,
2273                 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS - 1);
2274
2275         if (cea_revision >= 3) {
2276                 audio_info->mode_count = edid_caps->audio_mode_count;
2277
2278                 for (i = 0; i < audio_info->mode_count; ++i) {
2279                         audio_info->modes[i].format_code =
2280                                         (enum audio_format_code)
2281                                         (edid_caps->audio_modes[i].format_code);
2282                         audio_info->modes[i].channel_count =
2283                                         edid_caps->audio_modes[i].channel_count;
2284                         audio_info->modes[i].sample_rates.all =
2285                                         edid_caps->audio_modes[i].sample_rate;
2286                         audio_info->modes[i].sample_size =
2287                                         edid_caps->audio_modes[i].sample_size;
2288                 }
2289         }
2290
2291         audio_info->flags.all = edid_caps->speaker_flags;
2292
2293         /* TODO: We only check for the progressive mode, check for interlace mode too */
2294         if (drm_connector->latency_present[0]) {
2295                 audio_info->video_latency = drm_connector->video_latency[0];
2296                 audio_info->audio_latency = drm_connector->audio_latency[0];
2297         }
2298
2299         /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
2300
2301 }
2302
2303 static void
2304 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
2305                                       struct drm_display_mode *dst_mode)
2306 {
2307         dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
2308         dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
2309         dst_mode->crtc_clock = src_mode->crtc_clock;
2310         dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
2311         dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
2312         dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
2313         dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
2314         dst_mode->crtc_htotal = src_mode->crtc_htotal;
2315         dst_mode->crtc_hskew = src_mode->crtc_hskew;
2316         dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
2317         dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
2318         dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
2319         dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
2320         dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
2321 }
2322
2323 static void
2324 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
2325                                         const struct drm_display_mode *native_mode,
2326                                         bool scale_enabled)
2327 {
2328         if (scale_enabled) {
2329                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2330         } else if (native_mode->clock == drm_mode->clock &&
2331                         native_mode->htotal == drm_mode->htotal &&
2332                         native_mode->vtotal == drm_mode->vtotal) {
2333                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2334         } else {
2335                 /* no scaling nor amdgpu inserted, no need to patch */
2336         }
2337 }
2338
2339 static int create_fake_sink(struct amdgpu_dm_connector *aconnector)
2340 {
2341         struct dc_sink *sink = NULL;
2342         struct dc_sink_init_data sink_init_data = { 0 };
2343
2344         sink_init_data.link = aconnector->dc_link;
2345         sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
2346
2347         sink = dc_sink_create(&sink_init_data);
2348         if (!sink) {
2349                 DRM_ERROR("Failed to create sink!\n");
2350                 return -ENOMEM;
2351         }
2352
2353         sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
2354         aconnector->fake_enable = true;
2355
2356         aconnector->dc_sink = sink;
2357         aconnector->dc_link->local_sink = sink;
2358
2359         return 0;
2360 }
2361
2362 static void set_multisync_trigger_params(
2363                 struct dc_stream_state *stream)
2364 {
2365         if (stream->triggered_crtc_reset.enabled) {
2366                 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
2367                 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
2368         }
2369 }
2370
2371 static void set_master_stream(struct dc_stream_state *stream_set[],
2372                               int stream_count)
2373 {
2374         int j, highest_rfr = 0, master_stream = 0;
2375
2376         for (j = 0;  j < stream_count; j++) {
2377                 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
2378                         int refresh_rate = 0;
2379
2380                         refresh_rate = (stream_set[j]->timing.pix_clk_khz*1000)/
2381                                 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
2382                         if (refresh_rate > highest_rfr) {
2383                                 highest_rfr = refresh_rate;
2384                                 master_stream = j;
2385                         }
2386                 }
2387         }
2388         for (j = 0;  j < stream_count; j++) {
2389                 if (stream_set[j])
2390                         stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
2391         }
2392 }
2393
2394 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
2395 {
2396         int i = 0;
2397
2398         if (context->stream_count < 2)
2399                 return;
2400         for (i = 0; i < context->stream_count ; i++) {
2401                 if (!context->streams[i])
2402                         continue;
2403                 /* TODO: add a function to read AMD VSDB bits and will set
2404                  * crtc_sync_master.multi_sync_enabled flag
2405                  * For now its set to false
2406                  */
2407                 set_multisync_trigger_params(context->streams[i]);
2408         }
2409         set_master_stream(context->streams, context->stream_count);
2410 }
2411
2412 static struct dc_stream_state *
2413 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
2414                        const struct drm_display_mode *drm_mode,
2415                        const struct dm_connector_state *dm_state)
2416 {
2417         struct drm_display_mode *preferred_mode = NULL;
2418         struct drm_connector *drm_connector;
2419         struct dc_stream_state *stream = NULL;
2420         struct drm_display_mode mode = *drm_mode;
2421         bool native_mode_found = false;
2422
2423         if (aconnector == NULL) {
2424                 DRM_ERROR("aconnector is NULL!\n");
2425                 return stream;
2426         }
2427
2428         drm_connector = &aconnector->base;
2429
2430         if (!aconnector->dc_sink) {
2431                 /*
2432                  * Create dc_sink when necessary to MST
2433                  * Don't apply fake_sink to MST
2434                  */
2435                 if (aconnector->mst_port) {
2436                         dm_dp_mst_dc_sink_create(drm_connector);
2437                         return stream;
2438                 }
2439
2440                 if (create_fake_sink(aconnector))
2441                         return stream;
2442         }
2443
2444         stream = dc_create_stream_for_sink(aconnector->dc_sink);
2445
2446         if (stream == NULL) {
2447                 DRM_ERROR("Failed to create stream for sink!\n");
2448                 return stream;
2449         }
2450
2451         list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
2452                 /* Search for preferred mode */
2453                 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
2454                         native_mode_found = true;
2455                         break;
2456                 }
2457         }
2458         if (!native_mode_found)
2459                 preferred_mode = list_first_entry_or_null(
2460                                 &aconnector->base.modes,
2461                                 struct drm_display_mode,
2462                                 head);
2463
2464         if (preferred_mode == NULL) {
2465                 /* This may not be an error, the use case is when we we have no
2466                  * usermode calls to reset and set mode upon hotplug. In this
2467                  * case, we call set mode ourselves to restore the previous mode
2468                  * and the modelist may not be filled in in time.
2469                  */
2470                 DRM_DEBUG_DRIVER("No preferred mode found\n");
2471         } else {
2472                 decide_crtc_timing_for_drm_display_mode(
2473                                 &mode, preferred_mode,
2474                                 dm_state ? (dm_state->scaling != RMX_OFF) : false);
2475         }
2476
2477         if (!dm_state)
2478                 drm_mode_set_crtcinfo(&mode, 0);
2479
2480         fill_stream_properties_from_drm_display_mode(stream,
2481                         &mode, &aconnector->base);
2482         update_stream_scaling_settings(&mode, dm_state, stream);
2483
2484         fill_audio_info(
2485                 &stream->audio_info,
2486                 drm_connector,
2487                 aconnector->dc_sink);
2488
2489         update_stream_signal(stream);
2490
2491         return stream;
2492 }
2493
2494 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
2495 {
2496         drm_crtc_cleanup(crtc);
2497         kfree(crtc);
2498 }
2499
2500 static void dm_crtc_destroy_state(struct drm_crtc *crtc,
2501                                   struct drm_crtc_state *state)
2502 {
2503         struct dm_crtc_state *cur = to_dm_crtc_state(state);
2504
2505         /* TODO Destroy dc_stream objects are stream object is flattened */
2506         if (cur->stream)
2507                 dc_stream_release(cur->stream);
2508
2509
2510         __drm_atomic_helper_crtc_destroy_state(state);
2511
2512
2513         kfree(state);
2514 }
2515
2516 static void dm_crtc_reset_state(struct drm_crtc *crtc)
2517 {
2518         struct dm_crtc_state *state;
2519
2520         if (crtc->state)
2521                 dm_crtc_destroy_state(crtc, crtc->state);
2522
2523         state = kzalloc(sizeof(*state), GFP_KERNEL);
2524         if (WARN_ON(!state))
2525                 return;
2526
2527         crtc->state = &state->base;
2528         crtc->state->crtc = crtc;
2529
2530 }
2531
2532 static struct drm_crtc_state *
2533 dm_crtc_duplicate_state(struct drm_crtc *crtc)
2534 {
2535         struct dm_crtc_state *state, *cur;
2536
2537         cur = to_dm_crtc_state(crtc->state);
2538
2539         if (WARN_ON(!crtc->state))
2540                 return NULL;
2541
2542         state = kzalloc(sizeof(*state), GFP_KERNEL);
2543         if (!state)
2544                 return NULL;
2545
2546         __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
2547
2548         if (cur->stream) {
2549                 state->stream = cur->stream;
2550                 dc_stream_retain(state->stream);
2551         }
2552
2553         /* TODO Duplicate dc_stream after objects are stream object is flattened */
2554
2555         return &state->base;
2556 }
2557
2558
2559 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
2560 {
2561         enum dc_irq_source irq_source;
2562         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2563         struct amdgpu_device *adev = crtc->dev->dev_private;
2564
2565         irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
2566         return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2567 }
2568
2569 static int dm_enable_vblank(struct drm_crtc *crtc)
2570 {
2571         return dm_set_vblank(crtc, true);
2572 }
2573
2574 static void dm_disable_vblank(struct drm_crtc *crtc)
2575 {
2576         dm_set_vblank(crtc, false);
2577 }
2578
2579 /* Implemented only the options currently availible for the driver */
2580 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
2581         .reset = dm_crtc_reset_state,
2582         .destroy = amdgpu_dm_crtc_destroy,
2583         .gamma_set = drm_atomic_helper_legacy_gamma_set,
2584         .set_config = drm_atomic_helper_set_config,
2585         .page_flip = drm_atomic_helper_page_flip,
2586         .atomic_duplicate_state = dm_crtc_duplicate_state,
2587         .atomic_destroy_state = dm_crtc_destroy_state,
2588         .set_crc_source = amdgpu_dm_crtc_set_crc_source,
2589         .enable_vblank = dm_enable_vblank,
2590         .disable_vblank = dm_disable_vblank,
2591 };
2592
2593 static enum drm_connector_status
2594 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
2595 {
2596         bool connected;
2597         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2598
2599         /* Notes:
2600          * 1. This interface is NOT called in context of HPD irq.
2601          * 2. This interface *is called* in context of user-mode ioctl. Which
2602          * makes it a bad place for *any* MST-related activit. */
2603
2604         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
2605             !aconnector->fake_enable)
2606                 connected = (aconnector->dc_sink != NULL);
2607         else
2608                 connected = (aconnector->base.force == DRM_FORCE_ON);
2609
2610         return (connected ? connector_status_connected :
2611                         connector_status_disconnected);
2612 }
2613
2614 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
2615                                             struct drm_connector_state *connector_state,
2616                                             struct drm_property *property,
2617                                             uint64_t val)
2618 {
2619         struct drm_device *dev = connector->dev;
2620         struct amdgpu_device *adev = dev->dev_private;
2621         struct dm_connector_state *dm_old_state =
2622                 to_dm_connector_state(connector->state);
2623         struct dm_connector_state *dm_new_state =
2624                 to_dm_connector_state(connector_state);
2625
2626         int ret = -EINVAL;
2627
2628         if (property == dev->mode_config.scaling_mode_property) {
2629                 enum amdgpu_rmx_type rmx_type;
2630
2631                 switch (val) {
2632                 case DRM_MODE_SCALE_CENTER:
2633                         rmx_type = RMX_CENTER;
2634                         break;
2635                 case DRM_MODE_SCALE_ASPECT:
2636                         rmx_type = RMX_ASPECT;
2637                         break;
2638                 case DRM_MODE_SCALE_FULLSCREEN:
2639                         rmx_type = RMX_FULL;
2640                         break;
2641                 case DRM_MODE_SCALE_NONE:
2642                 default:
2643                         rmx_type = RMX_OFF;
2644                         break;
2645                 }
2646
2647                 if (dm_old_state->scaling == rmx_type)
2648                         return 0;
2649
2650                 dm_new_state->scaling = rmx_type;
2651                 ret = 0;
2652         } else if (property == adev->mode_info.underscan_hborder_property) {
2653                 dm_new_state->underscan_hborder = val;
2654                 ret = 0;
2655         } else if (property == adev->mode_info.underscan_vborder_property) {
2656                 dm_new_state->underscan_vborder = val;
2657                 ret = 0;
2658         } else if (property == adev->mode_info.underscan_property) {
2659                 dm_new_state->underscan_enable = val;
2660                 ret = 0;
2661         }
2662
2663         return ret;
2664 }
2665
2666 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
2667                                             const struct drm_connector_state *state,
2668                                             struct drm_property *property,
2669                                             uint64_t *val)
2670 {
2671         struct drm_device *dev = connector->dev;
2672         struct amdgpu_device *adev = dev->dev_private;
2673         struct dm_connector_state *dm_state =
2674                 to_dm_connector_state(state);
2675         int ret = -EINVAL;
2676
2677         if (property == dev->mode_config.scaling_mode_property) {
2678                 switch (dm_state->scaling) {
2679                 case RMX_CENTER:
2680                         *val = DRM_MODE_SCALE_CENTER;
2681                         break;
2682                 case RMX_ASPECT:
2683                         *val = DRM_MODE_SCALE_ASPECT;
2684                         break;
2685                 case RMX_FULL:
2686                         *val = DRM_MODE_SCALE_FULLSCREEN;
2687                         break;
2688                 case RMX_OFF:
2689                 default:
2690                         *val = DRM_MODE_SCALE_NONE;
2691                         break;
2692                 }
2693                 ret = 0;
2694         } else if (property == adev->mode_info.underscan_hborder_property) {
2695                 *val = dm_state->underscan_hborder;
2696                 ret = 0;
2697         } else if (property == adev->mode_info.underscan_vborder_property) {
2698                 *val = dm_state->underscan_vborder;
2699                 ret = 0;
2700         } else if (property == adev->mode_info.underscan_property) {
2701                 *val = dm_state->underscan_enable;
2702                 ret = 0;
2703         }
2704         return ret;
2705 }
2706
2707 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
2708 {
2709         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2710         const struct dc_link *link = aconnector->dc_link;
2711         struct amdgpu_device *adev = connector->dev->dev_private;
2712         struct amdgpu_display_manager *dm = &adev->dm;
2713 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2714         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2715
2716         if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
2717             link->type != dc_connection_none) {
2718                 amdgpu_dm_register_backlight_device(dm);
2719
2720                 if (dm->backlight_dev) {
2721                         backlight_device_unregister(dm->backlight_dev);
2722                         dm->backlight_dev = NULL;
2723                 }
2724
2725         }
2726 #endif
2727         drm_connector_unregister(connector);
2728         drm_connector_cleanup(connector);
2729         kfree(connector);
2730 }
2731
2732 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
2733 {
2734         struct dm_connector_state *state =
2735                 to_dm_connector_state(connector->state);
2736
2737         kfree(state);
2738
2739         state = kzalloc(sizeof(*state), GFP_KERNEL);
2740
2741         if (state) {
2742                 state->scaling = RMX_OFF;
2743                 state->underscan_enable = false;
2744                 state->underscan_hborder = 0;
2745                 state->underscan_vborder = 0;
2746
2747                 connector->state = &state->base;
2748                 connector->state->connector = connector;
2749         }
2750 }
2751
2752 struct drm_connector_state *
2753 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
2754 {
2755         struct dm_connector_state *state =
2756                 to_dm_connector_state(connector->state);
2757
2758         struct dm_connector_state *new_state =
2759                         kmemdup(state, sizeof(*state), GFP_KERNEL);
2760
2761         if (new_state) {
2762                 __drm_atomic_helper_connector_duplicate_state(connector,
2763                                                               &new_state->base);
2764                 return &new_state->base;
2765         }
2766
2767         return NULL;
2768 }
2769
2770 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
2771         .reset = amdgpu_dm_connector_funcs_reset,
2772         .detect = amdgpu_dm_connector_detect,
2773         .fill_modes = drm_helper_probe_single_connector_modes,
2774         .destroy = amdgpu_dm_connector_destroy,
2775         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
2776         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2777         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
2778         .atomic_get_property = amdgpu_dm_connector_atomic_get_property
2779 };
2780
2781 static struct drm_encoder *best_encoder(struct drm_connector *connector)
2782 {
2783         int enc_id = connector->encoder_ids[0];
2784         struct drm_mode_object *obj;
2785         struct drm_encoder *encoder;
2786
2787         DRM_DEBUG_DRIVER("Finding the best encoder\n");
2788
2789         /* pick the encoder ids */
2790         if (enc_id) {
2791                 obj = drm_mode_object_find(connector->dev, NULL, enc_id, DRM_MODE_OBJECT_ENCODER);
2792                 if (!obj) {
2793                         DRM_ERROR("Couldn't find a matching encoder for our connector\n");
2794                         return NULL;
2795                 }
2796                 encoder = obj_to_encoder(obj);
2797                 return encoder;
2798         }
2799         DRM_ERROR("No encoder id\n");
2800         return NULL;
2801 }
2802
2803 static int get_modes(struct drm_connector *connector)
2804 {
2805         return amdgpu_dm_connector_get_modes(connector);
2806 }
2807
2808 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
2809 {
2810         struct dc_sink_init_data init_params = {
2811                         .link = aconnector->dc_link,
2812                         .sink_signal = SIGNAL_TYPE_VIRTUAL
2813         };
2814         struct edid *edid;
2815
2816         if (!aconnector->base.edid_blob_ptr) {
2817                 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
2818                                 aconnector->base.name);
2819
2820                 aconnector->base.force = DRM_FORCE_OFF;
2821                 aconnector->base.override_edid = false;
2822                 return;
2823         }
2824
2825         edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
2826
2827         aconnector->edid = edid;
2828
2829         aconnector->dc_em_sink = dc_link_add_remote_sink(
2830                 aconnector->dc_link,
2831                 (uint8_t *)edid,
2832                 (edid->extensions + 1) * EDID_LENGTH,
2833                 &init_params);
2834
2835         if (aconnector->base.force == DRM_FORCE_ON)
2836                 aconnector->dc_sink = aconnector->dc_link->local_sink ?
2837                 aconnector->dc_link->local_sink :
2838                 aconnector->dc_em_sink;
2839 }
2840
2841 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
2842 {
2843         struct dc_link *link = (struct dc_link *)aconnector->dc_link;
2844
2845         /* In case of headless boot with force on for DP managed connector
2846          * Those settings have to be != 0 to get initial modeset
2847          */
2848         if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
2849                 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
2850                 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
2851         }
2852
2853
2854         aconnector->base.override_edid = true;
2855         create_eml_sink(aconnector);
2856 }
2857
2858 int amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
2859                                    struct drm_display_mode *mode)
2860 {
2861         int result = MODE_ERROR;
2862         struct dc_sink *dc_sink;
2863         struct amdgpu_device *adev = connector->dev->dev_private;
2864         /* TODO: Unhardcode stream count */
2865         struct dc_stream_state *stream;
2866         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2867         enum dc_status dc_result = DC_OK;
2868
2869         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
2870                         (mode->flags & DRM_MODE_FLAG_DBLSCAN))
2871                 return result;
2872
2873         /* Only run this the first time mode_valid is called to initilialize
2874          * EDID mgmt
2875          */
2876         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
2877                 !aconnector->dc_em_sink)
2878                 handle_edid_mgmt(aconnector);
2879
2880         dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
2881
2882         if (dc_sink == NULL) {
2883                 DRM_ERROR("dc_sink is NULL!\n");
2884                 goto fail;
2885         }
2886
2887         stream = create_stream_for_sink(aconnector, mode, NULL);
2888         if (stream == NULL) {
2889                 DRM_ERROR("Failed to create stream for sink!\n");
2890                 goto fail;
2891         }
2892
2893         dc_result = dc_validate_stream(adev->dm.dc, stream);
2894
2895         if (dc_result == DC_OK)
2896                 result = MODE_OK;
2897         else
2898                 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
2899                               mode->vdisplay,
2900                               mode->hdisplay,
2901                               mode->clock,
2902                               dc_result);
2903
2904         dc_stream_release(stream);
2905
2906 fail:
2907         /* TODO: error handling*/
2908         return result;
2909 }
2910
2911 static const struct drm_connector_helper_funcs
2912 amdgpu_dm_connector_helper_funcs = {
2913         /*
2914          * If hotplug a second bigger display in FB Con mode, bigger resolution
2915          * modes will be filtered by drm_mode_validate_size(), and those modes
2916          * is missing after user start lightdm. So we need to renew modes list.
2917          * in get_modes call back, not just return the modes count
2918          */
2919         .get_modes = get_modes,
2920         .mode_valid = amdgpu_dm_connector_mode_valid,
2921         .best_encoder = best_encoder
2922 };
2923
2924 static void dm_crtc_helper_disable(struct drm_crtc *crtc)
2925 {
2926 }
2927
2928 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
2929                                        struct drm_crtc_state *state)
2930 {
2931         struct amdgpu_device *adev = crtc->dev->dev_private;
2932         struct dc *dc = adev->dm.dc;
2933         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
2934         int ret = -EINVAL;
2935
2936         if (unlikely(!dm_crtc_state->stream &&
2937                      modeset_required(state, NULL, dm_crtc_state->stream))) {
2938                 WARN_ON(1);
2939                 return ret;
2940         }
2941
2942         /* In some use cases, like reset, no stream  is attached */
2943         if (!dm_crtc_state->stream)
2944                 return 0;
2945
2946         if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
2947                 return 0;
2948
2949         return ret;
2950 }
2951
2952 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
2953                                       const struct drm_display_mode *mode,
2954                                       struct drm_display_mode *adjusted_mode)
2955 {
2956         return true;
2957 }
2958
2959 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
2960         .disable = dm_crtc_helper_disable,
2961         .atomic_check = dm_crtc_helper_atomic_check,
2962         .mode_fixup = dm_crtc_helper_mode_fixup
2963 };
2964
2965 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
2966 {
2967
2968 }
2969
2970 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
2971                                           struct drm_crtc_state *crtc_state,
2972                                           struct drm_connector_state *conn_state)
2973 {
2974         return 0;
2975 }
2976
2977 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
2978         .disable = dm_encoder_helper_disable,
2979         .atomic_check = dm_encoder_helper_atomic_check
2980 };
2981
2982 static void dm_drm_plane_reset(struct drm_plane *plane)
2983 {
2984         struct dm_plane_state *amdgpu_state = NULL;
2985
2986         if (plane->state)
2987                 plane->funcs->atomic_destroy_state(plane, plane->state);
2988
2989         amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
2990         WARN_ON(amdgpu_state == NULL);
2991
2992         if (amdgpu_state) {
2993                 plane->state = &amdgpu_state->base;
2994                 plane->state->plane = plane;
2995                 plane->state->rotation = DRM_MODE_ROTATE_0;
2996         }
2997 }
2998
2999 static struct drm_plane_state *
3000 dm_drm_plane_duplicate_state(struct drm_plane *plane)
3001 {
3002         struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
3003
3004         old_dm_plane_state = to_dm_plane_state(plane->state);
3005         dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
3006         if (!dm_plane_state)
3007                 return NULL;
3008
3009         __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
3010
3011         if (old_dm_plane_state->dc_state) {
3012                 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
3013                 dc_plane_state_retain(dm_plane_state->dc_state);
3014         }
3015
3016         return &dm_plane_state->base;
3017 }
3018
3019 void dm_drm_plane_destroy_state(struct drm_plane *plane,
3020                                 struct drm_plane_state *state)
3021 {
3022         struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3023
3024         if (dm_plane_state->dc_state)
3025                 dc_plane_state_release(dm_plane_state->dc_state);
3026
3027         drm_atomic_helper_plane_destroy_state(plane, state);
3028 }
3029
3030 static const struct drm_plane_funcs dm_plane_funcs = {
3031         .update_plane   = drm_atomic_helper_update_plane,
3032         .disable_plane  = drm_atomic_helper_disable_plane,
3033         .destroy        = drm_plane_cleanup,
3034         .reset = dm_drm_plane_reset,
3035         .atomic_duplicate_state = dm_drm_plane_duplicate_state,
3036         .atomic_destroy_state = dm_drm_plane_destroy_state,
3037 };
3038
3039 static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
3040                                       struct drm_plane_state *new_state)
3041 {
3042         struct amdgpu_framebuffer *afb;
3043         struct drm_gem_object *obj;
3044         struct amdgpu_device *adev;
3045         struct amdgpu_bo *rbo;
3046         uint64_t chroma_addr = 0;
3047         struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
3048         unsigned int awidth;
3049         uint32_t domain;
3050         int r;
3051
3052         dm_plane_state_old = to_dm_plane_state(plane->state);
3053         dm_plane_state_new = to_dm_plane_state(new_state);
3054
3055         if (!new_state->fb) {
3056                 DRM_DEBUG_DRIVER("No FB bound\n");
3057                 return 0;
3058         }
3059
3060         afb = to_amdgpu_framebuffer(new_state->fb);
3061
3062         obj = afb->obj;
3063         rbo = gem_to_amdgpu_bo(obj);
3064         adev = amdgpu_ttm_adev(rbo->tbo.bdev);
3065         r = amdgpu_bo_reserve(rbo, false);
3066         if (unlikely(r != 0))
3067                 return r;
3068
3069         if (plane->type != DRM_PLANE_TYPE_CURSOR)
3070                 domain = amdgpu_display_framebuffer_domains(adev);
3071         else
3072                 domain = AMDGPU_GEM_DOMAIN_VRAM;
3073
3074         r = amdgpu_bo_pin(rbo, domain, &afb->address);
3075
3076         amdgpu_bo_unreserve(rbo);
3077
3078         if (unlikely(r != 0)) {
3079                 if (r != -ERESTARTSYS)
3080                         DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
3081                 return r;
3082         }
3083
3084         amdgpu_bo_ref(rbo);
3085
3086         if (dm_plane_state_new->dc_state &&
3087                         dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
3088                 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
3089
3090                 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
3091                         plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);
3092                         plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
3093                 } else {
3094                         awidth = ALIGN(new_state->fb->width, 64);
3095                         plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3096                         plane_state->address.video_progressive.luma_addr.low_part
3097                                                         = lower_32_bits(afb->address);
3098                         plane_state->address.video_progressive.luma_addr.high_part
3099                                                         = upper_32_bits(afb->address);
3100                         chroma_addr = afb->address + (u64)awidth * new_state->fb->height;
3101                         plane_state->address.video_progressive.chroma_addr.low_part
3102                                                         = lower_32_bits(chroma_addr);
3103                         plane_state->address.video_progressive.chroma_addr.high_part
3104                                                         = upper_32_bits(chroma_addr);
3105                 }
3106         }
3107
3108         /* It's a hack for s3 since in 4.9 kernel filter out cursor buffer
3109          * prepare and cleanup in drm_atomic_helper_prepare_planes
3110          * and drm_atomic_helper_cleanup_planes because fb doens't in s3.
3111          * IN 4.10 kernel this code should be removed and amdgpu_device_suspend
3112          * code touching fram buffers should be avoided for DC.
3113          */
3114         if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3115                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_state->crtc);
3116
3117                 acrtc->cursor_bo = obj;
3118         }
3119         return 0;
3120 }
3121
3122 static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
3123                                        struct drm_plane_state *old_state)
3124 {
3125         struct amdgpu_bo *rbo;
3126         struct amdgpu_framebuffer *afb;
3127         int r;
3128
3129         if (!old_state->fb)
3130                 return;
3131
3132         afb = to_amdgpu_framebuffer(old_state->fb);
3133         rbo = gem_to_amdgpu_bo(afb->obj);
3134         r = amdgpu_bo_reserve(rbo, false);
3135         if (unlikely(r)) {
3136                 DRM_ERROR("failed to reserve rbo before unpin\n");
3137                 return;
3138         }
3139
3140         amdgpu_bo_unpin(rbo);
3141         amdgpu_bo_unreserve(rbo);
3142         amdgpu_bo_unref(&rbo);
3143 }
3144
3145 static int dm_plane_atomic_check(struct drm_plane *plane,
3146                                  struct drm_plane_state *state)
3147 {
3148         struct amdgpu_device *adev = plane->dev->dev_private;
3149         struct dc *dc = adev->dm.dc;
3150         struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3151
3152         if (!dm_plane_state->dc_state)
3153                 return 0;
3154
3155         if (!fill_rects_from_plane_state(state, dm_plane_state->dc_state))
3156                 return -EINVAL;
3157
3158         if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
3159                 return 0;
3160
3161         return -EINVAL;
3162 }
3163
3164 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
3165         .prepare_fb = dm_plane_helper_prepare_fb,
3166         .cleanup_fb = dm_plane_helper_cleanup_fb,
3167         .atomic_check = dm_plane_atomic_check,
3168 };
3169
3170 /*
3171  * TODO: these are currently initialized to rgb formats only.
3172  * For future use cases we should either initialize them dynamically based on
3173  * plane capabilities, or initialize this array to all formats, so internal drm
3174  * check will succeed, and let DC to implement proper check
3175  */
3176 static const uint32_t rgb_formats[] = {
3177         DRM_FORMAT_RGB888,
3178         DRM_FORMAT_XRGB8888,
3179         DRM_FORMAT_ARGB8888,
3180         DRM_FORMAT_RGBA8888,
3181         DRM_FORMAT_XRGB2101010,
3182         DRM_FORMAT_XBGR2101010,
3183         DRM_FORMAT_ARGB2101010,
3184         DRM_FORMAT_ABGR2101010,
3185 };
3186
3187 static const uint32_t yuv_formats[] = {
3188         DRM_FORMAT_NV12,
3189         DRM_FORMAT_NV21,
3190 };
3191
3192 static const u32 cursor_formats[] = {
3193         DRM_FORMAT_ARGB8888
3194 };
3195
3196 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
3197                                 struct amdgpu_plane *aplane,
3198                                 unsigned long possible_crtcs)
3199 {
3200         int res = -EPERM;
3201
3202         switch (aplane->base.type) {
3203         case DRM_PLANE_TYPE_PRIMARY:
3204                 res = drm_universal_plane_init(
3205                                 dm->adev->ddev,
3206                                 &aplane->base,
3207                                 possible_crtcs,
3208                                 &dm_plane_funcs,
3209                                 rgb_formats,
3210                                 ARRAY_SIZE(rgb_formats),
3211                                 NULL, aplane->base.type, NULL);
3212                 break;
3213         case DRM_PLANE_TYPE_OVERLAY:
3214                 res = drm_universal_plane_init(
3215                                 dm->adev->ddev,
3216                                 &aplane->base,
3217                                 possible_crtcs,
3218                                 &dm_plane_funcs,
3219                                 yuv_formats,
3220                                 ARRAY_SIZE(yuv_formats),
3221                                 NULL, aplane->base.type, NULL);
3222                 break;
3223         case DRM_PLANE_TYPE_CURSOR:
3224                 res = drm_universal_plane_init(
3225                                 dm->adev->ddev,
3226                                 &aplane->base,
3227                                 possible_crtcs,
3228                                 &dm_plane_funcs,
3229                                 cursor_formats,
3230                                 ARRAY_SIZE(cursor_formats),
3231                                 NULL, aplane->base.type, NULL);
3232                 break;
3233         }
3234
3235         drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs);
3236
3237         /* Create (reset) the plane state */
3238         if (aplane->base.funcs->reset)
3239                 aplane->base.funcs->reset(&aplane->base);
3240
3241
3242         return res;
3243 }
3244
3245 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
3246                                struct drm_plane *plane,
3247                                uint32_t crtc_index)
3248 {
3249         struct amdgpu_crtc *acrtc = NULL;
3250         struct amdgpu_plane *cursor_plane;
3251
3252         int res = -ENOMEM;
3253
3254         cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
3255         if (!cursor_plane)
3256                 goto fail;
3257
3258         cursor_plane->base.type = DRM_PLANE_TYPE_CURSOR;
3259         res = amdgpu_dm_plane_init(dm, cursor_plane, 0);
3260
3261         acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
3262         if (!acrtc)
3263                 goto fail;
3264
3265         res = drm_crtc_init_with_planes(
3266                         dm->ddev,
3267                         &acrtc->base,
3268                         plane,
3269                         &cursor_plane->base,
3270                         &amdgpu_dm_crtc_funcs, NULL);
3271
3272         if (res)
3273                 goto fail;
3274
3275         drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
3276
3277         /* Create (reset) the plane state */
3278         if (acrtc->base.funcs->reset)
3279                 acrtc->base.funcs->reset(&acrtc->base);
3280
3281         acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
3282         acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
3283
3284         acrtc->crtc_id = crtc_index;
3285         acrtc->base.enabled = false;
3286
3287         dm->adev->mode_info.crtcs[crtc_index] = acrtc;
3288         drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
3289                                    true, MAX_COLOR_LUT_ENTRIES);
3290         drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
3291
3292         return 0;
3293
3294 fail:
3295         kfree(acrtc);
3296         kfree(cursor_plane);
3297         return res;
3298 }
3299
3300
3301 static int to_drm_connector_type(enum signal_type st)
3302 {
3303         switch (st) {
3304         case SIGNAL_TYPE_HDMI_TYPE_A:
3305                 return DRM_MODE_CONNECTOR_HDMIA;
3306         case SIGNAL_TYPE_EDP:
3307                 return DRM_MODE_CONNECTOR_eDP;
3308         case SIGNAL_TYPE_RGB:
3309                 return DRM_MODE_CONNECTOR_VGA;
3310         case SIGNAL_TYPE_DISPLAY_PORT:
3311         case SIGNAL_TYPE_DISPLAY_PORT_MST:
3312                 return DRM_MODE_CONNECTOR_DisplayPort;
3313         case SIGNAL_TYPE_DVI_DUAL_LINK:
3314         case SIGNAL_TYPE_DVI_SINGLE_LINK:
3315                 return DRM_MODE_CONNECTOR_DVID;
3316         case SIGNAL_TYPE_VIRTUAL:
3317                 return DRM_MODE_CONNECTOR_VIRTUAL;
3318
3319         default:
3320                 return DRM_MODE_CONNECTOR_Unknown;
3321         }
3322 }
3323
3324 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
3325 {
3326         const struct drm_connector_helper_funcs *helper =
3327                 connector->helper_private;
3328         struct drm_encoder *encoder;
3329         struct amdgpu_encoder *amdgpu_encoder;
3330
3331         encoder = helper->best_encoder(connector);
3332
3333         if (encoder == NULL)
3334                 return;
3335
3336         amdgpu_encoder = to_amdgpu_encoder(encoder);
3337
3338         amdgpu_encoder->native_mode.clock = 0;
3339
3340         if (!list_empty(&connector->probed_modes)) {
3341                 struct drm_display_mode *preferred_mode = NULL;
3342
3343                 list_for_each_entry(preferred_mode,
3344                                     &connector->probed_modes,
3345                                     head) {
3346                         if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
3347                                 amdgpu_encoder->native_mode = *preferred_mode;
3348
3349                         break;
3350                 }
3351
3352         }
3353 }
3354
3355 static struct drm_display_mode *
3356 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
3357                              char *name,
3358                              int hdisplay, int vdisplay)
3359 {
3360         struct drm_device *dev = encoder->dev;
3361         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3362         struct drm_display_mode *mode = NULL;
3363         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3364
3365         mode = drm_mode_duplicate(dev, native_mode);
3366
3367         if (mode == NULL)
3368                 return NULL;
3369
3370         mode->hdisplay = hdisplay;
3371         mode->vdisplay = vdisplay;
3372         mode->type &= ~DRM_MODE_TYPE_PREFERRED;
3373         strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
3374
3375         return mode;
3376
3377 }
3378
3379 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3380                                                  struct drm_connector *connector)
3381 {
3382         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3383         struct drm_display_mode *mode = NULL;
3384         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3385         struct amdgpu_dm_connector *amdgpu_dm_connector =
3386                                 to_amdgpu_dm_connector(connector);
3387         int i;
3388         int n;
3389         struct mode_size {
3390                 char name[DRM_DISPLAY_MODE_LEN];
3391                 int w;
3392                 int h;
3393         } common_modes[] = {
3394                 {  "640x480",  640,  480},
3395                 {  "800x600",  800,  600},
3396                 { "1024x768", 1024,  768},
3397                 { "1280x720", 1280,  720},
3398                 { "1280x800", 1280,  800},
3399                 {"1280x1024", 1280, 1024},
3400                 { "1440x900", 1440,  900},
3401                 {"1680x1050", 1680, 1050},
3402                 {"1600x1200", 1600, 1200},
3403                 {"1920x1080", 1920, 1080},
3404                 {"1920x1200", 1920, 1200}
3405         };
3406
3407         n = ARRAY_SIZE(common_modes);
3408
3409         for (i = 0; i < n; i++) {
3410                 struct drm_display_mode *curmode = NULL;
3411                 bool mode_existed = false;
3412
3413                 if (common_modes[i].w > native_mode->hdisplay ||
3414                     common_modes[i].h > native_mode->vdisplay ||
3415                    (common_modes[i].w == native_mode->hdisplay &&
3416                     common_modes[i].h == native_mode->vdisplay))
3417                         continue;
3418
3419                 list_for_each_entry(curmode, &connector->probed_modes, head) {
3420                         if (common_modes[i].w == curmode->hdisplay &&
3421                             common_modes[i].h == curmode->vdisplay) {
3422                                 mode_existed = true;
3423                                 break;
3424                         }
3425                 }
3426
3427                 if (mode_existed)
3428                         continue;
3429
3430                 mode = amdgpu_dm_create_common_mode(encoder,
3431                                 common_modes[i].name, common_modes[i].w,
3432                                 common_modes[i].h);
3433                 drm_mode_probed_add(connector, mode);
3434                 amdgpu_dm_connector->num_modes++;
3435         }
3436 }
3437
3438 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
3439                                               struct edid *edid)
3440 {
3441         struct amdgpu_dm_connector *amdgpu_dm_connector =
3442                         to_amdgpu_dm_connector(connector);
3443
3444         if (edid) {
3445                 /* empty probed_modes */
3446                 INIT_LIST_HEAD(&connector->probed_modes);
3447                 amdgpu_dm_connector->num_modes =
3448                                 drm_add_edid_modes(connector, edid);
3449
3450                 amdgpu_dm_get_native_mode(connector);
3451         } else {
3452                 amdgpu_dm_connector->num_modes = 0;
3453         }
3454 }
3455
3456 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
3457 {
3458         const struct drm_connector_helper_funcs *helper =
3459                         connector->helper_private;
3460         struct amdgpu_dm_connector *amdgpu_dm_connector =
3461                         to_amdgpu_dm_connector(connector);
3462         struct drm_encoder *encoder;
3463         struct edid *edid = amdgpu_dm_connector->edid;
3464
3465         encoder = helper->best_encoder(connector);
3466         amdgpu_dm_connector_ddc_get_modes(connector, edid);
3467         amdgpu_dm_connector_add_common_modes(encoder, connector);
3468
3469 #if defined(CONFIG_DRM_AMD_DC_FBC)
3470         amdgpu_dm_fbc_init(connector);
3471 #endif
3472         return amdgpu_dm_connector->num_modes;
3473 }
3474
3475 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
3476                                      struct amdgpu_dm_connector *aconnector,
3477                                      int connector_type,
3478                                      struct dc_link *link,
3479                                      int link_index)
3480 {
3481         struct amdgpu_device *adev = dm->ddev->dev_private;
3482
3483         aconnector->connector_id = link_index;
3484         aconnector->dc_link = link;
3485         aconnector->base.interlace_allowed = false;
3486         aconnector->base.doublescan_allowed = false;
3487         aconnector->base.stereo_allowed = false;
3488         aconnector->base.dpms = DRM_MODE_DPMS_OFF;
3489         aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
3490
3491         mutex_init(&aconnector->hpd_lock);
3492
3493         /* configure support HPD hot plug connector_>polled default value is 0
3494          * which means HPD hot plug not supported
3495          */
3496         switch (connector_type) {
3497         case DRM_MODE_CONNECTOR_HDMIA:
3498                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3499                 break;
3500         case DRM_MODE_CONNECTOR_DisplayPort:
3501                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3502                 break;
3503         case DRM_MODE_CONNECTOR_DVID:
3504                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3505                 break;
3506         default:
3507                 break;
3508         }
3509
3510         drm_object_attach_property(&aconnector->base.base,
3511                                 dm->ddev->mode_config.scaling_mode_property,
3512                                 DRM_MODE_SCALE_NONE);
3513
3514         drm_object_attach_property(&aconnector->base.base,
3515                                 adev->mode_info.underscan_property,
3516                                 UNDERSCAN_OFF);
3517         drm_object_attach_property(&aconnector->base.base,
3518                                 adev->mode_info.underscan_hborder_property,
3519                                 0);
3520         drm_object_attach_property(&aconnector->base.base,
3521                                 adev->mode_info.underscan_vborder_property,
3522                                 0);
3523
3524 }
3525
3526 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
3527                               struct i2c_msg *msgs, int num)
3528 {
3529         struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
3530         struct ddc_service *ddc_service = i2c->ddc_service;
3531         struct i2c_command cmd;
3532         int i;
3533         int result = -EIO;
3534
3535         cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
3536
3537         if (!cmd.payloads)
3538                 return result;
3539
3540         cmd.number_of_payloads = num;
3541         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
3542         cmd.speed = 100;
3543
3544         for (i = 0; i < num; i++) {
3545                 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
3546                 cmd.payloads[i].address = msgs[i].addr;
3547                 cmd.payloads[i].length = msgs[i].len;
3548                 cmd.payloads[i].data = msgs[i].buf;
3549         }
3550
3551         if (dal_i2caux_submit_i2c_command(
3552                         ddc_service->ctx->i2caux,
3553                         ddc_service->ddc_pin,
3554                         &cmd))
3555                 result = num;
3556
3557         kfree(cmd.payloads);
3558         return result;
3559 }
3560
3561 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
3562 {
3563         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3564 }
3565
3566 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
3567         .master_xfer = amdgpu_dm_i2c_xfer,
3568         .functionality = amdgpu_dm_i2c_func,
3569 };
3570
3571 static struct amdgpu_i2c_adapter *
3572 create_i2c(struct ddc_service *ddc_service,
3573            int link_index,
3574            int *res)
3575 {
3576         struct amdgpu_device *adev = ddc_service->ctx->driver_context;
3577         struct amdgpu_i2c_adapter *i2c;
3578
3579         i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
3580         if (!i2c)
3581                 return NULL;
3582         i2c->base.owner = THIS_MODULE;
3583         i2c->base.class = I2C_CLASS_DDC;
3584         i2c->base.dev.parent = &adev->pdev->dev;
3585         i2c->base.algo = &amdgpu_dm_i2c_algo;
3586         snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
3587         i2c_set_adapdata(&i2c->base, i2c);
3588         i2c->ddc_service = ddc_service;
3589
3590         return i2c;
3591 }
3592
3593
3594 /* Note: this function assumes that dc_link_detect() was called for the
3595  * dc_link which will be represented by this aconnector.
3596  */
3597 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
3598                                     struct amdgpu_dm_connector *aconnector,
3599                                     uint32_t link_index,
3600                                     struct amdgpu_encoder *aencoder)
3601 {
3602         int res = 0;
3603         int connector_type;
3604         struct dc *dc = dm->dc;
3605         struct dc_link *link = dc_get_link_at_index(dc, link_index);
3606         struct amdgpu_i2c_adapter *i2c;
3607
3608         link->priv = aconnector;
3609
3610         DRM_DEBUG_DRIVER("%s()\n", __func__);
3611
3612         i2c = create_i2c(link->ddc, link->link_index, &res);
3613         if (!i2c) {
3614                 DRM_ERROR("Failed to create i2c adapter data\n");
3615                 return -ENOMEM;
3616         }
3617
3618         aconnector->i2c = i2c;
3619         res = i2c_add_adapter(&i2c->base);
3620
3621         if (res) {
3622                 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
3623                 goto out_free;
3624         }
3625
3626         connector_type = to_drm_connector_type(link->connector_signal);
3627
3628         res = drm_connector_init(
3629                         dm->ddev,
3630                         &aconnector->base,
3631                         &amdgpu_dm_connector_funcs,
3632                         connector_type);
3633
3634         if (res) {
3635                 DRM_ERROR("connector_init failed\n");
3636                 aconnector->connector_id = -1;
3637                 goto out_free;
3638         }
3639
3640         drm_connector_helper_add(
3641                         &aconnector->base,
3642                         &amdgpu_dm_connector_helper_funcs);
3643
3644         if (aconnector->base.funcs->reset)
3645                 aconnector->base.funcs->reset(&aconnector->base);
3646
3647         amdgpu_dm_connector_init_helper(
3648                 dm,
3649                 aconnector,
3650                 connector_type,
3651                 link,
3652                 link_index);
3653
3654         drm_mode_connector_attach_encoder(
3655                 &aconnector->base, &aencoder->base);
3656
3657         drm_connector_register(&aconnector->base);
3658
3659         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
3660                 || connector_type == DRM_MODE_CONNECTOR_eDP)
3661                 amdgpu_dm_initialize_dp_connector(dm, aconnector);
3662
3663 out_free:
3664         if (res) {
3665                 kfree(i2c);
3666                 aconnector->i2c = NULL;
3667         }
3668         return res;
3669 }
3670
3671 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
3672 {
3673         switch (adev->mode_info.num_crtc) {
3674         case 1:
3675                 return 0x1;
3676         case 2:
3677                 return 0x3;
3678         case 3:
3679                 return 0x7;
3680         case 4:
3681                 return 0xf;
3682         case 5:
3683                 return 0x1f;
3684         case 6:
3685         default:
3686                 return 0x3f;
3687         }
3688 }
3689
3690 static int amdgpu_dm_encoder_init(struct drm_device *dev,
3691                                   struct amdgpu_encoder *aencoder,
3692                                   uint32_t link_index)
3693 {
3694         struct amdgpu_device *adev = dev->dev_private;
3695
3696         int res = drm_encoder_init(dev,
3697                                    &aencoder->base,
3698                                    &amdgpu_dm_encoder_funcs,
3699                                    DRM_MODE_ENCODER_TMDS,
3700                                    NULL);
3701
3702         aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
3703
3704         if (!res)
3705                 aencoder->encoder_id = link_index;
3706         else
3707                 aencoder->encoder_id = -1;
3708
3709         drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
3710
3711         return res;
3712 }
3713
3714 static void manage_dm_interrupts(struct amdgpu_device *adev,
3715                                  struct amdgpu_crtc *acrtc,
3716                                  bool enable)
3717 {
3718         /*
3719          * this is not correct translation but will work as soon as VBLANK
3720          * constant is the same as PFLIP
3721          */
3722         int irq_type =
3723                 amdgpu_display_crtc_idx_to_irq_type(
3724                         adev,
3725                         acrtc->crtc_id);
3726
3727         if (enable) {
3728                 drm_crtc_vblank_on(&acrtc->base);
3729                 amdgpu_irq_get(
3730                         adev,
3731                         &adev->pageflip_irq,
3732                         irq_type);
3733         } else {
3734
3735                 amdgpu_irq_put(
3736                         adev,
3737                         &adev->pageflip_irq,
3738                         irq_type);
3739                 drm_crtc_vblank_off(&acrtc->base);
3740         }
3741 }
3742
3743 static bool
3744 is_scaling_state_different(const struct dm_connector_state *dm_state,
3745                            const struct dm_connector_state *old_dm_state)
3746 {
3747         if (dm_state->scaling != old_dm_state->scaling)
3748                 return true;
3749         if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
3750                 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
3751                         return true;
3752         } else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
3753                 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
3754                         return true;
3755         } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
3756                    dm_state->underscan_vborder != old_dm_state->underscan_vborder)
3757                 return true;
3758         return false;
3759 }
3760
3761 static void remove_stream(struct amdgpu_device *adev,
3762                           struct amdgpu_crtc *acrtc,
3763                           struct dc_stream_state *stream)
3764 {
3765         /* this is the update mode case */
3766         if (adev->dm.freesync_module)
3767                 mod_freesync_remove_stream(adev->dm.freesync_module, stream);
3768
3769         acrtc->otg_inst = -1;
3770         acrtc->enabled = false;
3771 }
3772
3773 static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
3774                                struct dc_cursor_position *position)
3775 {
3776         struct amdgpu_crtc *amdgpu_crtc = amdgpu_crtc = to_amdgpu_crtc(crtc);
3777         int x, y;
3778         int xorigin = 0, yorigin = 0;
3779
3780         if (!crtc || !plane->state->fb) {
3781                 position->enable = false;
3782                 position->x = 0;
3783                 position->y = 0;
3784                 return 0;
3785         }
3786
3787         if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
3788             (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
3789                 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
3790                           __func__,
3791                           plane->state->crtc_w,
3792                           plane->state->crtc_h);
3793                 return -EINVAL;
3794         }
3795
3796         x = plane->state->crtc_x;
3797         y = plane->state->crtc_y;
3798         /* avivo cursor are offset into the total surface */
3799         x += crtc->primary->state->src_x >> 16;
3800         y += crtc->primary->state->src_y >> 16;
3801         if (x < 0) {
3802                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
3803                 x = 0;
3804         }
3805         if (y < 0) {
3806                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
3807                 y = 0;
3808         }
3809         position->enable = true;
3810         position->x = x;
3811         position->y = y;
3812         position->x_hotspot = xorigin;
3813         position->y_hotspot = yorigin;
3814
3815         return 0;
3816 }
3817
3818 static void handle_cursor_update(struct drm_plane *plane,
3819                                  struct drm_plane_state *old_plane_state)
3820 {
3821         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
3822         struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
3823         struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
3824         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3825         uint64_t address = afb ? afb->address : 0;
3826         struct dc_cursor_position position;
3827         struct dc_cursor_attributes attributes;
3828         int ret;
3829
3830         if (!plane->state->fb && !old_plane_state->fb)
3831                 return;
3832
3833         DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
3834                          __func__,
3835                          amdgpu_crtc->crtc_id,
3836                          plane->state->crtc_w,
3837                          plane->state->crtc_h);
3838
3839         ret = get_cursor_position(plane, crtc, &position);
3840         if (ret)
3841                 return;
3842
3843         if (!position.enable) {
3844                 /* turn off cursor */
3845                 if (crtc_state && crtc_state->stream)
3846                         dc_stream_set_cursor_position(crtc_state->stream,
3847                                                       &position);
3848                 return;
3849         }
3850
3851         amdgpu_crtc->cursor_width = plane->state->crtc_w;
3852         amdgpu_crtc->cursor_height = plane->state->crtc_h;
3853
3854         attributes.address.high_part = upper_32_bits(address);
3855         attributes.address.low_part  = lower_32_bits(address);
3856         attributes.width             = plane->state->crtc_w;
3857         attributes.height            = plane->state->crtc_h;
3858         attributes.color_format      = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
3859         attributes.rotation_angle    = 0;
3860         attributes.attribute_flags.value = 0;
3861
3862         attributes.pitch = attributes.width;
3863
3864         if (crtc_state->stream) {
3865                 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
3866                                                          &attributes))
3867                         DRM_ERROR("DC failed to set cursor attributes\n");
3868
3869                 if (!dc_stream_set_cursor_position(crtc_state->stream,
3870                                                    &position))
3871                         DRM_ERROR("DC failed to set cursor position\n");
3872         }
3873 }
3874
3875 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
3876 {
3877
3878         assert_spin_locked(&acrtc->base.dev->event_lock);
3879         WARN_ON(acrtc->event);
3880
3881         acrtc->event = acrtc->base.state->event;
3882
3883         /* Set the flip status */
3884         acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
3885
3886         /* Mark this event as consumed */
3887         acrtc->base.state->event = NULL;
3888
3889         DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
3890                                                  acrtc->crtc_id);
3891 }
3892
3893 /*
3894  * Executes flip
3895  *
3896  * Waits on all BO's fences and for proper vblank count
3897  */
3898 static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
3899                               struct drm_framebuffer *fb,
3900                               uint32_t target,
3901                               struct dc_state *state)
3902 {
3903         unsigned long flags;
3904         uint32_t target_vblank;
3905         int r, vpos, hpos;
3906         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3907         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
3908         struct amdgpu_bo *abo = gem_to_amdgpu_bo(afb->obj);
3909         struct amdgpu_device *adev = crtc->dev->dev_private;
3910         bool async_flip = (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
3911         struct dc_flip_addrs addr = { {0} };
3912         /* TODO eliminate or rename surface_update */
3913         struct dc_surface_update surface_updates[1] = { {0} };
3914         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
3915
3916
3917         /* Prepare wait for target vblank early - before the fence-waits */
3918         target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
3919                         amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);
3920
3921         /* TODO This might fail and hence better not used, wait
3922          * explicitly on fences instead
3923          * and in general should be called for
3924          * blocking commit to as per framework helpers
3925          */
3926         r = amdgpu_bo_reserve(abo, true);
3927         if (unlikely(r != 0)) {
3928                 DRM_ERROR("failed to reserve buffer before flip\n");
3929                 WARN_ON(1);
3930         }
3931
3932         /* Wait for all fences on this FB */
3933         WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
3934                                                                     MAX_SCHEDULE_TIMEOUT) < 0);
3935
3936         amdgpu_bo_unreserve(abo);
3937
3938         /* Wait until we're out of the vertical blank period before the one
3939          * targeted by the flip
3940          */
3941         while ((acrtc->enabled &&
3942                 (amdgpu_display_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id,
3943                                                     0, &vpos, &hpos, NULL,
3944                                                     NULL, &crtc->hwmode)
3945                  & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
3946                 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
3947                 (int)(target_vblank -
3948                   amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
3949                 usleep_range(1000, 1100);
3950         }
3951
3952         /* Flip */
3953         spin_lock_irqsave(&crtc->dev->event_lock, flags);
3954         /* update crtc fb */
3955         crtc->primary->fb = fb;
3956
3957         WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE);
3958         WARN_ON(!acrtc_state->stream);
3959
3960         addr.address.grph.addr.low_part = lower_32_bits(afb->address);
3961         addr.address.grph.addr.high_part = upper_32_bits(afb->address);
3962         addr.flip_immediate = async_flip;
3963
3964
3965         if (acrtc->base.state->event)
3966                 prepare_flip_isr(acrtc);
3967
3968         surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->plane_states[0];
3969         surface_updates->flip_addr = &addr;
3970
3971
3972         dc_commit_updates_for_stream(adev->dm.dc,
3973                                              surface_updates,
3974                                              1,
3975                                              acrtc_state->stream,
3976                                              NULL,
3977                                              &surface_updates->surface,
3978                                              state);
3979
3980         DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
3981                          __func__,
3982                          addr.address.grph.addr.high_part,
3983                          addr.address.grph.addr.low_part);
3984
3985
3986         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
3987 }
3988
3989 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
3990                                     struct drm_device *dev,
3991                                     struct amdgpu_display_manager *dm,
3992                                     struct drm_crtc *pcrtc,
3993                                     bool *wait_for_vblank)
3994 {
3995         uint32_t i;
3996         struct drm_plane *plane;
3997         struct drm_plane_state *old_plane_state, *new_plane_state;
3998         struct dc_stream_state *dc_stream_attach;
3999         struct dc_plane_state *plane_states_constructed[MAX_SURFACES];
4000         struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
4001         struct drm_crtc_state *new_pcrtc_state =
4002                         drm_atomic_get_new_crtc_state(state, pcrtc);
4003         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
4004         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4005         int planes_count = 0;
4006         unsigned long flags;
4007
4008         /* update planes when needed */
4009         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
4010                 struct drm_crtc *crtc = new_plane_state->crtc;
4011                 struct drm_crtc_state *new_crtc_state;
4012                 struct drm_framebuffer *fb = new_plane_state->fb;
4013                 bool pflip_needed;
4014                 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
4015
4016                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
4017                         handle_cursor_update(plane, old_plane_state);
4018                         continue;
4019                 }
4020
4021                 if (!fb || !crtc || pcrtc != crtc)
4022                         continue;
4023
4024                 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
4025                 if (!new_crtc_state->active)
4026                         continue;
4027
4028                 pflip_needed = !state->allow_modeset;
4029
4030                 spin_lock_irqsave(&crtc->dev->event_lock, flags);
4031                 if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) {
4032                         DRM_ERROR("%s: acrtc %d, already busy\n",
4033                                   __func__,
4034                                   acrtc_attach->crtc_id);
4035                         /* In commit tail framework this cannot happen */
4036                         WARN_ON(1);
4037                 }
4038                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
4039
4040                 if (!pflip_needed) {
4041                         WARN_ON(!dm_new_plane_state->dc_state);
4042
4043                         plane_states_constructed[planes_count] = dm_new_plane_state->dc_state;
4044
4045                         dc_stream_attach = acrtc_state->stream;
4046                         planes_count++;
4047
4048                 } else if (new_crtc_state->planes_changed) {
4049                         /* Assume even ONE crtc with immediate flip means
4050                          * entire can't wait for VBLANK
4051                          * TODO Check if it's correct
4052                          */
4053                         *wait_for_vblank =
4054                                         new_pcrtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
4055                                 false : true;
4056
4057                         /* TODO: Needs rework for multiplane flip */
4058                         if (plane->type == DRM_PLANE_TYPE_PRIMARY)
4059                                 drm_crtc_vblank_get(crtc);
4060
4061                         amdgpu_dm_do_flip(
4062                                 crtc,
4063                                 fb,
4064                                 (uint32_t)drm_crtc_vblank_count(crtc) + *wait_for_vblank,
4065                                 dm_state->context);
4066                 }
4067
4068         }
4069
4070         if (planes_count) {
4071                 unsigned long flags;
4072
4073                 if (new_pcrtc_state->event) {
4074
4075                         drm_crtc_vblank_get(pcrtc);
4076
4077                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
4078                         prepare_flip_isr(acrtc_attach);
4079                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
4080                 }
4081
4082                 if (false == dc_commit_planes_to_stream(dm->dc,
4083                                                         plane_states_constructed,
4084                                                         planes_count,
4085                                                         dc_stream_attach,
4086                                                         dm_state->context))
4087                         dm_error("%s: Failed to attach plane!\n", __func__);
4088         } else {
4089                 /*TODO BUG Here should go disable planes on CRTC. */
4090         }
4091 }
4092
4093 /**
4094  * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
4095  * @crtc_state: the DRM CRTC state
4096  * @stream_state: the DC stream state.
4097  *
4098  * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
4099  * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
4100  */
4101 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
4102                                                 struct dc_stream_state *stream_state)
4103 {
4104         stream_state->mode_changed = crtc_state->mode_changed;
4105 }
4106
4107 static int amdgpu_dm_atomic_commit(struct drm_device *dev,
4108                                    struct drm_atomic_state *state,
4109                                    bool nonblock)
4110 {
4111         struct drm_crtc *crtc;
4112         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
4113         struct amdgpu_device *adev = dev->dev_private;
4114         int i;
4115
4116         /*
4117          * We evade vblanks and pflips on crtc that
4118          * should be changed. We do it here to flush & disable
4119          * interrupts before drm_swap_state is called in drm_atomic_helper_commit
4120          * it will update crtc->dm_crtc_state->stream pointer which is used in
4121          * the ISRs.
4122          */
4123         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
4124                 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4125                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4126
4127                 if (drm_atomic_crtc_needs_modeset(new_crtc_state) && dm_old_crtc_state->stream)
4128                         manage_dm_interrupts(adev, acrtc, false);
4129         }
4130         /* Add check here for SoC's that support hardware cursor plane, to
4131          * unset legacy_cursor_update */
4132
4133         return drm_atomic_helper_commit(dev, state, nonblock);
4134
4135         /*TODO Handle EINTR, reenable IRQ*/
4136 }
4137
4138 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
4139 {
4140         struct drm_device *dev = state->dev;
4141         struct amdgpu_device *adev = dev->dev_private;
4142         struct amdgpu_display_manager *dm = &adev->dm;
4143         struct dm_atomic_state *dm_state;
4144         uint32_t i, j;
4145         struct drm_crtc *crtc;
4146         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
4147         unsigned long flags;
4148         bool wait_for_vblank = true;
4149         struct drm_connector *connector;
4150         struct drm_connector_state *old_con_state, *new_con_state;
4151         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
4152
4153         drm_atomic_helper_update_legacy_modeset_state(dev, state);
4154
4155         dm_state = to_dm_atomic_state(state);
4156
4157         /* update changed items */
4158         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
4159                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4160
4161                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4162                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4163
4164                 DRM_DEBUG_DRIVER(
4165                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4166                         "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4167                         "connectors_changed:%d\n",
4168                         acrtc->crtc_id,
4169                         new_crtc_state->enable,
4170                         new_crtc_state->active,
4171                         new_crtc_state->planes_changed,
4172                         new_crtc_state->mode_changed,
4173                         new_crtc_state->active_changed,
4174                         new_crtc_state->connectors_changed);
4175
4176                 /* Copy all transient state flags into dc state */
4177                 if (dm_new_crtc_state->stream) {
4178                         amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
4179                                                             dm_new_crtc_state->stream);
4180                 }
4181
4182                 /* handles headless hotplug case, updating new_state and
4183                  * aconnector as needed
4184                  */
4185
4186                 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
4187
4188                         DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
4189
4190                         if (!dm_new_crtc_state->stream) {
4191                                 /*
4192                                  * this could happen because of issues with
4193                                  * userspace notifications delivery.
4194                                  * In this case userspace tries to set mode on
4195                                  * display which is disconnect in fact.
4196                                  * dc_sink in NULL in this case on aconnector.
4197                                  * We expect reset mode will come soon.
4198                                  *
4199                                  * This can also happen when unplug is done
4200                                  * during resume sequence ended
4201                                  *
4202                                  * In this case, we want to pretend we still
4203                                  * have a sink to keep the pipe running so that
4204                                  * hw state is consistent with the sw state
4205                                  */
4206                                 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
4207                                                 __func__, acrtc->base.base.id);
4208                                 continue;
4209                         }
4210
4211                         if (dm_old_crtc_state->stream)
4212                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
4213
4214                         acrtc->enabled = true;
4215                         acrtc->hw_mode = new_crtc_state->mode;
4216                         crtc->hwmode = new_crtc_state->mode;
4217                 } else if (modereset_required(new_crtc_state)) {
4218                         DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
4219
4220                         /* i.e. reset mode */
4221                         if (dm_old_crtc_state->stream)
4222                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
4223                 }
4224         } /* for_each_crtc_in_state() */
4225
4226         /*
4227          * Add streams after required streams from new and replaced streams
4228          * are removed from freesync module
4229          */
4230         if (adev->dm.freesync_module) {
4231                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
4232                                               new_crtc_state, i) {
4233                         struct amdgpu_dm_connector *aconnector = NULL;
4234                         struct dm_connector_state *dm_new_con_state = NULL;
4235                         struct amdgpu_crtc *acrtc = NULL;
4236                         bool modeset_needed;
4237
4238                         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4239                         dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4240                         modeset_needed = modeset_required(
4241                                         new_crtc_state,
4242                                         dm_new_crtc_state->stream,
4243                                         dm_old_crtc_state->stream);
4244                         /* We add stream to freesync if:
4245                          * 1. Said stream is not null, and
4246                          * 2. A modeset is requested. This means that the
4247                          *    stream was removed previously, and needs to be
4248                          *    replaced.
4249                          */
4250                         if (dm_new_crtc_state->stream == NULL ||
4251                                         !modeset_needed)
4252                                 continue;
4253
4254                         acrtc = to_amdgpu_crtc(crtc);
4255
4256                         aconnector =
4257                                 amdgpu_dm_find_first_crtc_matching_connector(
4258                                         state, crtc);
4259                         if (!aconnector) {
4260                                 DRM_DEBUG_DRIVER("Atomic commit: Failed to "
4261                                                  "find connector for acrtc "
4262                                                  "id:%d skipping freesync "
4263                                                  "init\n",
4264                                                  acrtc->crtc_id);
4265                                 continue;
4266                         }
4267
4268                         mod_freesync_add_stream(adev->dm.freesync_module,
4269                                                 dm_new_crtc_state->stream,
4270                                                 &aconnector->caps);
4271                         new_con_state = drm_atomic_get_new_connector_state(
4272                                         state, &aconnector->base);
4273                         dm_new_con_state = to_dm_connector_state(new_con_state);
4274
4275                         mod_freesync_set_user_enable(adev->dm.freesync_module,
4276                                                      &dm_new_crtc_state->stream,
4277                                                      1,
4278                                                      &dm_new_con_state->user_enable);
4279                 }
4280         }
4281
4282         if (dm_state->context) {
4283                 dm_enable_per_frame_crtc_master_sync(dm_state->context);
4284                 WARN_ON(!dc_commit_state(dm->dc, dm_state->context));
4285         }
4286
4287         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
4288                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4289
4290                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4291
4292                 if (dm_new_crtc_state->stream != NULL) {
4293                         const struct dc_stream_status *status =
4294                                         dc_stream_get_status(dm_new_crtc_state->stream);
4295
4296                         if (!status)
4297                                 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
4298                         else
4299                                 acrtc->otg_inst = status->primary_otg_inst;
4300                 }
4301         }
4302
4303         /* Handle scaling and underscan changes*/
4304         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
4305                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
4306                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
4307                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
4308                 struct dc_stream_status *status = NULL;
4309
4310                 if (acrtc)
4311                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
4312
4313                 /* Skip any modesets/resets */
4314                 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
4315                         continue;
4316
4317                 /* Skip any thing not scale or underscan changes */
4318                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
4319                         continue;
4320
4321                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4322
4323                 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
4324                                 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
4325
4326                 if (!dm_new_crtc_state->stream)
4327                         continue;
4328
4329                 status = dc_stream_get_status(dm_new_crtc_state->stream);
4330                 WARN_ON(!status);
4331                 WARN_ON(!status->plane_count);
4332
4333                 /*TODO How it works with MPO ?*/
4334                 if (!dc_commit_planes_to_stream(
4335                                 dm->dc,
4336                                 status->plane_states,
4337                                 status->plane_count,
4338                                 dm_new_crtc_state->stream,
4339                                 dm_state->context))
4340                         dm_error("%s: Failed to update stream scaling!\n", __func__);
4341         }
4342
4343         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
4344                         new_crtc_state, i) {
4345                 /*
4346                  * loop to enable interrupts on newly arrived crtc
4347                  */
4348                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4349                 bool modeset_needed;
4350
4351                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4352                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4353                 modeset_needed = modeset_required(
4354                                 new_crtc_state,
4355                                 dm_new_crtc_state->stream,
4356                                 dm_old_crtc_state->stream);
4357
4358                 if (dm_new_crtc_state->stream == NULL || !modeset_needed)
4359                         continue;
4360
4361                 if (adev->dm.freesync_module)
4362                         mod_freesync_notify_mode_change(
4363                                 adev->dm.freesync_module,
4364                                 &dm_new_crtc_state->stream, 1);
4365
4366                 manage_dm_interrupts(adev, acrtc, true);
4367         }
4368
4369         /* update planes when needed per crtc*/
4370         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
4371                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4372
4373                 if (dm_new_crtc_state->stream)
4374                         amdgpu_dm_commit_planes(state, dev, dm, crtc, &wait_for_vblank);
4375         }
4376
4377
4378         /*
4379          * send vblank event on all events not handled in flip and
4380          * mark consumed event for drm_atomic_helper_commit_hw_done
4381          */
4382         spin_lock_irqsave(&adev->ddev->event_lock, flags);
4383         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
4384
4385                 if (new_crtc_state->event)
4386                         drm_send_event_locked(dev, &new_crtc_state->event->base);
4387
4388                 new_crtc_state->event = NULL;
4389         }
4390         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
4391
4392         /* Signal HW programming completion */
4393         drm_atomic_helper_commit_hw_done(state);
4394
4395         if (wait_for_vblank)
4396                 drm_atomic_helper_wait_for_flip_done(dev, state);
4397
4398         drm_atomic_helper_cleanup_planes(dev, state);
4399 }
4400
4401
4402 static int dm_force_atomic_commit(struct drm_connector *connector)
4403 {
4404         int ret = 0;
4405         struct drm_device *ddev = connector->dev;
4406         struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
4407         struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4408         struct drm_plane *plane = disconnected_acrtc->base.primary;
4409         struct drm_connector_state *conn_state;
4410         struct drm_crtc_state *crtc_state;
4411         struct drm_plane_state *plane_state;
4412
4413         if (!state)
4414                 return -ENOMEM;
4415
4416         state->acquire_ctx = ddev->mode_config.acquire_ctx;
4417
4418         /* Construct an atomic state to restore previous display setting */
4419
4420         /*
4421          * Attach connectors to drm_atomic_state
4422          */
4423         conn_state = drm_atomic_get_connector_state(state, connector);
4424
4425         ret = PTR_ERR_OR_ZERO(conn_state);
4426         if (ret)
4427                 goto err;
4428
4429         /* Attach crtc to drm_atomic_state*/
4430         crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
4431
4432         ret = PTR_ERR_OR_ZERO(crtc_state);
4433         if (ret)
4434                 goto err;
4435
4436         /* force a restore */
4437         crtc_state->mode_changed = true;
4438
4439         /* Attach plane to drm_atomic_state */
4440         plane_state = drm_atomic_get_plane_state(state, plane);
4441
4442         ret = PTR_ERR_OR_ZERO(plane_state);
4443         if (ret)
4444                 goto err;
4445
4446
4447         /* Call commit internally with the state we just constructed */
4448         ret = drm_atomic_commit(state);
4449         if (!ret)
4450                 return 0;
4451
4452 err:
4453         DRM_ERROR("Restoring old state failed with %i\n", ret);
4454         drm_atomic_state_put(state);
4455
4456         return ret;
4457 }
4458
4459 /*
4460  * This functions handle all cases when set mode does not come upon hotplug.
4461  * This include when the same display is unplugged then plugged back into the
4462  * same port and when we are running without usermode desktop manager supprot
4463  */
4464 void dm_restore_drm_connector_state(struct drm_device *dev,
4465                                     struct drm_connector *connector)
4466 {
4467         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
4468         struct amdgpu_crtc *disconnected_acrtc;
4469         struct dm_crtc_state *acrtc_state;
4470
4471         if (!aconnector->dc_sink || !connector->state || !connector->encoder)
4472                 return;
4473
4474         disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4475         if (!disconnected_acrtc)
4476                 return;
4477
4478         acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
4479         if (!acrtc_state->stream)
4480                 return;
4481
4482         /*
4483          * If the previous sink is not released and different from the current,
4484          * we deduce we are in a state where we can not rely on usermode call
4485          * to turn on the display, so we do it here
4486          */
4487         if (acrtc_state->stream->sink != aconnector->dc_sink)
4488                 dm_force_atomic_commit(&aconnector->base);
4489 }
4490
4491 /*`
4492  * Grabs all modesetting locks to serialize against any blocking commits,
4493  * Waits for completion of all non blocking commits.
4494  */
4495 static int do_aquire_global_lock(struct drm_device *dev,
4496                                  struct drm_atomic_state *state)
4497 {
4498         struct drm_crtc *crtc;
4499         struct drm_crtc_commit *commit;
4500         long ret;
4501
4502         /* Adding all modeset locks to aquire_ctx will
4503          * ensure that when the framework release it the
4504          * extra locks we are locking here will get released to
4505          */
4506         ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
4507         if (ret)
4508                 return ret;
4509
4510         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4511                 spin_lock(&crtc->commit_lock);
4512                 commit = list_first_entry_or_null(&crtc->commit_list,
4513                                 struct drm_crtc_commit, commit_entry);
4514                 if (commit)
4515                         drm_crtc_commit_get(commit);
4516                 spin_unlock(&crtc->commit_lock);
4517
4518                 if (!commit)
4519                         continue;
4520
4521                 /* Make sure all pending HW programming completed and
4522                  * page flips done
4523                  */
4524                 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
4525
4526                 if (ret > 0)
4527                         ret = wait_for_completion_interruptible_timeout(
4528                                         &commit->flip_done, 10*HZ);
4529
4530                 if (ret == 0)
4531                         DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
4532                                   "timed out\n", crtc->base.id, crtc->name);
4533
4534                 drm_crtc_commit_put(commit);
4535         }
4536
4537         return ret < 0 ? ret : 0;
4538 }
4539
4540 static int dm_update_crtcs_state(struct dc *dc,
4541                                  struct drm_atomic_state *state,
4542                                  bool enable,
4543                                  bool *lock_and_validation_needed)
4544 {
4545         struct drm_crtc *crtc;
4546         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
4547         int i;
4548         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
4549         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4550         struct dc_stream_state *new_stream;
4551         int ret = 0;
4552
4553         /*TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set */
4554         /* update changed items */
4555         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
4556                 struct amdgpu_crtc *acrtc = NULL;
4557                 struct amdgpu_dm_connector *aconnector = NULL;
4558                 struct drm_connector_state *new_con_state = NULL;
4559                 struct dm_connector_state *dm_conn_state = NULL;
4560                 struct drm_plane_state *new_plane_state = NULL;
4561
4562                 new_stream = NULL;
4563
4564                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4565                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4566                 acrtc = to_amdgpu_crtc(crtc);
4567
4568                 new_plane_state = drm_atomic_get_new_plane_state(state, new_crtc_state->crtc->primary);
4569
4570                 if (new_crtc_state->enable && new_plane_state && !new_plane_state->fb) {
4571                         ret = -EINVAL;
4572                         goto fail;
4573                 }
4574
4575                 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
4576
4577                 /* TODO This hack should go away */
4578                 if (aconnector && enable) {
4579                         // Make sure fake sink is created in plug-in scenario
4580                         new_con_state = drm_atomic_get_connector_state(state,
4581                                                                     &aconnector->base);
4582
4583                         if (IS_ERR(new_con_state)) {
4584                                 ret = PTR_ERR_OR_ZERO(new_con_state);
4585                                 break;
4586                         }
4587
4588                         dm_conn_state = to_dm_connector_state(new_con_state);
4589
4590                         new_stream = create_stream_for_sink(aconnector,
4591                                                              &new_crtc_state->mode,
4592                                                             dm_conn_state);
4593
4594                         /*
4595                          * we can have no stream on ACTION_SET if a display
4596                          * was disconnected during S3, in this case it not and
4597                          * error, the OS will be updated after detection, and
4598                          * do the right thing on next atomic commit
4599                          */
4600
4601                         if (!new_stream) {
4602                                 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
4603                                                 __func__, acrtc->base.base.id);
4604                                 break;
4605                         }
4606
4607                         if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
4608                             dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
4609                                 new_crtc_state->mode_changed = false;
4610                                 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
4611                                                  new_crtc_state->mode_changed);
4612                         }
4613                 }
4614
4615                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
4616                         goto next_crtc;
4617
4618                 DRM_DEBUG_DRIVER(
4619                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4620                         "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4621                         "connectors_changed:%d\n",
4622                         acrtc->crtc_id,
4623                         new_crtc_state->enable,
4624                         new_crtc_state->active,
4625                         new_crtc_state->planes_changed,
4626                         new_crtc_state->mode_changed,
4627                         new_crtc_state->active_changed,
4628                         new_crtc_state->connectors_changed);
4629
4630                 /* Remove stream for any changed/disabled CRTC */
4631                 if (!enable) {
4632
4633                         if (!dm_old_crtc_state->stream)
4634                                 goto next_crtc;
4635
4636                         DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
4637                                         crtc->base.id);
4638
4639                         /* i.e. reset mode */
4640                         if (dc_remove_stream_from_ctx(
4641                                         dc,
4642                                         dm_state->context,
4643                                         dm_old_crtc_state->stream) != DC_OK) {
4644                                 ret = -EINVAL;
4645                                 goto fail;
4646                         }
4647
4648                         dc_stream_release(dm_old_crtc_state->stream);
4649                         dm_new_crtc_state->stream = NULL;
4650
4651                         *lock_and_validation_needed = true;
4652
4653                 } else {/* Add stream for any updated/enabled CRTC */
4654                         /*
4655                          * Quick fix to prevent NULL pointer on new_stream when
4656                          * added MST connectors not found in existing crtc_state in the chained mode
4657                          * TODO: need to dig out the root cause of that
4658                          */
4659                         if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
4660                                 goto next_crtc;
4661
4662                         if (modereset_required(new_crtc_state))
4663                                 goto next_crtc;
4664
4665                         if (modeset_required(new_crtc_state, new_stream,
4666                                              dm_old_crtc_state->stream)) {
4667
4668                                 WARN_ON(dm_new_crtc_state->stream);
4669
4670                                 dm_new_crtc_state->stream = new_stream;
4671
4672                                 dc_stream_retain(new_stream);
4673
4674                                 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
4675                                                         crtc->base.id);
4676
4677                                 if (dc_add_stream_to_ctx(
4678                                                 dc,
4679                                                 dm_state->context,
4680                                                 dm_new_crtc_state->stream) != DC_OK) {
4681                                         ret = -EINVAL;
4682                                         goto fail;
4683                                 }
4684
4685                                 *lock_and_validation_needed = true;
4686                         }
4687                 }
4688
4689 next_crtc:
4690                 /* Release extra reference */
4691                 if (new_stream)
4692                          dc_stream_release(new_stream);
4693
4694                 /*
4695                  * We want to do dc stream updates that do not require a
4696                  * full modeset below.
4697                  */
4698                 if (!enable || !aconnector || modereset_required(new_crtc_state))
4699                         continue;
4700                 /*
4701                  * Given above conditions, the dc state cannot be NULL because:
4702                  * 1. We're attempting to enable a CRTC. Which has a...
4703                  * 2. Valid connector attached, and
4704                  * 3. User does not want to reset it (disable or mark inactive,
4705                  *    which can happen on a CRTC that's already disabled).
4706                  * => It currently exists.
4707                  */
4708                 BUG_ON(dm_new_crtc_state->stream == NULL);
4709
4710                 /* Color managment settings */
4711                 if (dm_new_crtc_state->base.color_mgmt_changed) {
4712                         ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state);
4713                         if (ret)
4714                                 goto fail;
4715                         amdgpu_dm_set_ctm(dm_new_crtc_state);
4716                 }
4717         }
4718
4719         return ret;
4720
4721 fail:
4722         if (new_stream)
4723                 dc_stream_release(new_stream);
4724         return ret;
4725 }
4726
4727 static int dm_update_planes_state(struct dc *dc,
4728                                   struct drm_atomic_state *state,
4729                                   bool enable,
4730                                   bool *lock_and_validation_needed)
4731 {
4732         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
4733         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
4734         struct drm_plane *plane;
4735         struct drm_plane_state *old_plane_state, *new_plane_state;
4736         struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
4737         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4738         struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
4739         int i ;
4740         /* TODO return page_flip_needed() function */
4741         bool pflip_needed  = !state->allow_modeset;
4742         int ret = 0;
4743
4744
4745         /* Add new planes, in reverse order as DC expectation */
4746         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
4747                 new_plane_crtc = new_plane_state->crtc;
4748                 old_plane_crtc = old_plane_state->crtc;
4749                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
4750                 dm_old_plane_state = to_dm_plane_state(old_plane_state);
4751
4752                 /*TODO Implement atomic check for cursor plane */
4753                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4754                         continue;
4755
4756                 /* Remove any changed/removed planes */
4757                 if (!enable) {
4758                         if (pflip_needed)
4759                                 continue;
4760
4761                         if (!old_plane_crtc)
4762                                 continue;
4763
4764                         old_crtc_state = drm_atomic_get_old_crtc_state(
4765                                         state, old_plane_crtc);
4766                         dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4767
4768                         if (!dm_old_crtc_state->stream)
4769                                 continue;
4770
4771                         DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
4772                                         plane->base.id, old_plane_crtc->base.id);
4773
4774                         if (!dc_remove_plane_from_context(
4775                                         dc,
4776                                         dm_old_crtc_state->stream,
4777                                         dm_old_plane_state->dc_state,
4778                                         dm_state->context)) {
4779
4780                                 ret = EINVAL;
4781                                 return ret;
4782                         }
4783
4784
4785                         dc_plane_state_release(dm_old_plane_state->dc_state);
4786                         dm_new_plane_state->dc_state = NULL;
4787
4788                         *lock_and_validation_needed = true;
4789
4790                 } else { /* Add new planes */
4791                         struct dc_plane_state *dc_new_plane_state;
4792
4793                         if (drm_atomic_plane_disabling(plane->state, new_plane_state))
4794                                 continue;
4795
4796                         if (!new_plane_crtc)
4797                                 continue;
4798
4799                         new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
4800                         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4801
4802                         if (!dm_new_crtc_state->stream)
4803                                 continue;
4804
4805                         if (pflip_needed)
4806                                 continue;
4807
4808                         WARN_ON(dm_new_plane_state->dc_state);
4809
4810                         dc_new_plane_state = dc_create_plane_state(dc);
4811                         if (!dc_new_plane_state)
4812                                 return -ENOMEM;
4813
4814                         DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
4815                                         plane->base.id, new_plane_crtc->base.id);
4816
4817                         ret = fill_plane_attributes(
4818                                 new_plane_crtc->dev->dev_private,
4819                                 dc_new_plane_state,
4820                                 new_plane_state,
4821                                 new_crtc_state);
4822                         if (ret) {
4823                                 dc_plane_state_release(dc_new_plane_state);
4824                                 return ret;
4825                         }
4826
4827                         /*
4828                          * Any atomic check errors that occur after this will
4829                          * not need a release. The plane state will be attached
4830                          * to the stream, and therefore part of the atomic
4831                          * state. It'll be released when the atomic state is
4832                          * cleaned.
4833                          */
4834                         if (!dc_add_plane_to_context(
4835                                         dc,
4836                                         dm_new_crtc_state->stream,
4837                                         dc_new_plane_state,
4838                                         dm_state->context)) {
4839
4840                                 dc_plane_state_release(dc_new_plane_state);
4841                                 return -EINVAL;
4842                         }
4843
4844                         dm_new_plane_state->dc_state = dc_new_plane_state;
4845
4846                         /* Tell DC to do a full surface update every time there
4847                          * is a plane change. Inefficient, but works for now.
4848                          */
4849                         dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
4850
4851                         *lock_and_validation_needed = true;
4852                 }
4853         }
4854
4855
4856         return ret;
4857 }
4858
4859 static int amdgpu_dm_atomic_check(struct drm_device *dev,
4860                                   struct drm_atomic_state *state)
4861 {
4862         struct amdgpu_device *adev = dev->dev_private;
4863         struct dc *dc = adev->dm.dc;
4864         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4865         struct drm_connector *connector;
4866         struct drm_connector_state *old_con_state, *new_con_state;
4867         struct drm_crtc *crtc;
4868         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
4869         int ret, i;
4870
4871         /*
4872          * This bool will be set for true for any modeset/reset
4873          * or plane update which implies non fast surface update.
4874          */
4875         bool lock_and_validation_needed = false;
4876
4877         ret = drm_atomic_helper_check_modeset(dev, state);
4878         if (ret)
4879                 goto fail;
4880
4881         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
4882                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
4883                     !new_crtc_state->color_mgmt_changed)
4884                         continue;
4885
4886                 if (!new_crtc_state->enable)
4887                         continue;
4888
4889                 ret = drm_atomic_add_affected_connectors(state, crtc);
4890                 if (ret)
4891                         return ret;
4892
4893                 ret = drm_atomic_add_affected_planes(state, crtc);
4894                 if (ret)
4895                         goto fail;
4896         }
4897
4898         dm_state->context = dc_create_state();
4899         ASSERT(dm_state->context);
4900         dc_resource_state_copy_construct_current(dc, dm_state->context);
4901
4902         /* Remove exiting planes if they are modified */
4903         ret = dm_update_planes_state(dc, state, false, &lock_and_validation_needed);
4904         if (ret) {
4905                 goto fail;
4906         }
4907
4908         /* Disable all crtcs which require disable */
4909         ret = dm_update_crtcs_state(dc, state, false, &lock_and_validation_needed);
4910         if (ret) {
4911                 goto fail;
4912         }
4913
4914         /* Enable all crtcs which require enable */
4915         ret = dm_update_crtcs_state(dc, state, true, &lock_and_validation_needed);
4916         if (ret) {
4917                 goto fail;
4918         }
4919
4920         /* Add new/modified planes */
4921         ret = dm_update_planes_state(dc, state, true, &lock_and_validation_needed);
4922         if (ret) {
4923                 goto fail;
4924         }
4925
4926         /* Run this here since we want to validate the streams we created */
4927         ret = drm_atomic_helper_check_planes(dev, state);
4928         if (ret)
4929                 goto fail;
4930
4931         /* Check scaling and underscan changes*/
4932         /*TODO Removed scaling changes validation due to inability to commit
4933          * new stream into context w\o causing full reset. Need to
4934          * decide how to handle.
4935          */
4936         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
4937                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
4938                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
4939                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
4940
4941                 /* Skip any modesets/resets */
4942                 if (!acrtc || drm_atomic_crtc_needs_modeset(
4943                                 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
4944                         continue;
4945
4946                 /* Skip any thing not scale or underscan changes */
4947                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
4948                         continue;
4949
4950                 lock_and_validation_needed = true;
4951         }
4952
4953         /*
4954          * For full updates case when
4955          * removing/adding/updating  streams on once CRTC while flipping
4956          * on another CRTC,
4957          * acquiring global lock  will guarantee that any such full
4958          * update commit
4959          * will wait for completion of any outstanding flip using DRMs
4960          * synchronization events.
4961          */
4962
4963         if (lock_and_validation_needed) {
4964
4965                 ret = do_aquire_global_lock(dev, state);
4966                 if (ret)
4967                         goto fail;
4968
4969                 if (dc_validate_global_state(dc, dm_state->context) != DC_OK) {
4970                         ret = -EINVAL;
4971                         goto fail;
4972                 }
4973         }
4974
4975         /* Must be success */
4976         WARN_ON(ret);
4977         return ret;
4978
4979 fail:
4980         if (ret == -EDEADLK)
4981                 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
4982         else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
4983                 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
4984         else
4985                 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
4986
4987         return ret;
4988 }
4989
4990 static bool is_dp_capable_without_timing_msa(struct dc *dc,
4991                                              struct amdgpu_dm_connector *amdgpu_dm_connector)
4992 {
4993         uint8_t dpcd_data;
4994         bool capable = false;
4995
4996         if (amdgpu_dm_connector->dc_link &&
4997                 dm_helpers_dp_read_dpcd(
4998                                 NULL,
4999                                 amdgpu_dm_connector->dc_link,
5000                                 DP_DOWN_STREAM_PORT_COUNT,
5001                                 &dpcd_data,
5002                                 sizeof(dpcd_data))) {
5003                 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
5004         }
5005
5006         return capable;
5007 }
5008 void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector,
5009                                            struct edid *edid)
5010 {
5011         int i;
5012         uint64_t val_capable;
5013         bool edid_check_required;
5014         struct detailed_timing *timing;
5015         struct detailed_non_pixel *data;
5016         struct detailed_data_monitor_range *range;
5017         struct amdgpu_dm_connector *amdgpu_dm_connector =
5018                         to_amdgpu_dm_connector(connector);
5019
5020         struct drm_device *dev = connector->dev;
5021         struct amdgpu_device *adev = dev->dev_private;
5022
5023         edid_check_required = false;
5024         if (!amdgpu_dm_connector->dc_sink) {
5025                 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
5026                 return;
5027         }
5028         if (!adev->dm.freesync_module)
5029                 return;
5030         /*
5031          * if edid non zero restrict freesync only for dp and edp
5032          */
5033         if (edid) {
5034                 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
5035                         || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
5036                         edid_check_required = is_dp_capable_without_timing_msa(
5037                                                 adev->dm.dc,
5038                                                 amdgpu_dm_connector);
5039                 }
5040         }
5041         val_capable = 0;
5042         if (edid_check_required == true && (edid->version > 1 ||
5043            (edid->version == 1 && edid->revision > 1))) {
5044                 for (i = 0; i < 4; i++) {
5045
5046                         timing  = &edid->detailed_timings[i];
5047                         data    = &timing->data.other_data;
5048                         range   = &data->data.range;
5049                         /*
5050                          * Check if monitor has continuous frequency mode
5051                          */
5052                         if (data->type != EDID_DETAIL_MONITOR_RANGE)
5053                                 continue;
5054                         /*
5055                          * Check for flag range limits only. If flag == 1 then
5056                          * no additional timing information provided.
5057                          * Default GTF, GTF Secondary curve and CVT are not
5058                          * supported
5059                          */
5060                         if (range->flags != 1)
5061                                 continue;
5062
5063                         amdgpu_dm_connector->min_vfreq = range->min_vfreq;
5064                         amdgpu_dm_connector->max_vfreq = range->max_vfreq;
5065                         amdgpu_dm_connector->pixel_clock_mhz =
5066                                 range->pixel_clock_mhz * 10;
5067                         break;
5068                 }
5069
5070                 if (amdgpu_dm_connector->max_vfreq -
5071                                 amdgpu_dm_connector->min_vfreq > 10) {
5072                         amdgpu_dm_connector->caps.supported = true;
5073                         amdgpu_dm_connector->caps.min_refresh_in_micro_hz =
5074                                         amdgpu_dm_connector->min_vfreq * 1000000;
5075                         amdgpu_dm_connector->caps.max_refresh_in_micro_hz =
5076                                         amdgpu_dm_connector->max_vfreq * 1000000;
5077                                 val_capable = 1;
5078                 }
5079         }
5080
5081         /*
5082          * TODO figure out how to notify user-mode or DRM of freesync caps
5083          * once we figure out how to deal with freesync in an upstreamable
5084          * fashion
5085          */
5086
5087 }
5088
5089 void amdgpu_dm_remove_sink_from_freesync_module(struct drm_connector *connector)
5090 {
5091         /*
5092          * TODO fill in once we figure out how to deal with freesync in
5093          * an upstreamable fashion
5094          */
5095 }