drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 /* The caprices of the preprocessor require that this be declared right here */
  27 #define CREATE_TRACE_POINTS
  28
  29 #include "dm_services_types.h"
  30 #include "dc.h"
  31 #include "link_enc_cfg.h"
  32 #include "dc/inc/core_types.h"
  33 #include "dal_asic_id.h"
  34 #include "dmub/dmub_srv.h"
  35 #include "dc/inc/hw/dmcu.h"
  36 #include "dc/inc/hw/abm.h"
  37 #include "dc/dc_dmub_srv.h"
  38 #include "dc/dc_edid_parser.h"
  39 #include "dc/dc_stat.h"
  40 #include "amdgpu_dm_trace.h"
  41 #include "dpcd_defs.h"
  42 #include "link/protocols/link_dpcd.h"
  43 #include "link_service_types.h"
  44 #include "link/protocols/link_dp_capability.h"
  45 #include "link/protocols/link_ddc.h"
  46
  47 #include "vid.h"
  48 #include "amdgpu.h"
  49 #include "amdgpu_display.h"
  50 #include "amdgpu_ucode.h"
  51 #include "atom.h"
  52 #include "amdgpu_dm.h"
  53 #include "amdgpu_dm_plane.h"
  54 #include "amdgpu_dm_crtc.h"
  55 #include "amdgpu_dm_hdcp.h"
  56 #include <drm/display/drm_hdcp_helper.h>
  57 #include "amdgpu_pm.h"
  58 #include "amdgpu_atombios.h"
  59
  60 #include "amd_shared.h"
  61 #include "amdgpu_dm_irq.h"
  62 #include "dm_helpers.h"
  63 #include "amdgpu_dm_mst_types.h"
  64 #if defined(CONFIG_DEBUG_FS)
  65 #include "amdgpu_dm_debugfs.h"
  66 #endif
  67 #include "amdgpu_dm_psr.h"
  68 #include "amdgpu_dm_replay.h"
  69
  70 #include "ivsrcid/ivsrcid_vislands30.h"
  71
  72 #include <linux/backlight.h>
  73 #include <linux/module.h>
  74 #include <linux/moduleparam.h>
  75 #include <linux/types.h>
  76 #include <linux/pm_runtime.h>
  77 #include <linux/pci.h>
  78 #include <linux/firmware.h>
  79 #include <linux/component.h>
  80 #include <linux/dmi.h>
  81
  82 #include <drm/display/drm_dp_mst_helper.h>
  83 #include <drm/display/drm_hdmi_helper.h>
  84 #include <drm/drm_atomic.h>
  85 #include <drm/drm_atomic_uapi.h>
  86 #include <drm/drm_atomic_helper.h>
  87 #include <drm/drm_blend.h>
  88 #include <drm/drm_fourcc.h>
  89 #include <drm/drm_edid.h>
  90 #include <drm/drm_eld.h>
  91 #include <drm/drm_vblank.h>
  92 #include <drm/drm_audio_component.h>
  93 #include <drm/drm_gem_atomic_helper.h>
  94 #include <drm/drm_plane_helper.h>
  95
  96 #include <acpi/video.h>
  97
  98 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
  99
 100 #include "dcn/dcn_1_0_offset.h"
 101 #include "dcn/dcn_1_0_sh_mask.h"
 102 #include "soc15_hw_ip.h"
 103 #include "soc15_common.h"
 104 #include "vega10_ip_offset.h"
 105
 106 #include "gc/gc_11_0_0_offset.h"
 107 #include "gc/gc_11_0_0_sh_mask.h"
 108
 109 #include "modules/inc/mod_freesync.h"
 110 #include "modules/power/power_helpers.h"
 111
 112 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
 113 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
 114 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
 115 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
 116 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
 117 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
 118 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
 119 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
 120 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
 121 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
 122 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
 123 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
 124 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
 125 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
 126 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
 127 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
 128 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"
 129 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
 130 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
 131 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
 132 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
 133 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
 134
 135 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
 136 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
 137 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
 138 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
 139
 140 #define FIRMWARE_RAVEN_DMCU             "amdgpu/raven_dmcu.bin"
 141 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
 142
 143 #define FIRMWARE_NAVI12_DMCU            "amdgpu/navi12_dmcu.bin"
 144 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
 145
 146 #define FIRMWARE_DCN_35_DMUB "amdgpu/dcn_3_5_dmcub.bin"
 147 MODULE_FIRMWARE(FIRMWARE_DCN_35_DMUB);
 148
 149 /* Number of bytes in PSP header for firmware. */
 150 #define PSP_HEADER_BYTES 0x100
 151
 152 /* Number of bytes in PSP footer for firmware. */
 153 #define PSP_FOOTER_BYTES 0x100
 154
 155 /**
 156  * DOC: overview
 157  *
 158  * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
 159  * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
 160  * requests into DC requests, and DC responses into DRM responses.
 161  *
 162  * The root control structure is &struct amdgpu_display_manager.
 163  */
 164
 165 /* basic init/fini API */
 166 static int amdgpu_dm_init(struct amdgpu_device *adev);
 167 static void amdgpu_dm_fini(struct amdgpu_device *adev);
 168 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
 169
 170 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
 171 {
 172         switch (link->dpcd_caps.dongle_type) {
 173         case DISPLAY_DONGLE_NONE:
 174                 return DRM_MODE_SUBCONNECTOR_Native;
 175         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
 176                 return DRM_MODE_SUBCONNECTOR_VGA;
 177         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
 178         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 179                 return DRM_MODE_SUBCONNECTOR_DVID;
 180         case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
 181         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 182                 return DRM_MODE_SUBCONNECTOR_HDMIA;
 183         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 184         default:
 185                 return DRM_MODE_SUBCONNECTOR_Unknown;
 186         }
 187 }
 188
 189 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
 190 {
 191         struct dc_link *link = aconnector->dc_link;
 192         struct drm_connector *connector = &aconnector->base;
 193         enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
 194
 195         if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
 196                 return;
 197
 198         if (aconnector->dc_sink)
 199                 subconnector = get_subconnector_type(link);
 200
 201         drm_object_property_set_value(&connector->base,
 202                         connector->dev->mode_config.dp_subconnector_property,
 203                         subconnector);
 204 }
 205
 206 /*
 207  * initializes drm_device display related structures, based on the information
 208  * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
 209  * drm_encoder, drm_mode_config
 210  *
 211  * Returns 0 on success
 212  */
 213 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
 214 /* removes and deallocates the drm structures, created by the above function */
 215 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
 216
 217 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
 218                                     struct amdgpu_dm_connector *amdgpu_dm_connector,
 219                                     u32 link_index,
 220                                     struct amdgpu_encoder *amdgpu_encoder);
 221 static int amdgpu_dm_encoder_init(struct drm_device *dev,
 222                                   struct amdgpu_encoder *aencoder,
 223                                   uint32_t link_index);
 224
 225 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
 226
 227 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
 228
 229 static int amdgpu_dm_atomic_check(struct drm_device *dev,
 230                                   struct drm_atomic_state *state);
 231
 232 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);
 233 static void handle_hpd_rx_irq(void *param);
 234
 235 static bool
 236 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
 237                                  struct drm_crtc_state *new_crtc_state);
 238 /*
 239  * dm_vblank_get_counter
 240  *
 241  * @brief
 242  * Get counter for number of vertical blanks
 243  *
 244  * @param
 245  * struct amdgpu_device *adev - [in] desired amdgpu device
 246  * int disp_idx - [in] which CRTC to get the counter from
 247  *
 248  * @return
 249  * Counter for vertical blanks
 250  */
 251 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 252 {
 253         struct amdgpu_crtc *acrtc = NULL;
 254
 255         if (crtc >= adev->mode_info.num_crtc)
 256                 return 0;
 257
 258         acrtc = adev->mode_info.crtcs[crtc];
 259
 260         if (!acrtc->dm_irq_params.stream) {
 261                 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 262                           crtc);
 263                 return 0;
 264         }
 265
 266         return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
 267 }
 268
 269 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 270                                   u32 *vbl, u32 *position)
 271 {
 272         u32 v_blank_start, v_blank_end, h_position, v_position;
 273         struct amdgpu_crtc *acrtc = NULL;
 274
 275         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 276                 return -EINVAL;
 277
 278         acrtc = adev->mode_info.crtcs[crtc];
 279
 280         if (!acrtc->dm_irq_params.stream) {
 281                 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 282                           crtc);
 283                 return 0;
 284         }
 285
 286         /*
 287          * TODO rework base driver to use values directly.
 288          * for now parse it back into reg-format
 289          */
 290         dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
 291                                  &v_blank_start,
 292                                  &v_blank_end,
 293                                  &h_position,
 294                                  &v_position);
 295
 296         *position = v_position | (h_position << 16);
 297         *vbl = v_blank_start | (v_blank_end << 16);
 298
 299         return 0;
 300 }
 301
 302 static bool dm_is_idle(void *handle)
 303 {
 304         /* XXX todo */
 305         return true;
 306 }
 307
 308 static int dm_wait_for_idle(void *handle)
 309 {
 310         /* XXX todo */
 311         return 0;
 312 }
 313
 314 static bool dm_check_soft_reset(void *handle)
 315 {
 316         return false;
 317 }
 318
 319 static int dm_soft_reset(void *handle)
 320 {
 321         /* XXX todo */
 322         return 0;
 323 }
 324
 325 static struct amdgpu_crtc *
 326 get_crtc_by_otg_inst(struct amdgpu_device *adev,
 327                      int otg_inst)
 328 {
 329         struct drm_device *dev = adev_to_drm(adev);
 330         struct drm_crtc *crtc;
 331         struct amdgpu_crtc *amdgpu_crtc;
 332
 333         if (WARN_ON(otg_inst == -1))
 334                 return adev->mode_info.crtcs[0];
 335
 336         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 337                 amdgpu_crtc = to_amdgpu_crtc(crtc);
 338
 339                 if (amdgpu_crtc->otg_inst == otg_inst)
 340                         return amdgpu_crtc;
 341         }
 342
 343         return NULL;
 344 }
 345
 346 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
 347                                               struct dm_crtc_state *new_state)
 348 {
 349         if (new_state->freesync_config.state ==  VRR_STATE_ACTIVE_FIXED)
 350                 return true;
 351         else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state))
 352                 return true;
 353         else
 354                 return false;
 355 }
 356
 357 static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update,
 358                                         int planes_count)
 359 {
 360         int i, j;
 361
 362         for (i = 0, j = planes_count - 1; i < j; i++, j--)
 363                 swap(array_of_surface_update[i], array_of_surface_update[j]);
 364 }
 365
 366 /**
 367  * update_planes_and_stream_adapter() - Send planes to be updated in DC
 368  *
 369  * DC has a generic way to update planes and stream via
 370  * dc_update_planes_and_stream function; however, DM might need some
 371  * adjustments and preparation before calling it. This function is a wrapper
 372  * for the dc_update_planes_and_stream that does any required configuration
 373  * before passing control to DC.
 374  *
 375  * @dc: Display Core control structure
 376  * @update_type: specify whether it is FULL/MEDIUM/FAST update
 377  * @planes_count: planes count to update
 378  * @stream: stream state
 379  * @stream_update: stream update
 380  * @array_of_surface_update: dc surface update pointer
 381  *
 382  */
 383 static inline bool update_planes_and_stream_adapter(struct dc *dc,
 384                                                     int update_type,
 385                                                     int planes_count,
 386                                                     struct dc_stream_state *stream,
 387                                                     struct dc_stream_update *stream_update,
 388                                                     struct dc_surface_update *array_of_surface_update)
 389 {
 390         reverse_planes_order(array_of_surface_update, planes_count);
 391
 392         /*
 393          * Previous frame finished and HW is ready for optimization.
 394          */
 395         if (update_type == UPDATE_TYPE_FAST)
 396                 dc_post_update_surfaces_to_stream(dc);
 397
 398         return dc_update_planes_and_stream(dc,
 399                                            array_of_surface_update,
 400                                            planes_count,
 401                                            stream,
 402                                            stream_update);
 403 }
 404
 405 /**
 406  * dm_pflip_high_irq() - Handle pageflip interrupt
 407  * @interrupt_params: ignored
 408  *
 409  * Handles the pageflip interrupt by notifying all interested parties
 410  * that the pageflip has been completed.
 411  */
 412 static void dm_pflip_high_irq(void *interrupt_params)
 413 {
 414         struct amdgpu_crtc *amdgpu_crtc;
 415         struct common_irq_params *irq_params = interrupt_params;
 416         struct amdgpu_device *adev = irq_params->adev;
 417         struct drm_device *dev = adev_to_drm(adev);
 418         unsigned long flags;
 419         struct drm_pending_vblank_event *e;
 420         u32 vpos, hpos, v_blank_start, v_blank_end;
 421         bool vrr_active;
 422
 423         amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
 424
 425         /* IRQ could occur when in initial stage */
 426         /* TODO work and BO cleanup */
 427         if (amdgpu_crtc == NULL) {
 428                 drm_dbg_state(dev, "CRTC is null, returning.\n");
 429                 return;
 430         }
 431
 432         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 433
 434         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
 435                 drm_dbg_state(dev,
 436                               "amdgpu_crtc->pflip_status = %d != AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p]\n",
 437                               amdgpu_crtc->pflip_status, AMDGPU_FLIP_SUBMITTED,
 438                               amdgpu_crtc->crtc_id, amdgpu_crtc);
 439                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 440                 return;
 441         }
 442
 443         /* page flip completed. */
 444         e = amdgpu_crtc->event;
 445         amdgpu_crtc->event = NULL;
 446
 447         WARN_ON(!e);
 448
 449         vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc);
 450
 451         /* Fixed refresh rate, or VRR scanout position outside front-porch? */
 452         if (!vrr_active ||
 453             !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
 454                                       &v_blank_end, &hpos, &vpos) ||
 455             (vpos < v_blank_start)) {
 456                 /* Update to correct count and vblank timestamp if racing with
 457                  * vblank irq. This also updates to the correct vblank timestamp
 458                  * even in VRR mode, as scanout is past the front-porch atm.
 459                  */
 460                 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
 461
 462                 /* Wake up userspace by sending the pageflip event with proper
 463                  * count and timestamp of vblank of flip completion.
 464                  */
 465                 if (e) {
 466                         drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
 467
 468                         /* Event sent, so done with vblank for this flip */
 469                         drm_crtc_vblank_put(&amdgpu_crtc->base);
 470                 }
 471         } else if (e) {
 472                 /* VRR active and inside front-porch: vblank count and
 473                  * timestamp for pageflip event will only be up to date after
 474                  * drm_crtc_handle_vblank() has been executed from late vblank
 475                  * irq handler after start of back-porch (vline 0). We queue the
 476                  * pageflip event for send-out by drm_crtc_handle_vblank() with
 477                  * updated timestamp and count, once it runs after us.
 478                  *
 479                  * We need to open-code this instead of using the helper
 480                  * drm_crtc_arm_vblank_event(), as that helper would
 481                  * call drm_crtc_accurate_vblank_count(), which we must
 482                  * not call in VRR mode while we are in front-porch!
 483                  */
 484
 485                 /* sequence will be replaced by real count during send-out. */
 486                 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
 487                 e->pipe = amdgpu_crtc->crtc_id;
 488
 489                 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
 490                 e = NULL;
 491         }
 492
 493         /* Keep track of vblank of this flip for flip throttling. We use the
 494          * cooked hw counter, as that one incremented at start of this vblank
 495          * of pageflip completion, so last_flip_vblank is the forbidden count
 496          * for queueing new pageflips if vsync + VRR is enabled.
 497          */
 498         amdgpu_crtc->dm_irq_params.last_flip_vblank =
 499                 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
 500
 501         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 502         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 503
 504         drm_dbg_state(dev,
 505                       "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
 506                       amdgpu_crtc->crtc_id, amdgpu_crtc, vrr_active, (int)!e);
 507 }
 508
 509 static void dm_vupdate_high_irq(void *interrupt_params)
 510 {
 511         struct common_irq_params *irq_params = interrupt_params;
 512         struct amdgpu_device *adev = irq_params->adev;
 513         struct amdgpu_crtc *acrtc;
 514         struct drm_device *drm_dev;
 515         struct drm_vblank_crtc *vblank;
 516         ktime_t frame_duration_ns, previous_timestamp;
 517         unsigned long flags;
 518         int vrr_active;
 519
 520         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
 521
 522         if (acrtc) {
 523                 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
 524                 drm_dev = acrtc->base.dev;
 525                 vblank = &drm_dev->vblank[acrtc->base.index];
 526                 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
 527                 frame_duration_ns = vblank->time - previous_timestamp;
 528
 529                 if (frame_duration_ns > 0) {
 530                         trace_amdgpu_refresh_rate_track(acrtc->base.index,
 531                                                 frame_duration_ns,
 532                                                 ktime_divns(NSEC_PER_SEC, frame_duration_ns));
 533                         atomic64_set(&irq_params->previous_timestamp, vblank->time);
 534                 }
 535
 536                 drm_dbg_vbl(drm_dev,
 537                             "crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
 538                             vrr_active);
 539
 540                 /* Core vblank handling is done here after end of front-porch in
 541                  * vrr mode, as vblank timestamping will give valid results
 542                  * while now done after front-porch. This will also deliver
 543                  * page-flip completion events that have been queued to us
 544                  * if a pageflip happened inside front-porch.
 545                  */
 546                 if (vrr_active) {
 547                         amdgpu_dm_crtc_handle_vblank(acrtc);
 548
 549                         /* BTR processing for pre-DCE12 ASICs */
 550                         if (acrtc->dm_irq_params.stream &&
 551                             adev->family < AMDGPU_FAMILY_AI) {
 552                                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 553                                 mod_freesync_handle_v_update(
 554                                     adev->dm.freesync_module,
 555                                     acrtc->dm_irq_params.stream,
 556                                     &acrtc->dm_irq_params.vrr_params);
 557
 558                                 dc_stream_adjust_vmin_vmax(
 559                                     adev->dm.dc,
 560                                     acrtc->dm_irq_params.stream,
 561                                     &acrtc->dm_irq_params.vrr_params.adjust);
 562                                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 563                         }
 564                 }
 565         }
 566 }
 567
 568 /**
 569  * dm_crtc_high_irq() - Handles CRTC interrupt
 570  * @interrupt_params: used for determining the CRTC instance
 571  *
 572  * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
 573  * event handler.
 574  */
 575 static void dm_crtc_high_irq(void *interrupt_params)
 576 {
 577         struct common_irq_params *irq_params = interrupt_params;
 578         struct amdgpu_device *adev = irq_params->adev;
 579         struct amdgpu_crtc *acrtc;
 580         unsigned long flags;
 581         int vrr_active;
 582
 583         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
 584         if (!acrtc)
 585                 return;
 586
 587         vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
 588
 589         drm_dbg_vbl(adev_to_drm(adev),
 590                     "crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
 591                     vrr_active, acrtc->dm_irq_params.active_planes);
 592
 593         /**
 594          * Core vblank handling at start of front-porch is only possible
 595          * in non-vrr mode, as only there vblank timestamping will give
 596          * valid results while done in front-porch. Otherwise defer it
 597          * to dm_vupdate_high_irq after end of front-porch.
 598          */
 599         if (!vrr_active)
 600                 amdgpu_dm_crtc_handle_vblank(acrtc);
 601
 602         /**
 603          * Following stuff must happen at start of vblank, for crc
 604          * computation and below-the-range btr support in vrr mode.
 605          */
 606         amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
 607
 608         /* BTR updates need to happen before VUPDATE on Vega and above. */
 609         if (adev->family < AMDGPU_FAMILY_AI)
 610                 return;
 611
 612         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 613
 614         if (acrtc->dm_irq_params.stream &&
 615             acrtc->dm_irq_params.vrr_params.supported &&
 616             acrtc->dm_irq_params.freesync_config.state ==
 617                     VRR_STATE_ACTIVE_VARIABLE) {
 618                 mod_freesync_handle_v_update(adev->dm.freesync_module,
 619                                              acrtc->dm_irq_params.stream,
 620                                              &acrtc->dm_irq_params.vrr_params);
 621
 622                 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
 623                                            &acrtc->dm_irq_params.vrr_params.adjust);
 624         }
 625
 626         /*
 627          * If there aren't any active_planes then DCH HUBP may be clock-gated.
 628          * In that case, pageflip completion interrupts won't fire and pageflip
 629          * completion events won't get delivered. Prevent this by sending
 630          * pending pageflip events from here if a flip is still pending.
 631          *
 632          * If any planes are enabled, use dm_pflip_high_irq() instead, to
 633          * avoid race conditions between flip programming and completion,
 634          * which could cause too early flip completion events.
 635          */
 636         if (adev->family >= AMDGPU_FAMILY_RV &&
 637             acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
 638             acrtc->dm_irq_params.active_planes == 0) {
 639                 if (acrtc->event) {
 640                         drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
 641                         acrtc->event = NULL;
 642                         drm_crtc_vblank_put(&acrtc->base);
 643                 }
 644                 acrtc->pflip_status = AMDGPU_FLIP_NONE;
 645         }
 646
 647         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 648 }
 649
 650 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 651 /**
 652  * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
 653  * DCN generation ASICs
 654  * @interrupt_params: interrupt parameters
 655  *
 656  * Used to set crc window/read out crc value at vertical line 0 position
 657  */
 658 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
 659 {
 660         struct common_irq_params *irq_params = interrupt_params;
 661         struct amdgpu_device *adev = irq_params->adev;
 662         struct amdgpu_crtc *acrtc;
 663
 664         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
 665
 666         if (!acrtc)
 667                 return;
 668
 669         amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
 670 }
 671 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
 672
 673 /**
 674  * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
 675  * @adev: amdgpu_device pointer
 676  * @notify: dmub notification structure
 677  *
 678  * Dmub AUX or SET_CONFIG command completion processing callback
 679  * Copies dmub notification to DM which is to be read by AUX command.
 680  * issuing thread and also signals the event to wake up the thread.
 681  */
 682 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
 683                                         struct dmub_notification *notify)
 684 {
 685         if (adev->dm.dmub_notify)
 686                 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));
 687         if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)
 688                 complete(&adev->dm.dmub_aux_transfer_done);
 689 }
 690
 691 /**
 692  * dmub_hpd_callback - DMUB HPD interrupt processing callback.
 693  * @adev: amdgpu_device pointer
 694  * @notify: dmub notification structure
 695  *
 696  * Dmub Hpd interrupt processing callback. Gets displayindex through the
 697  * ink index and calls helper to do the processing.
 698  */
 699 static void dmub_hpd_callback(struct amdgpu_device *adev,
 700                               struct dmub_notification *notify)
 701 {
 702         struct amdgpu_dm_connector *aconnector;
 703         struct amdgpu_dm_connector *hpd_aconnector = NULL;
 704         struct drm_connector *connector;
 705         struct drm_connector_list_iter iter;
 706         struct dc_link *link;
 707         u8 link_index = 0;
 708         struct drm_device *dev;
 709
 710         if (adev == NULL)
 711                 return;
 712
 713         if (notify == NULL) {
 714                 DRM_ERROR("DMUB HPD callback notification was NULL");
 715                 return;
 716         }
 717
 718         if (notify->link_index > adev->dm.dc->link_count) {
 719                 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index);
 720                 return;
 721         }
 722
 723         link_index = notify->link_index;
 724         link = adev->dm.dc->links[link_index];
 725         dev = adev->dm.ddev;
 726
 727         drm_connector_list_iter_begin(dev, &iter);
 728         drm_for_each_connector_iter(connector, &iter) {
 729                 aconnector = to_amdgpu_dm_connector(connector);
 730                 if (link && aconnector->dc_link == link) {
 731                         if (notify->type == DMUB_NOTIFICATION_HPD)
 732                                 DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index);
 733                         else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 734                                 DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index);
 735                         else
 736                                 DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n",
 737                                                 notify->type, link_index);
 738
 739                         hpd_aconnector = aconnector;
 740                         break;
 741                 }
 742         }
 743         drm_connector_list_iter_end(&iter);
 744
 745         if (hpd_aconnector) {
 746                 if (notify->type == DMUB_NOTIFICATION_HPD)
 747                         handle_hpd_irq_helper(hpd_aconnector);
 748                 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 749                         handle_hpd_rx_irq(hpd_aconnector);
 750         }
 751 }
 752
 753 /**
 754  * register_dmub_notify_callback - Sets callback for DMUB notify
 755  * @adev: amdgpu_device pointer
 756  * @type: Type of dmub notification
 757  * @callback: Dmub interrupt callback function
 758  * @dmub_int_thread_offload: offload indicator
 759  *
 760  * API to register a dmub callback handler for a dmub notification
 761  * Also sets indicator whether callback processing to be offloaded.
 762  * to dmub interrupt handling thread
 763  * Return: true if successfully registered, false if there is existing registration
 764  */
 765 static bool register_dmub_notify_callback(struct amdgpu_device *adev,
 766                                           enum dmub_notification_type type,
 767                                           dmub_notify_interrupt_callback_t callback,
 768                                           bool dmub_int_thread_offload)
 769 {
 770         if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {
 771                 adev->dm.dmub_callback[type] = callback;
 772                 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;
 773         } else
 774                 return false;
 775
 776         return true;
 777 }
 778
 779 static void dm_handle_hpd_work(struct work_struct *work)
 780 {
 781         struct dmub_hpd_work *dmub_hpd_wrk;
 782
 783         dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);
 784
 785         if (!dmub_hpd_wrk->dmub_notify) {
 786                 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL");
 787                 return;
 788         }
 789
 790         if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {
 791                 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,
 792                 dmub_hpd_wrk->dmub_notify);
 793         }
 794
 795         kfree(dmub_hpd_wrk->dmub_notify);
 796         kfree(dmub_hpd_wrk);
 797
 798 }
 799
 800 #define DMUB_TRACE_MAX_READ 64
 801 /**
 802  * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
 803  * @interrupt_params: used for determining the Outbox instance
 804  *
 805  * Handles the Outbox Interrupt
 806  * event handler.
 807  */
 808 static void dm_dmub_outbox1_low_irq(void *interrupt_params)
 809 {
 810         struct dmub_notification notify;
 811         struct common_irq_params *irq_params = interrupt_params;
 812         struct amdgpu_device *adev = irq_params->adev;
 813         struct amdgpu_display_manager *dm = &adev->dm;
 814         struct dmcub_trace_buf_entry entry = { 0 };
 815         u32 count = 0;
 816         struct dmub_hpd_work *dmub_hpd_wrk;
 817         struct dc_link *plink = NULL;
 818
 819         if (dc_enable_dmub_notifications(adev->dm.dc) &&
 820                 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
 821
 822                 do {
 823                         dc_stat_get_dmub_notification(adev->dm.dc, &notify);
 824                         if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {
 825                                 DRM_ERROR("DM: notify type %d invalid!", notify.type);
 826                                 continue;
 827                         }
 828                         if (!dm->dmub_callback[notify.type]) {
 829                                 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type);
 830                                 continue;
 831                         }
 832                         if (dm->dmub_thread_offload[notify.type] == true) {
 833                                 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);
 834                                 if (!dmub_hpd_wrk) {
 835                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk");
 836                                         return;
 837                                 }
 838                                 dmub_hpd_wrk->dmub_notify = kmemdup(&notify, sizeof(struct dmub_notification),
 839                                                                     GFP_ATOMIC);
 840                                 if (!dmub_hpd_wrk->dmub_notify) {
 841                                         kfree(dmub_hpd_wrk);
 842                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify");
 843                                         return;
 844                                 }
 845                                 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
 846                                 dmub_hpd_wrk->adev = adev;
 847                                 if (notify.type == DMUB_NOTIFICATION_HPD) {
 848                                         plink = adev->dm.dc->links[notify.link_index];
 849                                         if (plink) {
 850                                                 plink->hpd_status =
 851                                                         notify.hpd_status == DP_HPD_PLUG;
 852                                         }
 853                                 }
 854                                 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
 855                         } else {
 856                                 dm->dmub_callback[notify.type](adev, &notify);
 857                         }
 858                 } while (notify.pending_notification);
 859         }
 860
 861
 862         do {
 863                 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
 864                         trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
 865                                                         entry.param0, entry.param1);
 866
 867                         DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
 868                                  entry.trace_code, entry.tick_count, entry.param0, entry.param1);
 869                 } else
 870                         break;
 871
 872                 count++;
 873
 874         } while (count <= DMUB_TRACE_MAX_READ);
 875
 876         if (count > DMUB_TRACE_MAX_READ)
 877                 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
 878 }
 879
 880 static int dm_set_clockgating_state(void *handle,
 881                   enum amd_clockgating_state state)
 882 {
 883         return 0;
 884 }
 885
 886 static int dm_set_powergating_state(void *handle,
 887                   enum amd_powergating_state state)
 888 {
 889         return 0;
 890 }
 891
 892 /* Prototypes of private functions */
 893 static int dm_early_init(void *handle);
 894
 895 /* Allocate memory for FBC compressed data  */
 896 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 897 {
 898         struct drm_device *dev = connector->dev;
 899         struct amdgpu_device *adev = drm_to_adev(dev);
 900         struct dm_compressor_info *compressor = &adev->dm.compressor;
 901         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
 902         struct drm_display_mode *mode;
 903         unsigned long max_size = 0;
 904
 905         if (adev->dm.dc->fbc_compressor == NULL)
 906                 return;
 907
 908         if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
 909                 return;
 910
 911         if (compressor->bo_ptr)
 912                 return;
 913
 914
 915         list_for_each_entry(mode, &connector->modes, head) {
 916                 if (max_size < mode->htotal * mode->vtotal)
 917                         max_size = mode->htotal * mode->vtotal;
 918         }
 919
 920         if (max_size) {
 921                 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
 922                             AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
 923                             &compressor->gpu_addr, &compressor->cpu_addr);
 924
 925                 if (r)
 926                         DRM_ERROR("DM: Failed to initialize FBC\n");
 927                 else {
 928                         adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
 929                         DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
 930                 }
 931
 932         }
 933
 934 }
 935
 936 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
 937                                           int pipe, bool *enabled,
 938                                           unsigned char *buf, int max_bytes)
 939 {
 940         struct drm_device *dev = dev_get_drvdata(kdev);
 941         struct amdgpu_device *adev = drm_to_adev(dev);
 942         struct drm_connector *connector;
 943         struct drm_connector_list_iter conn_iter;
 944         struct amdgpu_dm_connector *aconnector;
 945         int ret = 0;
 946
 947         *enabled = false;
 948
 949         mutex_lock(&adev->dm.audio_lock);
 950
 951         drm_connector_list_iter_begin(dev, &conn_iter);
 952         drm_for_each_connector_iter(connector, &conn_iter) {
 953                 aconnector = to_amdgpu_dm_connector(connector);
 954                 if (aconnector->audio_inst != port)
 955                         continue;
 956
 957                 *enabled = true;
 958                 ret = drm_eld_size(connector->eld);
 959                 memcpy(buf, connector->eld, min(max_bytes, ret));
 960
 961                 break;
 962         }
 963         drm_connector_list_iter_end(&conn_iter);
 964
 965         mutex_unlock(&adev->dm.audio_lock);
 966
 967         DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
 968
 969         return ret;
 970 }
 971
 972 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
 973         .get_eld = amdgpu_dm_audio_component_get_eld,
 974 };
 975
 976 static int amdgpu_dm_audio_component_bind(struct device *kdev,
 977                                        struct device *hda_kdev, void *data)
 978 {
 979         struct drm_device *dev = dev_get_drvdata(kdev);
 980         struct amdgpu_device *adev = drm_to_adev(dev);
 981         struct drm_audio_component *acomp = data;
 982
 983         acomp->ops = &amdgpu_dm_audio_component_ops;
 984         acomp->dev = kdev;
 985         adev->dm.audio_component = acomp;
 986
 987         return 0;
 988 }
 989
 990 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
 991                                           struct device *hda_kdev, void *data)
 992 {
 993         struct drm_device *dev = dev_get_drvdata(kdev);
 994         struct amdgpu_device *adev = drm_to_adev(dev);
 995         struct drm_audio_component *acomp = data;
 996
 997         acomp->ops = NULL;
 998         acomp->dev = NULL;
 999         adev->dm.audio_component = NULL;
1000 }
1001
1002 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
1003         .bind   = amdgpu_dm_audio_component_bind,
1004         .unbind = amdgpu_dm_audio_component_unbind,
1005 };
1006
1007 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
1008 {
1009         int i, ret;
1010
1011         if (!amdgpu_audio)
1012                 return 0;
1013
1014         adev->mode_info.audio.enabled = true;
1015
1016         adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
1017
1018         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1019                 adev->mode_info.audio.pin[i].channels = -1;
1020                 adev->mode_info.audio.pin[i].rate = -1;
1021                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1022                 adev->mode_info.audio.pin[i].status_bits = 0;
1023                 adev->mode_info.audio.pin[i].category_code = 0;
1024                 adev->mode_info.audio.pin[i].connected = false;
1025                 adev->mode_info.audio.pin[i].id =
1026                         adev->dm.dc->res_pool->audios[i]->inst;
1027                 adev->mode_info.audio.pin[i].offset = 0;
1028         }
1029
1030         ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1031         if (ret < 0)
1032                 return ret;
1033
1034         adev->dm.audio_registered = true;
1035
1036         return 0;
1037 }
1038
1039 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
1040 {
1041         if (!amdgpu_audio)
1042                 return;
1043
1044         if (!adev->mode_info.audio.enabled)
1045                 return;
1046
1047         if (adev->dm.audio_registered) {
1048                 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1049                 adev->dm.audio_registered = false;
1050         }
1051
1052         /* TODO: Disable audio? */
1053
1054         adev->mode_info.audio.enabled = false;
1055 }
1056
1057 static  void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
1058 {
1059         struct drm_audio_component *acomp = adev->dm.audio_component;
1060
1061         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
1062                 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
1063
1064                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
1065                                                  pin, -1);
1066         }
1067 }
1068
1069 static int dm_dmub_hw_init(struct amdgpu_device *adev)
1070 {
1071         const struct dmcub_firmware_header_v1_0 *hdr;
1072         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1073         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
1074         const struct firmware *dmub_fw = adev->dm.dmub_fw;
1075         struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1076         struct abm *abm = adev->dm.dc->res_pool->abm;
1077         struct dc_context *ctx = adev->dm.dc->ctx;
1078         struct dmub_srv_hw_params hw_params;
1079         enum dmub_status status;
1080         const unsigned char *fw_inst_const, *fw_bss_data;
1081         u32 i, fw_inst_const_size, fw_bss_data_size;
1082         bool has_hw_support;
1083
1084         if (!dmub_srv)
1085                 /* DMUB isn't supported on the ASIC. */
1086                 return 0;
1087
1088         if (!fb_info) {
1089                 DRM_ERROR("No framebuffer info for DMUB service.\n");
1090                 return -EINVAL;
1091         }
1092
1093         if (!dmub_fw) {
1094                 /* Firmware required for DMUB support. */
1095                 DRM_ERROR("No firmware provided for DMUB.\n");
1096                 return -EINVAL;
1097         }
1098
1099         /* initialize register offsets for ASICs with runtime initialization available */
1100         if (dmub_srv->hw_funcs.init_reg_offsets)
1101                 dmub_srv->hw_funcs.init_reg_offsets(dmub_srv, ctx);
1102
1103         status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
1104         if (status != DMUB_STATUS_OK) {
1105                 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
1106                 return -EINVAL;
1107         }
1108
1109         if (!has_hw_support) {
1110                 DRM_INFO("DMUB unsupported on ASIC\n");
1111                 return 0;
1112         }
1113
1114         /* Reset DMCUB if it was previously running - before we overwrite its memory. */
1115         status = dmub_srv_hw_reset(dmub_srv);
1116         if (status != DMUB_STATUS_OK)
1117                 DRM_WARN("Error resetting DMUB HW: %d\n", status);
1118
1119         hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
1120
1121         fw_inst_const = dmub_fw->data +
1122                         le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1123                         PSP_HEADER_BYTES;
1124
1125         fw_bss_data = dmub_fw->data +
1126                       le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1127                       le32_to_cpu(hdr->inst_const_bytes);
1128
1129         /* Copy firmware and bios info into FB memory. */
1130         fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1131                              PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1132
1133         fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1134
1135         /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
1136          * amdgpu_ucode_init_single_fw will load dmub firmware
1137          * fw_inst_const part to cw0; otherwise, the firmware back door load
1138          * will be done by dm_dmub_hw_init
1139          */
1140         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1141                 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
1142                                 fw_inst_const_size);
1143         }
1144
1145         if (fw_bss_data_size)
1146                 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
1147                        fw_bss_data, fw_bss_data_size);
1148
1149         /* Copy firmware bios info into FB memory. */
1150         memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
1151                adev->bios_size);
1152
1153         /* Reset regions that need to be reset. */
1154         memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
1155         fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
1156
1157         memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
1158                fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
1159
1160         memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
1161                fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
1162
1163         /* Initialize hardware. */
1164         memset(&hw_params, 0, sizeof(hw_params));
1165         hw_params.fb_base = adev->gmc.fb_start;
1166         hw_params.fb_offset = adev->vm_manager.vram_base_offset;
1167
1168         /* backdoor load firmware and trigger dmub running */
1169         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1170                 hw_params.load_inst_const = true;
1171
1172         if (dmcu)
1173                 hw_params.psp_version = dmcu->psp_version;
1174
1175         for (i = 0; i < fb_info->num_fb; ++i)
1176                 hw_params.fb[i] = &fb_info->fb[i];
1177
1178         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1179         case IP_VERSION(3, 1, 3):
1180         case IP_VERSION(3, 1, 4):
1181         case IP_VERSION(3, 5, 0):
1182                 hw_params.dpia_supported = true;
1183                 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
1184                 break;
1185         default:
1186                 break;
1187         }
1188
1189         status = dmub_srv_hw_init(dmub_srv, &hw_params);
1190         if (status != DMUB_STATUS_OK) {
1191                 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
1192                 return -EINVAL;
1193         }
1194
1195         /* Wait for firmware load to finish. */
1196         status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1197         if (status != DMUB_STATUS_OK)
1198                 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1199
1200         /* Init DMCU and ABM if available. */
1201         if (dmcu && abm) {
1202                 dmcu->funcs->dmcu_init(dmcu);
1203                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1204         }
1205
1206         if (!adev->dm.dc->ctx->dmub_srv)
1207                 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
1208         if (!adev->dm.dc->ctx->dmub_srv) {
1209                 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
1210                 return -ENOMEM;
1211         }
1212
1213         DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
1214                  adev->dm.dmcub_fw_version);
1215
1216         return 0;
1217 }
1218
1219 static void dm_dmub_hw_resume(struct amdgpu_device *adev)
1220 {
1221         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1222         enum dmub_status status;
1223         bool init;
1224
1225         if (!dmub_srv) {
1226                 /* DMUB isn't supported on the ASIC. */
1227                 return;
1228         }
1229
1230         status = dmub_srv_is_hw_init(dmub_srv, &init);
1231         if (status != DMUB_STATUS_OK)
1232                 DRM_WARN("DMUB hardware init check failed: %d\n", status);
1233
1234         if (status == DMUB_STATUS_OK && init) {
1235                 /* Wait for firmware load to finish. */
1236                 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1237                 if (status != DMUB_STATUS_OK)
1238                         DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1239         } else {
1240                 /* Perform the full hardware initialization. */
1241                 dm_dmub_hw_init(adev);
1242         }
1243 }
1244
1245 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
1246 {
1247         u64 pt_base;
1248         u32 logical_addr_low;
1249         u32 logical_addr_high;
1250         u32 agp_base, agp_bot, agp_top;
1251         PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
1252
1253         memset(pa_config, 0, sizeof(*pa_config));
1254
1255         agp_base = 0;
1256         agp_bot = adev->gmc.agp_start >> 24;
1257         agp_top = adev->gmc.agp_end >> 24;
1258
1259         /* AGP aperture is disabled */
1260         if (agp_bot > agp_top) {
1261                 logical_addr_low = adev->gmc.fb_start >> 18;
1262                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1263                         /*
1264                          * Raven2 has a HW issue that it is unable to use the vram which
1265                          * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1266                          * workaround that increase system aperture high address (add 1)
1267                          * to get rid of the VM fault and hardware hang.
1268                          */
1269                         logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1;
1270                 else
1271                         logical_addr_high = adev->gmc.fb_end >> 18;
1272         } else {
1273                 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
1274                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1275                         /*
1276                          * Raven2 has a HW issue that it is unable to use the vram which
1277                          * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1278                          * workaround that increase system aperture high address (add 1)
1279                          * to get rid of the VM fault and hardware hang.
1280                          */
1281                         logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1282                 else
1283                         logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
1284         }
1285
1286         pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
1287
1288         page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >>
1289                                                    AMDGPU_GPU_PAGE_SHIFT);
1290         page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >>
1291                                                   AMDGPU_GPU_PAGE_SHIFT);
1292         page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >>
1293                                                  AMDGPU_GPU_PAGE_SHIFT);
1294         page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >>
1295                                                 AMDGPU_GPU_PAGE_SHIFT);
1296         page_table_base.high_part = upper_32_bits(pt_base);
1297         page_table_base.low_part = lower_32_bits(pt_base);
1298
1299         pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1300         pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1301
1302         pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24;
1303         pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1304         pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1305
1306         pa_config->system_aperture.fb_base = adev->gmc.fb_start;
1307         pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset;
1308         pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1309
1310         pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1311         pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1312         pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1313
1314         pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support;
1315
1316 }
1317
1318 static void force_connector_state(
1319         struct amdgpu_dm_connector *aconnector,
1320         enum drm_connector_force force_state)
1321 {
1322         struct drm_connector *connector = &aconnector->base;
1323
1324         mutex_lock(&connector->dev->mode_config.mutex);
1325         aconnector->base.force = force_state;
1326         mutex_unlock(&connector->dev->mode_config.mutex);
1327
1328         mutex_lock(&aconnector->hpd_lock);
1329         drm_kms_helper_connector_hotplug_event(connector);
1330         mutex_unlock(&aconnector->hpd_lock);
1331 }
1332
1333 static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
1334 {
1335         struct hpd_rx_irq_offload_work *offload_work;
1336         struct amdgpu_dm_connector *aconnector;
1337         struct dc_link *dc_link;
1338         struct amdgpu_device *adev;
1339         enum dc_connection_type new_connection_type = dc_connection_none;
1340         unsigned long flags;
1341         union test_response test_response;
1342
1343         memset(&test_response, 0, sizeof(test_response));
1344
1345         offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);
1346         aconnector = offload_work->offload_wq->aconnector;
1347
1348         if (!aconnector) {
1349                 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work");
1350                 goto skip;
1351         }
1352
1353         adev = drm_to_adev(aconnector->base.dev);
1354         dc_link = aconnector->dc_link;
1355
1356         mutex_lock(&aconnector->hpd_lock);
1357         if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
1358                 DRM_ERROR("KMS: Failed to detect connector\n");
1359         mutex_unlock(&aconnector->hpd_lock);
1360
1361         if (new_connection_type == dc_connection_none)
1362                 goto skip;
1363
1364         if (amdgpu_in_reset(adev))
1365                 goto skip;
1366
1367         if (offload_work->data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
1368                 offload_work->data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
1369                 dm_handle_mst_sideband_msg_ready_event(&aconnector->mst_mgr, DOWN_OR_UP_MSG_RDY_EVENT);
1370                 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1371                 offload_work->offload_wq->is_handling_mst_msg_rdy_event = false;
1372                 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1373                 goto skip;
1374         }
1375
1376         mutex_lock(&adev->dm.dc_lock);
1377         if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
1378                 dc_link_dp_handle_automated_test(dc_link);
1379
1380                 if (aconnector->timing_changed) {
1381                         /* force connector disconnect and reconnect */
1382                         force_connector_state(aconnector, DRM_FORCE_OFF);
1383                         msleep(100);
1384                         force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED);
1385                 }
1386
1387                 test_response.bits.ACK = 1;
1388
1389                 core_link_write_dpcd(
1390                 dc_link,
1391                 DP_TEST_RESPONSE,
1392                 &test_response.raw,
1393                 sizeof(test_response));
1394         } else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
1395                         dc_link_check_link_loss_status(dc_link, &offload_work->data) &&
1396                         dc_link_dp_allow_hpd_rx_irq(dc_link)) {
1397                 /* offload_work->data is from handle_hpd_rx_irq->
1398                  * schedule_hpd_rx_offload_work.this is defer handle
1399                  * for hpd short pulse. upon here, link status may be
1400                  * changed, need get latest link status from dpcd
1401                  * registers. if link status is good, skip run link
1402                  * training again.
1403                  */
1404                 union hpd_irq_data irq_data;
1405
1406                 memset(&irq_data, 0, sizeof(irq_data));
1407
1408                 /* before dc_link_dp_handle_link_loss, allow new link lost handle
1409                  * request be added to work queue if link lost at end of dc_link_
1410                  * dp_handle_link_loss
1411                  */
1412                 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1413                 offload_work->offload_wq->is_handling_link_loss = false;
1414                 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1415
1416                 if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) &&
1417                         dc_link_check_link_loss_status(dc_link, &irq_data))
1418                         dc_link_dp_handle_link_loss(dc_link);
1419         }
1420         mutex_unlock(&adev->dm.dc_lock);
1421
1422 skip:
1423         kfree(offload_work);
1424
1425 }
1426
1427 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)
1428 {
1429         int max_caps = dc->caps.max_links;
1430         int i = 0;
1431         struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
1432
1433         hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL);
1434
1435         if (!hpd_rx_offload_wq)
1436                 return NULL;
1437
1438
1439         for (i = 0; i < max_caps; i++) {
1440                 hpd_rx_offload_wq[i].wq =
1441                                     create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");
1442
1443                 if (hpd_rx_offload_wq[i].wq == NULL) {
1444                         DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");
1445                         goto out_err;
1446                 }
1447
1448                 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
1449         }
1450
1451         return hpd_rx_offload_wq;
1452
1453 out_err:
1454         for (i = 0; i < max_caps; i++) {
1455                 if (hpd_rx_offload_wq[i].wq)
1456                         destroy_workqueue(hpd_rx_offload_wq[i].wq);
1457         }
1458         kfree(hpd_rx_offload_wq);
1459         return NULL;
1460 }
1461
1462 struct amdgpu_stutter_quirk {
1463         u16 chip_vendor;
1464         u16 chip_device;
1465         u16 subsys_vendor;
1466         u16 subsys_device;
1467         u8 revision;
1468 };
1469
1470 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {
1471         /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */
1472         { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1473         { 0, 0, 0, 0, 0 },
1474 };
1475
1476 static bool dm_should_disable_stutter(struct pci_dev *pdev)
1477 {
1478         const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;
1479
1480         while (p && p->chip_device != 0) {
1481                 if (pdev->vendor == p->chip_vendor &&
1482                     pdev->device == p->chip_device &&
1483                     pdev->subsystem_vendor == p->subsys_vendor &&
1484                     pdev->subsystem_device == p->subsys_device &&
1485                     pdev->revision == p->revision) {
1486                         return true;
1487                 }
1488                 ++p;
1489         }
1490         return false;
1491 }
1492
1493 static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
1494         {
1495                 .matches = {
1496                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1497                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
1498                 },
1499         },
1500         {
1501                 .matches = {
1502                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1503                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
1504                 },
1505         },
1506         {
1507                 .matches = {
1508                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1509                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
1510                 },
1511         },
1512         {
1513                 .matches = {
1514                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1515                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"),
1516                 },
1517         },
1518         {
1519                 .matches = {
1520                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1521                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"),
1522                 },
1523         },
1524         {
1525                 .matches = {
1526                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1527                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"),
1528                 },
1529         },
1530         {
1531                 .matches = {
1532                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1533                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"),
1534                 },
1535         },
1536         {
1537                 .matches = {
1538                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1539                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"),
1540                 },
1541         },
1542         {
1543                 .matches = {
1544                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1545                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"),
1546                 },
1547         },
1548         {}
1549         /* TODO: refactor this from a fixed table to a dynamic option */
1550 };
1551
1552 static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
1553 {
1554         const struct dmi_system_id *dmi_id;
1555
1556         dm->aux_hpd_discon_quirk = false;
1557
1558         dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
1559         if (dmi_id) {
1560                 dm->aux_hpd_discon_quirk = true;
1561                 DRM_INFO("aux_hpd_discon_quirk attached\n");
1562         }
1563 }
1564
1565 static int amdgpu_dm_init(struct amdgpu_device *adev)
1566 {
1567         struct dc_init_data init_data;
1568         struct dc_callback_init init_params;
1569         int r;
1570
1571         adev->dm.ddev = adev_to_drm(adev);
1572         adev->dm.adev = adev;
1573
1574         /* Zero all the fields */
1575         memset(&init_data, 0, sizeof(init_data));
1576         memset(&init_params, 0, sizeof(init_params));
1577
1578         mutex_init(&adev->dm.dpia_aux_lock);
1579         mutex_init(&adev->dm.dc_lock);
1580         mutex_init(&adev->dm.audio_lock);
1581
1582         if (amdgpu_dm_irq_init(adev)) {
1583                 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1584                 goto error;
1585         }
1586
1587         init_data.asic_id.chip_family = adev->family;
1588
1589         init_data.asic_id.pci_revision_id = adev->pdev->revision;
1590         init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1591         init_data.asic_id.chip_id = adev->pdev->device;
1592
1593         init_data.asic_id.vram_width = adev->gmc.vram_width;
1594         /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1595         init_data.asic_id.atombios_base_address =
1596                 adev->mode_info.atom_context->bios;
1597
1598         init_data.driver = adev;
1599
1600         adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1601
1602         if (!adev->dm.cgs_device) {
1603                 DRM_ERROR("amdgpu: failed to create cgs device.\n");
1604                 goto error;
1605         }
1606
1607         init_data.cgs_device = adev->dm.cgs_device;
1608
1609         init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1610
1611         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1612         case IP_VERSION(2, 1, 0):
1613                 switch (adev->dm.dmcub_fw_version) {
1614                 case 0: /* development */
1615                 case 0x1: /* linux-firmware.git hash 6d9f399 */
1616                 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
1617                         init_data.flags.disable_dmcu = false;
1618                         break;
1619                 default:
1620                         init_data.flags.disable_dmcu = true;
1621                 }
1622                 break;
1623         case IP_VERSION(2, 0, 3):
1624                 init_data.flags.disable_dmcu = true;
1625                 break;
1626         default:
1627                 break;
1628         }
1629
1630         /* APU support S/G display by default except:
1631          * ASICs before Carrizo,
1632          * RAVEN1 (Users reported stability issue)
1633          */
1634
1635         if (adev->asic_type < CHIP_CARRIZO) {
1636                 init_data.flags.gpu_vm_support = false;
1637         } else if (adev->asic_type == CHIP_RAVEN) {
1638                 if (adev->apu_flags & AMD_APU_IS_RAVEN)
1639                         init_data.flags.gpu_vm_support = false;
1640                 else
1641                         init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0);
1642         } else {
1643                 init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0) && (adev->flags & AMD_IS_APU);
1644         }
1645
1646         adev->mode_info.gpu_vm_support = init_data.flags.gpu_vm_support;
1647
1648         if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1649                 init_data.flags.fbc_support = true;
1650
1651         if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1652                 init_data.flags.multi_mon_pp_mclk_switch = true;
1653
1654         if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1655                 init_data.flags.disable_fractional_pwm = true;
1656
1657         if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
1658                 init_data.flags.edp_no_power_sequencing = true;
1659
1660         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
1661                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
1662         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
1663                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
1664
1665         init_data.flags.seamless_boot_edp_requested = false;
1666
1667         if (amdgpu_device_seamless_boot_supported(adev)) {
1668                 init_data.flags.seamless_boot_edp_requested = true;
1669                 init_data.flags.allow_seamless_boot_optimization = true;
1670                 DRM_INFO("Seamless boot condition check passed\n");
1671         }
1672
1673         init_data.flags.enable_mipi_converter_optimization = true;
1674
1675         init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
1676         init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
1677         init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0];
1678
1679         INIT_LIST_HEAD(&adev->dm.da_list);
1680
1681         retrieve_dmi_info(&adev->dm);
1682
1683         /* Display Core create. */
1684         adev->dm.dc = dc_create(&init_data);
1685
1686         if (adev->dm.dc) {
1687                 DRM_INFO("Display Core v%s initialized on %s\n", DC_VER,
1688                          dce_version_to_string(adev->dm.dc->ctx->dce_version));
1689         } else {
1690                 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
1691                 goto error;
1692         }
1693
1694         if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1695                 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1696                 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1697         }
1698
1699         if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1700                 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1701         if (dm_should_disable_stutter(adev->pdev))
1702                 adev->dm.dc->debug.disable_stutter = true;
1703
1704         if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1705                 adev->dm.dc->debug.disable_stutter = true;
1706
1707         if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)
1708                 adev->dm.dc->debug.disable_dsc = true;
1709
1710         if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1711                 adev->dm.dc->debug.disable_clock_gate = true;
1712
1713         if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
1714                 adev->dm.dc->debug.force_subvp_mclk_switch = true;
1715
1716         adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
1717
1718         /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */
1719         adev->dm.dc->debug.ignore_cable_id = true;
1720
1721         /* TODO: There is a new drm mst change where the freedom of
1722          * vc_next_start_slot update is revoked/moved into drm, instead of in
1723          * driver. This forces us to make sure to get vc_next_start_slot updated
1724          * in drm function each time without considering if mst_state is active
1725          * or not. Otherwise, next time hotplug will give wrong start_slot
1726          * number. We are implementing a temporary solution to even notify drm
1727          * mst deallocation when link is no longer of MST type when uncommitting
1728          * the stream so we will have more time to work on a proper solution.
1729          * Ideally when dm_helpers_dp_mst_stop_top_mgr message is triggered, we
1730          * should notify drm to do a complete "reset" of its states and stop
1731          * calling further drm mst functions when link is no longer of an MST
1732          * type. This could happen when we unplug an MST hubs/displays. When
1733          * uncommit stream comes later after unplug, we should just reset
1734          * hardware states only.
1735          */
1736         adev->dm.dc->debug.temp_mst_deallocation_sequence = true;
1737
1738         if (adev->dm.dc->caps.dp_hdmi21_pcon_support)
1739                 DRM_INFO("DP-HDMI FRL PCON supported\n");
1740
1741         r = dm_dmub_hw_init(adev);
1742         if (r) {
1743                 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1744                 goto error;
1745         }
1746
1747         dc_hardware_init(adev->dm.dc);
1748
1749         adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc);
1750         if (!adev->dm.hpd_rx_offload_wq) {
1751                 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n");
1752                 goto error;
1753         }
1754
1755         if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
1756                 struct dc_phy_addr_space_config pa_config;
1757
1758                 mmhub_read_system_context(adev, &pa_config);
1759
1760                 // Call the DC init_memory func
1761                 dc_setup_system_context(adev->dm.dc, &pa_config);
1762         }
1763
1764         adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1765         if (!adev->dm.freesync_module) {
1766                 DRM_ERROR(
1767                 "amdgpu: failed to initialize freesync_module.\n");
1768         } else
1769                 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
1770                                 adev->dm.freesync_module);
1771
1772         amdgpu_dm_init_color_mod();
1773
1774         if (adev->dm.dc->caps.max_links > 0) {
1775                 adev->dm.vblank_control_workqueue =
1776                         create_singlethread_workqueue("dm_vblank_control_workqueue");
1777                 if (!adev->dm.vblank_control_workqueue)
1778                         DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
1779         }
1780
1781         if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
1782                 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
1783
1784                 if (!adev->dm.hdcp_workqueue)
1785                         DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1786                 else
1787                         DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
1788
1789                 dc_init_callbacks(adev->dm.dc, &init_params);
1790         }
1791         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1792                 init_completion(&adev->dm.dmub_aux_transfer_done);
1793                 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);
1794                 if (!adev->dm.dmub_notify) {
1795                         DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
1796                         goto error;
1797                 }
1798
1799                 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");
1800                 if (!adev->dm.delayed_hpd_wq) {
1801                         DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n");
1802                         goto error;
1803                 }
1804
1805                 amdgpu_dm_outbox_init(adev);
1806                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
1807                         dmub_aux_setconfig_callback, false)) {
1808                         DRM_ERROR("amdgpu: fail to register dmub aux callback");
1809                         goto error;
1810                 }
1811                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) {
1812                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1813                         goto error;
1814                 }
1815                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) {
1816                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1817                         goto error;
1818                 }
1819         }
1820
1821         /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
1822          * It is expected that DMUB will resend any pending notifications at this point, for
1823          * example HPD from DPIA.
1824          */
1825         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1826                 dc_enable_dmub_outbox(adev->dm.dc);
1827
1828                 /* DPIA trace goes to dmesg logs only if outbox is enabled */
1829                 if (amdgpu_dc_debug_mask & DC_ENABLE_DPIA_TRACE)
1830                         dc_dmub_srv_enable_dpia_trace(adev->dm.dc);
1831         }
1832
1833         if (amdgpu_dm_initialize_drm_device(adev)) {
1834                 DRM_ERROR(
1835                 "amdgpu: failed to initialize sw for display support.\n");
1836                 goto error;
1837         }
1838
1839         /* create fake encoders for MST */
1840         dm_dp_create_fake_mst_encoders(adev);
1841
1842         /* TODO: Add_display_info? */
1843
1844         /* TODO use dynamic cursor width */
1845         adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1846         adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
1847
1848         if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
1849                 DRM_ERROR(
1850                 "amdgpu: failed to initialize sw for display support.\n");
1851                 goto error;
1852         }
1853
1854 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1855         adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev);
1856         if (!adev->dm.secure_display_ctxs)
1857                 DRM_ERROR("amdgpu: failed to initialize secure display contexts.\n");
1858 #endif
1859
1860         DRM_DEBUG_DRIVER("KMS initialized.\n");
1861
1862         return 0;
1863 error:
1864         amdgpu_dm_fini(adev);
1865
1866         return -EINVAL;
1867 }
1868
1869 static int amdgpu_dm_early_fini(void *handle)
1870 {
1871         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1872
1873         amdgpu_dm_audio_fini(adev);
1874
1875         return 0;
1876 }
1877
1878 static void amdgpu_dm_fini(struct amdgpu_device *adev)
1879 {
1880         int i;
1881
1882         if (adev->dm.vblank_control_workqueue) {
1883                 destroy_workqueue(adev->dm.vblank_control_workqueue);
1884                 adev->dm.vblank_control_workqueue = NULL;
1885         }
1886
1887         amdgpu_dm_destroy_drm_device(&adev->dm);
1888
1889 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1890         if (adev->dm.secure_display_ctxs) {
1891                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1892                         if (adev->dm.secure_display_ctxs[i].crtc) {
1893                                 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work);
1894                                 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work);
1895                         }
1896                 }
1897                 kfree(adev->dm.secure_display_ctxs);
1898                 adev->dm.secure_display_ctxs = NULL;
1899         }
1900 #endif
1901         if (adev->dm.hdcp_workqueue) {
1902                 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
1903                 adev->dm.hdcp_workqueue = NULL;
1904         }
1905
1906         if (adev->dm.dc)
1907                 dc_deinit_callbacks(adev->dm.dc);
1908
1909         if (adev->dm.dc)
1910                 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1911
1912         if (dc_enable_dmub_notifications(adev->dm.dc)) {
1913                 kfree(adev->dm.dmub_notify);
1914                 adev->dm.dmub_notify = NULL;
1915                 destroy_workqueue(adev->dm.delayed_hpd_wq);
1916                 adev->dm.delayed_hpd_wq = NULL;
1917         }
1918
1919         if (adev->dm.dmub_bo)
1920                 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1921                                       &adev->dm.dmub_bo_gpu_addr,
1922                                       &adev->dm.dmub_bo_cpu_addr);
1923
1924         if (adev->dm.hpd_rx_offload_wq) {
1925                 for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
1926                         if (adev->dm.hpd_rx_offload_wq[i].wq) {
1927                                 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
1928                                 adev->dm.hpd_rx_offload_wq[i].wq = NULL;
1929                         }
1930                 }
1931
1932                 kfree(adev->dm.hpd_rx_offload_wq);
1933                 adev->dm.hpd_rx_offload_wq = NULL;
1934         }
1935
1936         /* DC Destroy TODO: Replace destroy DAL */
1937         if (adev->dm.dc)
1938                 dc_destroy(&adev->dm.dc);
1939         /*
1940          * TODO: pageflip, vlank interrupt
1941          *
1942          * amdgpu_dm_irq_fini(adev);
1943          */
1944
1945         if (adev->dm.cgs_device) {
1946                 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1947                 adev->dm.cgs_device = NULL;
1948         }
1949         if (adev->dm.freesync_module) {
1950                 mod_freesync_destroy(adev->dm.freesync_module);
1951                 adev->dm.freesync_module = NULL;
1952         }
1953
1954         mutex_destroy(&adev->dm.audio_lock);
1955         mutex_destroy(&adev->dm.dc_lock);
1956         mutex_destroy(&adev->dm.dpia_aux_lock);
1957 }
1958
1959 static int load_dmcu_fw(struct amdgpu_device *adev)
1960 {
1961         const char *fw_name_dmcu = NULL;
1962         int r;
1963         const struct dmcu_firmware_header_v1_0 *hdr;
1964
1965         switch (adev->asic_type) {
1966 #if defined(CONFIG_DRM_AMD_DC_SI)
1967         case CHIP_TAHITI:
1968         case CHIP_PITCAIRN:
1969         case CHIP_VERDE:
1970         case CHIP_OLAND:
1971 #endif
1972         case CHIP_BONAIRE:
1973         case CHIP_HAWAII:
1974         case CHIP_KAVERI:
1975         case CHIP_KABINI:
1976         case CHIP_MULLINS:
1977         case CHIP_TONGA:
1978         case CHIP_FIJI:
1979         case CHIP_CARRIZO:
1980         case CHIP_STONEY:
1981         case CHIP_POLARIS11:
1982         case CHIP_POLARIS10:
1983         case CHIP_POLARIS12:
1984         case CHIP_VEGAM:
1985         case CHIP_VEGA10:
1986         case CHIP_VEGA12:
1987         case CHIP_VEGA20:
1988                 return 0;
1989         case CHIP_NAVI12:
1990                 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
1991                 break;
1992         case CHIP_RAVEN:
1993                 if (ASICREV_IS_PICASSO(adev->external_rev_id))
1994                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1995                 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
1996                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1997                 else
1998                         return 0;
1999                 break;
2000         default:
2001                 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2002                 case IP_VERSION(2, 0, 2):
2003                 case IP_VERSION(2, 0, 3):
2004                 case IP_VERSION(2, 0, 0):
2005                 case IP_VERSION(2, 1, 0):
2006                 case IP_VERSION(3, 0, 0):
2007                 case IP_VERSION(3, 0, 2):
2008                 case IP_VERSION(3, 0, 3):
2009                 case IP_VERSION(3, 0, 1):
2010                 case IP_VERSION(3, 1, 2):
2011                 case IP_VERSION(3, 1, 3):
2012                 case IP_VERSION(3, 1, 4):
2013                 case IP_VERSION(3, 1, 5):
2014                 case IP_VERSION(3, 1, 6):
2015                 case IP_VERSION(3, 2, 0):
2016                 case IP_VERSION(3, 2, 1):
2017                 case IP_VERSION(3, 5, 0):
2018                         return 0;
2019                 default:
2020                         break;
2021                 }
2022                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2023                 return -EINVAL;
2024         }
2025
2026         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2027                 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
2028                 return 0;
2029         }
2030
2031         r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu);
2032         if (r == -ENODEV) {
2033                 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
2034                 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
2035                 adev->dm.fw_dmcu = NULL;
2036                 return 0;
2037         }
2038         if (r) {
2039                 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
2040                         fw_name_dmcu);
2041                 amdgpu_ucode_release(&adev->dm.fw_dmcu);
2042                 return r;
2043         }
2044
2045         hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
2046         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
2047         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
2048         adev->firmware.fw_size +=
2049                 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2050
2051         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
2052         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
2053         adev->firmware.fw_size +=
2054                 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2055
2056         adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
2057
2058         DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
2059
2060         return 0;
2061 }
2062
2063 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
2064 {
2065         struct amdgpu_device *adev = ctx;
2066
2067         return dm_read_reg(adev->dm.dc->ctx, address);
2068 }
2069
2070 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
2071                                      uint32_t value)
2072 {
2073         struct amdgpu_device *adev = ctx;
2074
2075         return dm_write_reg(adev->dm.dc->ctx, address, value);
2076 }
2077
2078 static int dm_dmub_sw_init(struct amdgpu_device *adev)
2079 {
2080         struct dmub_srv_create_params create_params;
2081         struct dmub_srv_region_params region_params;
2082         struct dmub_srv_region_info region_info;
2083         struct dmub_srv_fb_params fb_params;
2084         struct dmub_srv_fb_info *fb_info;
2085         struct dmub_srv *dmub_srv;
2086         const struct dmcub_firmware_header_v1_0 *hdr;
2087         enum dmub_asic dmub_asic;
2088         enum dmub_status status;
2089         int r;
2090
2091         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2092         case IP_VERSION(2, 1, 0):
2093                 dmub_asic = DMUB_ASIC_DCN21;
2094                 break;
2095         case IP_VERSION(3, 0, 0):
2096                 dmub_asic = DMUB_ASIC_DCN30;
2097                 break;
2098         case IP_VERSION(3, 0, 1):
2099                 dmub_asic = DMUB_ASIC_DCN301;
2100                 break;
2101         case IP_VERSION(3, 0, 2):
2102                 dmub_asic = DMUB_ASIC_DCN302;
2103                 break;
2104         case IP_VERSION(3, 0, 3):
2105                 dmub_asic = DMUB_ASIC_DCN303;
2106                 break;
2107         case IP_VERSION(3, 1, 2):
2108         case IP_VERSION(3, 1, 3):
2109                 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
2110                 break;
2111         case IP_VERSION(3, 1, 4):
2112                 dmub_asic = DMUB_ASIC_DCN314;
2113                 break;
2114         case IP_VERSION(3, 1, 5):
2115                 dmub_asic = DMUB_ASIC_DCN315;
2116                 break;
2117         case IP_VERSION(3, 1, 6):
2118                 dmub_asic = DMUB_ASIC_DCN316;
2119                 break;
2120         case IP_VERSION(3, 2, 0):
2121                 dmub_asic = DMUB_ASIC_DCN32;
2122                 break;
2123         case IP_VERSION(3, 2, 1):
2124                 dmub_asic = DMUB_ASIC_DCN321;
2125                 break;
2126         case IP_VERSION(3, 5, 0):
2127                 dmub_asic = DMUB_ASIC_DCN35;
2128                 break;
2129         default:
2130                 /* ASIC doesn't support DMUB. */
2131                 return 0;
2132         }
2133
2134         hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
2135         adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
2136
2137         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2138                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
2139                         AMDGPU_UCODE_ID_DMCUB;
2140                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
2141                         adev->dm.dmub_fw;
2142                 adev->firmware.fw_size +=
2143                         ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
2144
2145                 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
2146                          adev->dm.dmcub_fw_version);
2147         }
2148
2149
2150         adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
2151         dmub_srv = adev->dm.dmub_srv;
2152
2153         if (!dmub_srv) {
2154                 DRM_ERROR("Failed to allocate DMUB service!\n");
2155                 return -ENOMEM;
2156         }
2157
2158         memset(&create_params, 0, sizeof(create_params));
2159         create_params.user_ctx = adev;
2160         create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
2161         create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
2162         create_params.asic = dmub_asic;
2163
2164         /* Create the DMUB service. */
2165         status = dmub_srv_create(dmub_srv, &create_params);
2166         if (status != DMUB_STATUS_OK) {
2167                 DRM_ERROR("Error creating DMUB service: %d\n", status);
2168                 return -EINVAL;
2169         }
2170
2171         /* Calculate the size of all the regions for the DMUB service. */
2172         memset(&region_params, 0, sizeof(region_params));
2173
2174         region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
2175                                         PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
2176         region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
2177         region_params.vbios_size = adev->bios_size;
2178         region_params.fw_bss_data = region_params.bss_data_size ?
2179                 adev->dm.dmub_fw->data +
2180                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2181                 le32_to_cpu(hdr->inst_const_bytes) : NULL;
2182         region_params.fw_inst_const =
2183                 adev->dm.dmub_fw->data +
2184                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2185                 PSP_HEADER_BYTES;
2186
2187         status = dmub_srv_calc_region_info(dmub_srv, &region_params,
2188                                            &region_info);
2189
2190         if (status != DMUB_STATUS_OK) {
2191                 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
2192                 return -EINVAL;
2193         }
2194
2195         /*
2196          * Allocate a framebuffer based on the total size of all the regions.
2197          * TODO: Move this into GART.
2198          */
2199         r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
2200                                     AMDGPU_GEM_DOMAIN_VRAM |
2201                                     AMDGPU_GEM_DOMAIN_GTT,
2202                                     &adev->dm.dmub_bo,
2203                                     &adev->dm.dmub_bo_gpu_addr,
2204                                     &adev->dm.dmub_bo_cpu_addr);
2205         if (r)
2206                 return r;
2207
2208         /* Rebase the regions on the framebuffer address. */
2209         memset(&fb_params, 0, sizeof(fb_params));
2210         fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
2211         fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
2212         fb_params.region_info = &region_info;
2213
2214         adev->dm.dmub_fb_info =
2215                 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
2216         fb_info = adev->dm.dmub_fb_info;
2217
2218         if (!fb_info) {
2219                 DRM_ERROR(
2220                         "Failed to allocate framebuffer info for DMUB service!\n");
2221                 return -ENOMEM;
2222         }
2223
2224         status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info);
2225         if (status != DMUB_STATUS_OK) {
2226                 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
2227                 return -EINVAL;
2228         }
2229
2230         return 0;
2231 }
2232
2233 static int dm_sw_init(void *handle)
2234 {
2235         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2236         int r;
2237
2238         r = dm_dmub_sw_init(adev);
2239         if (r)
2240                 return r;
2241
2242         return load_dmcu_fw(adev);
2243 }
2244
2245 static int dm_sw_fini(void *handle)
2246 {
2247         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2248
2249         kfree(adev->dm.dmub_fb_info);
2250         adev->dm.dmub_fb_info = NULL;
2251
2252         if (adev->dm.dmub_srv) {
2253                 dmub_srv_destroy(adev->dm.dmub_srv);
2254                 adev->dm.dmub_srv = NULL;
2255         }
2256
2257         amdgpu_ucode_release(&adev->dm.dmub_fw);
2258         amdgpu_ucode_release(&adev->dm.fw_dmcu);
2259
2260         return 0;
2261 }
2262
2263 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
2264 {
2265         struct amdgpu_dm_connector *aconnector;
2266         struct drm_connector *connector;
2267         struct drm_connector_list_iter iter;
2268         int ret = 0;
2269
2270         drm_connector_list_iter_begin(dev, &iter);
2271         drm_for_each_connector_iter(connector, &iter) {
2272                 aconnector = to_amdgpu_dm_connector(connector);
2273                 if (aconnector->dc_link->type == dc_connection_mst_branch &&
2274                     aconnector->mst_mgr.aux) {
2275                         DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
2276                                          aconnector,
2277                                          aconnector->base.base.id);
2278
2279                         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
2280                         if (ret < 0) {
2281                                 DRM_ERROR("DM_MST: Failed to start MST\n");
2282                                 aconnector->dc_link->type =
2283                                         dc_connection_single;
2284                                 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2285                                                                      aconnector->dc_link);
2286                                 break;
2287                         }
2288                 }
2289         }
2290         drm_connector_list_iter_end(&iter);
2291
2292         return ret;
2293 }
2294
2295 static int dm_late_init(void *handle)
2296 {
2297         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2298
2299         struct dmcu_iram_parameters params;
2300         unsigned int linear_lut[16];
2301         int i;
2302         struct dmcu *dmcu = NULL;
2303
2304         dmcu = adev->dm.dc->res_pool->dmcu;
2305
2306         for (i = 0; i < 16; i++)
2307                 linear_lut[i] = 0xFFFF * i / 15;
2308
2309         params.set = 0;
2310         params.backlight_ramping_override = false;
2311         params.backlight_ramping_start = 0xCCCC;
2312         params.backlight_ramping_reduction = 0xCCCCCCCC;
2313         params.backlight_lut_array_size = 16;
2314         params.backlight_lut_array = linear_lut;
2315
2316         /* Min backlight level after ABM reduction,  Don't allow below 1%
2317          * 0xFFFF x 0.01 = 0x28F
2318          */
2319         params.min_abm_backlight = 0x28F;
2320         /* In the case where abm is implemented on dmcub,
2321          * dmcu object will be null.
2322          * ABM 2.4 and up are implemented on dmcub.
2323          */
2324         if (dmcu) {
2325                 if (!dmcu_load_iram(dmcu, params))
2326                         return -EINVAL;
2327         } else if (adev->dm.dc->ctx->dmub_srv) {
2328                 struct dc_link *edp_links[MAX_NUM_EDP];
2329                 int edp_num;
2330
2331                 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num);
2332                 for (i = 0; i < edp_num; i++) {
2333                         if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
2334                                 return -EINVAL;
2335                 }
2336         }
2337
2338         return detect_mst_link_for_all_connectors(adev_to_drm(adev));
2339 }
2340
2341 static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr)
2342 {
2343         int ret;
2344         u8 guid[16];
2345         u64 tmp64;
2346
2347         mutex_lock(&mgr->lock);
2348         if (!mgr->mst_primary)
2349                 goto out_fail;
2350
2351         if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) {
2352                 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n");
2353                 goto out_fail;
2354         }
2355
2356         ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
2357                                  DP_MST_EN |
2358                                  DP_UP_REQ_EN |
2359                                  DP_UPSTREAM_IS_SRC);
2360         if (ret < 0) {
2361                 drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n");
2362                 goto out_fail;
2363         }
2364
2365         /* Some hubs forget their guids after they resume */
2366         ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, guid, 16);
2367         if (ret != 16) {
2368                 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n");
2369                 goto out_fail;
2370         }
2371
2372         if (memchr_inv(guid, 0, 16) == NULL) {
2373                 tmp64 = get_jiffies_64();
2374                 memcpy(&guid[0], &tmp64, sizeof(u64));
2375                 memcpy(&guid[8], &tmp64, sizeof(u64));
2376
2377                 ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, guid, 16);
2378
2379                 if (ret != 16) {
2380                         drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked during suspend?\n");
2381                         goto out_fail;
2382                 }
2383         }
2384
2385         memcpy(mgr->mst_primary->guid, guid, 16);
2386
2387 out_fail:
2388         mutex_unlock(&mgr->lock);
2389 }
2390
2391 static void s3_handle_mst(struct drm_device *dev, bool suspend)
2392 {
2393         struct amdgpu_dm_connector *aconnector;
2394         struct drm_connector *connector;
2395         struct drm_connector_list_iter iter;
2396         struct drm_dp_mst_topology_mgr *mgr;
2397
2398         drm_connector_list_iter_begin(dev, &iter);
2399         drm_for_each_connector_iter(connector, &iter) {
2400                 aconnector = to_amdgpu_dm_connector(connector);
2401                 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2402                     aconnector->mst_root)
2403                         continue;
2404
2405                 mgr = &aconnector->mst_mgr;
2406
2407                 if (suspend) {
2408                         drm_dp_mst_topology_mgr_suspend(mgr);
2409                 } else {
2410                         /* if extended timeout is supported in hardware,
2411                          * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
2412                          * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
2413                          */
2414                         try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
2415                         if (!dp_is_lttpr_present(aconnector->dc_link))
2416                                 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
2417
2418                         /* TODO: move resume_mst_branch_status() into drm mst resume again
2419                          * once topology probing work is pulled out from mst resume into mst
2420                          * resume 2nd step. mst resume 2nd step should be called after old
2421                          * state getting restored (i.e. drm_atomic_helper_resume()).
2422                          */
2423                         resume_mst_branch_status(mgr);
2424                 }
2425         }
2426         drm_connector_list_iter_end(&iter);
2427 }
2428
2429 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
2430 {
2431         int ret = 0;
2432
2433         /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
2434          * on window driver dc implementation.
2435          * For Navi1x, clock settings of dcn watermarks are fixed. the settings
2436          * should be passed to smu during boot up and resume from s3.
2437          * boot up: dc calculate dcn watermark clock settings within dc_create,
2438          * dcn20_resource_construct
2439          * then call pplib functions below to pass the settings to smu:
2440          * smu_set_watermarks_for_clock_ranges
2441          * smu_set_watermarks_table
2442          * navi10_set_watermarks_table
2443          * smu_write_watermarks_table
2444          *
2445          * For Renoir, clock settings of dcn watermark are also fixed values.
2446          * dc has implemented different flow for window driver:
2447          * dc_hardware_init / dc_set_power_state
2448          * dcn10_init_hw
2449          * notify_wm_ranges
2450          * set_wm_ranges
2451          * -- Linux
2452          * smu_set_watermarks_for_clock_ranges
2453          * renoir_set_watermarks_table
2454          * smu_write_watermarks_table
2455          *
2456          * For Linux,
2457          * dc_hardware_init -> amdgpu_dm_init
2458          * dc_set_power_state --> dm_resume
2459          *
2460          * therefore, this function apply to navi10/12/14 but not Renoir
2461          * *
2462          */
2463         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2464         case IP_VERSION(2, 0, 2):
2465         case IP_VERSION(2, 0, 0):
2466                 break;
2467         default:
2468                 return 0;
2469         }
2470
2471         ret = amdgpu_dpm_write_watermarks_table(adev);
2472         if (ret) {
2473                 DRM_ERROR("Failed to update WMTABLE!\n");
2474                 return ret;
2475         }
2476
2477         return 0;
2478 }
2479
2480 /**
2481  * dm_hw_init() - Initialize DC device
2482  * @handle: The base driver device containing the amdgpu_dm device.
2483  *
2484  * Initialize the &struct amdgpu_display_manager device. This involves calling
2485  * the initializers of each DM component, then populating the struct with them.
2486  *
2487  * Although the function implies hardware initialization, both hardware and
2488  * software are initialized here. Splitting them out to their relevant init
2489  * hooks is a future TODO item.
2490  *
2491  * Some notable things that are initialized here:
2492  *
2493  * - Display Core, both software and hardware
2494  * - DC modules that we need (freesync and color management)
2495  * - DRM software states
2496  * - Interrupt sources and handlers
2497  * - Vblank support
2498  * - Debug FS entries, if enabled
2499  */
2500 static int dm_hw_init(void *handle)
2501 {
2502         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2503         /* Create DAL display manager */
2504         amdgpu_dm_init(adev);
2505         amdgpu_dm_hpd_init(adev);
2506
2507         return 0;
2508 }
2509
2510 /**
2511  * dm_hw_fini() - Teardown DC device
2512  * @handle: The base driver device containing the amdgpu_dm device.
2513  *
2514  * Teardown components within &struct amdgpu_display_manager that require
2515  * cleanup. This involves cleaning up the DRM device, DC, and any modules that
2516  * were loaded. Also flush IRQ workqueues and disable them.
2517  */
2518 static int dm_hw_fini(void *handle)
2519 {
2520         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2521
2522         amdgpu_dm_hpd_fini(adev);
2523
2524         amdgpu_dm_irq_fini(adev);
2525         amdgpu_dm_fini(adev);
2526         return 0;
2527 }
2528
2529
2530 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
2531                                  struct dc_state *state, bool enable)
2532 {
2533         enum dc_irq_source irq_source;
2534         struct amdgpu_crtc *acrtc;
2535         int rc = -EBUSY;
2536         int i = 0;
2537
2538         for (i = 0; i < state->stream_count; i++) {
2539                 acrtc = get_crtc_by_otg_inst(
2540                                 adev, state->stream_status[i].primary_otg_inst);
2541
2542                 if (acrtc && state->stream_status[i].plane_count != 0) {
2543                         irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
2544                         rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2545                         if (rc)
2546                                 DRM_WARN("Failed to %s pflip interrupts\n",
2547                                          enable ? "enable" : "disable");
2548
2549                         if (enable) {
2550                                 if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc->base.state)))
2551                                         rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, true);
2552                         } else
2553                                 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, false);
2554
2555                         if (rc)
2556                                 DRM_WARN("Failed to %sable vupdate interrupt\n", enable ? "en" : "dis");
2557
2558                         irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
2559                         /* During gpu-reset we disable and then enable vblank irq, so
2560                          * don't use amdgpu_irq_get/put() to avoid refcount change.
2561                          */
2562                         if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))
2563                                 DRM_WARN("Failed to %sable vblank interrupt\n", enable ? "en" : "dis");
2564                 }
2565         }
2566
2567 }
2568
2569 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
2570 {
2571         struct dc_state *context = NULL;
2572         enum dc_status res = DC_ERROR_UNEXPECTED;
2573         int i;
2574         struct dc_stream_state *del_streams[MAX_PIPES];
2575         int del_streams_count = 0;
2576
2577         memset(del_streams, 0, sizeof(del_streams));
2578
2579         context = dc_create_state(dc);
2580         if (context == NULL)
2581                 goto context_alloc_fail;
2582
2583         dc_resource_state_copy_construct_current(dc, context);
2584
2585         /* First remove from context all streams */
2586         for (i = 0; i < context->stream_count; i++) {
2587                 struct dc_stream_state *stream = context->streams[i];
2588
2589                 del_streams[del_streams_count++] = stream;
2590         }
2591
2592         /* Remove all planes for removed streams and then remove the streams */
2593         for (i = 0; i < del_streams_count; i++) {
2594                 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
2595                         res = DC_FAIL_DETACH_SURFACES;
2596                         goto fail;
2597                 }
2598
2599                 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
2600                 if (res != DC_OK)
2601                         goto fail;
2602         }
2603
2604         res = dc_commit_streams(dc, context->streams, context->stream_count);
2605
2606 fail:
2607         dc_release_state(context);
2608
2609 context_alloc_fail:
2610         return res;
2611 }
2612
2613 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
2614 {
2615         int i;
2616
2617         if (dm->hpd_rx_offload_wq) {
2618                 for (i = 0; i < dm->dc->caps.max_links; i++)
2619                         flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
2620         }
2621 }
2622
2623 static int dm_suspend(void *handle)
2624 {
2625         struct amdgpu_device *adev = handle;
2626         struct amdgpu_display_manager *dm = &adev->dm;
2627         int ret = 0;
2628
2629         if (amdgpu_in_reset(adev)) {
2630                 mutex_lock(&dm->dc_lock);
2631
2632                 dc_allow_idle_optimizations(adev->dm.dc, false);
2633
2634                 dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
2635
2636                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
2637
2638                 amdgpu_dm_commit_zero_streams(dm->dc);
2639
2640                 amdgpu_dm_irq_suspend(adev);
2641
2642                 hpd_rx_irq_work_suspend(dm);
2643
2644                 return ret;
2645         }
2646
2647         WARN_ON(adev->dm.cached_state);
2648         adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
2649         if (IS_ERR(adev->dm.cached_state))
2650                 return PTR_ERR(adev->dm.cached_state);
2651
2652         s3_handle_mst(adev_to_drm(adev), true);
2653
2654         amdgpu_dm_irq_suspend(adev);
2655
2656         hpd_rx_irq_work_suspend(dm);
2657
2658         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
2659
2660         return 0;
2661 }
2662
2663 struct amdgpu_dm_connector *
2664 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
2665                                              struct drm_crtc *crtc)
2666 {
2667         u32 i;
2668         struct drm_connector_state *new_con_state;
2669         struct drm_connector *connector;
2670         struct drm_crtc *crtc_from_state;
2671
2672         for_each_new_connector_in_state(state, connector, new_con_state, i) {
2673                 crtc_from_state = new_con_state->crtc;
2674
2675                 if (crtc_from_state == crtc)
2676                         return to_amdgpu_dm_connector(connector);
2677         }
2678
2679         return NULL;
2680 }
2681
2682 static void emulated_link_detect(struct dc_link *link)
2683 {
2684         struct dc_sink_init_data sink_init_data = { 0 };
2685         struct display_sink_capability sink_caps = { 0 };
2686         enum dc_edid_status edid_status;
2687         struct dc_context *dc_ctx = link->ctx;
2688         struct drm_device *dev = adev_to_drm(dc_ctx->driver_context);
2689         struct dc_sink *sink = NULL;
2690         struct dc_sink *prev_sink = NULL;
2691
2692         link->type = dc_connection_none;
2693         prev_sink = link->local_sink;
2694
2695         if (prev_sink)
2696                 dc_sink_release(prev_sink);
2697
2698         switch (link->connector_signal) {
2699         case SIGNAL_TYPE_HDMI_TYPE_A: {
2700                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2701                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
2702                 break;
2703         }
2704
2705         case SIGNAL_TYPE_DVI_SINGLE_LINK: {
2706                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2707                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
2708                 break;
2709         }
2710
2711         case SIGNAL_TYPE_DVI_DUAL_LINK: {
2712                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2713                 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
2714                 break;
2715         }
2716
2717         case SIGNAL_TYPE_LVDS: {
2718                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2719                 sink_caps.signal = SIGNAL_TYPE_LVDS;
2720                 break;
2721         }
2722
2723         case SIGNAL_TYPE_EDP: {
2724                 sink_caps.transaction_type =
2725                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2726                 sink_caps.signal = SIGNAL_TYPE_EDP;
2727                 break;
2728         }
2729
2730         case SIGNAL_TYPE_DISPLAY_PORT: {
2731                 sink_caps.transaction_type =
2732                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2733                 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
2734                 break;
2735         }
2736
2737         default:
2738                 drm_err(dev, "Invalid connector type! signal:%d\n",
2739                         link->connector_signal);
2740                 return;
2741         }
2742
2743         sink_init_data.link = link;
2744         sink_init_data.sink_signal = sink_caps.signal;
2745
2746         sink = dc_sink_create(&sink_init_data);
2747         if (!sink) {
2748                 drm_err(dev, "Failed to create sink!\n");
2749                 return;
2750         }
2751
2752         /* dc_sink_create returns a new reference */
2753         link->local_sink = sink;
2754
2755         edid_status = dm_helpers_read_local_edid(
2756                         link->ctx,
2757                         link,
2758                         sink);
2759
2760         if (edid_status != EDID_OK)
2761                 drm_err(dev, "Failed to read EDID\n");
2762
2763 }
2764
2765 static void dm_gpureset_commit_state(struct dc_state *dc_state,
2766                                      struct amdgpu_display_manager *dm)
2767 {
2768         struct {
2769                 struct dc_surface_update surface_updates[MAX_SURFACES];
2770                 struct dc_plane_info plane_infos[MAX_SURFACES];
2771                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
2772                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
2773                 struct dc_stream_update stream_update;
2774         } *bundle;
2775         int k, m;
2776
2777         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
2778
2779         if (!bundle) {
2780                 drm_err(dm->ddev, "Failed to allocate update bundle\n");
2781                 goto cleanup;
2782         }
2783
2784         for (k = 0; k < dc_state->stream_count; k++) {
2785                 bundle->stream_update.stream = dc_state->streams[k];
2786
2787                 for (m = 0; m < dc_state->stream_status->plane_count; m++) {
2788                         bundle->surface_updates[m].surface =
2789                                 dc_state->stream_status->plane_states[m];
2790                         bundle->surface_updates[m].surface->force_full_update =
2791                                 true;
2792                 }
2793
2794                 update_planes_and_stream_adapter(dm->dc,
2795                                          UPDATE_TYPE_FULL,
2796                                          dc_state->stream_status->plane_count,
2797                                          dc_state->streams[k],
2798                                          &bundle->stream_update,
2799                                          bundle->surface_updates);
2800         }
2801
2802 cleanup:
2803         kfree(bundle);
2804 }
2805
2806 static int dm_resume(void *handle)
2807 {
2808         struct amdgpu_device *adev = handle;
2809         struct drm_device *ddev = adev_to_drm(adev);
2810         struct amdgpu_display_manager *dm = &adev->dm;
2811         struct amdgpu_dm_connector *aconnector;
2812         struct drm_connector *connector;
2813         struct drm_connector_list_iter iter;
2814         struct drm_crtc *crtc;
2815         struct drm_crtc_state *new_crtc_state;
2816         struct dm_crtc_state *dm_new_crtc_state;
2817         struct drm_plane *plane;
2818         struct drm_plane_state *new_plane_state;
2819         struct dm_plane_state *dm_new_plane_state;
2820         struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
2821         enum dc_connection_type new_connection_type = dc_connection_none;
2822         struct dc_state *dc_state;
2823         int i, r, j, ret;
2824         bool need_hotplug = false;
2825
2826         if (dm->dc->caps.ips_support) {
2827                 dc_dmub_srv_exit_low_power_state(dm->dc);
2828         }
2829
2830         if (amdgpu_in_reset(adev)) {
2831                 dc_state = dm->cached_dc_state;
2832
2833                 /*
2834                  * The dc->current_state is backed up into dm->cached_dc_state
2835                  * before we commit 0 streams.
2836                  *
2837                  * DC will clear link encoder assignments on the real state
2838                  * but the changes won't propagate over to the copy we made
2839                  * before the 0 streams commit.
2840                  *
2841                  * DC expects that link encoder assignments are *not* valid
2842                  * when committing a state, so as a workaround we can copy
2843                  * off of the current state.
2844                  *
2845                  * We lose the previous assignments, but we had already
2846                  * commit 0 streams anyway.
2847                  */
2848                 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
2849
2850                 r = dm_dmub_hw_init(adev);
2851                 if (r)
2852                         DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2853
2854                 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2855
2856                 dc_resume(dm->dc);
2857
2858                 amdgpu_dm_irq_resume_early(adev);
2859
2860                 for (i = 0; i < dc_state->stream_count; i++) {
2861                         dc_state->streams[i]->mode_changed = true;
2862                         for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
2863                                 dc_state->stream_status[i].plane_states[j]->update_flags.raw
2864                                         = 0xffffffff;
2865                         }
2866                 }
2867
2868                 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2869                         amdgpu_dm_outbox_init(adev);
2870                         dc_enable_dmub_outbox(adev->dm.dc);
2871                 }
2872
2873                 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
2874
2875                 dm_gpureset_commit_state(dm->cached_dc_state, dm);
2876
2877                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2878
2879                 dc_release_state(dm->cached_dc_state);
2880                 dm->cached_dc_state = NULL;
2881
2882                 amdgpu_dm_irq_resume_late(adev);
2883
2884                 mutex_unlock(&dm->dc_lock);
2885
2886                 return 0;
2887         }
2888         /* Recreate dc_state - DC invalidates it when setting power state to S3. */
2889         dc_release_state(dm_state->context);
2890         dm_state->context = dc_create_state(dm->dc);
2891         /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2892         dc_resource_state_construct(dm->dc, dm_state->context);
2893
2894         /* Before powering on DC we need to re-initialize DMUB. */
2895         dm_dmub_hw_resume(adev);
2896
2897         /* Re-enable outbox interrupts for DPIA. */
2898         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2899                 amdgpu_dm_outbox_init(adev);
2900                 dc_enable_dmub_outbox(adev->dm.dc);
2901         }
2902
2903         /* power on hardware */
2904         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2905
2906         /* program HPD filter */
2907         dc_resume(dm->dc);
2908
2909         /*
2910          * early enable HPD Rx IRQ, should be done before set mode as short
2911          * pulse interrupts are used for MST
2912          */
2913         amdgpu_dm_irq_resume_early(adev);
2914
2915         /* On resume we need to rewrite the MSTM control bits to enable MST*/
2916         s3_handle_mst(ddev, false);
2917
2918         /* Do detection*/
2919         drm_connector_list_iter_begin(ddev, &iter);
2920         drm_for_each_connector_iter(connector, &iter) {
2921                 aconnector = to_amdgpu_dm_connector(connector);
2922
2923                 if (!aconnector->dc_link)
2924                         continue;
2925
2926                 /*
2927                  * this is the case when traversing through already created end sink
2928                  * MST connectors, should be skipped
2929                  */
2930                 if (aconnector && aconnector->mst_root)
2931                         continue;
2932
2933                 mutex_lock(&aconnector->hpd_lock);
2934                 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
2935                         DRM_ERROR("KMS: Failed to detect connector\n");
2936
2937                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2938                         emulated_link_detect(aconnector->dc_link);
2939                 } else {
2940                         mutex_lock(&dm->dc_lock);
2941                         dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
2942                         mutex_unlock(&dm->dc_lock);
2943                 }
2944
2945                 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2946                         aconnector->fake_enable = false;
2947
2948                 if (aconnector->dc_sink)
2949                         dc_sink_release(aconnector->dc_sink);
2950                 aconnector->dc_sink = NULL;
2951                 amdgpu_dm_update_connector_after_detect(aconnector);
2952                 mutex_unlock(&aconnector->hpd_lock);
2953         }
2954         drm_connector_list_iter_end(&iter);
2955
2956         /* Force mode set in atomic commit */
2957         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
2958                 new_crtc_state->active_changed = true;
2959
2960         /*
2961          * atomic_check is expected to create the dc states. We need to release
2962          * them here, since they were duplicated as part of the suspend
2963          * procedure.
2964          */
2965         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
2966                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2967                 if (dm_new_crtc_state->stream) {
2968                         WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
2969                         dc_stream_release(dm_new_crtc_state->stream);
2970                         dm_new_crtc_state->stream = NULL;
2971                 }
2972         }
2973
2974         for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
2975                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
2976                 if (dm_new_plane_state->dc_state) {
2977                         WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
2978                         dc_plane_state_release(dm_new_plane_state->dc_state);
2979                         dm_new_plane_state->dc_state = NULL;
2980                 }
2981         }
2982
2983         drm_atomic_helper_resume(ddev, dm->cached_state);
2984
2985         dm->cached_state = NULL;
2986
2987         /* Do mst topology probing after resuming cached state*/
2988         drm_connector_list_iter_begin(ddev, &iter);
2989         drm_for_each_connector_iter(connector, &iter) {
2990                 aconnector = to_amdgpu_dm_connector(connector);
2991                 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2992                     aconnector->mst_root)
2993                         continue;
2994
2995                 ret = drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr, true);
2996
2997                 if (ret < 0) {
2998                         dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2999                                         aconnector->dc_link);
3000                         need_hotplug = true;
3001                 }
3002         }
3003         drm_connector_list_iter_end(&iter);
3004
3005         if (need_hotplug)
3006                 drm_kms_helper_hotplug_event(ddev);
3007
3008         amdgpu_dm_irq_resume_late(adev);
3009
3010         amdgpu_dm_smu_write_watermarks_table(adev);
3011
3012         return 0;
3013 }
3014
3015 /**
3016  * DOC: DM Lifecycle
3017  *
3018  * DM (and consequently DC) is registered in the amdgpu base driver as a IP
3019  * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
3020  * the base driver's device list to be initialized and torn down accordingly.
3021  *
3022  * The functions to do so are provided as hooks in &struct amd_ip_funcs.
3023  */
3024
3025 static const struct amd_ip_funcs amdgpu_dm_funcs = {
3026         .name = "dm",
3027         .early_init = dm_early_init,
3028         .late_init = dm_late_init,
3029         .sw_init = dm_sw_init,
3030         .sw_fini = dm_sw_fini,
3031         .early_fini = amdgpu_dm_early_fini,
3032         .hw_init = dm_hw_init,
3033         .hw_fini = dm_hw_fini,
3034         .suspend = dm_suspend,
3035         .resume = dm_resume,
3036         .is_idle = dm_is_idle,
3037         .wait_for_idle = dm_wait_for_idle,
3038         .check_soft_reset = dm_check_soft_reset,
3039         .soft_reset = dm_soft_reset,
3040         .set_clockgating_state = dm_set_clockgating_state,
3041         .set_powergating_state = dm_set_powergating_state,
3042 };
3043
3044 const struct amdgpu_ip_block_version dm_ip_block = {
3045         .type = AMD_IP_BLOCK_TYPE_DCE,
3046         .major = 1,
3047         .minor = 0,
3048         .rev = 0,
3049         .funcs = &amdgpu_dm_funcs,
3050 };
3051
3052
3053 /**
3054  * DOC: atomic
3055  *
3056  * *WIP*
3057  */
3058
3059 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
3060         .fb_create = amdgpu_display_user_framebuffer_create,
3061         .get_format_info = amdgpu_dm_plane_get_format_info,
3062         .atomic_check = amdgpu_dm_atomic_check,
3063         .atomic_commit = drm_atomic_helper_commit,
3064 };
3065
3066 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
3067         .atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
3068         .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
3069 };
3070
3071 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
3072 {
3073         struct amdgpu_dm_backlight_caps *caps;
3074         struct drm_connector *conn_base;
3075         struct amdgpu_device *adev;
3076         struct drm_luminance_range_info *luminance_range;
3077
3078         if (aconnector->bl_idx == -1 ||
3079             aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP)
3080                 return;
3081
3082         conn_base = &aconnector->base;
3083         adev = drm_to_adev(conn_base->dev);
3084
3085         caps = &adev->dm.backlight_caps[aconnector->bl_idx];
3086         caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
3087         caps->aux_support = false;
3088
3089         if (caps->ext_caps->bits.oled == 1
3090             /*
3091              * ||
3092              * caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
3093              * caps->ext_caps->bits.hdr_aux_backlight_control == 1
3094              */)
3095                 caps->aux_support = true;
3096
3097         if (amdgpu_backlight == 0)
3098                 caps->aux_support = false;
3099         else if (amdgpu_backlight == 1)
3100                 caps->aux_support = true;
3101
3102         luminance_range = &conn_base->display_info.luminance_range;
3103
3104         if (luminance_range->max_luminance) {
3105                 caps->aux_min_input_signal = luminance_range->min_luminance;
3106                 caps->aux_max_input_signal = luminance_range->max_luminance;
3107         } else {
3108                 caps->aux_min_input_signal = 0;
3109                 caps->aux_max_input_signal = 512;
3110         }
3111 }
3112
3113 void amdgpu_dm_update_connector_after_detect(
3114                 struct amdgpu_dm_connector *aconnector)
3115 {
3116         struct drm_connector *connector = &aconnector->base;
3117         struct drm_device *dev = connector->dev;
3118         struct dc_sink *sink;
3119
3120         /* MST handled by drm_mst framework */
3121         if (aconnector->mst_mgr.mst_state == true)
3122                 return;
3123
3124         sink = aconnector->dc_link->local_sink;
3125         if (sink)
3126                 dc_sink_retain(sink);
3127
3128         /*
3129          * Edid mgmt connector gets first update only in mode_valid hook and then
3130          * the connector sink is set to either fake or physical sink depends on link status.
3131          * Skip if already done during boot.
3132          */
3133         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
3134                         && aconnector->dc_em_sink) {
3135
3136                 /*
3137                  * For S3 resume with headless use eml_sink to fake stream
3138                  * because on resume connector->sink is set to NULL
3139                  */
3140                 mutex_lock(&dev->mode_config.mutex);
3141
3142                 if (sink) {
3143                         if (aconnector->dc_sink) {
3144                                 amdgpu_dm_update_freesync_caps(connector, NULL);
3145                                 /*
3146                                  * retain and release below are used to
3147                                  * bump up refcount for sink because the link doesn't point
3148                                  * to it anymore after disconnect, so on next crtc to connector
3149                                  * reshuffle by UMD we will get into unwanted dc_sink release
3150                                  */
3151                                 dc_sink_release(aconnector->dc_sink);
3152                         }
3153                         aconnector->dc_sink = sink;
3154                         dc_sink_retain(aconnector->dc_sink);
3155                         amdgpu_dm_update_freesync_caps(connector,
3156                                         aconnector->edid);
3157                 } else {
3158                         amdgpu_dm_update_freesync_caps(connector, NULL);
3159                         if (!aconnector->dc_sink) {
3160                                 aconnector->dc_sink = aconnector->dc_em_sink;
3161                                 dc_sink_retain(aconnector->dc_sink);
3162                         }
3163                 }
3164
3165                 mutex_unlock(&dev->mode_config.mutex);
3166
3167                 if (sink)
3168                         dc_sink_release(sink);
3169                 return;
3170         }
3171
3172         /*
3173          * TODO: temporary guard to look for proper fix
3174          * if this sink is MST sink, we should not do anything
3175          */
3176         if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3177                 dc_sink_release(sink);
3178                 return;
3179         }
3180
3181         if (aconnector->dc_sink == sink) {
3182                 /*
3183                  * We got a DP short pulse (Link Loss, DP CTS, etc...).
3184                  * Do nothing!!
3185                  */
3186                 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
3187                                 aconnector->connector_id);
3188                 if (sink)
3189                         dc_sink_release(sink);
3190                 return;
3191         }
3192
3193         DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
3194                 aconnector->connector_id, aconnector->dc_sink, sink);
3195
3196         mutex_lock(&dev->mode_config.mutex);
3197
3198         /*
3199          * 1. Update status of the drm connector
3200          * 2. Send an event and let userspace tell us what to do
3201          */
3202         if (sink) {
3203                 /*
3204                  * TODO: check if we still need the S3 mode update workaround.
3205                  * If yes, put it here.
3206                  */
3207                 if (aconnector->dc_sink) {
3208                         amdgpu_dm_update_freesync_caps(connector, NULL);
3209                         dc_sink_release(aconnector->dc_sink);
3210                 }
3211
3212                 aconnector->dc_sink = sink;
3213                 dc_sink_retain(aconnector->dc_sink);
3214                 if (sink->dc_edid.length == 0) {
3215                         aconnector->edid = NULL;
3216                         if (aconnector->dc_link->aux_mode) {
3217                                 drm_dp_cec_unset_edid(
3218                                         &aconnector->dm_dp_aux.aux);
3219                         }
3220                 } else {
3221                         aconnector->edid =
3222                                 (struct edid *)sink->dc_edid.raw_edid;
3223
3224                         if (aconnector->dc_link->aux_mode)
3225                                 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
3226                                                     aconnector->edid);
3227                 }
3228
3229                 if (!aconnector->timing_requested) {
3230                         aconnector->timing_requested =
3231                                 kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL);
3232                         if (!aconnector->timing_requested)
3233                                 drm_err(dev,
3234                                         "failed to create aconnector->requested_timing\n");
3235                 }
3236
3237                 drm_connector_update_edid_property(connector, aconnector->edid);
3238                 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
3239                 update_connector_ext_caps(aconnector);
3240         } else {
3241                 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
3242                 amdgpu_dm_update_freesync_caps(connector, NULL);
3243                 drm_connector_update_edid_property(connector, NULL);
3244                 aconnector->num_modes = 0;
3245                 dc_sink_release(aconnector->dc_sink);
3246                 aconnector->dc_sink = NULL;
3247                 aconnector->edid = NULL;
3248                 kfree(aconnector->timing_requested);
3249                 aconnector->timing_requested = NULL;
3250                 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
3251                 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
3252                         connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
3253         }
3254
3255         mutex_unlock(&dev->mode_config.mutex);
3256
3257         update_subconnector_property(aconnector);
3258
3259         if (sink)
3260                 dc_sink_release(sink);
3261 }
3262
3263 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
3264 {
3265         struct drm_connector *connector = &aconnector->base;
3266         struct drm_device *dev = connector->dev;
3267         enum dc_connection_type new_connection_type = dc_connection_none;
3268         struct amdgpu_device *adev = drm_to_adev(dev);
3269         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
3270         bool ret = false;
3271
3272         if (adev->dm.disable_hpd_irq)
3273                 return;
3274
3275         /*
3276          * In case of failure or MST no need to update connector status or notify the OS
3277          * since (for MST case) MST does this in its own context.
3278          */
3279         mutex_lock(&aconnector->hpd_lock);
3280
3281         if (adev->dm.hdcp_workqueue) {
3282                 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
3283                 dm_con_state->update_hdcp = true;
3284         }
3285         if (aconnector->fake_enable)
3286                 aconnector->fake_enable = false;
3287
3288         aconnector->timing_changed = false;
3289
3290         if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
3291                 DRM_ERROR("KMS: Failed to detect connector\n");
3292
3293         if (aconnector->base.force && new_connection_type == dc_connection_none) {
3294                 emulated_link_detect(aconnector->dc_link);
3295
3296                 drm_modeset_lock_all(dev);
3297                 dm_restore_drm_connector_state(dev, connector);
3298                 drm_modeset_unlock_all(dev);
3299
3300                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3301                         drm_kms_helper_connector_hotplug_event(connector);
3302         } else {
3303                 mutex_lock(&adev->dm.dc_lock);
3304                 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3305                 mutex_unlock(&adev->dm.dc_lock);
3306                 if (ret) {
3307                         amdgpu_dm_update_connector_after_detect(aconnector);
3308
3309                         drm_modeset_lock_all(dev);
3310                         dm_restore_drm_connector_state(dev, connector);
3311                         drm_modeset_unlock_all(dev);
3312
3313                         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3314                                 drm_kms_helper_connector_hotplug_event(connector);
3315                 }
3316         }
3317         mutex_unlock(&aconnector->hpd_lock);
3318
3319 }
3320
3321 static void handle_hpd_irq(void *param)
3322 {
3323         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3324
3325         handle_hpd_irq_helper(aconnector);
3326
3327 }
3328
3329 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,
3330                                                         union hpd_irq_data hpd_irq_data)
3331 {
3332         struct hpd_rx_irq_offload_work *offload_work =
3333                                 kzalloc(sizeof(*offload_work), GFP_KERNEL);
3334
3335         if (!offload_work) {
3336                 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n");
3337                 return;
3338         }
3339
3340         INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);
3341         offload_work->data = hpd_irq_data;
3342         offload_work->offload_wq = offload_wq;
3343
3344         queue_work(offload_wq->wq, &offload_work->work);
3345         DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");
3346 }
3347
3348 static void handle_hpd_rx_irq(void *param)
3349 {
3350         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3351         struct drm_connector *connector = &aconnector->base;
3352         struct drm_device *dev = connector->dev;
3353         struct dc_link *dc_link = aconnector->dc_link;
3354         bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
3355         bool result = false;
3356         enum dc_connection_type new_connection_type = dc_connection_none;
3357         struct amdgpu_device *adev = drm_to_adev(dev);
3358         union hpd_irq_data hpd_irq_data;
3359         bool link_loss = false;
3360         bool has_left_work = false;
3361         int idx = dc_link->link_index;
3362         struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];
3363
3364         memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
3365
3366         if (adev->dm.disable_hpd_irq)
3367                 return;
3368
3369         /*
3370          * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
3371          * conflict, after implement i2c helper, this mutex should be
3372          * retired.
3373          */
3374         mutex_lock(&aconnector->hpd_lock);
3375
3376         result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,
3377                                                 &link_loss, true, &has_left_work);
3378
3379         if (!has_left_work)
3380                 goto out;
3381
3382         if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3383                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3384                 goto out;
3385         }
3386
3387         if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {
3388                 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
3389                         hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
3390                         bool skip = false;
3391
3392                         /*
3393                          * DOWN_REP_MSG_RDY is also handled by polling method
3394                          * mgr->cbs->poll_hpd_irq()
3395                          */
3396                         spin_lock(&offload_wq->offload_lock);
3397                         skip = offload_wq->is_handling_mst_msg_rdy_event;
3398
3399                         if (!skip)
3400                                 offload_wq->is_handling_mst_msg_rdy_event = true;
3401
3402                         spin_unlock(&offload_wq->offload_lock);
3403
3404                         if (!skip)
3405                                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3406
3407                         goto out;
3408                 }
3409
3410                 if (link_loss) {
3411                         bool skip = false;
3412
3413                         spin_lock(&offload_wq->offload_lock);
3414                         skip = offload_wq->is_handling_link_loss;
3415
3416                         if (!skip)
3417                                 offload_wq->is_handling_link_loss = true;
3418
3419                         spin_unlock(&offload_wq->offload_lock);
3420
3421                         if (!skip)
3422                                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3423
3424                         goto out;
3425                 }
3426         }
3427
3428 out:
3429         if (result && !is_mst_root_connector) {
3430                 /* Downstream Port status changed. */
3431                 if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
3432                         DRM_ERROR("KMS: Failed to detect connector\n");
3433
3434                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3435                         emulated_link_detect(dc_link);
3436
3437                         if (aconnector->fake_enable)
3438                                 aconnector->fake_enable = false;
3439
3440                         amdgpu_dm_update_connector_after_detect(aconnector);
3441
3442
3443                         drm_modeset_lock_all(dev);
3444                         dm_restore_drm_connector_state(dev, connector);
3445                         drm_modeset_unlock_all(dev);
3446
3447                         drm_kms_helper_connector_hotplug_event(connector);
3448                 } else {
3449                         bool ret = false;
3450
3451                         mutex_lock(&adev->dm.dc_lock);
3452                         ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
3453                         mutex_unlock(&adev->dm.dc_lock);
3454
3455                         if (ret) {
3456                                 if (aconnector->fake_enable)
3457                                         aconnector->fake_enable = false;
3458
3459                                 amdgpu_dm_update_connector_after_detect(aconnector);
3460
3461                                 drm_modeset_lock_all(dev);
3462                                 dm_restore_drm_connector_state(dev, connector);
3463                                 drm_modeset_unlock_all(dev);
3464
3465                                 drm_kms_helper_connector_hotplug_event(connector);
3466                         }
3467                 }
3468         }
3469         if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
3470                 if (adev->dm.hdcp_workqueue)
3471                         hdcp_handle_cpirq(adev->dm.hdcp_workqueue,  aconnector->base.index);
3472         }
3473
3474         if (dc_link->type != dc_connection_mst_branch)
3475                 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
3476
3477         mutex_unlock(&aconnector->hpd_lock);
3478 }
3479
3480 static void register_hpd_handlers(struct amdgpu_device *adev)
3481 {
3482         struct drm_device *dev = adev_to_drm(adev);
3483         struct drm_connector *connector;
3484         struct amdgpu_dm_connector *aconnector;
3485         const struct dc_link *dc_link;
3486         struct dc_interrupt_params int_params = {0};
3487
3488         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3489         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3490
3491         list_for_each_entry(connector,
3492                         &dev->mode_config.connector_list, head) {
3493
3494                 aconnector = to_amdgpu_dm_connector(connector);
3495                 dc_link = aconnector->dc_link;
3496
3497                 if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) {
3498                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3499                         int_params.irq_source = dc_link->irq_source_hpd;
3500
3501                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3502                                         handle_hpd_irq,
3503                                         (void *) aconnector);
3504                 }
3505
3506                 if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) {
3507
3508                         /* Also register for DP short pulse (hpd_rx). */
3509                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3510                         int_params.irq_source = dc_link->irq_source_hpd_rx;
3511
3512                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3513                                         handle_hpd_rx_irq,
3514                                         (void *) aconnector);
3515                 }
3516
3517                 if (adev->dm.hpd_rx_offload_wq)
3518                         adev->dm.hpd_rx_offload_wq[connector->index].aconnector =
3519                                 aconnector;
3520         }
3521 }
3522
3523 #if defined(CONFIG_DRM_AMD_DC_SI)
3524 /* Register IRQ sources and initialize IRQ callbacks */
3525 static int dce60_register_irq_handlers(struct amdgpu_device *adev)
3526 {
3527         struct dc *dc = adev->dm.dc;
3528         struct common_irq_params *c_irq_params;
3529         struct dc_interrupt_params int_params = {0};
3530         int r;
3531         int i;
3532         unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3533
3534         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3535         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3536
3537         /*
3538          * Actions of amdgpu_irq_add_id():
3539          * 1. Register a set() function with base driver.
3540          *    Base driver will call set() function to enable/disable an
3541          *    interrupt in DC hardware.
3542          * 2. Register amdgpu_dm_irq_handler().
3543          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3544          *    coming from DC hardware.
3545          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3546          *    for acknowledging and handling.
3547          */
3548
3549         /* Use VBLANK interrupt */
3550         for (i = 0; i < adev->mode_info.num_crtc; i++) {
3551                 r = amdgpu_irq_add_id(adev, client_id, i + 1, &adev->crtc_irq);
3552                 if (r) {
3553                         DRM_ERROR("Failed to add crtc irq id!\n");
3554                         return r;
3555                 }
3556
3557                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3558                 int_params.irq_source =
3559                         dc_interrupt_to_irq_source(dc, i + 1, 0);
3560
3561                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3562
3563                 c_irq_params->adev = adev;
3564                 c_irq_params->irq_src = int_params.irq_source;
3565
3566                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3567                                 dm_crtc_high_irq, c_irq_params);
3568         }
3569
3570         /* Use GRPH_PFLIP interrupt */
3571         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3572                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3573                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3574                 if (r) {
3575                         DRM_ERROR("Failed to add page flip irq id!\n");
3576                         return r;
3577                 }
3578
3579                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3580                 int_params.irq_source =
3581                         dc_interrupt_to_irq_source(dc, i, 0);
3582
3583                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3584
3585                 c_irq_params->adev = adev;
3586                 c_irq_params->irq_src = int_params.irq_source;
3587
3588                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3589                                 dm_pflip_high_irq, c_irq_params);
3590
3591         }
3592
3593         /* HPD */
3594         r = amdgpu_irq_add_id(adev, client_id,
3595                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3596         if (r) {
3597                 DRM_ERROR("Failed to add hpd irq id!\n");
3598                 return r;
3599         }
3600
3601         register_hpd_handlers(adev);
3602
3603         return 0;
3604 }
3605 #endif
3606
3607 /* Register IRQ sources and initialize IRQ callbacks */
3608 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
3609 {
3610         struct dc *dc = adev->dm.dc;
3611         struct common_irq_params *c_irq_params;
3612         struct dc_interrupt_params int_params = {0};
3613         int r;
3614         int i;
3615         unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3616
3617         if (adev->family >= AMDGPU_FAMILY_AI)
3618                 client_id = SOC15_IH_CLIENTID_DCE;
3619
3620         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3621         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3622
3623         /*
3624          * Actions of amdgpu_irq_add_id():
3625          * 1. Register a set() function with base driver.
3626          *    Base driver will call set() function to enable/disable an
3627          *    interrupt in DC hardware.
3628          * 2. Register amdgpu_dm_irq_handler().
3629          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3630          *    coming from DC hardware.
3631          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3632          *    for acknowledging and handling.
3633          */
3634
3635         /* Use VBLANK interrupt */
3636         for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
3637                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
3638                 if (r) {
3639                         DRM_ERROR("Failed to add crtc irq id!\n");
3640                         return r;
3641                 }
3642
3643                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3644                 int_params.irq_source =
3645                         dc_interrupt_to_irq_source(dc, i, 0);
3646
3647                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3648
3649                 c_irq_params->adev = adev;
3650                 c_irq_params->irq_src = int_params.irq_source;
3651
3652                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3653                                 dm_crtc_high_irq, c_irq_params);
3654         }
3655
3656         /* Use VUPDATE interrupt */
3657         for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
3658                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
3659                 if (r) {
3660                         DRM_ERROR("Failed to add vupdate irq id!\n");
3661                         return r;
3662                 }
3663
3664                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3665                 int_params.irq_source =
3666                         dc_interrupt_to_irq_source(dc, i, 0);
3667
3668                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3669
3670                 c_irq_params->adev = adev;
3671                 c_irq_params->irq_src = int_params.irq_source;
3672
3673                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3674                                 dm_vupdate_high_irq, c_irq_params);
3675         }
3676
3677         /* Use GRPH_PFLIP interrupt */
3678         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3679                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3680                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3681                 if (r) {
3682                         DRM_ERROR("Failed to add page flip irq id!\n");
3683                         return r;
3684                 }
3685
3686                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3687                 int_params.irq_source =
3688                         dc_interrupt_to_irq_source(dc, i, 0);
3689
3690                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3691
3692                 c_irq_params->adev = adev;
3693                 c_irq_params->irq_src = int_params.irq_source;
3694
3695                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3696                                 dm_pflip_high_irq, c_irq_params);
3697
3698         }
3699
3700         /* HPD */
3701         r = amdgpu_irq_add_id(adev, client_id,
3702                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3703         if (r) {
3704                 DRM_ERROR("Failed to add hpd irq id!\n");
3705                 return r;
3706         }
3707
3708         register_hpd_handlers(adev);
3709
3710         return 0;
3711 }
3712
3713 /* Register IRQ sources and initialize IRQ callbacks */
3714 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
3715 {
3716         struct dc *dc = adev->dm.dc;
3717         struct common_irq_params *c_irq_params;
3718         struct dc_interrupt_params int_params = {0};
3719         int r;
3720         int i;
3721 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3722         static const unsigned int vrtl_int_srcid[] = {
3723                 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
3724                 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
3725                 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
3726                 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
3727                 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
3728                 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
3729         };
3730 #endif
3731
3732         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3733         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3734
3735         /*
3736          * Actions of amdgpu_irq_add_id():
3737          * 1. Register a set() function with base driver.
3738          *    Base driver will call set() function to enable/disable an
3739          *    interrupt in DC hardware.
3740          * 2. Register amdgpu_dm_irq_handler().
3741          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3742          *    coming from DC hardware.
3743          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3744          *    for acknowledging and handling.
3745          */
3746
3747         /* Use VSTARTUP interrupt */
3748         for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
3749                         i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
3750                         i++) {
3751                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
3752
3753                 if (r) {
3754                         DRM_ERROR("Failed to add crtc irq id!\n");
3755                         return r;
3756                 }
3757
3758                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3759                 int_params.irq_source =
3760                         dc_interrupt_to_irq_source(dc, i, 0);
3761
3762                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3763
3764                 c_irq_params->adev = adev;
3765                 c_irq_params->irq_src = int_params.irq_source;
3766
3767                 amdgpu_dm_irq_register_interrupt(
3768                         adev, &int_params, dm_crtc_high_irq, c_irq_params);
3769         }
3770
3771         /* Use otg vertical line interrupt */
3772 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3773         for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
3774                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
3775                                 vrtl_int_srcid[i], &adev->vline0_irq);
3776
3777                 if (r) {
3778                         DRM_ERROR("Failed to add vline0 irq id!\n");
3779                         return r;
3780                 }
3781
3782                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3783                 int_params.irq_source =
3784                         dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
3785
3786                 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {
3787                         DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]);
3788                         break;
3789                 }
3790
3791                 c_irq_params = &adev->dm.vline0_params[int_params.irq_source
3792                                         - DC_IRQ_SOURCE_DC1_VLINE0];
3793
3794                 c_irq_params->adev = adev;
3795                 c_irq_params->irq_src = int_params.irq_source;
3796
3797                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3798                                 dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
3799         }
3800 #endif
3801
3802         /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
3803          * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
3804          * to trigger at end of each vblank, regardless of state of the lock,
3805          * matching DCE behaviour.
3806          */
3807         for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
3808              i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
3809              i++) {
3810                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
3811
3812                 if (r) {
3813                         DRM_ERROR("Failed to add vupdate irq id!\n");
3814                         return r;
3815                 }
3816
3817                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3818                 int_params.irq_source =
3819                         dc_interrupt_to_irq_source(dc, i, 0);
3820
3821                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3822
3823                 c_irq_params->adev = adev;
3824                 c_irq_params->irq_src = int_params.irq_source;
3825
3826                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3827                                 dm_vupdate_high_irq, c_irq_params);
3828         }
3829
3830         /* Use GRPH_PFLIP interrupt */
3831         for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
3832                         i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;
3833                         i++) {
3834                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
3835                 if (r) {
3836                         DRM_ERROR("Failed to add page flip irq id!\n");
3837                         return r;
3838                 }
3839
3840                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3841                 int_params.irq_source =
3842                         dc_interrupt_to_irq_source(dc, i, 0);
3843
3844                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3845
3846                 c_irq_params->adev = adev;
3847                 c_irq_params->irq_src = int_params.irq_source;
3848
3849                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3850                                 dm_pflip_high_irq, c_irq_params);
3851
3852         }
3853
3854         /* HPD */
3855         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
3856                         &adev->hpd_irq);
3857         if (r) {
3858                 DRM_ERROR("Failed to add hpd irq id!\n");
3859                 return r;
3860         }
3861
3862         register_hpd_handlers(adev);
3863
3864         return 0;
3865 }
3866 /* Register Outbox IRQ sources and initialize IRQ callbacks */
3867 static int register_outbox_irq_handlers(struct amdgpu_device *adev)
3868 {
3869         struct dc *dc = adev->dm.dc;
3870         struct common_irq_params *c_irq_params;
3871         struct dc_interrupt_params int_params = {0};
3872         int r, i;
3873
3874         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3875         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3876
3877         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,
3878                         &adev->dmub_outbox_irq);
3879         if (r) {
3880                 DRM_ERROR("Failed to add outbox irq id!\n");
3881                 return r;
3882         }
3883
3884         if (dc->ctx->dmub_srv) {
3885                 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
3886                 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3887                 int_params.irq_source =
3888                 dc_interrupt_to_irq_source(dc, i, 0);
3889
3890                 c_irq_params = &adev->dm.dmub_outbox_params[0];
3891
3892                 c_irq_params->adev = adev;
3893                 c_irq_params->irq_src = int_params.irq_source;
3894
3895                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3896                                 dm_dmub_outbox1_low_irq, c_irq_params);
3897         }
3898
3899         return 0;
3900 }
3901
3902 /*
3903  * Acquires the lock for the atomic state object and returns
3904  * the new atomic state.
3905  *
3906  * This should only be called during atomic check.
3907  */
3908 int dm_atomic_get_state(struct drm_atomic_state *state,
3909                         struct dm_atomic_state **dm_state)
3910 {
3911         struct drm_device *dev = state->dev;
3912         struct amdgpu_device *adev = drm_to_adev(dev);
3913         struct amdgpu_display_manager *dm = &adev->dm;
3914         struct drm_private_state *priv_state;
3915
3916         if (*dm_state)
3917                 return 0;
3918
3919         priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3920         if (IS_ERR(priv_state))
3921                 return PTR_ERR(priv_state);
3922
3923         *dm_state = to_dm_atomic_state(priv_state);
3924
3925         return 0;
3926 }
3927
3928 static struct dm_atomic_state *
3929 dm_atomic_get_new_state(struct drm_atomic_state *state)
3930 {
3931         struct drm_device *dev = state->dev;
3932         struct amdgpu_device *adev = drm_to_adev(dev);
3933         struct amdgpu_display_manager *dm = &adev->dm;
3934         struct drm_private_obj *obj;
3935         struct drm_private_state *new_obj_state;
3936         int i;
3937
3938         for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3939                 if (obj->funcs == dm->atomic_obj.funcs)
3940                         return to_dm_atomic_state(new_obj_state);
3941         }
3942
3943         return NULL;
3944 }
3945
3946 static struct drm_private_state *
3947 dm_atomic_duplicate_state(struct drm_private_obj *obj)
3948 {
3949         struct dm_atomic_state *old_state, *new_state;
3950
3951         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
3952         if (!new_state)
3953                 return NULL;
3954
3955         __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
3956
3957         old_state = to_dm_atomic_state(obj->state);
3958
3959         if (old_state && old_state->context)
3960                 new_state->context = dc_copy_state(old_state->context);
3961
3962         if (!new_state->context) {
3963                 kfree(new_state);
3964                 return NULL;
3965         }
3966
3967         return &new_state->base;
3968 }
3969
3970 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
3971                                     struct drm_private_state *state)
3972 {
3973         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
3974
3975         if (dm_state && dm_state->context)
3976                 dc_release_state(dm_state->context);
3977
3978         kfree(dm_state);
3979 }
3980
3981 static struct drm_private_state_funcs dm_atomic_state_funcs = {
3982         .atomic_duplicate_state = dm_atomic_duplicate_state,
3983         .atomic_destroy_state = dm_atomic_destroy_state,
3984 };
3985
3986 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
3987 {
3988         struct dm_atomic_state *state;
3989         int r;
3990
3991         adev->mode_info.mode_config_initialized = true;
3992
3993         adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
3994         adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
3995
3996         adev_to_drm(adev)->mode_config.max_width = 16384;
3997         adev_to_drm(adev)->mode_config.max_height = 16384;
3998
3999         adev_to_drm(adev)->mode_config.preferred_depth = 24;
4000         if (adev->asic_type == CHIP_HAWAII)
4001                 /* disable prefer shadow for now due to hibernation issues */
4002                 adev_to_drm(adev)->mode_config.prefer_shadow = 0;
4003         else
4004                 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
4005         /* indicates support for immediate flip */
4006         adev_to_drm(adev)->mode_config.async_page_flip = true;
4007
4008         state = kzalloc(sizeof(*state), GFP_KERNEL);
4009         if (!state)
4010                 return -ENOMEM;
4011
4012         state->context = dc_create_state(adev->dm.dc);
4013         if (!state->context) {
4014                 kfree(state);
4015                 return -ENOMEM;
4016         }
4017
4018         dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
4019
4020         drm_atomic_private_obj_init(adev_to_drm(adev),
4021                                     &adev->dm.atomic_obj,
4022                                     &state->base,
4023                                     &dm_atomic_state_funcs);
4024
4025         r = amdgpu_display_modeset_create_props(adev);
4026         if (r) {
4027                 dc_release_state(state->context);
4028                 kfree(state);
4029                 return r;
4030         }
4031
4032         r = amdgpu_dm_audio_init(adev);
4033         if (r) {
4034                 dc_release_state(state->context);
4035                 kfree(state);
4036                 return r;
4037         }
4038
4039         return 0;
4040 }
4041
4042 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
4043 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
4044 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
4045
4046 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
4047                                             int bl_idx)
4048 {
4049 #if defined(CONFIG_ACPI)
4050         struct amdgpu_dm_backlight_caps caps;
4051
4052         memset(&caps, 0, sizeof(caps));
4053
4054         if (dm->backlight_caps[bl_idx].caps_valid)
4055                 return;
4056
4057         amdgpu_acpi_get_backlight_caps(&caps);
4058         if (caps.caps_valid) {
4059                 dm->backlight_caps[bl_idx].caps_valid = true;
4060                 if (caps.aux_support)
4061                         return;
4062                 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;
4063                 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;
4064         } else {
4065                 dm->backlight_caps[bl_idx].min_input_signal =
4066                                 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4067                 dm->backlight_caps[bl_idx].max_input_signal =
4068                                 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4069         }
4070 #else
4071         if (dm->backlight_caps[bl_idx].aux_support)
4072                 return;
4073
4074         dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4075         dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4076 #endif
4077 }
4078
4079 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
4080                                 unsigned int *min, unsigned int *max)
4081 {
4082         if (!caps)
4083                 return 0;
4084
4085         if (caps->aux_support) {
4086                 // Firmware limits are in nits, DC API wants millinits.
4087                 *max = 1000 * caps->aux_max_input_signal;
4088                 *min = 1000 * caps->aux_min_input_signal;
4089         } else {
4090                 // Firmware limits are 8-bit, PWM control is 16-bit.
4091                 *max = 0x101 * caps->max_input_signal;
4092                 *min = 0x101 * caps->min_input_signal;
4093         }
4094         return 1;
4095 }
4096
4097 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
4098                                         uint32_t brightness)
4099 {
4100         unsigned int min, max;
4101
4102         if (!get_brightness_range(caps, &min, &max))
4103                 return brightness;
4104
4105         // Rescale 0..255 to min..max
4106         return min + DIV_ROUND_CLOSEST((max - min) * brightness,
4107                                        AMDGPU_MAX_BL_LEVEL);
4108 }
4109
4110 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
4111                                       uint32_t brightness)
4112 {
4113         unsigned int min, max;
4114
4115         if (!get_brightness_range(caps, &min, &max))
4116                 return brightness;
4117
4118         if (brightness < min)
4119                 return 0;
4120         // Rescale min..max to 0..255
4121         return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
4122                                  max - min);
4123 }
4124
4125 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
4126                                          int bl_idx,
4127                                          u32 user_brightness)
4128 {
4129         struct amdgpu_dm_backlight_caps caps;
4130         struct dc_link *link;
4131         u32 brightness;
4132         bool rc;
4133
4134         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4135         caps = dm->backlight_caps[bl_idx];
4136
4137         dm->brightness[bl_idx] = user_brightness;
4138         /* update scratch register */
4139         if (bl_idx == 0)
4140                 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);
4141         brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]);
4142         link = (struct dc_link *)dm->backlight_link[bl_idx];
4143
4144         /* Change brightness based on AUX property */
4145         if (caps.aux_support) {
4146                 rc = dc_link_set_backlight_level_nits(link, true, brightness,
4147                                                       AUX_BL_DEFAULT_TRANSITION_TIME_MS);
4148                 if (!rc)
4149                         DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
4150         } else {
4151                 rc = dc_link_set_backlight_level(link, brightness, 0);
4152                 if (!rc)
4153                         DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
4154         }
4155
4156         if (rc)
4157                 dm->actual_brightness[bl_idx] = user_brightness;
4158 }
4159
4160 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
4161 {
4162         struct amdgpu_display_manager *dm = bl_get_data(bd);
4163         int i;
4164
4165         for (i = 0; i < dm->num_of_edps; i++) {
4166                 if (bd == dm->backlight_dev[i])
4167                         break;
4168         }
4169         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4170                 i = 0;
4171         amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);
4172
4173         return 0;
4174 }
4175
4176 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
4177                                          int bl_idx)
4178 {
4179         int ret;
4180         struct amdgpu_dm_backlight_caps caps;
4181         struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];
4182
4183         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4184         caps = dm->backlight_caps[bl_idx];
4185
4186         if (caps.aux_support) {
4187                 u32 avg, peak;
4188                 bool rc;
4189
4190                 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
4191                 if (!rc)
4192                         return dm->brightness[bl_idx];
4193                 return convert_brightness_to_user(&caps, avg);
4194         }
4195
4196         ret = dc_link_get_backlight_level(link);
4197
4198         if (ret == DC_ERROR_UNEXPECTED)
4199                 return dm->brightness[bl_idx];
4200
4201         return convert_brightness_to_user(&caps, ret);
4202 }
4203
4204 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
4205 {
4206         struct amdgpu_display_manager *dm = bl_get_data(bd);
4207         int i;
4208
4209         for (i = 0; i < dm->num_of_edps; i++) {
4210                 if (bd == dm->backlight_dev[i])
4211                         break;
4212         }
4213         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4214                 i = 0;
4215         return amdgpu_dm_backlight_get_level(dm, i);
4216 }
4217
4218 static const struct backlight_ops amdgpu_dm_backlight_ops = {
4219         .options = BL_CORE_SUSPENDRESUME,
4220         .get_brightness = amdgpu_dm_backlight_get_brightness,
4221         .update_status  = amdgpu_dm_backlight_update_status,
4222 };
4223
4224 static void
4225 amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector)
4226 {
4227         struct drm_device *drm = aconnector->base.dev;
4228         struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm;
4229         struct backlight_properties props = { 0 };
4230         char bl_name[16];
4231
4232         if (aconnector->bl_idx == -1)
4233                 return;
4234
4235         if (!acpi_video_backlight_use_native()) {
4236                 drm_info(drm, "Skipping amdgpu DM backlight registration\n");
4237                 /* Try registering an ACPI video backlight device instead. */
4238                 acpi_video_register_backlight();
4239                 return;
4240         }
4241
4242         props.max_brightness = AMDGPU_MAX_BL_LEVEL;
4243         props.brightness = AMDGPU_MAX_BL_LEVEL;
4244         props.type = BACKLIGHT_RAW;
4245
4246         snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
4247                  drm->primary->index + aconnector->bl_idx);
4248
4249         dm->backlight_dev[aconnector->bl_idx] =
4250                 backlight_device_register(bl_name, aconnector->base.kdev, dm,
4251                                           &amdgpu_dm_backlight_ops, &props);
4252
4253         if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) {
4254                 DRM_ERROR("DM: Backlight registration failed!\n");
4255                 dm->backlight_dev[aconnector->bl_idx] = NULL;
4256         } else
4257                 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4258 }
4259
4260 static int initialize_plane(struct amdgpu_display_manager *dm,
4261                             struct amdgpu_mode_info *mode_info, int plane_id,
4262                             enum drm_plane_type plane_type,
4263                             const struct dc_plane_cap *plane_cap)
4264 {
4265         struct drm_plane *plane;
4266         unsigned long possible_crtcs;
4267         int ret = 0;
4268
4269         plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
4270         if (!plane) {
4271                 DRM_ERROR("KMS: Failed to allocate plane\n");
4272                 return -ENOMEM;
4273         }
4274         plane->type = plane_type;
4275
4276         /*
4277          * HACK: IGT tests expect that the primary plane for a CRTC
4278          * can only have one possible CRTC. Only expose support for
4279          * any CRTC if they're not going to be used as a primary plane
4280          * for a CRTC - like overlay or underlay planes.
4281          */
4282         possible_crtcs = 1 << plane_id;
4283         if (plane_id >= dm->dc->caps.max_streams)
4284                 possible_crtcs = 0xff;
4285
4286         ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
4287
4288         if (ret) {
4289                 DRM_ERROR("KMS: Failed to initialize plane\n");
4290                 kfree(plane);
4291                 return ret;
4292         }
4293
4294         if (mode_info)
4295                 mode_info->planes[plane_id] = plane;
4296
4297         return ret;
4298 }
4299
4300
4301 static void setup_backlight_device(struct amdgpu_display_manager *dm,
4302                                    struct amdgpu_dm_connector *aconnector)
4303 {
4304         struct dc_link *link = aconnector->dc_link;
4305         int bl_idx = dm->num_of_edps;
4306
4307         if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) ||
4308             link->type == dc_connection_none)
4309                 return;
4310
4311         if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) {
4312                 drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n");
4313                 return;
4314         }
4315
4316         aconnector->bl_idx = bl_idx;
4317
4318         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4319         dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL;
4320         dm->backlight_link[bl_idx] = link;
4321         dm->num_of_edps++;
4322
4323         update_connector_ext_caps(aconnector);
4324 }
4325
4326 static void amdgpu_set_panel_orientation(struct drm_connector *connector);
4327
4328 /*
4329  * In this architecture, the association
4330  * connector -> encoder -> crtc
4331  * id not really requried. The crtc and connector will hold the
4332  * display_index as an abstraction to use with DAL component
4333  *
4334  * Returns 0 on success
4335  */
4336 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4337 {
4338         struct amdgpu_display_manager *dm = &adev->dm;
4339         s32 i;
4340         struct amdgpu_dm_connector *aconnector = NULL;
4341         struct amdgpu_encoder *aencoder = NULL;
4342         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4343         u32 link_cnt;
4344         s32 primary_planes;
4345         enum dc_connection_type new_connection_type = dc_connection_none;
4346         const struct dc_plane_cap *plane;
4347         bool psr_feature_enabled = false;
4348         bool replay_feature_enabled = false;
4349         int max_overlay = dm->dc->caps.max_slave_planes;
4350
4351         dm->display_indexes_num = dm->dc->caps.max_streams;
4352         /* Update the actual used number of crtc */
4353         adev->mode_info.num_crtc = adev->dm.display_indexes_num;
4354
4355         amdgpu_dm_set_irq_funcs(adev);
4356
4357         link_cnt = dm->dc->caps.max_links;
4358         if (amdgpu_dm_mode_config_init(dm->adev)) {
4359                 DRM_ERROR("DM: Failed to initialize mode config\n");
4360                 return -EINVAL;
4361         }
4362
4363         /* There is one primary plane per CRTC */
4364         primary_planes = dm->dc->caps.max_streams;
4365         ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
4366
4367         /*
4368          * Initialize primary planes, implicit planes for legacy IOCTLS.
4369          * Order is reversed to match iteration order in atomic check.
4370          */
4371         for (i = (primary_planes - 1); i >= 0; i--) {
4372                 plane = &dm->dc->caps.planes[i];
4373
4374                 if (initialize_plane(dm, mode_info, i,
4375                                      DRM_PLANE_TYPE_PRIMARY, plane)) {
4376                         DRM_ERROR("KMS: Failed to initialize primary plane\n");
4377                         goto fail;
4378                 }
4379         }
4380
4381         /*
4382          * Initialize overlay planes, index starting after primary planes.
4383          * These planes have a higher DRM index than the primary planes since
4384          * they should be considered as having a higher z-order.
4385          * Order is reversed to match iteration order in atomic check.
4386          *
4387          * Only support DCN for now, and only expose one so we don't encourage
4388          * userspace to use up all the pipes.
4389          */
4390         for (i = 0; i < dm->dc->caps.max_planes; ++i) {
4391                 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
4392
4393                 /* Do not create overlay if MPO disabled */
4394                 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
4395                         break;
4396
4397                 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
4398                         continue;
4399
4400                 if (!plane->pixel_format_support.argb8888)
4401                         continue;
4402
4403                 if (max_overlay-- == 0)
4404                         break;
4405
4406                 if (initialize_plane(dm, NULL, primary_planes + i,
4407                                      DRM_PLANE_TYPE_OVERLAY, plane)) {
4408                         DRM_ERROR("KMS: Failed to initialize overlay plane\n");
4409                         goto fail;
4410                 }
4411         }
4412
4413         for (i = 0; i < dm->dc->caps.max_streams; i++)
4414                 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4415                         DRM_ERROR("KMS: Failed to initialize crtc\n");
4416                         goto fail;
4417                 }
4418
4419         /* Use Outbox interrupt */
4420         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4421         case IP_VERSION(3, 0, 0):
4422         case IP_VERSION(3, 1, 2):
4423         case IP_VERSION(3, 1, 3):
4424         case IP_VERSION(3, 1, 4):
4425         case IP_VERSION(3, 1, 5):
4426         case IP_VERSION(3, 1, 6):
4427         case IP_VERSION(3, 2, 0):
4428         case IP_VERSION(3, 2, 1):
4429         case IP_VERSION(2, 1, 0):
4430         case IP_VERSION(3, 5, 0):
4431                 if (register_outbox_irq_handlers(dm->adev)) {
4432                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4433                         goto fail;
4434                 }
4435                 break;
4436         default:
4437                 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
4438                               amdgpu_ip_version(adev, DCE_HWIP, 0));
4439         }
4440
4441         /* Determine whether to enable PSR support by default. */
4442         if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {
4443                 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4444                 case IP_VERSION(3, 1, 2):
4445                 case IP_VERSION(3, 1, 3):
4446                 case IP_VERSION(3, 1, 4):
4447                 case IP_VERSION(3, 1, 5):
4448                 case IP_VERSION(3, 1, 6):
4449                 case IP_VERSION(3, 2, 0):
4450                 case IP_VERSION(3, 2, 1):
4451                 case IP_VERSION(3, 5, 0):
4452                         psr_feature_enabled = true;
4453                         break;
4454                 default:
4455                         psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;
4456                         break;
4457                 }
4458         }
4459
4460         if (!(amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) {
4461                 switch (adev->ip_versions[DCE_HWIP][0]) {
4462                 case IP_VERSION(3, 1, 4):
4463                 case IP_VERSION(3, 1, 5):
4464                 case IP_VERSION(3, 1, 6):
4465                 case IP_VERSION(3, 2, 0):
4466                 case IP_VERSION(3, 2, 1):
4467                         replay_feature_enabled = true;
4468                         break;
4469                 default:
4470                         replay_feature_enabled = amdgpu_dc_feature_mask & DC_REPLAY_MASK;
4471                         break;
4472                 }
4473         }
4474         /* loops over all connectors on the board */
4475         for (i = 0; i < link_cnt; i++) {
4476                 struct dc_link *link = NULL;
4477
4478                 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
4479                         DRM_ERROR(
4480                                 "KMS: Cannot support more than %d display indexes\n",
4481                                         AMDGPU_DM_MAX_DISPLAY_INDEX);
4482                         continue;
4483                 }
4484
4485                 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
4486                 if (!aconnector)
4487                         goto fail;
4488
4489                 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
4490                 if (!aencoder)
4491                         goto fail;
4492
4493                 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
4494                         DRM_ERROR("KMS: Failed to initialize encoder\n");
4495                         goto fail;
4496                 }
4497
4498                 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
4499                         DRM_ERROR("KMS: Failed to initialize connector\n");
4500                         goto fail;
4501                 }
4502
4503                 link = dc_get_link_at_index(dm->dc, i);
4504
4505                 if (!dc_link_detect_connection_type(link, &new_connection_type))
4506                         DRM_ERROR("KMS: Failed to detect connector\n");
4507
4508                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
4509                         emulated_link_detect(link);
4510                         amdgpu_dm_update_connector_after_detect(aconnector);
4511                 } else {
4512                         bool ret = false;
4513
4514                         mutex_lock(&dm->dc_lock);
4515                         ret = dc_link_detect(link, DETECT_REASON_BOOT);
4516                         mutex_unlock(&dm->dc_lock);
4517
4518                         if (ret) {
4519                                 amdgpu_dm_update_connector_after_detect(aconnector);
4520                                 setup_backlight_device(dm, aconnector);
4521
4522                                 /*
4523                                  * Disable psr if replay can be enabled
4524                                  */
4525                                 if (replay_feature_enabled && amdgpu_dm_setup_replay(link, aconnector))
4526                                         psr_feature_enabled = false;
4527
4528                                 if (psr_feature_enabled)
4529                                         amdgpu_dm_set_psr_caps(link);
4530
4531                                 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when
4532                                  * PSR is also supported.
4533                                  */
4534                                 if (link->psr_settings.psr_feature_enabled)
4535                                         adev_to_drm(adev)->vblank_disable_immediate = false;
4536                         }
4537                 }
4538                 amdgpu_set_panel_orientation(&aconnector->base);
4539         }
4540
4541         /* Software is initialized. Now we can register interrupt handlers. */
4542         switch (adev->asic_type) {
4543 #if defined(CONFIG_DRM_AMD_DC_SI)
4544         case CHIP_TAHITI:
4545         case CHIP_PITCAIRN:
4546         case CHIP_VERDE:
4547         case CHIP_OLAND:
4548                 if (dce60_register_irq_handlers(dm->adev)) {
4549                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4550                         goto fail;
4551                 }
4552                 break;
4553 #endif
4554         case CHIP_BONAIRE:
4555         case CHIP_HAWAII:
4556         case CHIP_KAVERI:
4557         case CHIP_KABINI:
4558         case CHIP_MULLINS:
4559         case CHIP_TONGA:
4560         case CHIP_FIJI:
4561         case CHIP_CARRIZO:
4562         case CHIP_STONEY:
4563         case CHIP_POLARIS11:
4564         case CHIP_POLARIS10:
4565         case CHIP_POLARIS12:
4566         case CHIP_VEGAM:
4567         case CHIP_VEGA10:
4568         case CHIP_VEGA12:
4569         case CHIP_VEGA20:
4570                 if (dce110_register_irq_handlers(dm->adev)) {
4571                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4572                         goto fail;
4573                 }
4574                 break;
4575         default:
4576                 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4577                 case IP_VERSION(1, 0, 0):
4578                 case IP_VERSION(1, 0, 1):
4579                 case IP_VERSION(2, 0, 2):
4580                 case IP_VERSION(2, 0, 3):
4581                 case IP_VERSION(2, 0, 0):
4582                 case IP_VERSION(2, 1, 0):
4583                 case IP_VERSION(3, 0, 0):
4584                 case IP_VERSION(3, 0, 2):
4585                 case IP_VERSION(3, 0, 3):
4586                 case IP_VERSION(3, 0, 1):
4587                 case IP_VERSION(3, 1, 2):
4588                 case IP_VERSION(3, 1, 3):
4589                 case IP_VERSION(3, 1, 4):
4590                 case IP_VERSION(3, 1, 5):
4591                 case IP_VERSION(3, 1, 6):
4592                 case IP_VERSION(3, 2, 0):
4593                 case IP_VERSION(3, 2, 1):
4594                 case IP_VERSION(3, 5, 0):
4595                         if (dcn10_register_irq_handlers(dm->adev)) {
4596                                 DRM_ERROR("DM: Failed to initialize IRQ\n");
4597                                 goto fail;
4598                         }
4599                         break;
4600                 default:
4601                         DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
4602                                         amdgpu_ip_version(adev, DCE_HWIP, 0));
4603                         goto fail;
4604                 }
4605                 break;
4606         }
4607
4608         return 0;
4609 fail:
4610         kfree(aencoder);
4611         kfree(aconnector);
4612
4613         return -EINVAL;
4614 }
4615
4616 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4617 {
4618         drm_atomic_private_obj_fini(&dm->atomic_obj);
4619 }
4620
4621 /******************************************************************************
4622  * amdgpu_display_funcs functions
4623  *****************************************************************************/
4624
4625 /*
4626  * dm_bandwidth_update - program display watermarks
4627  *
4628  * @adev: amdgpu_device pointer
4629  *
4630  * Calculate and program the display watermarks and line buffer allocation.
4631  */
4632 static void dm_bandwidth_update(struct amdgpu_device *adev)
4633 {
4634         /* TODO: implement later */
4635 }
4636
4637 static const struct amdgpu_display_funcs dm_display_funcs = {
4638         .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
4639         .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
4640         .backlight_set_level = NULL, /* never called for DC */
4641         .backlight_get_level = NULL, /* never called for DC */
4642         .hpd_sense = NULL,/* called unconditionally */
4643         .hpd_set_polarity = NULL, /* called unconditionally */
4644         .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4645         .page_flip_get_scanoutpos =
4646                 dm_crtc_get_scanoutpos,/* called unconditionally */
4647         .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
4648         .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4649 };
4650
4651 #if defined(CONFIG_DEBUG_KERNEL_DC)
4652
4653 static ssize_t s3_debug_store(struct device *device,
4654                               struct device_attribute *attr,
4655                               const char *buf,
4656                               size_t count)
4657 {
4658         int ret;
4659         int s3_state;
4660         struct drm_device *drm_dev = dev_get_drvdata(device);
4661         struct amdgpu_device *adev = drm_to_adev(drm_dev);
4662
4663         ret = kstrtoint(buf, 0, &s3_state);
4664
4665         if (ret == 0) {
4666                 if (s3_state) {
4667                         dm_resume(adev);
4668                         drm_kms_helper_hotplug_event(adev_to_drm(adev));
4669                 } else
4670                         dm_suspend(adev);
4671         }
4672
4673         return ret == 0 ? count : 0;
4674 }
4675
4676 DEVICE_ATTR_WO(s3_debug);
4677
4678 #endif
4679
4680 static int dm_init_microcode(struct amdgpu_device *adev)
4681 {
4682         char *fw_name_dmub;
4683         int r;
4684
4685         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4686         case IP_VERSION(2, 1, 0):
4687                 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
4688                 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
4689                         fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
4690                 break;
4691         case IP_VERSION(3, 0, 0):
4692                 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0))
4693                         fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
4694                 else
4695                         fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
4696                 break;
4697         case IP_VERSION(3, 0, 1):
4698                 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
4699                 break;
4700         case IP_VERSION(3, 0, 2):
4701                 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
4702                 break;
4703         case IP_VERSION(3, 0, 3):
4704                 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
4705                 break;
4706         case IP_VERSION(3, 1, 2):
4707         case IP_VERSION(3, 1, 3):
4708                 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
4709                 break;
4710         case IP_VERSION(3, 1, 4):
4711                 fw_name_dmub = FIRMWARE_DCN_314_DMUB;
4712                 break;
4713         case IP_VERSION(3, 1, 5):
4714                 fw_name_dmub = FIRMWARE_DCN_315_DMUB;
4715                 break;
4716         case IP_VERSION(3, 1, 6):
4717                 fw_name_dmub = FIRMWARE_DCN316_DMUB;
4718                 break;
4719         case IP_VERSION(3, 2, 0):
4720                 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
4721                 break;
4722         case IP_VERSION(3, 2, 1):
4723                 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
4724                 break;
4725         case IP_VERSION(3, 5, 0):
4726                 fw_name_dmub = FIRMWARE_DCN_35_DMUB;
4727                 break;
4728         default:
4729                 /* ASIC doesn't support DMUB. */
4730                 return 0;
4731         }
4732         r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub);
4733         return r;
4734 }
4735
4736 static int dm_early_init(void *handle)
4737 {
4738         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4739         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4740         struct atom_context *ctx = mode_info->atom_context;
4741         int index = GetIndexIntoMasterTable(DATA, Object_Header);
4742         u16 data_offset;
4743
4744         /* if there is no object header, skip DM */
4745         if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
4746                 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
4747                 dev_info(adev->dev, "No object header, skipping DM\n");
4748                 return -ENOENT;
4749         }
4750
4751         switch (adev->asic_type) {
4752 #if defined(CONFIG_DRM_AMD_DC_SI)
4753         case CHIP_TAHITI:
4754         case CHIP_PITCAIRN:
4755         case CHIP_VERDE:
4756                 adev->mode_info.num_crtc = 6;
4757                 adev->mode_info.num_hpd = 6;
4758                 adev->mode_info.num_dig = 6;
4759                 break;
4760         case CHIP_OLAND:
4761                 adev->mode_info.num_crtc = 2;
4762                 adev->mode_info.num_hpd = 2;
4763                 adev->mode_info.num_dig = 2;
4764                 break;
4765 #endif
4766         case CHIP_BONAIRE:
4767         case CHIP_HAWAII:
4768                 adev->mode_info.num_crtc = 6;
4769                 adev->mode_info.num_hpd = 6;
4770                 adev->mode_info.num_dig = 6;
4771                 break;
4772         case CHIP_KAVERI:
4773                 adev->mode_info.num_crtc = 4;
4774                 adev->mode_info.num_hpd = 6;
4775                 adev->mode_info.num_dig = 7;
4776                 break;
4777         case CHIP_KABINI:
4778         case CHIP_MULLINS:
4779                 adev->mode_info.num_crtc = 2;
4780                 adev->mode_info.num_hpd = 6;
4781                 adev->mode_info.num_dig = 6;
4782                 break;
4783         case CHIP_FIJI:
4784         case CHIP_TONGA:
4785                 adev->mode_info.num_crtc = 6;
4786                 adev->mode_info.num_hpd = 6;
4787                 adev->mode_info.num_dig = 7;
4788                 break;
4789         case CHIP_CARRIZO:
4790                 adev->mode_info.num_crtc = 3;
4791                 adev->mode_info.num_hpd = 6;
4792                 adev->mode_info.num_dig = 9;
4793                 break;
4794         case CHIP_STONEY:
4795                 adev->mode_info.num_crtc = 2;
4796                 adev->mode_info.num_hpd = 6;
4797                 adev->mode_info.num_dig = 9;
4798                 break;
4799         case CHIP_POLARIS11:
4800         case CHIP_POLARIS12:
4801                 adev->mode_info.num_crtc = 5;
4802                 adev->mode_info.num_hpd = 5;
4803                 adev->mode_info.num_dig = 5;
4804                 break;
4805         case CHIP_POLARIS10:
4806         case CHIP_VEGAM:
4807                 adev->mode_info.num_crtc = 6;
4808                 adev->mode_info.num_hpd = 6;
4809                 adev->mode_info.num_dig = 6;
4810                 break;
4811         case CHIP_VEGA10:
4812         case CHIP_VEGA12:
4813         case CHIP_VEGA20:
4814                 adev->mode_info.num_crtc = 6;
4815                 adev->mode_info.num_hpd = 6;
4816                 adev->mode_info.num_dig = 6;
4817                 break;
4818         default:
4819
4820                 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4821                 case IP_VERSION(2, 0, 2):
4822                 case IP_VERSION(3, 0, 0):
4823                         adev->mode_info.num_crtc = 6;
4824                         adev->mode_info.num_hpd = 6;
4825                         adev->mode_info.num_dig = 6;
4826                         break;
4827                 case IP_VERSION(2, 0, 0):
4828                 case IP_VERSION(3, 0, 2):
4829                         adev->mode_info.num_crtc = 5;
4830                         adev->mode_info.num_hpd = 5;
4831                         adev->mode_info.num_dig = 5;
4832                         break;
4833                 case IP_VERSION(2, 0, 3):
4834                 case IP_VERSION(3, 0, 3):
4835                         adev->mode_info.num_crtc = 2;
4836                         adev->mode_info.num_hpd = 2;
4837                         adev->mode_info.num_dig = 2;
4838                         break;
4839                 case IP_VERSION(1, 0, 0):
4840                 case IP_VERSION(1, 0, 1):
4841                 case IP_VERSION(3, 0, 1):
4842                 case IP_VERSION(2, 1, 0):
4843                 case IP_VERSION(3, 1, 2):
4844                 case IP_VERSION(3, 1, 3):
4845                 case IP_VERSION(3, 1, 4):
4846                 case IP_VERSION(3, 1, 5):
4847                 case IP_VERSION(3, 1, 6):
4848                 case IP_VERSION(3, 2, 0):
4849                 case IP_VERSION(3, 2, 1):
4850                 case IP_VERSION(3, 5, 0):
4851                         adev->mode_info.num_crtc = 4;
4852                         adev->mode_info.num_hpd = 4;
4853                         adev->mode_info.num_dig = 4;
4854                         break;
4855                 default:
4856                         DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
4857                                         amdgpu_ip_version(adev, DCE_HWIP, 0));
4858                         return -EINVAL;
4859                 }
4860                 break;
4861         }
4862
4863         if (adev->mode_info.funcs == NULL)
4864                 adev->mode_info.funcs = &dm_display_funcs;
4865
4866         /*
4867          * Note: Do NOT change adev->audio_endpt_rreg and
4868          * adev->audio_endpt_wreg because they are initialised in
4869          * amdgpu_device_init()
4870          */
4871 #if defined(CONFIG_DEBUG_KERNEL_DC)
4872         device_create_file(
4873                 adev_to_drm(adev)->dev,
4874                 &dev_attr_s3_debug);
4875 #endif
4876         adev->dc_enabled = true;
4877
4878         return dm_init_microcode(adev);
4879 }
4880
4881 static bool modereset_required(struct drm_crtc_state *crtc_state)
4882 {
4883         return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
4884 }
4885
4886 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
4887 {
4888         drm_encoder_cleanup(encoder);
4889         kfree(encoder);
4890 }
4891
4892 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
4893         .destroy = amdgpu_dm_encoder_destroy,
4894 };
4895
4896 static int
4897 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
4898                             const enum surface_pixel_format format,
4899                             enum dc_color_space *color_space)
4900 {
4901         bool full_range;
4902
4903         *color_space = COLOR_SPACE_SRGB;
4904
4905         /* DRM color properties only affect non-RGB formats. */
4906         if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
4907                 return 0;
4908
4909         full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4910
4911         switch (plane_state->color_encoding) {
4912         case DRM_COLOR_YCBCR_BT601:
4913                 if (full_range)
4914                         *color_space = COLOR_SPACE_YCBCR601;
4915                 else
4916                         *color_space = COLOR_SPACE_YCBCR601_LIMITED;
4917                 break;
4918
4919         case DRM_COLOR_YCBCR_BT709:
4920                 if (full_range)
4921                         *color_space = COLOR_SPACE_YCBCR709;
4922                 else
4923                         *color_space = COLOR_SPACE_YCBCR709_LIMITED;
4924                 break;
4925
4926         case DRM_COLOR_YCBCR_BT2020:
4927                 if (full_range)
4928                         *color_space = COLOR_SPACE_2020_YCBCR;
4929                 else
4930                         return -EINVAL;
4931                 break;
4932
4933         default:
4934                 return -EINVAL;
4935         }
4936
4937         return 0;
4938 }
4939
4940 static int
4941 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
4942                             const struct drm_plane_state *plane_state,
4943                             const u64 tiling_flags,
4944                             struct dc_plane_info *plane_info,
4945                             struct dc_plane_address *address,
4946                             bool tmz_surface,
4947                             bool force_disable_dcc)
4948 {
4949         const struct drm_framebuffer *fb = plane_state->fb;
4950         const struct amdgpu_framebuffer *afb =
4951                 to_amdgpu_framebuffer(plane_state->fb);
4952         int ret;
4953
4954         memset(plane_info, 0, sizeof(*plane_info));
4955
4956         switch (fb->format->format) {
4957         case DRM_FORMAT_C8:
4958                 plane_info->format =
4959                         SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
4960                 break;
4961         case DRM_FORMAT_RGB565:
4962                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
4963                 break;
4964         case DRM_FORMAT_XRGB8888:
4965         case DRM_FORMAT_ARGB8888:
4966                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
4967                 break;
4968         case DRM_FORMAT_XRGB2101010:
4969         case DRM_FORMAT_ARGB2101010:
4970                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
4971                 break;
4972         case DRM_FORMAT_XBGR2101010:
4973         case DRM_FORMAT_ABGR2101010:
4974                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
4975                 break;
4976         case DRM_FORMAT_XBGR8888:
4977         case DRM_FORMAT_ABGR8888:
4978                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
4979                 break;
4980         case DRM_FORMAT_NV21:
4981                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
4982                 break;
4983         case DRM_FORMAT_NV12:
4984                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
4985                 break;
4986         case DRM_FORMAT_P010:
4987                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
4988                 break;
4989         case DRM_FORMAT_XRGB16161616F:
4990         case DRM_FORMAT_ARGB16161616F:
4991                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
4992                 break;
4993         case DRM_FORMAT_XBGR16161616F:
4994         case DRM_FORMAT_ABGR16161616F:
4995                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
4996                 break;
4997         case DRM_FORMAT_XRGB16161616:
4998         case DRM_FORMAT_ARGB16161616:
4999                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
5000                 break;
5001         case DRM_FORMAT_XBGR16161616:
5002         case DRM_FORMAT_ABGR16161616:
5003                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
5004                 break;
5005         default:
5006                 DRM_ERROR(
5007                         "Unsupported screen format %p4cc\n",
5008                         &fb->format->format);
5009                 return -EINVAL;
5010         }
5011
5012         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
5013         case DRM_MODE_ROTATE_0:
5014                 plane_info->rotation = ROTATION_ANGLE_0;
5015                 break;
5016         case DRM_MODE_ROTATE_90:
5017                 plane_info->rotation = ROTATION_ANGLE_90;
5018                 break;
5019         case DRM_MODE_ROTATE_180:
5020                 plane_info->rotation = ROTATION_ANGLE_180;
5021                 break;
5022         case DRM_MODE_ROTATE_270:
5023                 plane_info->rotation = ROTATION_ANGLE_270;
5024                 break;
5025         default:
5026                 plane_info->rotation = ROTATION_ANGLE_0;
5027                 break;
5028         }
5029
5030
5031         plane_info->visible = true;
5032         plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
5033
5034         plane_info->layer_index = plane_state->normalized_zpos;
5035
5036         ret = fill_plane_color_attributes(plane_state, plane_info->format,
5037                                           &plane_info->color_space);
5038         if (ret)
5039                 return ret;
5040
5041         ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format,
5042                                            plane_info->rotation, tiling_flags,
5043                                            &plane_info->tiling_info,
5044                                            &plane_info->plane_size,
5045                                            &plane_info->dcc, address,
5046                                            tmz_surface, force_disable_dcc);
5047         if (ret)
5048                 return ret;
5049
5050         amdgpu_dm_plane_fill_blending_from_plane_state(
5051                 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,
5052                 &plane_info->global_alpha, &plane_info->global_alpha_value);
5053
5054         return 0;
5055 }
5056
5057 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
5058                                     struct dc_plane_state *dc_plane_state,
5059                                     struct drm_plane_state *plane_state,
5060                                     struct drm_crtc_state *crtc_state)
5061 {
5062         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5063         struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
5064         struct dc_scaling_info scaling_info;
5065         struct dc_plane_info plane_info;
5066         int ret;
5067         bool force_disable_dcc = false;
5068
5069         ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info);
5070         if (ret)
5071                 return ret;
5072
5073         dc_plane_state->src_rect = scaling_info.src_rect;
5074         dc_plane_state->dst_rect = scaling_info.dst_rect;
5075         dc_plane_state->clip_rect = scaling_info.clip_rect;
5076         dc_plane_state->scaling_quality = scaling_info.scaling_quality;
5077
5078         force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
5079         ret = fill_dc_plane_info_and_addr(adev, plane_state,
5080                                           afb->tiling_flags,
5081                                           &plane_info,
5082                                           &dc_plane_state->address,
5083                                           afb->tmz_surface,
5084                                           force_disable_dcc);
5085         if (ret)
5086                 return ret;
5087
5088         dc_plane_state->format = plane_info.format;
5089         dc_plane_state->color_space = plane_info.color_space;
5090         dc_plane_state->format = plane_info.format;
5091         dc_plane_state->plane_size = plane_info.plane_size;
5092         dc_plane_state->rotation = plane_info.rotation;
5093         dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
5094         dc_plane_state->stereo_format = plane_info.stereo_format;
5095         dc_plane_state->tiling_info = plane_info.tiling_info;
5096         dc_plane_state->visible = plane_info.visible;
5097         dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
5098         dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;
5099         dc_plane_state->global_alpha = plane_info.global_alpha;
5100         dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
5101         dc_plane_state->dcc = plane_info.dcc;
5102         dc_plane_state->layer_index = plane_info.layer_index;
5103         dc_plane_state->flip_int_enabled = true;
5104
5105         /*
5106          * Always set input transfer function, since plane state is refreshed
5107          * every time.
5108          */
5109         ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
5110         if (ret)
5111                 return ret;
5112
5113         return 0;
5114 }
5115
5116 static inline void fill_dc_dirty_rect(struct drm_plane *plane,
5117                                       struct rect *dirty_rect, int32_t x,
5118                                       s32 y, s32 width, s32 height,
5119                                       int *i, bool ffu)
5120 {
5121         WARN_ON(*i >= DC_MAX_DIRTY_RECTS);
5122
5123         dirty_rect->x = x;
5124         dirty_rect->y = y;
5125         dirty_rect->width = width;
5126         dirty_rect->height = height;
5127
5128         if (ffu)
5129                 drm_dbg(plane->dev,
5130                         "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
5131                         plane->base.id, width, height);
5132         else
5133                 drm_dbg(plane->dev,
5134                         "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)",
5135                         plane->base.id, x, y, width, height);
5136
5137         (*i)++;
5138 }
5139
5140 /**
5141  * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
5142  *
5143  * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
5144  *         remote fb
5145  * @old_plane_state: Old state of @plane
5146  * @new_plane_state: New state of @plane
5147  * @crtc_state: New state of CRTC connected to the @plane
5148  * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
5149  * @dirty_regions_changed: dirty regions changed
5150  *
5151  * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
5152  * (referred to as "damage clips" in DRM nomenclature) that require updating on
5153  * the eDP remote buffer. The responsibility of specifying the dirty regions is
5154  * amdgpu_dm's.
5155  *
5156  * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
5157  * plane with regions that require flushing to the eDP remote buffer. In
5158  * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
5159  * implicitly provide damage clips without any client support via the plane
5160  * bounds.
5161  */
5162 static void fill_dc_dirty_rects(struct drm_plane *plane,
5163                                 struct drm_plane_state *old_plane_state,
5164                                 struct drm_plane_state *new_plane_state,
5165                                 struct drm_crtc_state *crtc_state,
5166                                 struct dc_flip_addrs *flip_addrs,
5167                                 bool *dirty_regions_changed)
5168 {
5169         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5170         struct rect *dirty_rects = flip_addrs->dirty_rects;
5171         u32 num_clips;
5172         struct drm_mode_rect *clips;
5173         bool bb_changed;
5174         bool fb_changed;
5175         u32 i = 0;
5176         *dirty_regions_changed = false;
5177
5178         /*
5179          * Cursor plane has it's own dirty rect update interface. See
5180          * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
5181          */
5182         if (plane->type == DRM_PLANE_TYPE_CURSOR)
5183                 return;
5184
5185         num_clips = drm_plane_get_damage_clips_count(new_plane_state);
5186         clips = drm_plane_get_damage_clips(new_plane_state);
5187
5188         if (!dm_crtc_state->mpo_requested) {
5189                 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS)
5190                         goto ffu;
5191
5192                 for (; flip_addrs->dirty_rect_count < num_clips; clips++)
5193                         fill_dc_dirty_rect(new_plane_state->plane,
5194                                            &dirty_rects[flip_addrs->dirty_rect_count],
5195                                            clips->x1, clips->y1,
5196                                            clips->x2 - clips->x1, clips->y2 - clips->y1,
5197                                            &flip_addrs->dirty_rect_count,
5198                                            false);
5199                 return;
5200         }
5201
5202         /*
5203          * MPO is requested. Add entire plane bounding box to dirty rects if
5204          * flipped to or damaged.
5205          *
5206          * If plane is moved or resized, also add old bounding box to dirty
5207          * rects.
5208          */
5209         fb_changed = old_plane_state->fb->base.id !=
5210                      new_plane_state->fb->base.id;
5211         bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
5212                       old_plane_state->crtc_y != new_plane_state->crtc_y ||
5213                       old_plane_state->crtc_w != new_plane_state->crtc_w ||
5214                       old_plane_state->crtc_h != new_plane_state->crtc_h);
5215
5216         drm_dbg(plane->dev,
5217                 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
5218                 new_plane_state->plane->base.id,
5219                 bb_changed, fb_changed, num_clips);
5220
5221         *dirty_regions_changed = bb_changed;
5222
5223         if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS)
5224                 goto ffu;
5225
5226         if (bb_changed) {
5227                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5228                                    new_plane_state->crtc_x,
5229                                    new_plane_state->crtc_y,
5230                                    new_plane_state->crtc_w,
5231                                    new_plane_state->crtc_h, &i, false);
5232
5233                 /* Add old plane bounding-box if plane is moved or resized */
5234                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5235                                    old_plane_state->crtc_x,
5236                                    old_plane_state->crtc_y,
5237                                    old_plane_state->crtc_w,
5238                                    old_plane_state->crtc_h, &i, false);
5239         }
5240
5241         if (num_clips) {
5242                 for (; i < num_clips; clips++)
5243                         fill_dc_dirty_rect(new_plane_state->plane,
5244                                            &dirty_rects[i], clips->x1,
5245                                            clips->y1, clips->x2 - clips->x1,
5246                                            clips->y2 - clips->y1, &i, false);
5247         } else if (fb_changed && !bb_changed) {
5248                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5249                                    new_plane_state->crtc_x,
5250                                    new_plane_state->crtc_y,
5251                                    new_plane_state->crtc_w,
5252                                    new_plane_state->crtc_h, &i, false);
5253         }
5254
5255         flip_addrs->dirty_rect_count = i;
5256         return;
5257
5258 ffu:
5259         fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0,
5260                            dm_crtc_state->base.mode.crtc_hdisplay,
5261                            dm_crtc_state->base.mode.crtc_vdisplay,
5262                            &flip_addrs->dirty_rect_count, true);
5263 }
5264
5265 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
5266                                            const struct dm_connector_state *dm_state,
5267                                            struct dc_stream_state *stream)
5268 {
5269         enum amdgpu_rmx_type rmx_type;
5270
5271         struct rect src = { 0 }; /* viewport in composition space*/
5272         struct rect dst = { 0 }; /* stream addressable area */
5273
5274         /* no mode. nothing to be done */
5275         if (!mode)
5276                 return;
5277
5278         /* Full screen scaling by default */
5279         src.width = mode->hdisplay;
5280         src.height = mode->vdisplay;
5281         dst.width = stream->timing.h_addressable;
5282         dst.height = stream->timing.v_addressable;
5283
5284         if (dm_state) {
5285                 rmx_type = dm_state->scaling;
5286                 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
5287                         if (src.width * dst.height <
5288                                         src.height * dst.width) {
5289                                 /* height needs less upscaling/more downscaling */
5290                                 dst.width = src.width *
5291                                                 dst.height / src.height;
5292                         } else {
5293                                 /* width needs less upscaling/more downscaling */
5294                                 dst.height = src.height *
5295                                                 dst.width / src.width;
5296                         }
5297                 } else if (rmx_type == RMX_CENTER) {
5298                         dst = src;
5299                 }
5300
5301                 dst.x = (stream->timing.h_addressable - dst.width) / 2;
5302                 dst.y = (stream->timing.v_addressable - dst.height) / 2;
5303
5304                 if (dm_state->underscan_enable) {
5305                         dst.x += dm_state->underscan_hborder / 2;
5306                         dst.y += dm_state->underscan_vborder / 2;
5307                         dst.width -= dm_state->underscan_hborder;
5308                         dst.height -= dm_state->underscan_vborder;
5309                 }
5310         }
5311
5312         stream->src = src;
5313         stream->dst = dst;
5314
5315         DRM_DEBUG_KMS("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
5316                       dst.x, dst.y, dst.width, dst.height);
5317
5318 }
5319
5320 static enum dc_color_depth
5321 convert_color_depth_from_display_info(const struct drm_connector *connector,
5322                                       bool is_y420, int requested_bpc)
5323 {
5324         u8 bpc;
5325
5326         if (is_y420) {
5327                 bpc = 8;
5328
5329                 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
5330                 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
5331                         bpc = 16;
5332                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
5333                         bpc = 12;
5334                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
5335                         bpc = 10;
5336         } else {
5337                 bpc = (uint8_t)connector->display_info.bpc;
5338                 /* Assume 8 bpc by default if no bpc is specified. */
5339                 bpc = bpc ? bpc : 8;
5340         }
5341
5342         if (requested_bpc > 0) {
5343                 /*
5344                  * Cap display bpc based on the user requested value.
5345                  *
5346                  * The value for state->max_bpc may not correctly updated
5347                  * depending on when the connector gets added to the state
5348                  * or if this was called outside of atomic check, so it
5349                  * can't be used directly.
5350                  */
5351                 bpc = min_t(u8, bpc, requested_bpc);
5352
5353                 /* Round down to the nearest even number. */
5354                 bpc = bpc - (bpc & 1);
5355         }
5356
5357         switch (bpc) {
5358         case 0:
5359                 /*
5360                  * Temporary Work around, DRM doesn't parse color depth for
5361                  * EDID revision before 1.4
5362                  * TODO: Fix edid parsing
5363                  */
5364                 return COLOR_DEPTH_888;
5365         case 6:
5366                 return COLOR_DEPTH_666;
5367         case 8:
5368                 return COLOR_DEPTH_888;
5369         case 10:
5370                 return COLOR_DEPTH_101010;
5371         case 12:
5372                 return COLOR_DEPTH_121212;
5373         case 14:
5374                 return COLOR_DEPTH_141414;
5375         case 16:
5376                 return COLOR_DEPTH_161616;
5377         default:
5378                 return COLOR_DEPTH_UNDEFINED;
5379         }
5380 }
5381
5382 static enum dc_aspect_ratio
5383 get_aspect_ratio(const struct drm_display_mode *mode_in)
5384 {
5385         /* 1-1 mapping, since both enums follow the HDMI spec. */
5386         return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
5387 }
5388
5389 static enum dc_color_space
5390 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing,
5391                        const struct drm_connector_state *connector_state)
5392 {
5393         enum dc_color_space color_space = COLOR_SPACE_SRGB;
5394
5395         switch (connector_state->colorspace) {
5396         case DRM_MODE_COLORIMETRY_BT601_YCC:
5397                 if (dc_crtc_timing->flags.Y_ONLY)
5398                         color_space = COLOR_SPACE_YCBCR601_LIMITED;
5399                 else
5400                         color_space = COLOR_SPACE_YCBCR601;
5401                 break;
5402         case DRM_MODE_COLORIMETRY_BT709_YCC:
5403                 if (dc_crtc_timing->flags.Y_ONLY)
5404                         color_space = COLOR_SPACE_YCBCR709_LIMITED;
5405                 else
5406                         color_space = COLOR_SPACE_YCBCR709;
5407                 break;
5408         case DRM_MODE_COLORIMETRY_OPRGB:
5409                 color_space = COLOR_SPACE_ADOBERGB;
5410                 break;
5411         case DRM_MODE_COLORIMETRY_BT2020_RGB:
5412         case DRM_MODE_COLORIMETRY_BT2020_YCC:
5413                 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
5414                         color_space = COLOR_SPACE_2020_RGB_FULLRANGE;
5415                 else
5416                         color_space = COLOR_SPACE_2020_YCBCR;
5417                 break;
5418         case DRM_MODE_COLORIMETRY_DEFAULT: // ITU601
5419         default:
5420                 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) {
5421                         color_space = COLOR_SPACE_SRGB;
5422                 /*
5423                  * 27030khz is the separation point between HDTV and SDTV
5424                  * according to HDMI spec, we use YCbCr709 and YCbCr601
5425                  * respectively
5426                  */
5427                 } else if (dc_crtc_timing->pix_clk_100hz > 270300) {
5428                         if (dc_crtc_timing->flags.Y_ONLY)
5429                                 color_space =
5430                                         COLOR_SPACE_YCBCR709_LIMITED;
5431                         else
5432                                 color_space = COLOR_SPACE_YCBCR709;
5433                 } else {
5434                         if (dc_crtc_timing->flags.Y_ONLY)
5435                                 color_space =
5436                                         COLOR_SPACE_YCBCR601_LIMITED;
5437                         else
5438                                 color_space = COLOR_SPACE_YCBCR601;
5439                 }
5440                 break;
5441         }
5442
5443         return color_space;
5444 }
5445
5446 static enum display_content_type
5447 get_output_content_type(const struct drm_connector_state *connector_state)
5448 {
5449         switch (connector_state->content_type) {
5450         default:
5451         case DRM_MODE_CONTENT_TYPE_NO_DATA:
5452                 return DISPLAY_CONTENT_TYPE_NO_DATA;
5453         case DRM_MODE_CONTENT_TYPE_GRAPHICS:
5454                 return DISPLAY_CONTENT_TYPE_GRAPHICS;
5455         case DRM_MODE_CONTENT_TYPE_PHOTO:
5456                 return DISPLAY_CONTENT_TYPE_PHOTO;
5457         case DRM_MODE_CONTENT_TYPE_CINEMA:
5458                 return DISPLAY_CONTENT_TYPE_CINEMA;
5459         case DRM_MODE_CONTENT_TYPE_GAME:
5460                 return DISPLAY_CONTENT_TYPE_GAME;
5461         }
5462 }
5463
5464 static bool adjust_colour_depth_from_display_info(
5465         struct dc_crtc_timing *timing_out,
5466         const struct drm_display_info *info)
5467 {
5468         enum dc_color_depth depth = timing_out->display_color_depth;
5469         int normalized_clk;
5470
5471         do {
5472                 normalized_clk = timing_out->pix_clk_100hz / 10;
5473                 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
5474                 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
5475                         normalized_clk /= 2;
5476                 /* Adjusting pix clock following on HDMI spec based on colour depth */
5477                 switch (depth) {
5478                 case COLOR_DEPTH_888:
5479                         break;
5480                 case COLOR_DEPTH_101010:
5481                         normalized_clk = (normalized_clk * 30) / 24;
5482                         break;
5483                 case COLOR_DEPTH_121212:
5484                         normalized_clk = (normalized_clk * 36) / 24;
5485                         break;
5486                 case COLOR_DEPTH_161616:
5487                         normalized_clk = (normalized_clk * 48) / 24;
5488                         break;
5489                 default:
5490                         /* The above depths are the only ones valid for HDMI. */
5491                         return false;
5492                 }
5493                 if (normalized_clk <= info->max_tmds_clock) {
5494                         timing_out->display_color_depth = depth;
5495                         return true;
5496                 }
5497         } while (--depth > COLOR_DEPTH_666);
5498         return false;
5499 }
5500
5501 static void fill_stream_properties_from_drm_display_mode(
5502         struct dc_stream_state *stream,
5503         const struct drm_display_mode *mode_in,
5504         const struct drm_connector *connector,
5505         const struct drm_connector_state *connector_state,
5506         const struct dc_stream_state *old_stream,
5507         int requested_bpc)
5508 {
5509         struct dc_crtc_timing *timing_out = &stream->timing;
5510         const struct drm_display_info *info = &connector->display_info;
5511         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5512         struct hdmi_vendor_infoframe hv_frame;
5513         struct hdmi_avi_infoframe avi_frame;
5514
5515         memset(&hv_frame, 0, sizeof(hv_frame));
5516         memset(&avi_frame, 0, sizeof(avi_frame));
5517
5518         timing_out->h_border_left = 0;
5519         timing_out->h_border_right = 0;
5520         timing_out->v_border_top = 0;
5521         timing_out->v_border_bottom = 0;
5522         /* TODO: un-hardcode */
5523         if (drm_mode_is_420_only(info, mode_in)
5524                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5525                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5526         else if (drm_mode_is_420_also(info, mode_in)
5527                         && aconnector->force_yuv420_output)
5528                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5529         else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444)
5530                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5531                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
5532         else
5533                 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
5534
5535         timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
5536         timing_out->display_color_depth = convert_color_depth_from_display_info(
5537                 connector,
5538                 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
5539                 requested_bpc);
5540         timing_out->scan_type = SCANNING_TYPE_NODATA;
5541         timing_out->hdmi_vic = 0;
5542
5543         if (old_stream) {
5544                 timing_out->vic = old_stream->timing.vic;
5545                 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5546                 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5547         } else {
5548                 timing_out->vic = drm_match_cea_mode(mode_in);
5549                 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5550                         timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5551                 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5552                         timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5553         }
5554
5555         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5556                 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
5557                 timing_out->vic = avi_frame.video_code;
5558                 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
5559                 timing_out->hdmi_vic = hv_frame.vic;
5560         }
5561
5562         if (is_freesync_video_mode(mode_in, aconnector)) {
5563                 timing_out->h_addressable = mode_in->hdisplay;
5564                 timing_out->h_total = mode_in->htotal;
5565                 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
5566                 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
5567                 timing_out->v_total = mode_in->vtotal;
5568                 timing_out->v_addressable = mode_in->vdisplay;
5569                 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
5570                 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
5571                 timing_out->pix_clk_100hz = mode_in->clock * 10;
5572         } else {
5573                 timing_out->h_addressable = mode_in->crtc_hdisplay;
5574                 timing_out->h_total = mode_in->crtc_htotal;
5575                 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
5576                 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
5577                 timing_out->v_total = mode_in->crtc_vtotal;
5578                 timing_out->v_addressable = mode_in->crtc_vdisplay;
5579                 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
5580                 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
5581                 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
5582         }
5583
5584         timing_out->aspect_ratio = get_aspect_ratio(mode_in);
5585
5586         stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5587         stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
5588         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5589                 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5590                     drm_mode_is_420_also(info, mode_in) &&
5591                     timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5592                         timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5593                         adjust_colour_depth_from_display_info(timing_out, info);
5594                 }
5595         }
5596
5597         stream->output_color_space = get_output_color_space(timing_out, connector_state);
5598         stream->content_type = get_output_content_type(connector_state);
5599 }
5600
5601 static void fill_audio_info(struct audio_info *audio_info,
5602                             const struct drm_connector *drm_connector,
5603                             const struct dc_sink *dc_sink)
5604 {
5605         int i = 0;
5606         int cea_revision = 0;
5607         const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5608
5609         audio_info->manufacture_id = edid_caps->manufacturer_id;
5610         audio_info->product_id = edid_caps->product_id;
5611
5612         cea_revision = drm_connector->display_info.cea_rev;
5613
5614         strscpy(audio_info->display_name,
5615                 edid_caps->display_name,
5616                 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
5617
5618         if (cea_revision >= 3) {
5619                 audio_info->mode_count = edid_caps->audio_mode_count;
5620
5621                 for (i = 0; i < audio_info->mode_count; ++i) {
5622                         audio_info->modes[i].format_code =
5623                                         (enum audio_format_code)
5624                                         (edid_caps->audio_modes[i].format_code);
5625                         audio_info->modes[i].channel_count =
5626                                         edid_caps->audio_modes[i].channel_count;
5627                         audio_info->modes[i].sample_rates.all =
5628                                         edid_caps->audio_modes[i].sample_rate;
5629                         audio_info->modes[i].sample_size =
5630                                         edid_caps->audio_modes[i].sample_size;
5631                 }
5632         }
5633
5634         audio_info->flags.all = edid_caps->speaker_flags;
5635
5636         /* TODO: We only check for the progressive mode, check for interlace mode too */
5637         if (drm_connector->latency_present[0]) {
5638                 audio_info->video_latency = drm_connector->video_latency[0];
5639                 audio_info->audio_latency = drm_connector->audio_latency[0];
5640         }
5641
5642         /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5643
5644 }
5645
5646 static void
5647 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5648                                       struct drm_display_mode *dst_mode)
5649 {
5650         dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5651         dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5652         dst_mode->crtc_clock = src_mode->crtc_clock;
5653         dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5654         dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
5655         dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
5656         dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5657         dst_mode->crtc_htotal = src_mode->crtc_htotal;
5658         dst_mode->crtc_hskew = src_mode->crtc_hskew;
5659         dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5660         dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5661         dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5662         dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5663         dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5664 }
5665
5666 static void
5667 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5668                                         const struct drm_display_mode *native_mode,
5669                                         bool scale_enabled)
5670 {
5671         if (scale_enabled) {
5672                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5673         } else if (native_mode->clock == drm_mode->clock &&
5674                         native_mode->htotal == drm_mode->htotal &&
5675                         native_mode->vtotal == drm_mode->vtotal) {
5676                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5677         } else {
5678                 /* no scaling nor amdgpu inserted, no need to patch */
5679         }
5680 }
5681
5682 static struct dc_sink *
5683 create_fake_sink(struct amdgpu_dm_connector *aconnector)
5684 {
5685         struct dc_sink_init_data sink_init_data = { 0 };
5686         struct dc_sink *sink = NULL;
5687
5688         sink_init_data.link = aconnector->dc_link;
5689         sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
5690
5691         sink = dc_sink_create(&sink_init_data);
5692         if (!sink) {
5693                 DRM_ERROR("Failed to create sink!\n");
5694                 return NULL;
5695         }
5696         sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
5697
5698         return sink;
5699 }
5700
5701 static void set_multisync_trigger_params(
5702                 struct dc_stream_state *stream)
5703 {
5704         struct dc_stream_state *master = NULL;
5705
5706         if (stream->triggered_crtc_reset.enabled) {
5707                 master = stream->triggered_crtc_reset.event_source;
5708                 stream->triggered_crtc_reset.event =
5709                         master->timing.flags.VSYNC_POSITIVE_POLARITY ?
5710                         CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
5711                 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
5712         }
5713 }
5714
5715 static void set_master_stream(struct dc_stream_state *stream_set[],
5716                               int stream_count)
5717 {
5718         int j, highest_rfr = 0, master_stream = 0;
5719
5720         for (j = 0;  j < stream_count; j++) {
5721                 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5722                         int refresh_rate = 0;
5723
5724                         refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
5725                                 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5726                         if (refresh_rate > highest_rfr) {
5727                                 highest_rfr = refresh_rate;
5728                                 master_stream = j;
5729                         }
5730                 }
5731         }
5732         for (j = 0;  j < stream_count; j++) {
5733                 if (stream_set[j])
5734                         stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5735         }
5736 }
5737
5738 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5739 {
5740         int i = 0;
5741         struct dc_stream_state *stream;
5742
5743         if (context->stream_count < 2)
5744                 return;
5745         for (i = 0; i < context->stream_count ; i++) {
5746                 if (!context->streams[i])
5747                         continue;
5748                 /*
5749                  * TODO: add a function to read AMD VSDB bits and set
5750                  * crtc_sync_master.multi_sync_enabled flag
5751                  * For now it's set to false
5752                  */
5753         }
5754
5755         set_master_stream(context->streams, context->stream_count);
5756
5757         for (i = 0; i < context->stream_count ; i++) {
5758                 stream = context->streams[i];
5759
5760                 if (!stream)
5761                         continue;
5762
5763                 set_multisync_trigger_params(stream);
5764         }
5765 }
5766
5767 /**
5768  * DOC: FreeSync Video
5769  *
5770  * When a userspace application wants to play a video, the content follows a
5771  * standard format definition that usually specifies the FPS for that format.
5772  * The below list illustrates some video format and the expected FPS,
5773  * respectively:
5774  *
5775  * - TV/NTSC (23.976 FPS)
5776  * - Cinema (24 FPS)
5777  * - TV/PAL (25 FPS)
5778  * - TV/NTSC (29.97 FPS)
5779  * - TV/NTSC (30 FPS)
5780  * - Cinema HFR (48 FPS)
5781  * - TV/PAL (50 FPS)
5782  * - Commonly used (60 FPS)
5783  * - Multiples of 24 (48,72,96 FPS)
5784  *
5785  * The list of standards video format is not huge and can be added to the
5786  * connector modeset list beforehand. With that, userspace can leverage
5787  * FreeSync to extends the front porch in order to attain the target refresh
5788  * rate. Such a switch will happen seamlessly, without screen blanking or
5789  * reprogramming of the output in any other way. If the userspace requests a
5790  * modesetting change compatible with FreeSync modes that only differ in the
5791  * refresh rate, DC will skip the full update and avoid blink during the
5792  * transition. For example, the video player can change the modesetting from
5793  * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
5794  * causing any display blink. This same concept can be applied to a mode
5795  * setting change.
5796  */
5797 static struct drm_display_mode *
5798 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
5799                 bool use_probed_modes)
5800 {
5801         struct drm_display_mode *m, *m_pref = NULL;
5802         u16 current_refresh, highest_refresh;
5803         struct list_head *list_head = use_probed_modes ?
5804                 &aconnector->base.probed_modes :
5805                 &aconnector->base.modes;
5806
5807         if (aconnector->freesync_vid_base.clock != 0)
5808                 return &aconnector->freesync_vid_base;
5809
5810         /* Find the preferred mode */
5811         list_for_each_entry(m, list_head, head) {
5812                 if (m->type & DRM_MODE_TYPE_PREFERRED) {
5813                         m_pref = m;
5814                         break;
5815                 }
5816         }
5817
5818         if (!m_pref) {
5819                 /* Probably an EDID with no preferred mode. Fallback to first entry */
5820                 m_pref = list_first_entry_or_null(
5821                                 &aconnector->base.modes, struct drm_display_mode, head);
5822                 if (!m_pref) {
5823                         DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
5824                         return NULL;
5825                 }
5826         }
5827
5828         highest_refresh = drm_mode_vrefresh(m_pref);
5829
5830         /*
5831          * Find the mode with highest refresh rate with same resolution.
5832          * For some monitors, preferred mode is not the mode with highest
5833          * supported refresh rate.
5834          */
5835         list_for_each_entry(m, list_head, head) {
5836                 current_refresh  = drm_mode_vrefresh(m);
5837
5838                 if (m->hdisplay == m_pref->hdisplay &&
5839                     m->vdisplay == m_pref->vdisplay &&
5840                     highest_refresh < current_refresh) {
5841                         highest_refresh = current_refresh;
5842                         m_pref = m;
5843                 }
5844         }
5845
5846         drm_mode_copy(&aconnector->freesync_vid_base, m_pref);
5847         return m_pref;
5848 }
5849
5850 static bool is_freesync_video_mode(const struct drm_display_mode *mode,
5851                 struct amdgpu_dm_connector *aconnector)
5852 {
5853         struct drm_display_mode *high_mode;
5854         int timing_diff;
5855
5856         high_mode = get_highest_refresh_rate_mode(aconnector, false);
5857         if (!high_mode || !mode)
5858                 return false;
5859
5860         timing_diff = high_mode->vtotal - mode->vtotal;
5861
5862         if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
5863             high_mode->hdisplay != mode->hdisplay ||
5864             high_mode->vdisplay != mode->vdisplay ||
5865             high_mode->hsync_start != mode->hsync_start ||
5866             high_mode->hsync_end != mode->hsync_end ||
5867             high_mode->htotal != mode->htotal ||
5868             high_mode->hskew != mode->hskew ||
5869             high_mode->vscan != mode->vscan ||
5870             high_mode->vsync_start - mode->vsync_start != timing_diff ||
5871             high_mode->vsync_end - mode->vsync_end != timing_diff)
5872                 return false;
5873         else
5874                 return true;
5875 }
5876
5877 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
5878                             struct dc_sink *sink, struct dc_stream_state *stream,
5879                             struct dsc_dec_dpcd_caps *dsc_caps)
5880 {
5881         stream->timing.flags.DSC = 0;
5882         dsc_caps->is_dsc_supported = false;
5883
5884         if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
5885             sink->sink_signal == SIGNAL_TYPE_EDP)) {
5886                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
5887                         sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
5888                         dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5889                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5890                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5891                                 dsc_caps);
5892         }
5893 }
5894
5895
5896 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
5897                                     struct dc_sink *sink, struct dc_stream_state *stream,
5898                                     struct dsc_dec_dpcd_caps *dsc_caps,
5899                                     uint32_t max_dsc_target_bpp_limit_override)
5900 {
5901         const struct dc_link_settings *verified_link_cap = NULL;
5902         u32 link_bw_in_kbps;
5903         u32 edp_min_bpp_x16, edp_max_bpp_x16;
5904         struct dc *dc = sink->ctx->dc;
5905         struct dc_dsc_bw_range bw_range = {0};
5906         struct dc_dsc_config dsc_cfg = {0};
5907         struct dc_dsc_config_options dsc_options = {0};
5908
5909         dc_dsc_get_default_config_option(dc, &dsc_options);
5910         dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5911
5912         verified_link_cap = dc_link_get_link_cap(stream->link);
5913         link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
5914         edp_min_bpp_x16 = 8 * 16;
5915         edp_max_bpp_x16 = 8 * 16;
5916
5917         if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)
5918                 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;
5919
5920         if (edp_max_bpp_x16 < edp_min_bpp_x16)
5921                 edp_min_bpp_x16 = edp_max_bpp_x16;
5922
5923         if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
5924                                 dc->debug.dsc_min_slice_height_override,
5925                                 edp_min_bpp_x16, edp_max_bpp_x16,
5926                                 dsc_caps,
5927                                 &stream->timing,
5928                                 dc_link_get_highest_encoding_format(aconnector->dc_link),
5929                                 &bw_range)) {
5930
5931                 if (bw_range.max_kbps < link_bw_in_kbps) {
5932                         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5933                                         dsc_caps,
5934                                         &dsc_options,
5935                                         0,
5936                                         &stream->timing,
5937                                         dc_link_get_highest_encoding_format(aconnector->dc_link),
5938                                         &dsc_cfg)) {
5939                                 stream->timing.dsc_cfg = dsc_cfg;
5940                                 stream->timing.flags.DSC = 1;
5941                                 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
5942                         }
5943                         return;
5944                 }
5945         }
5946
5947         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5948                                 dsc_caps,
5949                                 &dsc_options,
5950                                 link_bw_in_kbps,
5951                                 &stream->timing,
5952                                 dc_link_get_highest_encoding_format(aconnector->dc_link),
5953                                 &dsc_cfg)) {
5954                 stream->timing.dsc_cfg = dsc_cfg;
5955                 stream->timing.flags.DSC = 1;
5956         }
5957 }
5958
5959
5960 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
5961                                         struct dc_sink *sink, struct dc_stream_state *stream,
5962                                         struct dsc_dec_dpcd_caps *dsc_caps)
5963 {
5964         struct drm_connector *drm_connector = &aconnector->base;
5965         u32 link_bandwidth_kbps;
5966         struct dc *dc = sink->ctx->dc;
5967         u32 max_supported_bw_in_kbps, timing_bw_in_kbps;
5968         u32 dsc_max_supported_bw_in_kbps;
5969         u32 max_dsc_target_bpp_limit_override =
5970                 drm_connector->display_info.max_dsc_bpp;
5971         struct dc_dsc_config_options dsc_options = {0};
5972
5973         dc_dsc_get_default_config_option(dc, &dsc_options);
5974         dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5975
5976         link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
5977                                                         dc_link_get_link_cap(aconnector->dc_link));
5978
5979         /* Set DSC policy according to dsc_clock_en */
5980         dc_dsc_policy_set_enable_dsc_when_not_needed(
5981                 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
5982
5983         if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
5984             !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
5985             dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
5986
5987                 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
5988
5989         } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
5990                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
5991                         if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5992                                                 dsc_caps,
5993                                                 &dsc_options,
5994                                                 link_bandwidth_kbps,
5995                                                 &stream->timing,
5996                                                 dc_link_get_highest_encoding_format(aconnector->dc_link),
5997                                                 &stream->timing.dsc_cfg)) {
5998                                 stream->timing.flags.DSC = 1;
5999                                 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name);
6000                         }
6001                 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
6002                         timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing,
6003                                         dc_link_get_highest_encoding_format(aconnector->dc_link));
6004                         max_supported_bw_in_kbps = link_bandwidth_kbps;
6005                         dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
6006
6007                         if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
6008                                         max_supported_bw_in_kbps > 0 &&
6009                                         dsc_max_supported_bw_in_kbps > 0)
6010                                 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
6011                                                 dsc_caps,
6012                                                 &dsc_options,
6013                                                 dsc_max_supported_bw_in_kbps,
6014                                                 &stream->timing,
6015                                                 dc_link_get_highest_encoding_format(aconnector->dc_link),
6016                                                 &stream->timing.dsc_cfg)) {
6017                                         stream->timing.flags.DSC = 1;
6018                                         DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",
6019                                                                          __func__, drm_connector->name);
6020                                 }
6021                 }
6022         }
6023
6024         /* Overwrite the stream flag if DSC is enabled through debugfs */
6025         if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
6026                 stream->timing.flags.DSC = 1;
6027
6028         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
6029                 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
6030
6031         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
6032                 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
6033
6034         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
6035                 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
6036 }
6037
6038 static struct dc_stream_state *
6039 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6040                        const struct drm_display_mode *drm_mode,
6041                        const struct dm_connector_state *dm_state,
6042                        const struct dc_stream_state *old_stream,
6043                        int requested_bpc)
6044 {
6045         struct drm_display_mode *preferred_mode = NULL;
6046         struct drm_connector *drm_connector;
6047         const struct drm_connector_state *con_state = &dm_state->base;
6048         struct dc_stream_state *stream = NULL;
6049         struct drm_display_mode mode;
6050         struct drm_display_mode saved_mode;
6051         struct drm_display_mode *freesync_mode = NULL;
6052         bool native_mode_found = false;
6053         bool recalculate_timing = false;
6054         bool scale = dm_state->scaling != RMX_OFF;
6055         int mode_refresh;
6056         int preferred_refresh = 0;
6057         enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;
6058         struct dsc_dec_dpcd_caps dsc_caps;
6059
6060         struct dc_sink *sink = NULL;
6061
6062         drm_mode_init(&mode, drm_mode);
6063         memset(&saved_mode, 0, sizeof(saved_mode));
6064
6065         if (aconnector == NULL) {
6066                 DRM_ERROR("aconnector is NULL!\n");
6067                 return stream;
6068         }
6069
6070         drm_connector = &aconnector->base;
6071
6072         if (!aconnector->dc_sink) {
6073                 sink = create_fake_sink(aconnector);
6074                 if (!sink)
6075                         return stream;
6076         } else {
6077                 sink = aconnector->dc_sink;
6078                 dc_sink_retain(sink);
6079         }
6080
6081         stream = dc_create_stream_for_sink(sink);
6082
6083         if (stream == NULL) {
6084                 DRM_ERROR("Failed to create stream for sink!\n");
6085                 goto finish;
6086         }
6087
6088         stream->dm_stream_context = aconnector;
6089
6090         stream->timing.flags.LTE_340MCSC_SCRAMBLE =
6091                 drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
6092
6093         list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
6094                 /* Search for preferred mode */
6095                 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
6096                         native_mode_found = true;
6097                         break;
6098                 }
6099         }
6100         if (!native_mode_found)
6101                 preferred_mode = list_first_entry_or_null(
6102                                 &aconnector->base.modes,
6103                                 struct drm_display_mode,
6104                                 head);
6105
6106         mode_refresh = drm_mode_vrefresh(&mode);
6107
6108         if (preferred_mode == NULL) {
6109                 /*
6110                  * This may not be an error, the use case is when we have no
6111                  * usermode calls to reset and set mode upon hotplug. In this
6112                  * case, we call set mode ourselves to restore the previous mode
6113                  * and the modelist may not be filled in time.
6114                  */
6115                 DRM_DEBUG_DRIVER("No preferred mode found\n");
6116         } else {
6117                 recalculate_timing = is_freesync_video_mode(&mode, aconnector);
6118                 if (recalculate_timing) {
6119                         freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
6120                         drm_mode_copy(&saved_mode, &mode);
6121                         drm_mode_copy(&mode, freesync_mode);
6122                 } else {
6123                         decide_crtc_timing_for_drm_display_mode(
6124                                         &mode, preferred_mode, scale);
6125
6126                         preferred_refresh = drm_mode_vrefresh(preferred_mode);
6127                 }
6128         }
6129
6130         if (recalculate_timing)
6131                 drm_mode_set_crtcinfo(&saved_mode, 0);
6132
6133         /*
6134          * If scaling is enabled and refresh rate didn't change
6135          * we copy the vic and polarities of the old timings
6136          */
6137         if (!scale || mode_refresh != preferred_refresh)
6138                 fill_stream_properties_from_drm_display_mode(
6139                         stream, &mode, &aconnector->base, con_state, NULL,
6140                         requested_bpc);
6141         else
6142                 fill_stream_properties_from_drm_display_mode(
6143                         stream, &mode, &aconnector->base, con_state, old_stream,
6144                         requested_bpc);
6145
6146         if (aconnector->timing_changed) {
6147                 drm_dbg(aconnector->base.dev,
6148                         "overriding timing for automated test, bpc %d, changing to %d\n",
6149                         stream->timing.display_color_depth,
6150                         aconnector->timing_requested->display_color_depth);
6151                 stream->timing = *aconnector->timing_requested;
6152         }
6153
6154         /* SST DSC determination policy */
6155         update_dsc_caps(aconnector, sink, stream, &dsc_caps);
6156         if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
6157                 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
6158
6159         update_stream_scaling_settings(&mode, dm_state, stream);
6160
6161         fill_audio_info(
6162                 &stream->audio_info,
6163                 drm_connector,
6164                 sink);
6165
6166         update_stream_signal(stream, sink);
6167
6168         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
6169                 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
6170
6171         if (stream->link->psr_settings.psr_feature_enabled || stream->link->replay_settings.replay_feature_enabled) {
6172                 //
6173                 // should decide stream support vsc sdp colorimetry capability
6174                 // before building vsc info packet
6175                 //
6176                 stream->use_vsc_sdp_for_colorimetry = false;
6177                 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
6178                         stream->use_vsc_sdp_for_colorimetry =
6179                                 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
6180                 } else {
6181                         if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
6182                                 stream->use_vsc_sdp_for_colorimetry = true;
6183                 }
6184                 if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22)
6185                         tf = TRANSFER_FUNC_GAMMA_22;
6186                 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
6187                 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
6188
6189         }
6190 finish:
6191         dc_sink_release(sink);
6192
6193         return stream;
6194 }
6195
6196 static enum drm_connector_status
6197 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
6198 {
6199         bool connected;
6200         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6201
6202         /*
6203          * Notes:
6204          * 1. This interface is NOT called in context of HPD irq.
6205          * 2. This interface *is called* in context of user-mode ioctl. Which
6206          * makes it a bad place for *any* MST-related activity.
6207          */
6208
6209         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
6210             !aconnector->fake_enable)
6211                 connected = (aconnector->dc_sink != NULL);
6212         else
6213                 connected = (aconnector->base.force == DRM_FORCE_ON ||
6214                                 aconnector->base.force == DRM_FORCE_ON_DIGITAL);
6215
6216         update_subconnector_property(aconnector);
6217
6218         return (connected ? connector_status_connected :
6219                         connector_status_disconnected);
6220 }
6221
6222 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
6223                                             struct drm_connector_state *connector_state,
6224                                             struct drm_property *property,
6225                                             uint64_t val)
6226 {
6227         struct drm_device *dev = connector->dev;
6228         struct amdgpu_device *adev = drm_to_adev(dev);
6229         struct dm_connector_state *dm_old_state =
6230                 to_dm_connector_state(connector->state);
6231         struct dm_connector_state *dm_new_state =
6232                 to_dm_connector_state(connector_state);
6233
6234         int ret = -EINVAL;
6235
6236         if (property == dev->mode_config.scaling_mode_property) {
6237                 enum amdgpu_rmx_type rmx_type;
6238
6239                 switch (val) {
6240                 case DRM_MODE_SCALE_CENTER:
6241                         rmx_type = RMX_CENTER;
6242                         break;
6243                 case DRM_MODE_SCALE_ASPECT:
6244                         rmx_type = RMX_ASPECT;
6245                         break;
6246                 case DRM_MODE_SCALE_FULLSCREEN:
6247                         rmx_type = RMX_FULL;
6248                         break;
6249                 case DRM_MODE_SCALE_NONE:
6250                 default:
6251                         rmx_type = RMX_OFF;
6252                         break;
6253                 }
6254
6255                 if (dm_old_state->scaling == rmx_type)
6256                         return 0;
6257
6258                 dm_new_state->scaling = rmx_type;
6259                 ret = 0;
6260         } else if (property == adev->mode_info.underscan_hborder_property) {
6261                 dm_new_state->underscan_hborder = val;
6262                 ret = 0;
6263         } else if (property == adev->mode_info.underscan_vborder_property) {
6264                 dm_new_state->underscan_vborder = val;
6265                 ret = 0;
6266         } else if (property == adev->mode_info.underscan_property) {
6267                 dm_new_state->underscan_enable = val;
6268                 ret = 0;
6269         } else if (property == adev->mode_info.abm_level_property) {
6270                 dm_new_state->abm_level = val;
6271                 ret = 0;
6272         }
6273
6274         return ret;
6275 }
6276
6277 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
6278                                             const struct drm_connector_state *state,
6279                                             struct drm_property *property,
6280                                             uint64_t *val)
6281 {
6282         struct drm_device *dev = connector->dev;
6283         struct amdgpu_device *adev = drm_to_adev(dev);
6284         struct dm_connector_state *dm_state =
6285                 to_dm_connector_state(state);
6286         int ret = -EINVAL;
6287
6288         if (property == dev->mode_config.scaling_mode_property) {
6289                 switch (dm_state->scaling) {
6290                 case RMX_CENTER:
6291                         *val = DRM_MODE_SCALE_CENTER;
6292                         break;
6293                 case RMX_ASPECT:
6294                         *val = DRM_MODE_SCALE_ASPECT;
6295                         break;
6296                 case RMX_FULL:
6297                         *val = DRM_MODE_SCALE_FULLSCREEN;
6298                         break;
6299                 case RMX_OFF:
6300                 default:
6301                         *val = DRM_MODE_SCALE_NONE;
6302                         break;
6303                 }
6304                 ret = 0;
6305         } else if (property == adev->mode_info.underscan_hborder_property) {
6306                 *val = dm_state->underscan_hborder;
6307                 ret = 0;
6308         } else if (property == adev->mode_info.underscan_vborder_property) {
6309                 *val = dm_state->underscan_vborder;
6310                 ret = 0;
6311         } else if (property == adev->mode_info.underscan_property) {
6312                 *val = dm_state->underscan_enable;
6313                 ret = 0;
6314         } else if (property == adev->mode_info.abm_level_property) {
6315                 *val = dm_state->abm_level;
6316                 ret = 0;
6317         }
6318
6319         return ret;
6320 }
6321
6322 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
6323 {
6324         struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
6325
6326         drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
6327 }
6328
6329 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
6330 {
6331         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6332         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6333         struct amdgpu_display_manager *dm = &adev->dm;
6334
6335         /*
6336          * Call only if mst_mgr was initialized before since it's not done
6337          * for all connector types.
6338          */
6339         if (aconnector->mst_mgr.dev)
6340                 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
6341
6342         if (aconnector->bl_idx != -1) {
6343                 backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]);
6344                 dm->backlight_dev[aconnector->bl_idx] = NULL;
6345         }
6346
6347         if (aconnector->dc_em_sink)
6348                 dc_sink_release(aconnector->dc_em_sink);
6349         aconnector->dc_em_sink = NULL;
6350         if (aconnector->dc_sink)
6351                 dc_sink_release(aconnector->dc_sink);
6352         aconnector->dc_sink = NULL;
6353
6354         drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
6355         drm_connector_unregister(connector);
6356         drm_connector_cleanup(connector);
6357         if (aconnector->i2c) {
6358                 i2c_del_adapter(&aconnector->i2c->base);
6359                 kfree(aconnector->i2c);
6360         }
6361         kfree(aconnector->dm_dp_aux.aux.name);
6362
6363         kfree(connector);
6364 }
6365
6366 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
6367 {
6368         struct dm_connector_state *state =
6369                 to_dm_connector_state(connector->state);
6370
6371         if (connector->state)
6372                 __drm_atomic_helper_connector_destroy_state(connector->state);
6373
6374         kfree(state);
6375
6376         state = kzalloc(sizeof(*state), GFP_KERNEL);
6377
6378         if (state) {
6379                 state->scaling = RMX_OFF;
6380                 state->underscan_enable = false;
6381                 state->underscan_hborder = 0;
6382                 state->underscan_vborder = 0;
6383                 state->base.max_requested_bpc = 8;
6384                 state->vcpi_slots = 0;
6385                 state->pbn = 0;
6386
6387                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
6388                         state->abm_level = amdgpu_dm_abm_level;
6389
6390                 __drm_atomic_helper_connector_reset(connector, &state->base);
6391         }
6392 }
6393
6394 struct drm_connector_state *
6395 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
6396 {
6397         struct dm_connector_state *state =
6398                 to_dm_connector_state(connector->state);
6399
6400         struct dm_connector_state *new_state =
6401                         kmemdup(state, sizeof(*state), GFP_KERNEL);
6402
6403         if (!new_state)
6404                 return NULL;
6405
6406         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
6407
6408         new_state->freesync_capable = state->freesync_capable;
6409         new_state->abm_level = state->abm_level;
6410         new_state->scaling = state->scaling;
6411         new_state->underscan_enable = state->underscan_enable;
6412         new_state->underscan_hborder = state->underscan_hborder;
6413         new_state->underscan_vborder = state->underscan_vborder;
6414         new_state->vcpi_slots = state->vcpi_slots;
6415         new_state->pbn = state->pbn;
6416         return &new_state->base;
6417 }
6418
6419 static int
6420 amdgpu_dm_connector_late_register(struct drm_connector *connector)
6421 {
6422         struct amdgpu_dm_connector *amdgpu_dm_connector =
6423                 to_amdgpu_dm_connector(connector);
6424         int r;
6425
6426         amdgpu_dm_register_backlight_device(amdgpu_dm_connector);
6427
6428         if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
6429             (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
6430                 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
6431                 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
6432                 if (r)
6433                         return r;
6434         }
6435
6436 #if defined(CONFIG_DEBUG_FS)
6437         connector_debugfs_init(amdgpu_dm_connector);
6438 #endif
6439
6440         return 0;
6441 }
6442
6443 static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector)
6444 {
6445         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6446         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
6447         struct dc_link *dc_link = aconnector->dc_link;
6448         struct dc_sink *dc_em_sink = aconnector->dc_em_sink;
6449         struct edid *edid;
6450
6451         /*
6452          * Note: drm_get_edid gets edid in the following order:
6453          * 1) override EDID if set via edid_override debugfs,
6454          * 2) firmware EDID if set via edid_firmware module parameter
6455          * 3) regular DDC read.
6456          */
6457         edid = drm_get_edid(connector, &amdgpu_connector->ddc_bus->aux.ddc);
6458         if (!edid) {
6459                 DRM_ERROR("No EDID found on connector: %s.\n", connector->name);
6460                 return;
6461         }
6462
6463         aconnector->edid = edid;
6464
6465         /* Update emulated (virtual) sink's EDID */
6466         if (dc_em_sink && dc_link) {
6467                 memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps));
6468                 memmove(dc_em_sink->dc_edid.raw_edid, edid, (edid->extensions + 1) * EDID_LENGTH);
6469                 dm_helpers_parse_edid_caps(
6470                         dc_link,
6471                         &dc_em_sink->dc_edid,
6472                         &dc_em_sink->edid_caps);
6473         }
6474 }
6475
6476 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
6477         .reset = amdgpu_dm_connector_funcs_reset,
6478         .detect = amdgpu_dm_connector_detect,
6479         .fill_modes = drm_helper_probe_single_connector_modes,
6480         .destroy = amdgpu_dm_connector_destroy,
6481         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
6482         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6483         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
6484         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
6485         .late_register = amdgpu_dm_connector_late_register,
6486         .early_unregister = amdgpu_dm_connector_unregister,
6487         .force = amdgpu_dm_connector_funcs_force
6488 };
6489
6490 static int get_modes(struct drm_connector *connector)
6491 {
6492         return amdgpu_dm_connector_get_modes(connector);
6493 }
6494
6495 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
6496 {
6497         struct drm_connector *connector = &aconnector->base;
6498         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(&aconnector->base);
6499         struct dc_sink_init_data init_params = {
6500                         .link = aconnector->dc_link,
6501                         .sink_signal = SIGNAL_TYPE_VIRTUAL
6502         };
6503         struct edid *edid;
6504
6505         /*
6506          * Note: drm_get_edid gets edid in the following order:
6507          * 1) override EDID if set via edid_override debugfs,
6508          * 2) firmware EDID if set via edid_firmware module parameter
6509          * 3) regular DDC read.
6510          */
6511         edid = drm_get_edid(connector, &amdgpu_connector->ddc_bus->aux.ddc);
6512         if (!edid) {
6513                 DRM_ERROR("No EDID found on connector: %s.\n", connector->name);
6514                 return;
6515         }
6516
6517         if (drm_detect_hdmi_monitor(edid))
6518                 init_params.sink_signal = SIGNAL_TYPE_HDMI_TYPE_A;
6519
6520         aconnector->edid = edid;
6521
6522         aconnector->dc_em_sink = dc_link_add_remote_sink(
6523                 aconnector->dc_link,
6524                 (uint8_t *)edid,
6525                 (edid->extensions + 1) * EDID_LENGTH,
6526                 &init_params);
6527
6528         if (aconnector->base.force == DRM_FORCE_ON) {
6529                 aconnector->dc_sink = aconnector->dc_link->local_sink ?
6530                 aconnector->dc_link->local_sink :
6531                 aconnector->dc_em_sink;
6532                 dc_sink_retain(aconnector->dc_sink);
6533         }
6534 }
6535
6536 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
6537 {
6538         struct dc_link *link = (struct dc_link *)aconnector->dc_link;
6539
6540         /*
6541          * In case of headless boot with force on for DP managed connector
6542          * Those settings have to be != 0 to get initial modeset
6543          */
6544         if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6545                 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
6546                 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
6547         }
6548
6549         create_eml_sink(aconnector);
6550 }
6551
6552 static enum dc_status dm_validate_stream_and_context(struct dc *dc,
6553                                                 struct dc_stream_state *stream)
6554 {
6555         enum dc_status dc_result = DC_ERROR_UNEXPECTED;
6556         struct dc_plane_state *dc_plane_state = NULL;
6557         struct dc_state *dc_state = NULL;
6558
6559         if (!stream)
6560                 goto cleanup;
6561
6562         dc_plane_state = dc_create_plane_state(dc);
6563         if (!dc_plane_state)
6564                 goto cleanup;
6565
6566         dc_state = dc_create_state(dc);
6567         if (!dc_state)
6568                 goto cleanup;
6569
6570         /* populate stream to plane */
6571         dc_plane_state->src_rect.height  = stream->src.height;
6572         dc_plane_state->src_rect.width   = stream->src.width;
6573         dc_plane_state->dst_rect.height  = stream->src.height;
6574         dc_plane_state->dst_rect.width   = stream->src.width;
6575         dc_plane_state->clip_rect.height = stream->src.height;
6576         dc_plane_state->clip_rect.width  = stream->src.width;
6577         dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256;
6578         dc_plane_state->plane_size.surface_size.height = stream->src.height;
6579         dc_plane_state->plane_size.surface_size.width  = stream->src.width;
6580         dc_plane_state->plane_size.chroma_size.height  = stream->src.height;
6581         dc_plane_state->plane_size.chroma_size.width   = stream->src.width;
6582         dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
6583         dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
6584         dc_plane_state->rotation = ROTATION_ANGLE_0;
6585         dc_plane_state->is_tiling_rotated = false;
6586         dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL;
6587
6588         dc_result = dc_validate_stream(dc, stream);
6589         if (dc_result == DC_OK)
6590                 dc_result = dc_validate_plane(dc, dc_plane_state);
6591
6592         if (dc_result == DC_OK)
6593                 dc_result = dc_add_stream_to_ctx(dc, dc_state, stream);
6594
6595         if (dc_result == DC_OK && !dc_add_plane_to_context(
6596                                                 dc,
6597                                                 stream,
6598                                                 dc_plane_state,
6599                                                 dc_state))
6600                 dc_result = DC_FAIL_ATTACH_SURFACES;
6601
6602         if (dc_result == DC_OK)
6603                 dc_result = dc_validate_global_state(dc, dc_state, true);
6604
6605 cleanup:
6606         if (dc_state)
6607                 dc_release_state(dc_state);
6608
6609         if (dc_plane_state)
6610                 dc_plane_state_release(dc_plane_state);
6611
6612         return dc_result;
6613 }
6614
6615 struct dc_stream_state *
6616 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6617                                 const struct drm_display_mode *drm_mode,
6618                                 const struct dm_connector_state *dm_state,
6619                                 const struct dc_stream_state *old_stream)
6620 {
6621         struct drm_connector *connector = &aconnector->base;
6622         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6623         struct dc_stream_state *stream;
6624         const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
6625         int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
6626         enum dc_status dc_result = DC_OK;
6627
6628         do {
6629                 stream = create_stream_for_sink(aconnector, drm_mode,
6630                                                 dm_state, old_stream,
6631                                                 requested_bpc);
6632                 if (stream == NULL) {
6633                         DRM_ERROR("Failed to create stream for sink!\n");
6634                         break;
6635                 }
6636
6637                 dc_result = dc_validate_stream(adev->dm.dc, stream);
6638                 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
6639                         dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
6640
6641                 if (dc_result == DC_OK)
6642                         dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);
6643
6644                 if (dc_result != DC_OK) {
6645                         DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
6646                                       drm_mode->hdisplay,
6647                                       drm_mode->vdisplay,
6648                                       drm_mode->clock,
6649                                       dc_result,
6650                                       dc_status_to_str(dc_result));
6651
6652                         dc_stream_release(stream);
6653                         stream = NULL;
6654                         requested_bpc -= 2; /* lower bpc to retry validation */
6655                 }
6656
6657         } while (stream == NULL && requested_bpc >= 6);
6658
6659         if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
6660                 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
6661
6662                 aconnector->force_yuv420_output = true;
6663                 stream = create_validate_stream_for_sink(aconnector, drm_mode,
6664                                                 dm_state, old_stream);
6665                 aconnector->force_yuv420_output = false;
6666         }
6667
6668         return stream;
6669 }
6670
6671 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
6672                                    struct drm_display_mode *mode)
6673 {
6674         int result = MODE_ERROR;
6675         struct dc_sink *dc_sink;
6676         /* TODO: Unhardcode stream count */
6677         struct dc_stream_state *stream;
6678         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6679
6680         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6681                         (mode->flags & DRM_MODE_FLAG_DBLSCAN))
6682                 return result;
6683
6684         /*
6685          * Only run this the first time mode_valid is called to initilialize
6686          * EDID mgmt
6687          */
6688         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
6689                 !aconnector->dc_em_sink)
6690                 handle_edid_mgmt(aconnector);
6691
6692         dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
6693
6694         if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
6695                                 aconnector->base.force != DRM_FORCE_ON) {
6696                 DRM_ERROR("dc_sink is NULL!\n");
6697                 goto fail;
6698         }
6699
6700         drm_mode_set_crtcinfo(mode, 0);
6701
6702         stream = create_validate_stream_for_sink(aconnector, mode,
6703                                                  to_dm_connector_state(connector->state),
6704                                                  NULL);
6705         if (stream) {
6706                 dc_stream_release(stream);
6707                 result = MODE_OK;
6708         }
6709
6710 fail:
6711         /* TODO: error handling*/
6712         return result;
6713 }
6714
6715 static int fill_hdr_info_packet(const struct drm_connector_state *state,
6716                                 struct dc_info_packet *out)
6717 {
6718         struct hdmi_drm_infoframe frame;
6719         unsigned char buf[30]; /* 26 + 4 */
6720         ssize_t len;
6721         int ret, i;
6722
6723         memset(out, 0, sizeof(*out));
6724
6725         if (!state->hdr_output_metadata)
6726                 return 0;
6727
6728         ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
6729         if (ret)
6730                 return ret;
6731
6732         len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
6733         if (len < 0)
6734                 return (int)len;
6735
6736         /* Static metadata is a fixed 26 bytes + 4 byte header. */
6737         if (len != 30)
6738                 return -EINVAL;
6739
6740         /* Prepare the infopacket for DC. */
6741         switch (state->connector->connector_type) {
6742         case DRM_MODE_CONNECTOR_HDMIA:
6743                 out->hb0 = 0x87; /* type */
6744                 out->hb1 = 0x01; /* version */
6745                 out->hb2 = 0x1A; /* length */
6746                 out->sb[0] = buf[3]; /* checksum */
6747                 i = 1;
6748                 break;
6749
6750         case DRM_MODE_CONNECTOR_DisplayPort:
6751         case DRM_MODE_CONNECTOR_eDP:
6752                 out->hb0 = 0x00; /* sdp id, zero */
6753                 out->hb1 = 0x87; /* type */
6754                 out->hb2 = 0x1D; /* payload len - 1 */
6755                 out->hb3 = (0x13 << 2); /* sdp version */
6756                 out->sb[0] = 0x01; /* version */
6757                 out->sb[1] = 0x1A; /* length */
6758                 i = 2;
6759                 break;
6760
6761         default:
6762                 return -EINVAL;
6763         }
6764
6765         memcpy(&out->sb[i], &buf[4], 26);
6766         out->valid = true;
6767
6768         print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
6769                        sizeof(out->sb), false);
6770
6771         return 0;
6772 }
6773
6774 static int
6775 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
6776                                  struct drm_atomic_state *state)
6777 {
6778         struct drm_connector_state *new_con_state =
6779                 drm_atomic_get_new_connector_state(state, conn);
6780         struct drm_connector_state *old_con_state =
6781                 drm_atomic_get_old_connector_state(state, conn);
6782         struct drm_crtc *crtc = new_con_state->crtc;
6783         struct drm_crtc_state *new_crtc_state;
6784         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
6785         int ret;
6786
6787         trace_amdgpu_dm_connector_atomic_check(new_con_state);
6788
6789         if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
6790                 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
6791                 if (ret < 0)
6792                         return ret;
6793         }
6794
6795         if (!crtc)
6796                 return 0;
6797
6798         if (new_con_state->colorspace != old_con_state->colorspace) {
6799                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6800                 if (IS_ERR(new_crtc_state))
6801                         return PTR_ERR(new_crtc_state);
6802
6803                 new_crtc_state->mode_changed = true;
6804         }
6805
6806         if (new_con_state->content_type != old_con_state->content_type) {
6807                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6808                 if (IS_ERR(new_crtc_state))
6809                         return PTR_ERR(new_crtc_state);
6810
6811                 new_crtc_state->mode_changed = true;
6812         }
6813
6814         if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
6815                 struct dc_info_packet hdr_infopacket;
6816
6817                 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
6818                 if (ret)
6819                         return ret;
6820
6821                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6822                 if (IS_ERR(new_crtc_state))
6823                         return PTR_ERR(new_crtc_state);
6824
6825                 /*
6826                  * DC considers the stream backends changed if the
6827                  * static metadata changes. Forcing the modeset also
6828                  * gives a simple way for userspace to switch from
6829                  * 8bpc to 10bpc when setting the metadata to enter
6830                  * or exit HDR.
6831                  *
6832                  * Changing the static metadata after it's been
6833                  * set is permissible, however. So only force a
6834                  * modeset if we're entering or exiting HDR.
6835                  */
6836                 new_crtc_state->mode_changed = new_crtc_state->mode_changed ||
6837                         !old_con_state->hdr_output_metadata ||
6838                         !new_con_state->hdr_output_metadata;
6839         }
6840
6841         return 0;
6842 }
6843
6844 static const struct drm_connector_helper_funcs
6845 amdgpu_dm_connector_helper_funcs = {
6846         /*
6847          * If hotplugging a second bigger display in FB Con mode, bigger resolution
6848          * modes will be filtered by drm_mode_validate_size(), and those modes
6849          * are missing after user start lightdm. So we need to renew modes list.
6850          * in get_modes call back, not just return the modes count
6851          */
6852         .get_modes = get_modes,
6853         .mode_valid = amdgpu_dm_connector_mode_valid,
6854         .atomic_check = amdgpu_dm_connector_atomic_check,
6855 };
6856
6857 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6858 {
6859
6860 }
6861
6862 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
6863 {
6864         switch (display_color_depth) {
6865         case COLOR_DEPTH_666:
6866                 return 6;
6867         case COLOR_DEPTH_888:
6868                 return 8;
6869         case COLOR_DEPTH_101010:
6870                 return 10;
6871         case COLOR_DEPTH_121212:
6872                 return 12;
6873         case COLOR_DEPTH_141414:
6874                 return 14;
6875         case COLOR_DEPTH_161616:
6876                 return 16;
6877         default:
6878                 break;
6879         }
6880         return 0;
6881 }
6882
6883 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
6884                                           struct drm_crtc_state *crtc_state,
6885                                           struct drm_connector_state *conn_state)
6886 {
6887         struct drm_atomic_state *state = crtc_state->state;
6888         struct drm_connector *connector = conn_state->connector;
6889         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6890         struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
6891         const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6892         struct drm_dp_mst_topology_mgr *mst_mgr;
6893         struct drm_dp_mst_port *mst_port;
6894         struct drm_dp_mst_topology_state *mst_state;
6895         enum dc_color_depth color_depth;
6896         int clock, bpp = 0;
6897         bool is_y420 = false;
6898
6899         if (!aconnector->mst_output_port)
6900                 return 0;
6901
6902         mst_port = aconnector->mst_output_port;
6903         mst_mgr = &aconnector->mst_root->mst_mgr;
6904
6905         if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6906                 return 0;
6907
6908         mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
6909         if (IS_ERR(mst_state))
6910                 return PTR_ERR(mst_state);
6911
6912         if (!mst_state->pbn_div)
6913                 mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link);
6914
6915         if (!state->duplicated) {
6916                 int max_bpc = conn_state->max_requested_bpc;
6917
6918                 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
6919                           aconnector->force_yuv420_output;
6920                 color_depth = convert_color_depth_from_display_info(connector,
6921                                                                     is_y420,
6922                                                                     max_bpc);
6923                 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
6924                 clock = adjusted_mode->clock;
6925                 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
6926         }
6927
6928         dm_new_connector_state->vcpi_slots =
6929                 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
6930                                               dm_new_connector_state->pbn);
6931         if (dm_new_connector_state->vcpi_slots < 0) {
6932                 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
6933                 return dm_new_connector_state->vcpi_slots;
6934         }
6935         return 0;
6936 }
6937
6938 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
6939         .disable = dm_encoder_helper_disable,
6940         .atomic_check = dm_encoder_helper_atomic_check
6941 };
6942
6943 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
6944                                             struct dc_state *dc_state,
6945                                             struct dsc_mst_fairness_vars *vars)
6946 {
6947         struct dc_stream_state *stream = NULL;
6948         struct drm_connector *connector;
6949         struct drm_connector_state *new_con_state;
6950         struct amdgpu_dm_connector *aconnector;
6951         struct dm_connector_state *dm_conn_state;
6952         int i, j, ret;
6953         int vcpi, pbn_div, pbn, slot_num = 0;
6954
6955         for_each_new_connector_in_state(state, connector, new_con_state, i) {
6956
6957                 aconnector = to_amdgpu_dm_connector(connector);
6958
6959                 if (!aconnector->mst_output_port)
6960                         continue;
6961
6962                 if (!new_con_state || !new_con_state->crtc)
6963                         continue;
6964
6965                 dm_conn_state = to_dm_connector_state(new_con_state);
6966
6967                 for (j = 0; j < dc_state->stream_count; j++) {
6968                         stream = dc_state->streams[j];
6969                         if (!stream)
6970                                 continue;
6971
6972                         if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
6973                                 break;
6974
6975                         stream = NULL;
6976                 }
6977
6978                 if (!stream)
6979                         continue;
6980
6981                 pbn_div = dm_mst_get_pbn_divider(stream->link);
6982                 /* pbn is calculated by compute_mst_dsc_configs_for_state*/
6983                 for (j = 0; j < dc_state->stream_count; j++) {
6984                         if (vars[j].aconnector == aconnector) {
6985                                 pbn = vars[j].pbn;
6986                                 break;
6987                         }
6988                 }
6989
6990                 if (j == dc_state->stream_count)
6991                         continue;
6992
6993                 slot_num = DIV_ROUND_UP(pbn, pbn_div);
6994
6995                 if (stream->timing.flags.DSC != 1) {
6996                         dm_conn_state->pbn = pbn;
6997                         dm_conn_state->vcpi_slots = slot_num;
6998
6999                         ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port,
7000                                                            dm_conn_state->pbn, false);
7001                         if (ret < 0)
7002                                 return ret;
7003
7004                         continue;
7005                 }
7006
7007                 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true);
7008                 if (vcpi < 0)
7009                         return vcpi;
7010
7011                 dm_conn_state->pbn = pbn;
7012                 dm_conn_state->vcpi_slots = vcpi;
7013         }
7014         return 0;
7015 }
7016
7017 static int to_drm_connector_type(enum signal_type st)
7018 {
7019         switch (st) {
7020         case SIGNAL_TYPE_HDMI_TYPE_A:
7021                 return DRM_MODE_CONNECTOR_HDMIA;
7022         case SIGNAL_TYPE_EDP:
7023                 return DRM_MODE_CONNECTOR_eDP;
7024         case SIGNAL_TYPE_LVDS:
7025                 return DRM_MODE_CONNECTOR_LVDS;
7026         case SIGNAL_TYPE_RGB:
7027                 return DRM_MODE_CONNECTOR_VGA;
7028         case SIGNAL_TYPE_DISPLAY_PORT:
7029         case SIGNAL_TYPE_DISPLAY_PORT_MST:
7030                 return DRM_MODE_CONNECTOR_DisplayPort;
7031         case SIGNAL_TYPE_DVI_DUAL_LINK:
7032         case SIGNAL_TYPE_DVI_SINGLE_LINK:
7033                 return DRM_MODE_CONNECTOR_DVID;
7034         case SIGNAL_TYPE_VIRTUAL:
7035                 return DRM_MODE_CONNECTOR_VIRTUAL;
7036
7037         default:
7038                 return DRM_MODE_CONNECTOR_Unknown;
7039         }
7040 }
7041
7042 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
7043 {
7044         struct drm_encoder *encoder;
7045
7046         /* There is only one encoder per connector */
7047         drm_connector_for_each_possible_encoder(connector, encoder)
7048                 return encoder;
7049
7050         return NULL;
7051 }
7052
7053 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
7054 {
7055         struct drm_encoder *encoder;
7056         struct amdgpu_encoder *amdgpu_encoder;
7057
7058         encoder = amdgpu_dm_connector_to_encoder(connector);
7059
7060         if (encoder == NULL)
7061                 return;
7062
7063         amdgpu_encoder = to_amdgpu_encoder(encoder);
7064
7065         amdgpu_encoder->native_mode.clock = 0;
7066
7067         if (!list_empty(&connector->probed_modes)) {
7068                 struct drm_display_mode *preferred_mode = NULL;
7069
7070                 list_for_each_entry(preferred_mode,
7071                                     &connector->probed_modes,
7072                                     head) {
7073                         if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
7074                                 amdgpu_encoder->native_mode = *preferred_mode;
7075
7076                         break;
7077                 }
7078
7079         }
7080 }
7081
7082 static struct drm_display_mode *
7083 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
7084                              char *name,
7085                              int hdisplay, int vdisplay)
7086 {
7087         struct drm_device *dev = encoder->dev;
7088         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
7089         struct drm_display_mode *mode = NULL;
7090         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
7091
7092         mode = drm_mode_duplicate(dev, native_mode);
7093
7094         if (mode == NULL)
7095                 return NULL;
7096
7097         mode->hdisplay = hdisplay;
7098         mode->vdisplay = vdisplay;
7099         mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7100         strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
7101
7102         return mode;
7103
7104 }
7105
7106 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
7107                                                  struct drm_connector *connector)
7108 {
7109         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
7110         struct drm_display_mode *mode = NULL;
7111         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
7112         struct amdgpu_dm_connector *amdgpu_dm_connector =
7113                                 to_amdgpu_dm_connector(connector);
7114         int i;
7115         int n;
7116         struct mode_size {
7117                 char name[DRM_DISPLAY_MODE_LEN];
7118                 int w;
7119                 int h;
7120         } common_modes[] = {
7121                 {  "640x480",  640,  480},
7122                 {  "800x600",  800,  600},
7123                 { "1024x768", 1024,  768},
7124                 { "1280x720", 1280,  720},
7125                 { "1280x800", 1280,  800},
7126                 {"1280x1024", 1280, 1024},
7127                 { "1440x900", 1440,  900},
7128                 {"1680x1050", 1680, 1050},
7129                 {"1600x1200", 1600, 1200},
7130                 {"1920x1080", 1920, 1080},
7131                 {"1920x1200", 1920, 1200}
7132         };
7133
7134         n = ARRAY_SIZE(common_modes);
7135
7136         for (i = 0; i < n; i++) {
7137                 struct drm_display_mode *curmode = NULL;
7138                 bool mode_existed = false;
7139
7140                 if (common_modes[i].w > native_mode->hdisplay ||
7141                     common_modes[i].h > native_mode->vdisplay ||
7142                    (common_modes[i].w == native_mode->hdisplay &&
7143                     common_modes[i].h == native_mode->vdisplay))
7144                         continue;
7145
7146                 list_for_each_entry(curmode, &connector->probed_modes, head) {
7147                         if (common_modes[i].w == curmode->hdisplay &&
7148                             common_modes[i].h == curmode->vdisplay) {
7149                                 mode_existed = true;
7150                                 break;
7151                         }
7152                 }
7153
7154                 if (mode_existed)
7155                         continue;
7156
7157                 mode = amdgpu_dm_create_common_mode(encoder,
7158                                 common_modes[i].name, common_modes[i].w,
7159                                 common_modes[i].h);
7160                 if (!mode)
7161                         continue;
7162
7163                 drm_mode_probed_add(connector, mode);
7164                 amdgpu_dm_connector->num_modes++;
7165         }
7166 }
7167
7168 static void amdgpu_set_panel_orientation(struct drm_connector *connector)
7169 {
7170         struct drm_encoder *encoder;
7171         struct amdgpu_encoder *amdgpu_encoder;
7172         const struct drm_display_mode *native_mode;
7173
7174         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
7175             connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
7176                 return;
7177
7178         mutex_lock(&connector->dev->mode_config.mutex);
7179         amdgpu_dm_connector_get_modes(connector);
7180         mutex_unlock(&connector->dev->mode_config.mutex);
7181
7182         encoder = amdgpu_dm_connector_to_encoder(connector);
7183         if (!encoder)
7184                 return;
7185
7186         amdgpu_encoder = to_amdgpu_encoder(encoder);
7187
7188         native_mode = &amdgpu_encoder->native_mode;
7189         if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
7190                 return;
7191
7192         drm_connector_set_panel_orientation_with_quirk(connector,
7193                                                        DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
7194                                                        native_mode->hdisplay,
7195                                                        native_mode->vdisplay);
7196 }
7197
7198 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
7199                                               struct edid *edid)
7200 {
7201         struct amdgpu_dm_connector *amdgpu_dm_connector =
7202                         to_amdgpu_dm_connector(connector);
7203
7204         if (edid) {
7205                 /* empty probed_modes */
7206                 INIT_LIST_HEAD(&connector->probed_modes);
7207                 amdgpu_dm_connector->num_modes =
7208                                 drm_add_edid_modes(connector, edid);
7209
7210                 /* sorting the probed modes before calling function
7211                  * amdgpu_dm_get_native_mode() since EDID can have
7212                  * more than one preferred mode. The modes that are
7213                  * later in the probed mode list could be of higher
7214                  * and preferred resolution. For example, 3840x2160
7215                  * resolution in base EDID preferred timing and 4096x2160
7216                  * preferred resolution in DID extension block later.
7217                  */
7218                 drm_mode_sort(&connector->probed_modes);
7219                 amdgpu_dm_get_native_mode(connector);
7220
7221                 /* Freesync capabilities are reset by calling
7222                  * drm_add_edid_modes() and need to be
7223                  * restored here.
7224                  */
7225                 amdgpu_dm_update_freesync_caps(connector, edid);
7226         } else {
7227                 amdgpu_dm_connector->num_modes = 0;
7228         }
7229 }
7230
7231 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
7232                               struct drm_display_mode *mode)
7233 {
7234         struct drm_display_mode *m;
7235
7236         list_for_each_entry(m, &aconnector->base.probed_modes, head) {
7237                 if (drm_mode_equal(m, mode))
7238                         return true;
7239         }
7240
7241         return false;
7242 }
7243
7244 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
7245 {
7246         const struct drm_display_mode *m;
7247         struct drm_display_mode *new_mode;
7248         uint i;
7249         u32 new_modes_count = 0;
7250
7251         /* Standard FPS values
7252          *
7253          * 23.976       - TV/NTSC
7254          * 24           - Cinema
7255          * 25           - TV/PAL
7256          * 29.97        - TV/NTSC
7257          * 30           - TV/NTSC
7258          * 48           - Cinema HFR
7259          * 50           - TV/PAL
7260          * 60           - Commonly used
7261          * 48,72,96,120 - Multiples of 24
7262          */
7263         static const u32 common_rates[] = {
7264                 23976, 24000, 25000, 29970, 30000,
7265                 48000, 50000, 60000, 72000, 96000, 120000
7266         };
7267
7268         /*
7269          * Find mode with highest refresh rate with the same resolution
7270          * as the preferred mode. Some monitors report a preferred mode
7271          * with lower resolution than the highest refresh rate supported.
7272          */
7273
7274         m = get_highest_refresh_rate_mode(aconnector, true);
7275         if (!m)
7276                 return 0;
7277
7278         for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
7279                 u64 target_vtotal, target_vtotal_diff;
7280                 u64 num, den;
7281
7282                 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
7283                         continue;
7284
7285                 if (common_rates[i] < aconnector->min_vfreq * 1000 ||
7286                     common_rates[i] > aconnector->max_vfreq * 1000)
7287                         continue;
7288
7289                 num = (unsigned long long)m->clock * 1000 * 1000;
7290                 den = common_rates[i] * (unsigned long long)m->htotal;
7291                 target_vtotal = div_u64(num, den);
7292                 target_vtotal_diff = target_vtotal - m->vtotal;
7293
7294                 /* Check for illegal modes */
7295                 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
7296                     m->vsync_end + target_vtotal_diff < m->vsync_start ||
7297                     m->vtotal + target_vtotal_diff < m->vsync_end)
7298                         continue;
7299
7300                 new_mode = drm_mode_duplicate(aconnector->base.dev, m);
7301                 if (!new_mode)
7302                         goto out;
7303
7304                 new_mode->vtotal += (u16)target_vtotal_diff;
7305                 new_mode->vsync_start += (u16)target_vtotal_diff;
7306                 new_mode->vsync_end += (u16)target_vtotal_diff;
7307                 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7308                 new_mode->type |= DRM_MODE_TYPE_DRIVER;
7309
7310                 if (!is_duplicate_mode(aconnector, new_mode)) {
7311                         drm_mode_probed_add(&aconnector->base, new_mode);
7312                         new_modes_count += 1;
7313                 } else
7314                         drm_mode_destroy(aconnector->base.dev, new_mode);
7315         }
7316  out:
7317         return new_modes_count;
7318 }
7319
7320 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
7321                                                    struct edid *edid)
7322 {
7323         struct amdgpu_dm_connector *amdgpu_dm_connector =
7324                 to_amdgpu_dm_connector(connector);
7325
7326         if (!edid)
7327                 return;
7328
7329         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
7330                 amdgpu_dm_connector->num_modes +=
7331                         add_fs_modes(amdgpu_dm_connector);
7332 }
7333
7334 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
7335 {
7336         struct amdgpu_dm_connector *amdgpu_dm_connector =
7337                         to_amdgpu_dm_connector(connector);
7338         struct drm_encoder *encoder;
7339         struct edid *edid = amdgpu_dm_connector->edid;
7340         struct dc_link_settings *verified_link_cap =
7341                         &amdgpu_dm_connector->dc_link->verified_link_cap;
7342         const struct dc *dc = amdgpu_dm_connector->dc_link->dc;
7343
7344         encoder = amdgpu_dm_connector_to_encoder(connector);
7345
7346         if (!drm_edid_is_valid(edid)) {
7347                 amdgpu_dm_connector->num_modes =
7348                                 drm_add_modes_noedid(connector, 640, 480);
7349                 if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING)
7350                         amdgpu_dm_connector->num_modes +=
7351                                 drm_add_modes_noedid(connector, 1920, 1080);
7352         } else {
7353                 amdgpu_dm_connector_ddc_get_modes(connector, edid);
7354                 amdgpu_dm_connector_add_common_modes(encoder, connector);
7355                 amdgpu_dm_connector_add_freesync_modes(connector, edid);
7356         }
7357         amdgpu_dm_fbc_init(connector);
7358
7359         return amdgpu_dm_connector->num_modes;
7360 }
7361
7362 static const u32 supported_colorspaces =
7363         BIT(DRM_MODE_COLORIMETRY_BT709_YCC) |
7364         BIT(DRM_MODE_COLORIMETRY_OPRGB) |
7365         BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) |
7366         BIT(DRM_MODE_COLORIMETRY_BT2020_YCC);
7367
7368 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
7369                                      struct amdgpu_dm_connector *aconnector,
7370                                      int connector_type,
7371                                      struct dc_link *link,
7372                                      int link_index)
7373 {
7374         struct amdgpu_device *adev = drm_to_adev(dm->ddev);
7375
7376         /*
7377          * Some of the properties below require access to state, like bpc.
7378          * Allocate some default initial connector state with our reset helper.
7379          */
7380         if (aconnector->base.funcs->reset)
7381                 aconnector->base.funcs->reset(&aconnector->base);
7382
7383         aconnector->connector_id = link_index;
7384         aconnector->bl_idx = -1;
7385         aconnector->dc_link = link;
7386         aconnector->base.interlace_allowed = false;
7387         aconnector->base.doublescan_allowed = false;
7388         aconnector->base.stereo_allowed = false;
7389         aconnector->base.dpms = DRM_MODE_DPMS_OFF;
7390         aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
7391         aconnector->audio_inst = -1;
7392         aconnector->pack_sdp_v1_3 = false;
7393         aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE;
7394         memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info));
7395         mutex_init(&aconnector->hpd_lock);
7396         mutex_init(&aconnector->handle_mst_msg_ready);
7397
7398         /*
7399          * configure support HPD hot plug connector_>polled default value is 0
7400          * which means HPD hot plug not supported
7401          */
7402         switch (connector_type) {
7403         case DRM_MODE_CONNECTOR_HDMIA:
7404                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7405                 aconnector->base.ycbcr_420_allowed =
7406                         link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
7407                 break;
7408         case DRM_MODE_CONNECTOR_DisplayPort:
7409                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7410                 link->link_enc = link_enc_cfg_get_link_enc(link);
7411                 ASSERT(link->link_enc);
7412                 if (link->link_enc)
7413                         aconnector->base.ycbcr_420_allowed =
7414                         link->link_enc->features.dp_ycbcr420_supported ? true : false;
7415                 break;
7416         case DRM_MODE_CONNECTOR_DVID:
7417                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7418                 break;
7419         default:
7420                 break;
7421         }
7422
7423         drm_object_attach_property(&aconnector->base.base,
7424                                 dm->ddev->mode_config.scaling_mode_property,
7425                                 DRM_MODE_SCALE_NONE);
7426
7427         drm_object_attach_property(&aconnector->base.base,
7428                                 adev->mode_info.underscan_property,
7429                                 UNDERSCAN_OFF);
7430         drm_object_attach_property(&aconnector->base.base,
7431                                 adev->mode_info.underscan_hborder_property,
7432                                 0);
7433         drm_object_attach_property(&aconnector->base.base,
7434                                 adev->mode_info.underscan_vborder_property,
7435                                 0);
7436
7437         if (!aconnector->mst_root)
7438                 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
7439
7440         aconnector->base.state->max_bpc = 16;
7441         aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
7442
7443         if (connector_type == DRM_MODE_CONNECTOR_eDP &&
7444             (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
7445                 drm_object_attach_property(&aconnector->base.base,
7446                                 adev->mode_info.abm_level_property, 0);
7447         }
7448
7449         if (connector_type == DRM_MODE_CONNECTOR_HDMIA) {
7450                 /* Content Type is currently only implemented for HDMI. */
7451                 drm_connector_attach_content_type_property(&aconnector->base);
7452         }
7453
7454         if (connector_type == DRM_MODE_CONNECTOR_HDMIA) {
7455                 if (!drm_mode_create_hdmi_colorspace_property(&aconnector->base, supported_colorspaces))
7456                         drm_connector_attach_colorspace_property(&aconnector->base);
7457         } else if ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !aconnector->mst_root) ||
7458                    connector_type == DRM_MODE_CONNECTOR_eDP) {
7459                 if (!drm_mode_create_dp_colorspace_property(&aconnector->base, supported_colorspaces))
7460                         drm_connector_attach_colorspace_property(&aconnector->base);
7461         }
7462
7463         if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7464             connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7465             connector_type == DRM_MODE_CONNECTOR_eDP) {
7466                 drm_connector_attach_hdr_output_metadata_property(&aconnector->base);
7467
7468                 if (!aconnector->mst_root)
7469                         drm_connector_attach_vrr_capable_property(&aconnector->base);
7470
7471                 if (adev->dm.hdcp_workqueue)
7472                         drm_connector_attach_content_protection_property(&aconnector->base, true);
7473         }
7474 }
7475
7476 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
7477                               struct i2c_msg *msgs, int num)
7478 {
7479         struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
7480         struct ddc_service *ddc_service = i2c->ddc_service;
7481         struct i2c_command cmd;
7482         int i;
7483         int result = -EIO;
7484
7485         cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
7486
7487         if (!cmd.payloads)
7488                 return result;
7489
7490         cmd.number_of_payloads = num;
7491         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
7492         cmd.speed = 100;
7493
7494         for (i = 0; i < num; i++) {
7495                 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
7496                 cmd.payloads[i].address = msgs[i].addr;
7497                 cmd.payloads[i].length = msgs[i].len;
7498                 cmd.payloads[i].data = msgs[i].buf;
7499         }
7500
7501         if (dc_submit_i2c(
7502                         ddc_service->ctx->dc,
7503                         ddc_service->link->link_index,
7504                         &cmd))
7505                 result = num;
7506
7507         kfree(cmd.payloads);
7508         return result;
7509 }
7510
7511 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
7512 {
7513         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
7514 }
7515
7516 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
7517         .master_xfer = amdgpu_dm_i2c_xfer,
7518         .functionality = amdgpu_dm_i2c_func,
7519 };
7520
7521 static struct amdgpu_i2c_adapter *
7522 create_i2c(struct ddc_service *ddc_service,
7523            int link_index,
7524            int *res)
7525 {
7526         struct amdgpu_device *adev = ddc_service->ctx->driver_context;
7527         struct amdgpu_i2c_adapter *i2c;
7528
7529         i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
7530         if (!i2c)
7531                 return NULL;
7532         i2c->base.owner = THIS_MODULE;
7533         i2c->base.class = I2C_CLASS_DDC;
7534         i2c->base.dev.parent = &adev->pdev->dev;
7535         i2c->base.algo = &amdgpu_dm_i2c_algo;
7536         snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
7537         i2c_set_adapdata(&i2c->base, i2c);
7538         i2c->ddc_service = ddc_service;
7539
7540         return i2c;
7541 }
7542
7543
7544 /*
7545  * Note: this function assumes that dc_link_detect() was called for the
7546  * dc_link which will be represented by this aconnector.
7547  */
7548 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7549                                     struct amdgpu_dm_connector *aconnector,
7550                                     u32 link_index,
7551                                     struct amdgpu_encoder *aencoder)
7552 {
7553         int res = 0;
7554         int connector_type;
7555         struct dc *dc = dm->dc;
7556         struct dc_link *link = dc_get_link_at_index(dc, link_index);
7557         struct amdgpu_i2c_adapter *i2c;
7558
7559         link->priv = aconnector;
7560
7561
7562         i2c = create_i2c(link->ddc, link->link_index, &res);
7563         if (!i2c) {
7564                 DRM_ERROR("Failed to create i2c adapter data\n");
7565                 return -ENOMEM;
7566         }
7567
7568         aconnector->i2c = i2c;
7569         res = i2c_add_adapter(&i2c->base);
7570
7571         if (res) {
7572                 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7573                 goto out_free;
7574         }
7575
7576         connector_type = to_drm_connector_type(link->connector_signal);
7577
7578         res = drm_connector_init_with_ddc(
7579                         dm->ddev,
7580                         &aconnector->base,
7581                         &amdgpu_dm_connector_funcs,
7582                         connector_type,
7583                         &i2c->base);
7584
7585         if (res) {
7586                 DRM_ERROR("connector_init failed\n");
7587                 aconnector->connector_id = -1;
7588                 goto out_free;
7589         }
7590
7591         drm_connector_helper_add(
7592                         &aconnector->base,
7593                         &amdgpu_dm_connector_helper_funcs);
7594
7595         amdgpu_dm_connector_init_helper(
7596                 dm,
7597                 aconnector,
7598                 connector_type,
7599                 link,
7600                 link_index);
7601
7602         drm_connector_attach_encoder(
7603                 &aconnector->base, &aencoder->base);
7604
7605         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7606                 || connector_type == DRM_MODE_CONNECTOR_eDP)
7607                 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
7608
7609 out_free:
7610         if (res) {
7611                 kfree(i2c);
7612                 aconnector->i2c = NULL;
7613         }
7614         return res;
7615 }
7616
7617 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7618 {
7619         switch (adev->mode_info.num_crtc) {
7620         case 1:
7621                 return 0x1;
7622         case 2:
7623                 return 0x3;
7624         case 3:
7625                 return 0x7;
7626         case 4:
7627                 return 0xf;
7628         case 5:
7629                 return 0x1f;
7630         case 6:
7631         default:
7632                 return 0x3f;
7633         }
7634 }
7635
7636 static int amdgpu_dm_encoder_init(struct drm_device *dev,
7637                                   struct amdgpu_encoder *aencoder,
7638                                   uint32_t link_index)
7639 {
7640         struct amdgpu_device *adev = drm_to_adev(dev);
7641
7642         int res = drm_encoder_init(dev,
7643                                    &aencoder->base,
7644                                    &amdgpu_dm_encoder_funcs,
7645                                    DRM_MODE_ENCODER_TMDS,
7646                                    NULL);
7647
7648         aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7649
7650         if (!res)
7651                 aencoder->encoder_id = link_index;
7652         else
7653                 aencoder->encoder_id = -1;
7654
7655         drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7656
7657         return res;
7658 }
7659
7660 static void manage_dm_interrupts(struct amdgpu_device *adev,
7661                                  struct amdgpu_crtc *acrtc,
7662                                  bool enable)
7663 {
7664         /*
7665          * We have no guarantee that the frontend index maps to the same
7666          * backend index - some even map to more than one.
7667          *
7668          * TODO: Use a different interrupt or check DC itself for the mapping.
7669          */
7670         int irq_type =
7671                 amdgpu_display_crtc_idx_to_irq_type(
7672                         adev,
7673                         acrtc->crtc_id);
7674
7675         if (enable) {
7676                 drm_crtc_vblank_on(&acrtc->base);
7677                 amdgpu_irq_get(
7678                         adev,
7679                         &adev->pageflip_irq,
7680                         irq_type);
7681 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7682                 amdgpu_irq_get(
7683                         adev,
7684                         &adev->vline0_irq,
7685                         irq_type);
7686 #endif
7687         } else {
7688 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7689                 amdgpu_irq_put(
7690                         adev,
7691                         &adev->vline0_irq,
7692                         irq_type);
7693 #endif
7694                 amdgpu_irq_put(
7695                         adev,
7696                         &adev->pageflip_irq,
7697                         irq_type);
7698                 drm_crtc_vblank_off(&acrtc->base);
7699         }
7700 }
7701
7702 static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7703                                       struct amdgpu_crtc *acrtc)
7704 {
7705         int irq_type =
7706                 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7707
7708         /**
7709          * This reads the current state for the IRQ and force reapplies
7710          * the setting to hardware.
7711          */
7712         amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7713 }
7714
7715 static bool
7716 is_scaling_state_different(const struct dm_connector_state *dm_state,
7717                            const struct dm_connector_state *old_dm_state)
7718 {
7719         if (dm_state->scaling != old_dm_state->scaling)
7720                 return true;
7721         if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7722                 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7723                         return true;
7724         } else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7725                 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7726                         return true;
7727         } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7728                    dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7729                 return true;
7730         return false;
7731 }
7732
7733 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,
7734                                             struct drm_crtc_state *old_crtc_state,
7735                                             struct drm_connector_state *new_conn_state,
7736                                             struct drm_connector_state *old_conn_state,
7737                                             const struct drm_connector *connector,
7738                                             struct hdcp_workqueue *hdcp_w)
7739 {
7740         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7741         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
7742
7743         pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
7744                 connector->index, connector->status, connector->dpms);
7745         pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
7746                 old_conn_state->content_protection, new_conn_state->content_protection);
7747
7748         if (old_crtc_state)
7749                 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7750                 old_crtc_state->enable,
7751                 old_crtc_state->active,
7752                 old_crtc_state->mode_changed,
7753                 old_crtc_state->active_changed,
7754                 old_crtc_state->connectors_changed);
7755
7756         if (new_crtc_state)
7757                 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7758                 new_crtc_state->enable,
7759                 new_crtc_state->active,
7760                 new_crtc_state->mode_changed,
7761                 new_crtc_state->active_changed,
7762                 new_crtc_state->connectors_changed);
7763
7764         /* hdcp content type change */
7765         if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type &&
7766             new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7767                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7768                 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__);
7769                 return true;
7770         }
7771
7772         /* CP is being re enabled, ignore this */
7773         if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7774             new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7775                 if (new_crtc_state && new_crtc_state->mode_changed) {
7776                         new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7777                         pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__);
7778                         return true;
7779                 }
7780                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
7781                 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__);
7782                 return false;
7783         }
7784
7785         /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
7786          *
7787          * Handles:     UNDESIRED -> ENABLED
7788          */
7789         if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
7790             new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
7791                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7792
7793         /* Stream removed and re-enabled
7794          *
7795          * Can sometimes overlap with the HPD case,
7796          * thus set update_hdcp to false to avoid
7797          * setting HDCP multiple times.
7798          *
7799          * Handles:     DESIRED -> DESIRED (Special case)
7800          */
7801         if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) &&
7802                 new_conn_state->crtc && new_conn_state->crtc->enabled &&
7803                 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7804                 dm_con_state->update_hdcp = false;
7805                 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n",
7806                         __func__);
7807                 return true;
7808         }
7809
7810         /* Hot-plug, headless s3, dpms
7811          *
7812          * Only start HDCP if the display is connected/enabled.
7813          * update_hdcp flag will be set to false until the next
7814          * HPD comes in.
7815          *
7816          * Handles:     DESIRED -> DESIRED (Special case)
7817          */
7818         if (dm_con_state->update_hdcp &&
7819         new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
7820         connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
7821                 dm_con_state->update_hdcp = false;
7822                 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n",
7823                         __func__);
7824                 return true;
7825         }
7826
7827         if (old_conn_state->content_protection == new_conn_state->content_protection) {
7828                 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7829                         if (new_crtc_state && new_crtc_state->mode_changed) {
7830                                 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n",
7831                                         __func__);
7832                                 return true;
7833                         }
7834                         pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n",
7835                                 __func__);
7836                         return false;
7837                 }
7838
7839                 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__);
7840                 return false;
7841         }
7842
7843         if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
7844                 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n",
7845                         __func__);
7846                 return true;
7847         }
7848
7849         pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__);
7850         return false;
7851 }
7852
7853 static void remove_stream(struct amdgpu_device *adev,
7854                           struct amdgpu_crtc *acrtc,
7855                           struct dc_stream_state *stream)
7856 {
7857         /* this is the update mode case */
7858
7859         acrtc->otg_inst = -1;
7860         acrtc->enabled = false;
7861 }
7862
7863 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7864 {
7865
7866         assert_spin_locked(&acrtc->base.dev->event_lock);
7867         WARN_ON(acrtc->event);
7868
7869         acrtc->event = acrtc->base.state->event;
7870
7871         /* Set the flip status */
7872         acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
7873
7874         /* Mark this event as consumed */
7875         acrtc->base.state->event = NULL;
7876
7877         drm_dbg_state(acrtc->base.dev,
7878                       "crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
7879                       acrtc->crtc_id);
7880 }
7881
7882 static void update_freesync_state_on_stream(
7883         struct amdgpu_display_manager *dm,
7884         struct dm_crtc_state *new_crtc_state,
7885         struct dc_stream_state *new_stream,
7886         struct dc_plane_state *surface,
7887         u32 flip_timestamp_in_us)
7888 {
7889         struct mod_vrr_params vrr_params;
7890         struct dc_info_packet vrr_infopacket = {0};
7891         struct amdgpu_device *adev = dm->adev;
7892         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7893         unsigned long flags;
7894         bool pack_sdp_v1_3 = false;
7895         struct amdgpu_dm_connector *aconn;
7896         enum vrr_packet_type packet_type = PACKET_TYPE_VRR;
7897
7898         if (!new_stream)
7899                 return;
7900
7901         /*
7902          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7903          * For now it's sufficient to just guard against these conditions.
7904          */
7905
7906         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7907                 return;
7908
7909         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7910         vrr_params = acrtc->dm_irq_params.vrr_params;
7911
7912         if (surface) {
7913                 mod_freesync_handle_preflip(
7914                         dm->freesync_module,
7915                         surface,
7916                         new_stream,
7917                         flip_timestamp_in_us,
7918                         &vrr_params);
7919
7920                 if (adev->family < AMDGPU_FAMILY_AI &&
7921                     amdgpu_dm_crtc_vrr_active(new_crtc_state)) {
7922                         mod_freesync_handle_v_update(dm->freesync_module,
7923                                                      new_stream, &vrr_params);
7924
7925                         /* Need to call this before the frame ends. */
7926                         dc_stream_adjust_vmin_vmax(dm->dc,
7927                                                    new_crtc_state->stream,
7928                                                    &vrr_params.adjust);
7929                 }
7930         }
7931
7932         aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context;
7933
7934         if (aconn && (aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST || aconn->vsdb_info.replay_mode)) {
7935                 pack_sdp_v1_3 = aconn->pack_sdp_v1_3;
7936
7937                 if (aconn->vsdb_info.amd_vsdb_version == 1)
7938                         packet_type = PACKET_TYPE_FS_V1;
7939                 else if (aconn->vsdb_info.amd_vsdb_version == 2)
7940                         packet_type = PACKET_TYPE_FS_V2;
7941                 else if (aconn->vsdb_info.amd_vsdb_version == 3)
7942                         packet_type = PACKET_TYPE_FS_V3;
7943
7944                 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL,
7945                                         &new_stream->adaptive_sync_infopacket);
7946         }
7947
7948         mod_freesync_build_vrr_infopacket(
7949                 dm->freesync_module,
7950                 new_stream,
7951                 &vrr_params,
7952                 packet_type,
7953                 TRANSFER_FUNC_UNKNOWN,
7954                 &vrr_infopacket,
7955                 pack_sdp_v1_3);
7956
7957         new_crtc_state->freesync_vrr_info_changed |=
7958                 (memcmp(&new_crtc_state->vrr_infopacket,
7959                         &vrr_infopacket,
7960                         sizeof(vrr_infopacket)) != 0);
7961
7962         acrtc->dm_irq_params.vrr_params = vrr_params;
7963         new_crtc_state->vrr_infopacket = vrr_infopacket;
7964
7965         new_stream->vrr_infopacket = vrr_infopacket;
7966         new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params);
7967
7968         if (new_crtc_state->freesync_vrr_info_changed)
7969                 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
7970                               new_crtc_state->base.crtc->base.id,
7971                               (int)new_crtc_state->base.vrr_enabled,
7972                               (int)vrr_params.state);
7973
7974         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7975 }
7976
7977 static void update_stream_irq_parameters(
7978         struct amdgpu_display_manager *dm,
7979         struct dm_crtc_state *new_crtc_state)
7980 {
7981         struct dc_stream_state *new_stream = new_crtc_state->stream;
7982         struct mod_vrr_params vrr_params;
7983         struct mod_freesync_config config = new_crtc_state->freesync_config;
7984         struct amdgpu_device *adev = dm->adev;
7985         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7986         unsigned long flags;
7987
7988         if (!new_stream)
7989                 return;
7990
7991         /*
7992          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7993          * For now it's sufficient to just guard against these conditions.
7994          */
7995         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7996                 return;
7997
7998         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7999         vrr_params = acrtc->dm_irq_params.vrr_params;
8000
8001         if (new_crtc_state->vrr_supported &&
8002             config.min_refresh_in_uhz &&
8003             config.max_refresh_in_uhz) {
8004                 /*
8005                  * if freesync compatible mode was set, config.state will be set
8006                  * in atomic check
8007                  */
8008                 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
8009                     (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
8010                      new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
8011                         vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
8012                         vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
8013                         vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
8014                         vrr_params.state = VRR_STATE_ACTIVE_FIXED;
8015                 } else {
8016                         config.state = new_crtc_state->base.vrr_enabled ?
8017                                                      VRR_STATE_ACTIVE_VARIABLE :
8018                                                      VRR_STATE_INACTIVE;
8019                 }
8020         } else {
8021                 config.state = VRR_STATE_UNSUPPORTED;
8022         }
8023
8024         mod_freesync_build_vrr_params(dm->freesync_module,
8025                                       new_stream,
8026                                       &config, &vrr_params);
8027
8028         new_crtc_state->freesync_config = config;
8029         /* Copy state for access from DM IRQ handler */
8030         acrtc->dm_irq_params.freesync_config = config;
8031         acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
8032         acrtc->dm_irq_params.vrr_params = vrr_params;
8033         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8034 }
8035
8036 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
8037                                             struct dm_crtc_state *new_state)
8038 {
8039         bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state);
8040         bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state);
8041
8042         if (!old_vrr_active && new_vrr_active) {
8043                 /* Transition VRR inactive -> active:
8044                  * While VRR is active, we must not disable vblank irq, as a
8045                  * reenable after disable would compute bogus vblank/pflip
8046                  * timestamps if it likely happened inside display front-porch.
8047                  *
8048                  * We also need vupdate irq for the actual core vblank handling
8049                  * at end of vblank.
8050                  */
8051                 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0);
8052                 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
8053                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
8054                                  __func__, new_state->base.crtc->base.id);
8055         } else if (old_vrr_active && !new_vrr_active) {
8056                 /* Transition VRR active -> inactive:
8057                  * Allow vblank irq disable again for fixed refresh rate.
8058                  */
8059                 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0);
8060                 drm_crtc_vblank_put(new_state->base.crtc);
8061                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
8062                                  __func__, new_state->base.crtc->base.id);
8063         }
8064 }
8065
8066 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
8067 {
8068         struct drm_plane *plane;
8069         struct drm_plane_state *old_plane_state;
8070         int i;
8071
8072         /*
8073          * TODO: Make this per-stream so we don't issue redundant updates for
8074          * commits with multiple streams.
8075          */
8076         for_each_old_plane_in_state(state, plane, old_plane_state, i)
8077                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
8078                         amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state);
8079 }
8080
8081 static inline uint32_t get_mem_type(struct drm_framebuffer *fb)
8082 {
8083         struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
8084
8085         return abo->tbo.resource ? abo->tbo.resource->mem_type : 0;
8086 }
8087
8088 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
8089                                     struct drm_device *dev,
8090                                     struct amdgpu_display_manager *dm,
8091                                     struct drm_crtc *pcrtc,
8092                                     bool wait_for_vblank)
8093 {
8094         u32 i;
8095         u64 timestamp_ns = ktime_get_ns();
8096         struct drm_plane *plane;
8097         struct drm_plane_state *old_plane_state, *new_plane_state;
8098         struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
8099         struct drm_crtc_state *new_pcrtc_state =
8100                         drm_atomic_get_new_crtc_state(state, pcrtc);
8101         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
8102         struct dm_crtc_state *dm_old_crtc_state =
8103                         to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
8104         int planes_count = 0, vpos, hpos;
8105         unsigned long flags;
8106         u32 target_vblank, last_flip_vblank;
8107         bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);
8108         bool cursor_update = false;
8109         bool pflip_present = false;
8110         bool dirty_rects_changed = false;
8111         struct {
8112                 struct dc_surface_update surface_updates[MAX_SURFACES];
8113                 struct dc_plane_info plane_infos[MAX_SURFACES];
8114                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
8115                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
8116                 struct dc_stream_update stream_update;
8117         } *bundle;
8118
8119         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
8120
8121         if (!bundle) {
8122                 drm_err(dev, "Failed to allocate update bundle\n");
8123                 goto cleanup;
8124         }
8125
8126         /*
8127          * Disable the cursor first if we're disabling all the planes.
8128          * It'll remain on the screen after the planes are re-enabled
8129          * if we don't.
8130          */
8131         if (acrtc_state->active_planes == 0)
8132                 amdgpu_dm_commit_cursors(state);
8133
8134         /* update planes when needed */
8135         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
8136                 struct drm_crtc *crtc = new_plane_state->crtc;
8137                 struct drm_crtc_state *new_crtc_state;
8138                 struct drm_framebuffer *fb = new_plane_state->fb;
8139                 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
8140                 bool plane_needs_flip;
8141                 struct dc_plane_state *dc_plane;
8142                 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
8143
8144                 /* Cursor plane is handled after stream updates */
8145                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
8146                         if ((fb && crtc == pcrtc) ||
8147                             (old_plane_state->fb && old_plane_state->crtc == pcrtc))
8148                                 cursor_update = true;
8149
8150                         continue;
8151                 }
8152
8153                 if (!fb || !crtc || pcrtc != crtc)
8154                         continue;
8155
8156                 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
8157                 if (!new_crtc_state->active)
8158                         continue;
8159
8160                 dc_plane = dm_new_plane_state->dc_state;
8161                 if (!dc_plane)
8162                         continue;
8163
8164                 bundle->surface_updates[planes_count].surface = dc_plane;
8165                 if (new_pcrtc_state->color_mgmt_changed) {
8166                         bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
8167                         bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
8168                         bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
8169                 }
8170
8171                 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state,
8172                                      &bundle->scaling_infos[planes_count]);
8173
8174                 bundle->surface_updates[planes_count].scaling_info =
8175                         &bundle->scaling_infos[planes_count];
8176
8177                 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
8178
8179                 pflip_present = pflip_present || plane_needs_flip;
8180
8181                 if (!plane_needs_flip) {
8182                         planes_count += 1;
8183                         continue;
8184                 }
8185
8186                 fill_dc_plane_info_and_addr(
8187                         dm->adev, new_plane_state,
8188                         afb->tiling_flags,
8189                         &bundle->plane_infos[planes_count],
8190                         &bundle->flip_addrs[planes_count].address,
8191                         afb->tmz_surface, false);
8192
8193                 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
8194                                  new_plane_state->plane->index,
8195                                  bundle->plane_infos[planes_count].dcc.enable);
8196
8197                 bundle->surface_updates[planes_count].plane_info =
8198                         &bundle->plane_infos[planes_count];
8199
8200                 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled ||
8201                     acrtc_state->stream->link->replay_settings.replay_feature_enabled) {
8202                         fill_dc_dirty_rects(plane, old_plane_state,
8203                                             new_plane_state, new_crtc_state,
8204                                             &bundle->flip_addrs[planes_count],
8205                                             &dirty_rects_changed);
8206
8207                         /*
8208                          * If the dirty regions changed, PSR-SU need to be disabled temporarily
8209                          * and enabled it again after dirty regions are stable to avoid video glitch.
8210                          * PSR-SU will be enabled in vblank_control_worker() if user pause the video
8211                          * during the PSR-SU was disabled.
8212                          */
8213                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8214                             acrtc_attach->dm_irq_params.allow_psr_entry &&
8215 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8216                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8217 #endif
8218                             dirty_rects_changed) {
8219                                 mutex_lock(&dm->dc_lock);
8220                                 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns =
8221                                 timestamp_ns;
8222                                 if (acrtc_state->stream->link->psr_settings.psr_allow_active)
8223                                         amdgpu_dm_psr_disable(acrtc_state->stream);
8224                                 mutex_unlock(&dm->dc_lock);
8225                         }
8226                 }
8227
8228                 /*
8229                  * Only allow immediate flips for fast updates that don't
8230                  * change memory domain, FB pitch, DCC state, rotation or
8231                  * mirroring.
8232                  *
8233                  * dm_crtc_helper_atomic_check() only accepts async flips with
8234                  * fast updates.
8235                  */
8236                 if (crtc->state->async_flip &&
8237                     (acrtc_state->update_type != UPDATE_TYPE_FAST ||
8238                      get_mem_type(old_plane_state->fb) != get_mem_type(fb)))
8239                         drm_warn_once(state->dev,
8240                                       "[PLANE:%d:%s] async flip with non-fast update\n",
8241                                       plane->base.id, plane->name);
8242
8243                 bundle->flip_addrs[planes_count].flip_immediate =
8244                         crtc->state->async_flip &&
8245                         acrtc_state->update_type == UPDATE_TYPE_FAST &&
8246                         get_mem_type(old_plane_state->fb) == get_mem_type(fb);
8247
8248                 timestamp_ns = ktime_get_ns();
8249                 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
8250                 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
8251                 bundle->surface_updates[planes_count].surface = dc_plane;
8252
8253                 if (!bundle->surface_updates[planes_count].surface) {
8254                         DRM_ERROR("No surface for CRTC: id=%d\n",
8255                                         acrtc_attach->crtc_id);
8256                         continue;
8257                 }
8258
8259                 if (plane == pcrtc->primary)
8260                         update_freesync_state_on_stream(
8261                                 dm,
8262                                 acrtc_state,
8263                                 acrtc_state->stream,
8264                                 dc_plane,
8265                                 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
8266
8267                 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",
8268                                  __func__,
8269                                  bundle->flip_addrs[planes_count].address.grph.addr.high_part,
8270                                  bundle->flip_addrs[planes_count].address.grph.addr.low_part);
8271
8272                 planes_count += 1;
8273
8274         }
8275
8276         if (pflip_present) {
8277                 if (!vrr_active) {
8278                         /* Use old throttling in non-vrr fixed refresh rate mode
8279                          * to keep flip scheduling based on target vblank counts
8280                          * working in a backwards compatible way, e.g., for
8281                          * clients using the GLX_OML_sync_control extension or
8282                          * DRI3/Present extension with defined target_msc.
8283                          */
8284                         last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
8285                 } else {
8286                         /* For variable refresh rate mode only:
8287                          * Get vblank of last completed flip to avoid > 1 vrr
8288                          * flips per video frame by use of throttling, but allow
8289                          * flip programming anywhere in the possibly large
8290                          * variable vrr vblank interval for fine-grained flip
8291                          * timing control and more opportunity to avoid stutter
8292                          * on late submission of flips.
8293                          */
8294                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8295                         last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
8296                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8297                 }
8298
8299                 target_vblank = last_flip_vblank + wait_for_vblank;
8300
8301                 /*
8302                  * Wait until we're out of the vertical blank period before the one
8303                  * targeted by the flip
8304                  */
8305                 while ((acrtc_attach->enabled &&
8306                         (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
8307                                                             0, &vpos, &hpos, NULL,
8308                                                             NULL, &pcrtc->hwmode)
8309                          & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
8310                         (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
8311                         (int)(target_vblank -
8312                           amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
8313                         usleep_range(1000, 1100);
8314                 }
8315
8316                 /**
8317                  * Prepare the flip event for the pageflip interrupt to handle.
8318                  *
8319                  * This only works in the case where we've already turned on the
8320                  * appropriate hardware blocks (eg. HUBP) so in the transition case
8321                  * from 0 -> n planes we have to skip a hardware generated event
8322                  * and rely on sending it from software.
8323                  */
8324                 if (acrtc_attach->base.state->event &&
8325                     acrtc_state->active_planes > 0) {
8326                         drm_crtc_vblank_get(pcrtc);
8327
8328                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8329
8330                         WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
8331                         prepare_flip_isr(acrtc_attach);
8332
8333                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8334                 }
8335
8336                 if (acrtc_state->stream) {
8337                         if (acrtc_state->freesync_vrr_info_changed)
8338                                 bundle->stream_update.vrr_infopacket =
8339                                         &acrtc_state->stream->vrr_infopacket;
8340                 }
8341         } else if (cursor_update && acrtc_state->active_planes > 0 &&
8342                    acrtc_attach->base.state->event) {
8343                 drm_crtc_vblank_get(pcrtc);
8344
8345                 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8346
8347                 acrtc_attach->event = acrtc_attach->base.state->event;
8348                 acrtc_attach->base.state->event = NULL;
8349
8350                 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8351         }
8352
8353         /* Update the planes if changed or disable if we don't have any. */
8354         if ((planes_count || acrtc_state->active_planes == 0) &&
8355                 acrtc_state->stream) {
8356                 /*
8357                  * If PSR or idle optimizations are enabled then flush out
8358                  * any pending work before hardware programming.
8359                  */
8360                 if (dm->vblank_control_workqueue)
8361                         flush_workqueue(dm->vblank_control_workqueue);
8362
8363                 bundle->stream_update.stream = acrtc_state->stream;
8364                 if (new_pcrtc_state->mode_changed) {
8365                         bundle->stream_update.src = acrtc_state->stream->src;
8366                         bundle->stream_update.dst = acrtc_state->stream->dst;
8367                 }
8368
8369                 if (new_pcrtc_state->color_mgmt_changed) {
8370                         /*
8371                          * TODO: This isn't fully correct since we've actually
8372                          * already modified the stream in place.
8373                          */
8374                         bundle->stream_update.gamut_remap =
8375                                 &acrtc_state->stream->gamut_remap_matrix;
8376                         bundle->stream_update.output_csc_transform =
8377                                 &acrtc_state->stream->csc_color_matrix;
8378                         bundle->stream_update.out_transfer_func =
8379                                 acrtc_state->stream->out_transfer_func;
8380                 }
8381
8382                 acrtc_state->stream->abm_level = acrtc_state->abm_level;
8383                 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
8384                         bundle->stream_update.abm_level = &acrtc_state->abm_level;
8385
8386                 mutex_lock(&dm->dc_lock);
8387                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8388                                 acrtc_state->stream->link->psr_settings.psr_allow_active)
8389                         amdgpu_dm_psr_disable(acrtc_state->stream);
8390                 mutex_unlock(&dm->dc_lock);
8391
8392                 /*
8393                  * If FreeSync state on the stream has changed then we need to
8394                  * re-adjust the min/max bounds now that DC doesn't handle this
8395                  * as part of commit.
8396                  */
8397                 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
8398                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8399                         dc_stream_adjust_vmin_vmax(
8400                                 dm->dc, acrtc_state->stream,
8401                                 &acrtc_attach->dm_irq_params.vrr_params.adjust);
8402                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8403                 }
8404                 mutex_lock(&dm->dc_lock);
8405                 update_planes_and_stream_adapter(dm->dc,
8406                                          acrtc_state->update_type,
8407                                          planes_count,
8408                                          acrtc_state->stream,
8409                                          &bundle->stream_update,
8410                                          bundle->surface_updates);
8411
8412                 /**
8413                  * Enable or disable the interrupts on the backend.
8414                  *
8415                  * Most pipes are put into power gating when unused.
8416                  *
8417                  * When power gating is enabled on a pipe we lose the
8418                  * interrupt enablement state when power gating is disabled.
8419                  *
8420                  * So we need to update the IRQ control state in hardware
8421                  * whenever the pipe turns on (since it could be previously
8422                  * power gated) or off (since some pipes can't be power gated
8423                  * on some ASICs).
8424                  */
8425                 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
8426                         dm_update_pflip_irq_state(drm_to_adev(dev),
8427                                                   acrtc_attach);
8428
8429                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8430                                 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
8431                                 !acrtc_state->stream->link->psr_settings.psr_feature_enabled)
8432                         amdgpu_dm_link_setup_psr(acrtc_state->stream);
8433
8434                 /* Decrement skip count when PSR is enabled and we're doing fast updates. */
8435                 if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
8436                     acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8437                         struct amdgpu_dm_connector *aconn =
8438                                 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
8439
8440                         if (aconn->psr_skip_count > 0)
8441                                 aconn->psr_skip_count--;
8442
8443                         /* Allow PSR when skip count is 0. */
8444                         acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
8445
8446                         /*
8447                          * If sink supports PSR SU, there is no need to rely on
8448                          * a vblank event disable request to enable PSR. PSR SU
8449                          * can be enabled immediately once OS demonstrates an
8450                          * adequate number of fast atomic commits to notify KMD
8451                          * of update events. See `vblank_control_worker()`.
8452                          */
8453                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8454                             acrtc_attach->dm_irq_params.allow_psr_entry &&
8455 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8456                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8457 #endif
8458                             !acrtc_state->stream->link->psr_settings.psr_allow_active &&
8459                             (timestamp_ns -
8460                             acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) >
8461                             500000000)
8462                                 amdgpu_dm_psr_enable(acrtc_state->stream);
8463                 } else {
8464                         acrtc_attach->dm_irq_params.allow_psr_entry = false;
8465                 }
8466
8467                 mutex_unlock(&dm->dc_lock);
8468         }
8469
8470         /*
8471          * Update cursor state *after* programming all the planes.
8472          * This avoids redundant programming in the case where we're going
8473          * to be disabling a single plane - those pipes are being disabled.
8474          */
8475         if (acrtc_state->active_planes)
8476                 amdgpu_dm_commit_cursors(state);
8477
8478 cleanup:
8479         kfree(bundle);
8480 }
8481
8482 static void amdgpu_dm_commit_audio(struct drm_device *dev,
8483                                    struct drm_atomic_state *state)
8484 {
8485         struct amdgpu_device *adev = drm_to_adev(dev);
8486         struct amdgpu_dm_connector *aconnector;
8487         struct drm_connector *connector;
8488         struct drm_connector_state *old_con_state, *new_con_state;
8489         struct drm_crtc_state *new_crtc_state;
8490         struct dm_crtc_state *new_dm_crtc_state;
8491         const struct dc_stream_status *status;
8492         int i, inst;
8493
8494         /* Notify device removals. */
8495         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8496                 if (old_con_state->crtc != new_con_state->crtc) {
8497                         /* CRTC changes require notification. */
8498                         goto notify;
8499                 }
8500
8501                 if (!new_con_state->crtc)
8502                         continue;
8503
8504                 new_crtc_state = drm_atomic_get_new_crtc_state(
8505                         state, new_con_state->crtc);
8506
8507                 if (!new_crtc_state)
8508                         continue;
8509
8510                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8511                         continue;
8512
8513 notify:
8514                 aconnector = to_amdgpu_dm_connector(connector);
8515
8516                 mutex_lock(&adev->dm.audio_lock);
8517                 inst = aconnector->audio_inst;
8518                 aconnector->audio_inst = -1;
8519                 mutex_unlock(&adev->dm.audio_lock);
8520
8521                 amdgpu_dm_audio_eld_notify(adev, inst);
8522         }
8523
8524         /* Notify audio device additions. */
8525         for_each_new_connector_in_state(state, connector, new_con_state, i) {
8526                 if (!new_con_state->crtc)
8527                         continue;
8528
8529                 new_crtc_state = drm_atomic_get_new_crtc_state(
8530                         state, new_con_state->crtc);
8531
8532                 if (!new_crtc_state)
8533                         continue;
8534
8535                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8536                         continue;
8537
8538                 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
8539                 if (!new_dm_crtc_state->stream)
8540                         continue;
8541
8542                 status = dc_stream_get_status(new_dm_crtc_state->stream);
8543                 if (!status)
8544                         continue;
8545
8546                 aconnector = to_amdgpu_dm_connector(connector);
8547
8548                 mutex_lock(&adev->dm.audio_lock);
8549                 inst = status->audio_inst;
8550                 aconnector->audio_inst = inst;
8551                 mutex_unlock(&adev->dm.audio_lock);
8552
8553                 amdgpu_dm_audio_eld_notify(adev, inst);
8554         }
8555 }
8556
8557 /*
8558  * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
8559  * @crtc_state: the DRM CRTC state
8560  * @stream_state: the DC stream state.
8561  *
8562  * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
8563  * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
8564  */
8565 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
8566                                                 struct dc_stream_state *stream_state)
8567 {
8568         stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
8569 }
8570
8571 static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,
8572                                         struct dc_state *dc_state)
8573 {
8574         struct drm_device *dev = state->dev;
8575         struct amdgpu_device *adev = drm_to_adev(dev);
8576         struct amdgpu_display_manager *dm = &adev->dm;
8577         struct drm_crtc *crtc;
8578         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8579         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8580         bool mode_set_reset_required = false;
8581         u32 i;
8582
8583         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
8584                                       new_crtc_state, i) {
8585                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8586
8587                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8588
8589                 if (old_crtc_state->active &&
8590                     (!new_crtc_state->active ||
8591                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8592                         manage_dm_interrupts(adev, acrtc, false);
8593                         dc_stream_release(dm_old_crtc_state->stream);
8594                 }
8595         }
8596
8597         drm_atomic_helper_calc_timestamping_constants(state);
8598
8599         /* update changed items */
8600         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8601                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8602
8603                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8604                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8605
8606                 drm_dbg_state(state->dev,
8607                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
8608                         acrtc->crtc_id,
8609                         new_crtc_state->enable,
8610                         new_crtc_state->active,
8611                         new_crtc_state->planes_changed,
8612                         new_crtc_state->mode_changed,
8613                         new_crtc_state->active_changed,
8614                         new_crtc_state->connectors_changed);
8615
8616                 /* Disable cursor if disabling crtc */
8617                 if (old_crtc_state->active && !new_crtc_state->active) {
8618                         struct dc_cursor_position position;
8619
8620                         memset(&position, 0, sizeof(position));
8621                         mutex_lock(&dm->dc_lock);
8622                         dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8623                         mutex_unlock(&dm->dc_lock);
8624                 }
8625
8626                 /* Copy all transient state flags into dc state */
8627                 if (dm_new_crtc_state->stream) {
8628                         amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8629                                                             dm_new_crtc_state->stream);
8630                 }
8631
8632                 /* handles headless hotplug case, updating new_state and
8633                  * aconnector as needed
8634                  */
8635
8636                 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
8637
8638                         DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
8639
8640                         if (!dm_new_crtc_state->stream) {
8641                                 /*
8642                                  * this could happen because of issues with
8643                                  * userspace notifications delivery.
8644                                  * In this case userspace tries to set mode on
8645                                  * display which is disconnected in fact.
8646                                  * dc_sink is NULL in this case on aconnector.
8647                                  * We expect reset mode will come soon.
8648                                  *
8649                                  * This can also happen when unplug is done
8650                                  * during resume sequence ended
8651                                  *
8652                                  * In this case, we want to pretend we still
8653                                  * have a sink to keep the pipe running so that
8654                                  * hw state is consistent with the sw state
8655                                  */
8656                                 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8657                                                 __func__, acrtc->base.base.id);
8658                                 continue;
8659                         }
8660
8661                         if (dm_old_crtc_state->stream)
8662                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8663
8664                         pm_runtime_get_noresume(dev->dev);
8665
8666                         acrtc->enabled = true;
8667                         acrtc->hw_mode = new_crtc_state->mode;
8668                         crtc->hwmode = new_crtc_state->mode;
8669                         mode_set_reset_required = true;
8670                 } else if (modereset_required(new_crtc_state)) {
8671                         DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
8672                         /* i.e. reset mode */
8673                         if (dm_old_crtc_state->stream)
8674                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8675
8676                         mode_set_reset_required = true;
8677                 }
8678         } /* for_each_crtc_in_state() */
8679
8680         /* if there mode set or reset, disable eDP PSR */
8681         if (mode_set_reset_required) {
8682                 if (dm->vblank_control_workqueue)
8683                         flush_workqueue(dm->vblank_control_workqueue);
8684
8685                 amdgpu_dm_psr_disable_all(dm);
8686         }
8687
8688         dm_enable_per_frame_crtc_master_sync(dc_state);
8689         mutex_lock(&dm->dc_lock);
8690         WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
8691
8692         /* Allow idle optimization when vblank count is 0 for display off */
8693         if (dm->active_vblank_irq_count == 0)
8694                 dc_allow_idle_optimizations(dm->dc, true);
8695         mutex_unlock(&dm->dc_lock);
8696
8697         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8698                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8699
8700                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8701
8702                 if (dm_new_crtc_state->stream != NULL) {
8703                         const struct dc_stream_status *status =
8704                                         dc_stream_get_status(dm_new_crtc_state->stream);
8705
8706                         if (!status)
8707                                 status = dc_stream_get_status_from_state(dc_state,
8708                                                                          dm_new_crtc_state->stream);
8709                         if (!status)
8710                                 drm_err(dev,
8711                                         "got no status for stream %p on acrtc%p\n",
8712                                         dm_new_crtc_state->stream, acrtc);
8713                         else
8714                                 acrtc->otg_inst = status->primary_otg_inst;
8715                 }
8716         }
8717 }
8718
8719 /**
8720  * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
8721  * @state: The atomic state to commit
8722  *
8723  * This will tell DC to commit the constructed DC state from atomic_check,
8724  * programming the hardware. Any failures here implies a hardware failure, since
8725  * atomic check should have filtered anything non-kosher.
8726  */
8727 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
8728 {
8729         struct drm_device *dev = state->dev;
8730         struct amdgpu_device *adev = drm_to_adev(dev);
8731         struct amdgpu_display_manager *dm = &adev->dm;
8732         struct dm_atomic_state *dm_state;
8733         struct dc_state *dc_state = NULL;
8734         u32 i, j;
8735         struct drm_crtc *crtc;
8736         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8737         unsigned long flags;
8738         bool wait_for_vblank = true;
8739         struct drm_connector *connector;
8740         struct drm_connector_state *old_con_state, *new_con_state;
8741         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8742         int crtc_disable_count = 0;
8743
8744         trace_amdgpu_dm_atomic_commit_tail_begin(state);
8745
8746         if (dm->dc->caps.ips_support) {
8747                 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8748                         if (new_con_state->crtc &&
8749                                 new_con_state->crtc->state->active &&
8750                                 drm_atomic_crtc_needs_modeset(new_con_state->crtc->state)) {
8751                                 dc_dmub_srv_exit_low_power_state(dm->dc);
8752                                 break;
8753                         }
8754                 }
8755         }
8756
8757         drm_atomic_helper_update_legacy_modeset_state(dev, state);
8758         drm_dp_mst_atomic_wait_for_dependencies(state);
8759
8760         dm_state = dm_atomic_get_new_state(state);
8761         if (dm_state && dm_state->context) {
8762                 dc_state = dm_state->context;
8763                 amdgpu_dm_commit_streams(state, dc_state);
8764         }
8765
8766         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8767                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8768                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8769                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8770
8771                 if (!adev->dm.hdcp_workqueue)
8772                         continue;
8773
8774                 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);
8775
8776                 if (!connector)
8777                         continue;
8778
8779                 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
8780                         connector->index, connector->status, connector->dpms);
8781                 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
8782                         old_con_state->content_protection, new_con_state->content_protection);
8783
8784                 if (aconnector->dc_sink) {
8785                         if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
8786                                 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) {
8787                                 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",
8788                                 aconnector->dc_sink->edid_caps.display_name);
8789                         }
8790                 }
8791
8792                 new_crtc_state = NULL;
8793                 old_crtc_state = NULL;
8794
8795                 if (acrtc) {
8796                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8797                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8798                 }
8799
8800                 if (old_crtc_state)
8801                         pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8802                         old_crtc_state->enable,
8803                         old_crtc_state->active,
8804                         old_crtc_state->mode_changed,
8805                         old_crtc_state->active_changed,
8806                         old_crtc_state->connectors_changed);
8807
8808                 if (new_crtc_state)
8809                         pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8810                         new_crtc_state->enable,
8811                         new_crtc_state->active,
8812                         new_crtc_state->mode_changed,
8813                         new_crtc_state->active_changed,
8814                         new_crtc_state->connectors_changed);
8815         }
8816
8817         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8818                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8819                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8820                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8821
8822                 if (!adev->dm.hdcp_workqueue)
8823                         continue;
8824
8825                 new_crtc_state = NULL;
8826                 old_crtc_state = NULL;
8827
8828                 if (acrtc) {
8829                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8830                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8831                 }
8832
8833                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8834
8835                 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
8836                     connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8837                         hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
8838                         new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8839                         dm_new_con_state->update_hdcp = true;
8840                         continue;
8841                 }
8842
8843                 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state,
8844                                                                                         old_con_state, connector, adev->dm.hdcp_workqueue)) {
8845                         /* when display is unplugged from mst hub, connctor will
8846                          * be destroyed within dm_dp_mst_connector_destroy. connector
8847                          * hdcp perperties, like type, undesired, desired, enabled,
8848                          * will be lost. So, save hdcp properties into hdcp_work within
8849                          * amdgpu_dm_atomic_commit_tail. if the same display is
8850                          * plugged back with same display index, its hdcp properties
8851                          * will be retrieved from hdcp_work within dm_dp_mst_get_modes
8852                          */
8853
8854                         bool enable_encryption = false;
8855
8856                         if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
8857                                 enable_encryption = true;
8858
8859                         if (aconnector->dc_link && aconnector->dc_sink &&
8860                                 aconnector->dc_link->type == dc_connection_mst_branch) {
8861                                 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
8862                                 struct hdcp_workqueue *hdcp_w =
8863                                         &hdcp_work[aconnector->dc_link->link_index];
8864
8865                                 hdcp_w->hdcp_content_type[connector->index] =
8866                                         new_con_state->hdcp_content_type;
8867                                 hdcp_w->content_protection[connector->index] =
8868                                         new_con_state->content_protection;
8869                         }
8870
8871                         if (new_crtc_state && new_crtc_state->mode_changed &&
8872                                 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED)
8873                                 enable_encryption = true;
8874
8875                         DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);
8876
8877                         hdcp_update_display(
8878                                 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
8879                                 new_con_state->hdcp_content_type, enable_encryption);
8880                 }
8881         }
8882
8883         /* Handle connector state changes */
8884         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8885                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8886                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8887                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8888                 struct dc_surface_update *dummy_updates;
8889                 struct dc_stream_update stream_update;
8890                 struct dc_info_packet hdr_packet;
8891                 struct dc_stream_status *status = NULL;
8892                 bool abm_changed, hdr_changed, scaling_changed;
8893
8894                 memset(&stream_update, 0, sizeof(stream_update));
8895
8896                 if (acrtc) {
8897                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8898                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8899                 }
8900
8901                 /* Skip any modesets/resets */
8902                 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
8903                         continue;
8904
8905                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8906                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8907
8908                 scaling_changed = is_scaling_state_different(dm_new_con_state,
8909                                                              dm_old_con_state);
8910
8911                 abm_changed = dm_new_crtc_state->abm_level !=
8912                               dm_old_crtc_state->abm_level;
8913
8914                 hdr_changed =
8915                         !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
8916
8917                 if (!scaling_changed && !abm_changed && !hdr_changed)
8918                         continue;
8919
8920                 stream_update.stream = dm_new_crtc_state->stream;
8921                 if (scaling_changed) {
8922                         update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
8923                                         dm_new_con_state, dm_new_crtc_state->stream);
8924
8925                         stream_update.src = dm_new_crtc_state->stream->src;
8926                         stream_update.dst = dm_new_crtc_state->stream->dst;
8927                 }
8928
8929                 if (abm_changed) {
8930                         dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
8931
8932                         stream_update.abm_level = &dm_new_crtc_state->abm_level;
8933                 }
8934
8935                 if (hdr_changed) {
8936                         fill_hdr_info_packet(new_con_state, &hdr_packet);
8937                         stream_update.hdr_static_metadata = &hdr_packet;
8938                 }
8939
8940                 status = dc_stream_get_status(dm_new_crtc_state->stream);
8941
8942                 if (WARN_ON(!status))
8943                         continue;
8944
8945                 WARN_ON(!status->plane_count);
8946
8947                 /*
8948                  * TODO: DC refuses to perform stream updates without a dc_surface_update.
8949                  * Here we create an empty update on each plane.
8950                  * To fix this, DC should permit updating only stream properties.
8951                  */
8952                 dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_ATOMIC);
8953                 for (j = 0; j < status->plane_count; j++)
8954                         dummy_updates[j].surface = status->plane_states[0];
8955
8956
8957                 mutex_lock(&dm->dc_lock);
8958                 dc_update_planes_and_stream(dm->dc,
8959                                             dummy_updates,
8960                                             status->plane_count,
8961                                             dm_new_crtc_state->stream,
8962                                             &stream_update);
8963                 mutex_unlock(&dm->dc_lock);
8964                 kfree(dummy_updates);
8965         }
8966
8967         /**
8968          * Enable interrupts for CRTCs that are newly enabled or went through
8969          * a modeset. It was intentionally deferred until after the front end
8970          * state was modified to wait until the OTG was on and so the IRQ
8971          * handlers didn't access stale or invalid state.
8972          */
8973         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8974                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8975 #ifdef CONFIG_DEBUG_FS
8976                 enum amdgpu_dm_pipe_crc_source cur_crc_src;
8977 #endif
8978                 /* Count number of newly disabled CRTCs for dropping PM refs later. */
8979                 if (old_crtc_state->active && !new_crtc_state->active)
8980                         crtc_disable_count++;
8981
8982                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8983                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8984
8985                 /* For freesync config update on crtc state and params for irq */
8986                 update_stream_irq_parameters(dm, dm_new_crtc_state);
8987
8988 #ifdef CONFIG_DEBUG_FS
8989                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8990                 cur_crc_src = acrtc->dm_irq_params.crc_src;
8991                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8992 #endif
8993
8994                 if (new_crtc_state->active &&
8995                     (!old_crtc_state->active ||
8996                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8997                         dc_stream_retain(dm_new_crtc_state->stream);
8998                         acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
8999                         manage_dm_interrupts(adev, acrtc, true);
9000                 }
9001                 /* Handle vrr on->off / off->on transitions */
9002                 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
9003
9004 #ifdef CONFIG_DEBUG_FS
9005                 if (new_crtc_state->active &&
9006                     (!old_crtc_state->active ||
9007                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
9008                         /**
9009                          * Frontend may have changed so reapply the CRC capture
9010                          * settings for the stream.
9011                          */
9012                         if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
9013 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
9014                                 if (amdgpu_dm_crc_window_is_activated(crtc)) {
9015                                         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
9016                                         acrtc->dm_irq_params.window_param.update_win = true;
9017
9018                                         /**
9019                                          * It takes 2 frames for HW to stably generate CRC when
9020                                          * resuming from suspend, so we set skip_frame_cnt 2.
9021                                          */
9022                                         acrtc->dm_irq_params.window_param.skip_frame_cnt = 2;
9023                                         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
9024                                 }
9025 #endif
9026                                 if (amdgpu_dm_crtc_configure_crc_source(
9027                                         crtc, dm_new_crtc_state, cur_crc_src))
9028                                         DRM_DEBUG_DRIVER("Failed to configure crc source");
9029                         }
9030                 }
9031 #endif
9032         }
9033
9034         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
9035                 if (new_crtc_state->async_flip)
9036                         wait_for_vblank = false;
9037
9038         /* update planes when needed per crtc*/
9039         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
9040                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9041
9042                 if (dm_new_crtc_state->stream)
9043                         amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank);
9044         }
9045
9046         /* Update audio instances for each connector. */
9047         amdgpu_dm_commit_audio(dev, state);
9048
9049         /* restore the backlight level */
9050         for (i = 0; i < dm->num_of_edps; i++) {
9051                 if (dm->backlight_dev[i] &&
9052                     (dm->actual_brightness[i] != dm->brightness[i]))
9053                         amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
9054         }
9055
9056         /*
9057          * send vblank event on all events not handled in flip and
9058          * mark consumed event for drm_atomic_helper_commit_hw_done
9059          */
9060         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
9061         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
9062
9063                 if (new_crtc_state->event)
9064                         drm_send_event_locked(dev, &new_crtc_state->event->base);
9065
9066                 new_crtc_state->event = NULL;
9067         }
9068         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
9069
9070         /* Signal HW programming completion */
9071         drm_atomic_helper_commit_hw_done(state);
9072
9073         if (wait_for_vblank)
9074                 drm_atomic_helper_wait_for_flip_done(dev, state);
9075
9076         drm_atomic_helper_cleanup_planes(dev, state);
9077
9078         /* Don't free the memory if we are hitting this as part of suspend.
9079          * This way we don't free any memory during suspend; see
9080          * amdgpu_bo_free_kernel().  The memory will be freed in the first
9081          * non-suspend modeset or when the driver is torn down.
9082          */
9083         if (!adev->in_suspend) {
9084                 /* return the stolen vga memory back to VRAM */
9085                 if (!adev->mman.keep_stolen_vga_memory)
9086                         amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
9087                 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
9088         }
9089
9090         /*
9091          * Finally, drop a runtime PM reference for each newly disabled CRTC,
9092          * so we can put the GPU into runtime suspend if we're not driving any
9093          * displays anymore
9094          */
9095         for (i = 0; i < crtc_disable_count; i++)
9096                 pm_runtime_put_autosuspend(dev->dev);
9097         pm_runtime_mark_last_busy(dev->dev);
9098 }
9099
9100 static int dm_force_atomic_commit(struct drm_connector *connector)
9101 {
9102         int ret = 0;
9103         struct drm_device *ddev = connector->dev;
9104         struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
9105         struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
9106         struct drm_plane *plane = disconnected_acrtc->base.primary;
9107         struct drm_connector_state *conn_state;
9108         struct drm_crtc_state *crtc_state;
9109         struct drm_plane_state *plane_state;
9110
9111         if (!state)
9112                 return -ENOMEM;
9113
9114         state->acquire_ctx = ddev->mode_config.acquire_ctx;
9115
9116         /* Construct an atomic state to restore previous display setting */
9117
9118         /*
9119          * Attach connectors to drm_atomic_state
9120          */
9121         conn_state = drm_atomic_get_connector_state(state, connector);
9122
9123         ret = PTR_ERR_OR_ZERO(conn_state);
9124         if (ret)
9125                 goto out;
9126
9127         /* Attach crtc to drm_atomic_state*/
9128         crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
9129
9130         ret = PTR_ERR_OR_ZERO(crtc_state);
9131         if (ret)
9132                 goto out;
9133
9134         /* force a restore */
9135         crtc_state->mode_changed = true;
9136
9137         /* Attach plane to drm_atomic_state */
9138         plane_state = drm_atomic_get_plane_state(state, plane);
9139
9140         ret = PTR_ERR_OR_ZERO(plane_state);
9141         if (ret)
9142                 goto out;
9143
9144         /* Call commit internally with the state we just constructed */
9145         ret = drm_atomic_commit(state);
9146
9147 out:
9148         drm_atomic_state_put(state);
9149         if (ret)
9150                 DRM_ERROR("Restoring old state failed with %i\n", ret);
9151
9152         return ret;
9153 }
9154
9155 /*
9156  * This function handles all cases when set mode does not come upon hotplug.
9157  * This includes when a display is unplugged then plugged back into the
9158  * same port and when running without usermode desktop manager supprot
9159  */
9160 void dm_restore_drm_connector_state(struct drm_device *dev,
9161                                     struct drm_connector *connector)
9162 {
9163         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
9164         struct amdgpu_crtc *disconnected_acrtc;
9165         struct dm_crtc_state *acrtc_state;
9166
9167         if (!aconnector->dc_sink || !connector->state || !connector->encoder)
9168                 return;
9169
9170         disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
9171         if (!disconnected_acrtc)
9172                 return;
9173
9174         acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
9175         if (!acrtc_state->stream)
9176                 return;
9177
9178         /*
9179          * If the previous sink is not released and different from the current,
9180          * we deduce we are in a state where we can not rely on usermode call
9181          * to turn on the display, so we do it here
9182          */
9183         if (acrtc_state->stream->sink != aconnector->dc_sink)
9184                 dm_force_atomic_commit(&aconnector->base);
9185 }
9186
9187 /*
9188  * Grabs all modesetting locks to serialize against any blocking commits,
9189  * Waits for completion of all non blocking commits.
9190  */
9191 static int do_aquire_global_lock(struct drm_device *dev,
9192                                  struct drm_atomic_state *state)
9193 {
9194         struct drm_crtc *crtc;
9195         struct drm_crtc_commit *commit;
9196         long ret;
9197
9198         /*
9199          * Adding all modeset locks to aquire_ctx will
9200          * ensure that when the framework release it the
9201          * extra locks we are locking here will get released to
9202          */
9203         ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
9204         if (ret)
9205                 return ret;
9206
9207         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9208                 spin_lock(&crtc->commit_lock);
9209                 commit = list_first_entry_or_null(&crtc->commit_list,
9210                                 struct drm_crtc_commit, commit_entry);
9211                 if (commit)
9212                         drm_crtc_commit_get(commit);
9213                 spin_unlock(&crtc->commit_lock);
9214
9215                 if (!commit)
9216                         continue;
9217
9218                 /*
9219                  * Make sure all pending HW programming completed and
9220                  * page flips done
9221                  */
9222                 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
9223
9224                 if (ret > 0)
9225                         ret = wait_for_completion_interruptible_timeout(
9226                                         &commit->flip_done, 10*HZ);
9227
9228                 if (ret == 0)
9229                         DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done timed out\n",
9230                                   crtc->base.id, crtc->name);
9231
9232                 drm_crtc_commit_put(commit);
9233         }
9234
9235         return ret < 0 ? ret : 0;
9236 }
9237
9238 static void get_freesync_config_for_crtc(
9239         struct dm_crtc_state *new_crtc_state,
9240         struct dm_connector_state *new_con_state)
9241 {
9242         struct mod_freesync_config config = {0};
9243         struct amdgpu_dm_connector *aconnector =
9244                         to_amdgpu_dm_connector(new_con_state->base.connector);
9245         struct drm_display_mode *mode = &new_crtc_state->base.mode;
9246         int vrefresh = drm_mode_vrefresh(mode);
9247         bool fs_vid_mode = false;
9248
9249         new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
9250                                         vrefresh >= aconnector->min_vfreq &&
9251                                         vrefresh <= aconnector->max_vfreq;
9252
9253         if (new_crtc_state->vrr_supported) {
9254                 new_crtc_state->stream->ignore_msa_timing_param = true;
9255                 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
9256
9257                 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
9258                 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
9259                 config.vsif_supported = true;
9260                 config.btr = true;
9261
9262                 if (fs_vid_mode) {
9263                         config.state = VRR_STATE_ACTIVE_FIXED;
9264                         config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
9265                         goto out;
9266                 } else if (new_crtc_state->base.vrr_enabled) {
9267                         config.state = VRR_STATE_ACTIVE_VARIABLE;
9268                 } else {
9269                         config.state = VRR_STATE_INACTIVE;
9270                 }
9271         }
9272 out:
9273         new_crtc_state->freesync_config = config;
9274 }
9275
9276 static void reset_freesync_config_for_crtc(
9277         struct dm_crtc_state *new_crtc_state)
9278 {
9279         new_crtc_state->vrr_supported = false;
9280
9281         memset(&new_crtc_state->vrr_infopacket, 0,
9282                sizeof(new_crtc_state->vrr_infopacket));
9283 }
9284
9285 static bool
9286 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
9287                                  struct drm_crtc_state *new_crtc_state)
9288 {
9289         const struct drm_display_mode *old_mode, *new_mode;
9290
9291         if (!old_crtc_state || !new_crtc_state)
9292                 return false;
9293
9294         old_mode = &old_crtc_state->mode;
9295         new_mode = &new_crtc_state->mode;
9296
9297         if (old_mode->clock       == new_mode->clock &&
9298             old_mode->hdisplay    == new_mode->hdisplay &&
9299             old_mode->vdisplay    == new_mode->vdisplay &&
9300             old_mode->htotal      == new_mode->htotal &&
9301             old_mode->vtotal      != new_mode->vtotal &&
9302             old_mode->hsync_start == new_mode->hsync_start &&
9303             old_mode->vsync_start != new_mode->vsync_start &&
9304             old_mode->hsync_end   == new_mode->hsync_end &&
9305             old_mode->vsync_end   != new_mode->vsync_end &&
9306             old_mode->hskew       == new_mode->hskew &&
9307             old_mode->vscan       == new_mode->vscan &&
9308             (old_mode->vsync_end - old_mode->vsync_start) ==
9309             (new_mode->vsync_end - new_mode->vsync_start))
9310                 return true;
9311
9312         return false;
9313 }
9314
9315 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state)
9316 {
9317         u64 num, den, res;
9318         struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
9319
9320         dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
9321
9322         num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
9323         den = (unsigned long long)new_crtc_state->mode.htotal *
9324               (unsigned long long)new_crtc_state->mode.vtotal;
9325
9326         res = div_u64(num, den);
9327         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
9328 }
9329
9330 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
9331                          struct drm_atomic_state *state,
9332                          struct drm_crtc *crtc,
9333                          struct drm_crtc_state *old_crtc_state,
9334                          struct drm_crtc_state *new_crtc_state,
9335                          bool enable,
9336                          bool *lock_and_validation_needed)
9337 {
9338         struct dm_atomic_state *dm_state = NULL;
9339         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9340         struct dc_stream_state *new_stream;
9341         int ret = 0;
9342
9343         /*
9344          * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
9345          * update changed items
9346          */
9347         struct amdgpu_crtc *acrtc = NULL;
9348         struct amdgpu_dm_connector *aconnector = NULL;
9349         struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
9350         struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
9351
9352         new_stream = NULL;
9353
9354         dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9355         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9356         acrtc = to_amdgpu_crtc(crtc);
9357         aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
9358
9359         /* TODO This hack should go away */
9360         if (aconnector && enable) {
9361                 /* Make sure fake sink is created in plug-in scenario */
9362                 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
9363                                                             &aconnector->base);
9364                 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
9365                                                             &aconnector->base);
9366
9367                 if (IS_ERR(drm_new_conn_state)) {
9368                         ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
9369                         goto fail;
9370                 }
9371
9372                 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
9373                 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
9374
9375                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9376                         goto skip_modeset;
9377
9378                 new_stream = create_validate_stream_for_sink(aconnector,
9379                                                              &new_crtc_state->mode,
9380                                                              dm_new_conn_state,
9381                                                              dm_old_crtc_state->stream);
9382
9383                 /*
9384                  * we can have no stream on ACTION_SET if a display
9385                  * was disconnected during S3, in this case it is not an
9386                  * error, the OS will be updated after detection, and
9387                  * will do the right thing on next atomic commit
9388                  */
9389
9390                 if (!new_stream) {
9391                         DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
9392                                         __func__, acrtc->base.base.id);
9393                         ret = -ENOMEM;
9394                         goto fail;
9395                 }
9396
9397                 /*
9398                  * TODO: Check VSDB bits to decide whether this should
9399                  * be enabled or not.
9400                  */
9401                 new_stream->triggered_crtc_reset.enabled =
9402                         dm->force_timing_sync;
9403
9404                 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9405
9406                 ret = fill_hdr_info_packet(drm_new_conn_state,
9407                                            &new_stream->hdr_static_metadata);
9408                 if (ret)
9409                         goto fail;
9410
9411                 /*
9412                  * If we already removed the old stream from the context
9413                  * (and set the new stream to NULL) then we can't reuse
9414                  * the old stream even if the stream and scaling are unchanged.
9415                  * We'll hit the BUG_ON and black screen.
9416                  *
9417                  * TODO: Refactor this function to allow this check to work
9418                  * in all conditions.
9419                  */
9420                 if (dm_new_crtc_state->stream &&
9421                     is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
9422                         goto skip_modeset;
9423
9424                 if (dm_new_crtc_state->stream &&
9425                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9426                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
9427                         new_crtc_state->mode_changed = false;
9428                         DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
9429                                          new_crtc_state->mode_changed);
9430                 }
9431         }
9432
9433         /* mode_changed flag may get updated above, need to check again */
9434         if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9435                 goto skip_modeset;
9436
9437         drm_dbg_state(state->dev,
9438                 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
9439                 acrtc->crtc_id,
9440                 new_crtc_state->enable,
9441                 new_crtc_state->active,
9442                 new_crtc_state->planes_changed,
9443                 new_crtc_state->mode_changed,
9444                 new_crtc_state->active_changed,
9445                 new_crtc_state->connectors_changed);
9446
9447         /* Remove stream for any changed/disabled CRTC */
9448         if (!enable) {
9449
9450                 if (!dm_old_crtc_state->stream)
9451                         goto skip_modeset;
9452
9453                 /* Unset freesync video if it was active before */
9454                 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) {
9455                         dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE;
9456                         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0;
9457                 }
9458
9459                 /* Now check if we should set freesync video mode */
9460                 if (dm_new_crtc_state->stream &&
9461                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9462                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) &&
9463                     is_timing_unchanged_for_freesync(new_crtc_state,
9464                                                      old_crtc_state)) {
9465                         new_crtc_state->mode_changed = false;
9466                         DRM_DEBUG_DRIVER(
9467                                 "Mode change not required for front porch change, setting mode_changed to %d",
9468                                 new_crtc_state->mode_changed);
9469
9470                         set_freesync_fixed_config(dm_new_crtc_state);
9471
9472                         goto skip_modeset;
9473                 } else if (aconnector &&
9474                            is_freesync_video_mode(&new_crtc_state->mode,
9475                                                   aconnector)) {
9476                         struct drm_display_mode *high_mode;
9477
9478                         high_mode = get_highest_refresh_rate_mode(aconnector, false);
9479                         if (!drm_mode_equal(&new_crtc_state->mode, high_mode))
9480                                 set_freesync_fixed_config(dm_new_crtc_state);
9481                 }
9482
9483                 ret = dm_atomic_get_state(state, &dm_state);
9484                 if (ret)
9485                         goto fail;
9486
9487                 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
9488                                 crtc->base.id);
9489
9490                 /* i.e. reset mode */
9491                 if (dc_remove_stream_from_ctx(
9492                                 dm->dc,
9493                                 dm_state->context,
9494                                 dm_old_crtc_state->stream) != DC_OK) {
9495                         ret = -EINVAL;
9496                         goto fail;
9497                 }
9498
9499                 dc_stream_release(dm_old_crtc_state->stream);
9500                 dm_new_crtc_state->stream = NULL;
9501
9502                 reset_freesync_config_for_crtc(dm_new_crtc_state);
9503
9504                 *lock_and_validation_needed = true;
9505
9506         } else {/* Add stream for any updated/enabled CRTC */
9507                 /*
9508                  * Quick fix to prevent NULL pointer on new_stream when
9509                  * added MST connectors not found in existing crtc_state in the chained mode
9510                  * TODO: need to dig out the root cause of that
9511                  */
9512                 if (!aconnector)
9513                         goto skip_modeset;
9514
9515                 if (modereset_required(new_crtc_state))
9516                         goto skip_modeset;
9517
9518                 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream,
9519                                      dm_old_crtc_state->stream)) {
9520
9521                         WARN_ON(dm_new_crtc_state->stream);
9522
9523                         ret = dm_atomic_get_state(state, &dm_state);
9524                         if (ret)
9525                                 goto fail;
9526
9527                         dm_new_crtc_state->stream = new_stream;
9528
9529                         dc_stream_retain(new_stream);
9530
9531                         DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
9532                                          crtc->base.id);
9533
9534                         if (dc_add_stream_to_ctx(
9535                                         dm->dc,
9536                                         dm_state->context,
9537                                         dm_new_crtc_state->stream) != DC_OK) {
9538                                 ret = -EINVAL;
9539                                 goto fail;
9540                         }
9541
9542                         *lock_and_validation_needed = true;
9543                 }
9544         }
9545
9546 skip_modeset:
9547         /* Release extra reference */
9548         if (new_stream)
9549                 dc_stream_release(new_stream);
9550
9551         /*
9552          * We want to do dc stream updates that do not require a
9553          * full modeset below.
9554          */
9555         if (!(enable && aconnector && new_crtc_state->active))
9556                 return 0;
9557         /*
9558          * Given above conditions, the dc state cannot be NULL because:
9559          * 1. We're in the process of enabling CRTCs (just been added
9560          *    to the dc context, or already is on the context)
9561          * 2. Has a valid connector attached, and
9562          * 3. Is currently active and enabled.
9563          * => The dc stream state currently exists.
9564          */
9565         BUG_ON(dm_new_crtc_state->stream == NULL);
9566
9567         /* Scaling or underscan settings */
9568         if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
9569                                 drm_atomic_crtc_needs_modeset(new_crtc_state))
9570                 update_stream_scaling_settings(
9571                         &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
9572
9573         /* ABM settings */
9574         dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9575
9576         /*
9577          * Color management settings. We also update color properties
9578          * when a modeset is needed, to ensure it gets reprogrammed.
9579          */
9580         if (dm_new_crtc_state->base.color_mgmt_changed ||
9581             drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9582                 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
9583                 if (ret)
9584                         goto fail;
9585         }
9586
9587         /* Update Freesync settings. */
9588         get_freesync_config_for_crtc(dm_new_crtc_state,
9589                                      dm_new_conn_state);
9590
9591         return ret;
9592
9593 fail:
9594         if (new_stream)
9595                 dc_stream_release(new_stream);
9596         return ret;
9597 }
9598
9599 static bool should_reset_plane(struct drm_atomic_state *state,
9600                                struct drm_plane *plane,
9601                                struct drm_plane_state *old_plane_state,
9602                                struct drm_plane_state *new_plane_state)
9603 {
9604         struct drm_plane *other;
9605         struct drm_plane_state *old_other_state, *new_other_state;
9606         struct drm_crtc_state *new_crtc_state;
9607         int i;
9608
9609         /*
9610          * TODO: Remove this hack once the checks below are sufficient
9611          * enough to determine when we need to reset all the planes on
9612          * the stream.
9613          */
9614         if (state->allow_modeset)
9615                 return true;
9616
9617         /* Exit early if we know that we're adding or removing the plane. */
9618         if (old_plane_state->crtc != new_plane_state->crtc)
9619                 return true;
9620
9621         /* old crtc == new_crtc == NULL, plane not in context. */
9622         if (!new_plane_state->crtc)
9623                 return false;
9624
9625         new_crtc_state =
9626                 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
9627
9628         if (!new_crtc_state)
9629                 return true;
9630
9631         /* CRTC Degamma changes currently require us to recreate planes. */
9632         if (new_crtc_state->color_mgmt_changed)
9633                 return true;
9634
9635         if (drm_atomic_crtc_needs_modeset(new_crtc_state))
9636                 return true;
9637
9638         /*
9639          * If there are any new primary or overlay planes being added or
9640          * removed then the z-order can potentially change. To ensure
9641          * correct z-order and pipe acquisition the current DC architecture
9642          * requires us to remove and recreate all existing planes.
9643          *
9644          * TODO: Come up with a more elegant solution for this.
9645          */
9646         for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
9647                 struct amdgpu_framebuffer *old_afb, *new_afb;
9648
9649                 if (other->type == DRM_PLANE_TYPE_CURSOR)
9650                         continue;
9651
9652                 if (old_other_state->crtc != new_plane_state->crtc &&
9653                     new_other_state->crtc != new_plane_state->crtc)
9654                         continue;
9655
9656                 if (old_other_state->crtc != new_other_state->crtc)
9657                         return true;
9658
9659                 /* Src/dst size and scaling updates. */
9660                 if (old_other_state->src_w != new_other_state->src_w ||
9661                     old_other_state->src_h != new_other_state->src_h ||
9662                     old_other_state->crtc_w != new_other_state->crtc_w ||
9663                     old_other_state->crtc_h != new_other_state->crtc_h)
9664                         return true;
9665
9666                 /* Rotation / mirroring updates. */
9667                 if (old_other_state->rotation != new_other_state->rotation)
9668                         return true;
9669
9670                 /* Blending updates. */
9671                 if (old_other_state->pixel_blend_mode !=
9672                     new_other_state->pixel_blend_mode)
9673                         return true;
9674
9675                 /* Alpha updates. */
9676                 if (old_other_state->alpha != new_other_state->alpha)
9677                         return true;
9678
9679                 /* Colorspace changes. */
9680                 if (old_other_state->color_range != new_other_state->color_range ||
9681                     old_other_state->color_encoding != new_other_state->color_encoding)
9682                         return true;
9683
9684                 /* Framebuffer checks fall at the end. */
9685                 if (!old_other_state->fb || !new_other_state->fb)
9686                         continue;
9687
9688                 /* Pixel format changes can require bandwidth updates. */
9689                 if (old_other_state->fb->format != new_other_state->fb->format)
9690                         return true;
9691
9692                 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
9693                 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
9694
9695                 /* Tiling and DCC changes also require bandwidth updates. */
9696                 if (old_afb->tiling_flags != new_afb->tiling_flags ||
9697                     old_afb->base.modifier != new_afb->base.modifier)
9698                         return true;
9699         }
9700
9701         return false;
9702 }
9703
9704 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
9705                               struct drm_plane_state *new_plane_state,
9706                               struct drm_framebuffer *fb)
9707 {
9708         struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
9709         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
9710         unsigned int pitch;
9711         bool linear;
9712
9713         if (fb->width > new_acrtc->max_cursor_width ||
9714             fb->height > new_acrtc->max_cursor_height) {
9715                 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
9716                                  new_plane_state->fb->width,
9717                                  new_plane_state->fb->height);
9718                 return -EINVAL;
9719         }
9720         if (new_plane_state->src_w != fb->width << 16 ||
9721             new_plane_state->src_h != fb->height << 16) {
9722                 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9723                 return -EINVAL;
9724         }
9725
9726         /* Pitch in pixels */
9727         pitch = fb->pitches[0] / fb->format->cpp[0];
9728
9729         if (fb->width != pitch) {
9730                 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
9731                                  fb->width, pitch);
9732                 return -EINVAL;
9733         }
9734
9735         switch (pitch) {
9736         case 64:
9737         case 128:
9738         case 256:
9739                 /* FB pitch is supported by cursor plane */
9740                 break;
9741         default:
9742                 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
9743                 return -EINVAL;
9744         }
9745
9746         /* Core DRM takes care of checking FB modifiers, so we only need to
9747          * check tiling flags when the FB doesn't have a modifier.
9748          */
9749         if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
9750                 if (adev->family < AMDGPU_FAMILY_AI) {
9751                         linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
9752                                  AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
9753                                  AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
9754                 } else {
9755                         linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
9756                 }
9757                 if (!linear) {
9758                         DRM_DEBUG_ATOMIC("Cursor FB not linear");
9759                         return -EINVAL;
9760                 }
9761         }
9762
9763         return 0;
9764 }
9765
9766 static int dm_update_plane_state(struct dc *dc,
9767                                  struct drm_atomic_state *state,
9768                                  struct drm_plane *plane,
9769                                  struct drm_plane_state *old_plane_state,
9770                                  struct drm_plane_state *new_plane_state,
9771                                  bool enable,
9772                                  bool *lock_and_validation_needed,
9773                                  bool *is_top_most_overlay)
9774 {
9775
9776         struct dm_atomic_state *dm_state = NULL;
9777         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
9778         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9779         struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
9780         struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
9781         struct amdgpu_crtc *new_acrtc;
9782         bool needs_reset;
9783         int ret = 0;
9784
9785
9786         new_plane_crtc = new_plane_state->crtc;
9787         old_plane_crtc = old_plane_state->crtc;
9788         dm_new_plane_state = to_dm_plane_state(new_plane_state);
9789         dm_old_plane_state = to_dm_plane_state(old_plane_state);
9790
9791         if (plane->type == DRM_PLANE_TYPE_CURSOR) {
9792                 if (!enable || !new_plane_crtc ||
9793                         drm_atomic_plane_disabling(plane->state, new_plane_state))
9794                         return 0;
9795
9796                 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
9797
9798                 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
9799                         DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9800                         return -EINVAL;
9801                 }
9802
9803                 if (new_plane_state->fb) {
9804                         ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
9805                                                  new_plane_state->fb);
9806                         if (ret)
9807                                 return ret;
9808                 }
9809
9810                 return 0;
9811         }
9812
9813         needs_reset = should_reset_plane(state, plane, old_plane_state,
9814                                          new_plane_state);
9815
9816         /* Remove any changed/removed planes */
9817         if (!enable) {
9818                 if (!needs_reset)
9819                         return 0;
9820
9821                 if (!old_plane_crtc)
9822                         return 0;
9823
9824                 old_crtc_state = drm_atomic_get_old_crtc_state(
9825                                 state, old_plane_crtc);
9826                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9827
9828                 if (!dm_old_crtc_state->stream)
9829                         return 0;
9830
9831                 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
9832                                 plane->base.id, old_plane_crtc->base.id);
9833
9834                 ret = dm_atomic_get_state(state, &dm_state);
9835                 if (ret)
9836                         return ret;
9837
9838                 if (!dc_remove_plane_from_context(
9839                                 dc,
9840                                 dm_old_crtc_state->stream,
9841                                 dm_old_plane_state->dc_state,
9842                                 dm_state->context)) {
9843
9844                         return -EINVAL;
9845                 }
9846
9847                 if (dm_old_plane_state->dc_state)
9848                         dc_plane_state_release(dm_old_plane_state->dc_state);
9849
9850                 dm_new_plane_state->dc_state = NULL;
9851
9852                 *lock_and_validation_needed = true;
9853
9854         } else { /* Add new planes */
9855                 struct dc_plane_state *dc_new_plane_state;
9856
9857                 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
9858                         return 0;
9859
9860                 if (!new_plane_crtc)
9861                         return 0;
9862
9863                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
9864                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9865
9866                 if (!dm_new_crtc_state->stream)
9867                         return 0;
9868
9869                 if (!needs_reset)
9870                         return 0;
9871
9872                 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state);
9873                 if (ret)
9874                         return ret;
9875
9876                 WARN_ON(dm_new_plane_state->dc_state);
9877
9878                 dc_new_plane_state = dc_create_plane_state(dc);
9879                 if (!dc_new_plane_state)
9880                         return -ENOMEM;
9881
9882                 /* Block top most plane from being a video plane */
9883                 if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
9884                         if (amdgpu_dm_plane_is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay)
9885                                 return -EINVAL;
9886
9887                         *is_top_most_overlay = false;
9888                 }
9889
9890                 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
9891                                  plane->base.id, new_plane_crtc->base.id);
9892
9893                 ret = fill_dc_plane_attributes(
9894                         drm_to_adev(new_plane_crtc->dev),
9895                         dc_new_plane_state,
9896                         new_plane_state,
9897                         new_crtc_state);
9898                 if (ret) {
9899                         dc_plane_state_release(dc_new_plane_state);
9900                         return ret;
9901                 }
9902
9903                 ret = dm_atomic_get_state(state, &dm_state);
9904                 if (ret) {
9905                         dc_plane_state_release(dc_new_plane_state);
9906                         return ret;
9907                 }
9908
9909                 /*
9910                  * Any atomic check errors that occur after this will
9911                  * not need a release. The plane state will be attached
9912                  * to the stream, and therefore part of the atomic
9913                  * state. It'll be released when the atomic state is
9914                  * cleaned.
9915                  */
9916                 if (!dc_add_plane_to_context(
9917                                 dc,
9918                                 dm_new_crtc_state->stream,
9919                                 dc_new_plane_state,
9920                                 dm_state->context)) {
9921
9922                         dc_plane_state_release(dc_new_plane_state);
9923                         return -EINVAL;
9924                 }
9925
9926                 dm_new_plane_state->dc_state = dc_new_plane_state;
9927
9928                 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);
9929
9930                 /* Tell DC to do a full surface update every time there
9931                  * is a plane change. Inefficient, but works for now.
9932                  */
9933                 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
9934
9935                 *lock_and_validation_needed = true;
9936         }
9937
9938
9939         return ret;
9940 }
9941
9942 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,
9943                                        int *src_w, int *src_h)
9944 {
9945         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
9946         case DRM_MODE_ROTATE_90:
9947         case DRM_MODE_ROTATE_270:
9948                 *src_w = plane_state->src_h >> 16;
9949                 *src_h = plane_state->src_w >> 16;
9950                 break;
9951         case DRM_MODE_ROTATE_0:
9952         case DRM_MODE_ROTATE_180:
9953         default:
9954                 *src_w = plane_state->src_w >> 16;
9955                 *src_h = plane_state->src_h >> 16;
9956                 break;
9957         }
9958 }
9959
9960 static void
9961 dm_get_plane_scale(struct drm_plane_state *plane_state,
9962                    int *out_plane_scale_w, int *out_plane_scale_h)
9963 {
9964         int plane_src_w, plane_src_h;
9965
9966         dm_get_oriented_plane_size(plane_state, &plane_src_w, &plane_src_h);
9967         *out_plane_scale_w = plane_state->crtc_w * 1000 / plane_src_w;
9968         *out_plane_scale_h = plane_state->crtc_h * 1000 / plane_src_h;
9969 }
9970
9971 static int dm_check_crtc_cursor(struct drm_atomic_state *state,
9972                                 struct drm_crtc *crtc,
9973                                 struct drm_crtc_state *new_crtc_state)
9974 {
9975         struct drm_plane *cursor = crtc->cursor, *plane, *underlying;
9976         struct drm_plane_state *old_plane_state, *new_plane_state;
9977         struct drm_plane_state *new_cursor_state, *new_underlying_state;
9978         int i;
9979         int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h;
9980         bool any_relevant_change = false;
9981
9982         /* On DCE and DCN there is no dedicated hardware cursor plane. We get a
9983          * cursor per pipe but it's going to inherit the scaling and
9984          * positioning from the underlying pipe. Check the cursor plane's
9985          * blending properties match the underlying planes'.
9986          */
9987
9988         /* If no plane was enabled or changed scaling, no need to check again */
9989         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
9990                 int new_scale_w, new_scale_h, old_scale_w, old_scale_h;
9991
9992                 if (!new_plane_state || !new_plane_state->fb || new_plane_state->crtc != crtc)
9993                         continue;
9994
9995                 if (!old_plane_state || !old_plane_state->fb || old_plane_state->crtc != crtc) {
9996                         any_relevant_change = true;
9997                         break;
9998                 }
9999
10000                 if (new_plane_state->fb == old_plane_state->fb &&
10001                     new_plane_state->crtc_w == old_plane_state->crtc_w &&
10002                     new_plane_state->crtc_h == old_plane_state->crtc_h)
10003                         continue;
10004
10005                 dm_get_plane_scale(new_plane_state, &new_scale_w, &new_scale_h);
10006                 dm_get_plane_scale(old_plane_state, &old_scale_w, &old_scale_h);
10007
10008                 if (new_scale_w != old_scale_w || new_scale_h != old_scale_h) {
10009                         any_relevant_change = true;
10010                         break;
10011                 }
10012         }
10013
10014         if (!any_relevant_change)
10015                 return 0;
10016
10017         new_cursor_state = drm_atomic_get_plane_state(state, cursor);
10018         if (IS_ERR(new_cursor_state))
10019                 return PTR_ERR(new_cursor_state);
10020
10021         if (!new_cursor_state->fb)
10022                 return 0;
10023
10024         dm_get_plane_scale(new_cursor_state, &cursor_scale_w, &cursor_scale_h);
10025
10026         /* Need to check all enabled planes, even if this commit doesn't change
10027          * their state
10028          */
10029         i = drm_atomic_add_affected_planes(state, crtc);
10030         if (i)
10031                 return i;
10032
10033         for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) {
10034                 /* Narrow down to non-cursor planes on the same CRTC as the cursor */
10035                 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor)
10036                         continue;
10037
10038                 /* Ignore disabled planes */
10039                 if (!new_underlying_state->fb)
10040                         continue;
10041
10042                 dm_get_plane_scale(new_underlying_state,
10043                                    &underlying_scale_w, &underlying_scale_h);
10044
10045                 if (cursor_scale_w != underlying_scale_w ||
10046                     cursor_scale_h != underlying_scale_h) {
10047                         drm_dbg_atomic(crtc->dev,
10048                                        "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n",
10049                                        cursor->base.id, cursor->name, underlying->base.id, underlying->name);
10050                         return -EINVAL;
10051                 }
10052
10053                 /* If this plane covers the whole CRTC, no need to check planes underneath */
10054                 if (new_underlying_state->crtc_x <= 0 &&
10055                     new_underlying_state->crtc_y <= 0 &&
10056                     new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay &&
10057                     new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay)
10058                         break;
10059         }
10060
10061         return 0;
10062 }
10063
10064 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
10065 {
10066         struct drm_connector *connector;
10067         struct drm_connector_state *conn_state, *old_conn_state;
10068         struct amdgpu_dm_connector *aconnector = NULL;
10069         int i;
10070
10071         for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
10072                 if (!conn_state->crtc)
10073                         conn_state = old_conn_state;
10074
10075                 if (conn_state->crtc != crtc)
10076                         continue;
10077
10078                 aconnector = to_amdgpu_dm_connector(connector);
10079                 if (!aconnector->mst_output_port || !aconnector->mst_root)
10080                         aconnector = NULL;
10081                 else
10082                         break;
10083         }
10084
10085         if (!aconnector)
10086                 return 0;
10087
10088         return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr);
10089 }
10090
10091 /**
10092  * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
10093  *
10094  * @dev: The DRM device
10095  * @state: The atomic state to commit
10096  *
10097  * Validate that the given atomic state is programmable by DC into hardware.
10098  * This involves constructing a &struct dc_state reflecting the new hardware
10099  * state we wish to commit, then querying DC to see if it is programmable. It's
10100  * important not to modify the existing DC state. Otherwise, atomic_check
10101  * may unexpectedly commit hardware changes.
10102  *
10103  * When validating the DC state, it's important that the right locks are
10104  * acquired. For full updates case which removes/adds/updates streams on one
10105  * CRTC while flipping on another CRTC, acquiring global lock will guarantee
10106  * that any such full update commit will wait for completion of any outstanding
10107  * flip using DRMs synchronization events.
10108  *
10109  * Note that DM adds the affected connectors for all CRTCs in state, when that
10110  * might not seem necessary. This is because DC stream creation requires the
10111  * DC sink, which is tied to the DRM connector state. Cleaning this up should
10112  * be possible but non-trivial - a possible TODO item.
10113  *
10114  * Return: -Error code if validation failed.
10115  */
10116 static int amdgpu_dm_atomic_check(struct drm_device *dev,
10117                                   struct drm_atomic_state *state)
10118 {
10119         struct amdgpu_device *adev = drm_to_adev(dev);
10120         struct dm_atomic_state *dm_state = NULL;
10121         struct dc *dc = adev->dm.dc;
10122         struct drm_connector *connector;
10123         struct drm_connector_state *old_con_state, *new_con_state;
10124         struct drm_crtc *crtc;
10125         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
10126         struct drm_plane *plane;
10127         struct drm_plane_state *old_plane_state, *new_plane_state;
10128         enum dc_status status;
10129         int ret, i;
10130         bool lock_and_validation_needed = false;
10131         bool is_top_most_overlay = true;
10132         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
10133         struct drm_dp_mst_topology_mgr *mgr;
10134         struct drm_dp_mst_topology_state *mst_state;
10135         struct dsc_mst_fairness_vars vars[MAX_PIPES];
10136
10137         trace_amdgpu_dm_atomic_check_begin(state);
10138
10139         ret = drm_atomic_helper_check_modeset(dev, state);
10140         if (ret) {
10141                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n");
10142                 goto fail;
10143         }
10144
10145         /* Check connector changes */
10146         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10147                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10148                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10149
10150                 /* Skip connectors that are disabled or part of modeset already. */
10151                 if (!new_con_state->crtc)
10152                         continue;
10153
10154                 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
10155                 if (IS_ERR(new_crtc_state)) {
10156                         DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n");
10157                         ret = PTR_ERR(new_crtc_state);
10158                         goto fail;
10159                 }
10160
10161                 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level ||
10162                     dm_old_con_state->scaling != dm_new_con_state->scaling)
10163                         new_crtc_state->connectors_changed = true;
10164         }
10165
10166         if (dc_resource_is_dsc_encoding_supported(dc)) {
10167                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10168                         if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
10169                                 ret = add_affected_mst_dsc_crtcs(state, crtc);
10170                                 if (ret) {
10171                                         DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n");
10172                                         goto fail;
10173                                 }
10174                         }
10175                 }
10176         }
10177         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10178                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
10179
10180                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
10181                     !new_crtc_state->color_mgmt_changed &&
10182                     old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
10183                         dm_old_crtc_state->dsc_force_changed == false)
10184                         continue;
10185
10186                 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
10187                 if (ret) {
10188                         DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n");
10189                         goto fail;
10190                 }
10191
10192                 if (!new_crtc_state->enable)
10193                         continue;
10194
10195                 ret = drm_atomic_add_affected_connectors(state, crtc);
10196                 if (ret) {
10197                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n");
10198                         goto fail;
10199                 }
10200
10201                 ret = drm_atomic_add_affected_planes(state, crtc);
10202                 if (ret) {
10203                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n");
10204                         goto fail;
10205                 }
10206
10207                 if (dm_old_crtc_state->dsc_force_changed)
10208                         new_crtc_state->mode_changed = true;
10209         }
10210
10211         /*
10212          * Add all primary and overlay planes on the CRTC to the state
10213          * whenever a plane is enabled to maintain correct z-ordering
10214          * and to enable fast surface updates.
10215          */
10216         drm_for_each_crtc(crtc, dev) {
10217                 bool modified = false;
10218
10219                 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
10220                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
10221                                 continue;
10222
10223                         if (new_plane_state->crtc == crtc ||
10224                             old_plane_state->crtc == crtc) {
10225                                 modified = true;
10226                                 break;
10227                         }
10228                 }
10229
10230                 if (!modified)
10231                         continue;
10232
10233                 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
10234                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
10235                                 continue;
10236
10237                         new_plane_state =
10238                                 drm_atomic_get_plane_state(state, plane);
10239
10240                         if (IS_ERR(new_plane_state)) {
10241                                 ret = PTR_ERR(new_plane_state);
10242                                 DRM_DEBUG_DRIVER("new_plane_state is BAD\n");
10243                                 goto fail;
10244                         }
10245                 }
10246         }
10247
10248         /*
10249          * DC consults the zpos (layer_index in DC terminology) to determine the
10250          * hw plane on which to enable the hw cursor (see
10251          * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
10252          * atomic state, so call drm helper to normalize zpos.
10253          */
10254         ret = drm_atomic_normalize_zpos(dev, state);
10255         if (ret) {
10256                 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n");
10257                 goto fail;
10258         }
10259
10260         /* Remove exiting planes if they are modified */
10261         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10262                 if (old_plane_state->fb && new_plane_state->fb &&
10263                     get_mem_type(old_plane_state->fb) !=
10264                     get_mem_type(new_plane_state->fb))
10265                         lock_and_validation_needed = true;
10266
10267                 ret = dm_update_plane_state(dc, state, plane,
10268                                             old_plane_state,
10269                                             new_plane_state,
10270                                             false,
10271                                             &lock_and_validation_needed,
10272                                             &is_top_most_overlay);
10273                 if (ret) {
10274                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10275                         goto fail;
10276                 }
10277         }
10278
10279         /* Disable all crtcs which require disable */
10280         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10281                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10282                                            old_crtc_state,
10283                                            new_crtc_state,
10284                                            false,
10285                                            &lock_and_validation_needed);
10286                 if (ret) {
10287                         DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n");
10288                         goto fail;
10289                 }
10290         }
10291
10292         /* Enable all crtcs which require enable */
10293         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10294                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10295                                            old_crtc_state,
10296                                            new_crtc_state,
10297                                            true,
10298                                            &lock_and_validation_needed);
10299                 if (ret) {
10300                         DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n");
10301                         goto fail;
10302                 }
10303         }
10304
10305         /* Add new/modified planes */
10306         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10307                 ret = dm_update_plane_state(dc, state, plane,
10308                                             old_plane_state,
10309                                             new_plane_state,
10310                                             true,
10311                                             &lock_and_validation_needed,
10312                                             &is_top_most_overlay);
10313                 if (ret) {
10314                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10315                         goto fail;
10316                 }
10317         }
10318
10319         if (dc_resource_is_dsc_encoding_supported(dc)) {
10320                 ret = pre_validate_dsc(state, &dm_state, vars);
10321                 if (ret != 0)
10322                         goto fail;
10323         }
10324
10325         /* Run this here since we want to validate the streams we created */
10326         ret = drm_atomic_helper_check_planes(dev, state);
10327         if (ret) {
10328                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n");
10329                 goto fail;
10330         }
10331
10332         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10333                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10334                 if (dm_new_crtc_state->mpo_requested)
10335                         DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc);
10336         }
10337
10338         /* Check cursor planes scaling */
10339         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10340                 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
10341                 if (ret) {
10342                         DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n");
10343                         goto fail;
10344                 }
10345         }
10346
10347         if (state->legacy_cursor_update) {
10348                 /*
10349                  * This is a fast cursor update coming from the plane update
10350                  * helper, check if it can be done asynchronously for better
10351                  * performance.
10352                  */
10353                 state->async_update =
10354                         !drm_atomic_helper_async_check(dev, state);
10355
10356                 /*
10357                  * Skip the remaining global validation if this is an async
10358                  * update. Cursor updates can be done without affecting
10359                  * state or bandwidth calcs and this avoids the performance
10360                  * penalty of locking the private state object and
10361                  * allocating a new dc_state.
10362                  */
10363                 if (state->async_update)
10364                         return 0;
10365         }
10366
10367         /* Check scaling and underscan changes*/
10368         /* TODO Removed scaling changes validation due to inability to commit
10369          * new stream into context w\o causing full reset. Need to
10370          * decide how to handle.
10371          */
10372         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10373                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10374                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10375                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
10376
10377                 /* Skip any modesets/resets */
10378                 if (!acrtc || drm_atomic_crtc_needs_modeset(
10379                                 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
10380                         continue;
10381
10382                 /* Skip any thing not scale or underscan changes */
10383                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
10384                         continue;
10385
10386                 lock_and_validation_needed = true;
10387         }
10388
10389         /* set the slot info for each mst_state based on the link encoding format */
10390         for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
10391                 struct amdgpu_dm_connector *aconnector;
10392                 struct drm_connector *connector;
10393                 struct drm_connector_list_iter iter;
10394                 u8 link_coding_cap;
10395
10396                 drm_connector_list_iter_begin(dev, &iter);
10397                 drm_for_each_connector_iter(connector, &iter) {
10398                         if (connector->index == mst_state->mgr->conn_base_id) {
10399                                 aconnector = to_amdgpu_dm_connector(connector);
10400                                 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
10401                                 drm_dp_mst_update_slots(mst_state, link_coding_cap);
10402
10403                                 break;
10404                         }
10405                 }
10406                 drm_connector_list_iter_end(&iter);
10407         }
10408
10409         /**
10410          * Streams and planes are reset when there are changes that affect
10411          * bandwidth. Anything that affects bandwidth needs to go through
10412          * DC global validation to ensure that the configuration can be applied
10413          * to hardware.
10414          *
10415          * We have to currently stall out here in atomic_check for outstanding
10416          * commits to finish in this case because our IRQ handlers reference
10417          * DRM state directly - we can end up disabling interrupts too early
10418          * if we don't.
10419          *
10420          * TODO: Remove this stall and drop DM state private objects.
10421          */
10422         if (lock_and_validation_needed) {
10423                 ret = dm_atomic_get_state(state, &dm_state);
10424                 if (ret) {
10425                         DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n");
10426                         goto fail;
10427                 }
10428
10429                 ret = do_aquire_global_lock(dev, state);
10430                 if (ret) {
10431                         DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n");
10432                         goto fail;
10433                 }
10434
10435                 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);
10436                 if (ret) {
10437                         DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
10438                         ret = -EINVAL;
10439                         goto fail;
10440                 }
10441
10442                 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
10443                 if (ret) {
10444                         DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n");
10445                         goto fail;
10446                 }
10447
10448                 /*
10449                  * Perform validation of MST topology in the state:
10450                  * We need to perform MST atomic check before calling
10451                  * dc_validate_global_state(), or there is a chance
10452                  * to get stuck in an infinite loop and hang eventually.
10453                  */
10454                 ret = drm_dp_mst_atomic_check(state);
10455                 if (ret) {
10456                         DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n");
10457                         goto fail;
10458                 }
10459                 status = dc_validate_global_state(dc, dm_state->context, true);
10460                 if (status != DC_OK) {
10461                         DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)",
10462                                        dc_status_to_str(status), status);
10463                         ret = -EINVAL;
10464                         goto fail;
10465                 }
10466         } else {
10467                 /*
10468                  * The commit is a fast update. Fast updates shouldn't change
10469                  * the DC context, affect global validation, and can have their
10470                  * commit work done in parallel with other commits not touching
10471                  * the same resource. If we have a new DC context as part of
10472                  * the DM atomic state from validation we need to free it and
10473                  * retain the existing one instead.
10474                  *
10475                  * Furthermore, since the DM atomic state only contains the DC
10476                  * context and can safely be annulled, we can free the state
10477                  * and clear the associated private object now to free
10478                  * some memory and avoid a possible use-after-free later.
10479                  */
10480
10481                 for (i = 0; i < state->num_private_objs; i++) {
10482                         struct drm_private_obj *obj = state->private_objs[i].ptr;
10483
10484                         if (obj->funcs == adev->dm.atomic_obj.funcs) {
10485                                 int j = state->num_private_objs-1;
10486
10487                                 dm_atomic_destroy_state(obj,
10488                                                 state->private_objs[i].state);
10489
10490                                 /* If i is not at the end of the array then the
10491                                  * last element needs to be moved to where i was
10492                                  * before the array can safely be truncated.
10493                                  */
10494                                 if (i != j)
10495                                         state->private_objs[i] =
10496                                                 state->private_objs[j];
10497
10498                                 state->private_objs[j].ptr = NULL;
10499                                 state->private_objs[j].state = NULL;
10500                                 state->private_objs[j].old_state = NULL;
10501                                 state->private_objs[j].new_state = NULL;
10502
10503                                 state->num_private_objs = j;
10504                                 break;
10505                         }
10506                 }
10507         }
10508
10509         /* Store the overall update type for use later in atomic check. */
10510         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10511                 struct dm_crtc_state *dm_new_crtc_state =
10512                         to_dm_crtc_state(new_crtc_state);
10513
10514                 /*
10515                  * Only allow async flips for fast updates that don't change
10516                  * the FB pitch, the DCC state, rotation, etc.
10517                  */
10518                 if (new_crtc_state->async_flip && lock_and_validation_needed) {
10519                         drm_dbg_atomic(crtc->dev,
10520                                        "[CRTC:%d:%s] async flips are only supported for fast updates\n",
10521                                        crtc->base.id, crtc->name);
10522                         ret = -EINVAL;
10523                         goto fail;
10524                 }
10525
10526                 dm_new_crtc_state->update_type = lock_and_validation_needed ?
10527                         UPDATE_TYPE_FULL : UPDATE_TYPE_FAST;
10528         }
10529
10530         /* Must be success */
10531         WARN_ON(ret);
10532
10533         trace_amdgpu_dm_atomic_check_finish(state, ret);
10534
10535         return ret;
10536
10537 fail:
10538         if (ret == -EDEADLK)
10539                 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
10540         else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
10541                 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
10542         else
10543                 DRM_DEBUG_DRIVER("Atomic check failed with err: %d\n", ret);
10544
10545         trace_amdgpu_dm_atomic_check_finish(state, ret);
10546
10547         return ret;
10548 }
10549
10550 static bool is_dp_capable_without_timing_msa(struct dc *dc,
10551                                              struct amdgpu_dm_connector *amdgpu_dm_connector)
10552 {
10553         u8 dpcd_data;
10554         bool capable = false;
10555
10556         if (amdgpu_dm_connector->dc_link &&
10557                 dm_helpers_dp_read_dpcd(
10558                                 NULL,
10559                                 amdgpu_dm_connector->dc_link,
10560                                 DP_DOWN_STREAM_PORT_COUNT,
10561                                 &dpcd_data,
10562                                 sizeof(dpcd_data))) {
10563                 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
10564         }
10565
10566         return capable;
10567 }
10568
10569 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
10570                 unsigned int offset,
10571                 unsigned int total_length,
10572                 u8 *data,
10573                 unsigned int length,
10574                 struct amdgpu_hdmi_vsdb_info *vsdb)
10575 {
10576         bool res;
10577         union dmub_rb_cmd cmd;
10578         struct dmub_cmd_send_edid_cea *input;
10579         struct dmub_cmd_edid_cea_output *output;
10580
10581         if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES)
10582                 return false;
10583
10584         memset(&cmd, 0, sizeof(cmd));
10585
10586         input = &cmd.edid_cea.data.input;
10587
10588         cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;
10589         cmd.edid_cea.header.sub_type = 0;
10590         cmd.edid_cea.header.payload_bytes =
10591                 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);
10592         input->offset = offset;
10593         input->length = length;
10594         input->cea_total_length = total_length;
10595         memcpy(input->payload, data, length);
10596
10597         res = dm_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);
10598         if (!res) {
10599                 DRM_ERROR("EDID CEA parser failed\n");
10600                 return false;
10601         }
10602
10603         output = &cmd.edid_cea.data.output;
10604
10605         if (output->type == DMUB_CMD__EDID_CEA_ACK) {
10606                 if (!output->ack.success) {
10607                         DRM_ERROR("EDID CEA ack failed at offset %d\n",
10608                                         output->ack.offset);
10609                 }
10610         } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {
10611                 if (!output->amd_vsdb.vsdb_found)
10612                         return false;
10613
10614                 vsdb->freesync_supported = output->amd_vsdb.freesync_supported;
10615                 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;
10616                 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
10617                 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
10618         } else {
10619                 DRM_WARN("Unknown EDID CEA parser results\n");
10620                 return false;
10621         }
10622
10623         return true;
10624 }
10625
10626 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
10627                 u8 *edid_ext, int len,
10628                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10629 {
10630         int i;
10631
10632         /* send extension block to DMCU for parsing */
10633         for (i = 0; i < len; i += 8) {
10634                 bool res;
10635                 int offset;
10636
10637                 /* send 8 bytes a time */
10638                 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))
10639                         return false;
10640
10641                 if (i+8 == len) {
10642                         /* EDID block sent completed, expect result */
10643                         int version, min_rate, max_rate;
10644
10645                         res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);
10646                         if (res) {
10647                                 /* amd vsdb found */
10648                                 vsdb_info->freesync_supported = 1;
10649                                 vsdb_info->amd_vsdb_version = version;
10650                                 vsdb_info->min_refresh_rate_hz = min_rate;
10651                                 vsdb_info->max_refresh_rate_hz = max_rate;
10652                                 return true;
10653                         }
10654                         /* not amd vsdb */
10655                         return false;
10656                 }
10657
10658                 /* check for ack*/
10659                 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);
10660                 if (!res)
10661                         return false;
10662         }
10663
10664         return false;
10665 }
10666
10667 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
10668                 u8 *edid_ext, int len,
10669                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10670 {
10671         int i;
10672
10673         /* send extension block to DMCU for parsing */
10674         for (i = 0; i < len; i += 8) {
10675                 /* send 8 bytes a time */
10676                 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))
10677                         return false;
10678         }
10679
10680         return vsdb_info->freesync_supported;
10681 }
10682
10683 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
10684                 u8 *edid_ext, int len,
10685                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10686 {
10687         struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
10688         bool ret;
10689
10690         mutex_lock(&adev->dm.dc_lock);
10691         if (adev->dm.dmub_srv)
10692                 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);
10693         else
10694                 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);
10695         mutex_unlock(&adev->dm.dc_lock);
10696         return ret;
10697 }
10698
10699 static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10700                           struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10701 {
10702         u8 *edid_ext = NULL;
10703         int i;
10704         int j = 0;
10705
10706         if (edid == NULL || edid->extensions == 0)
10707                 return -ENODEV;
10708
10709         /* Find DisplayID extension */
10710         for (i = 0; i < edid->extensions; i++) {
10711                 edid_ext = (void *)(edid + (i + 1));
10712                 if (edid_ext[0] == DISPLAYID_EXT)
10713                         break;
10714         }
10715
10716         while (j < EDID_LENGTH) {
10717                 struct amd_vsdb_block *amd_vsdb = (struct amd_vsdb_block *)&edid_ext[j];
10718                 unsigned int ieeeId = (amd_vsdb->ieee_id[2] << 16) | (amd_vsdb->ieee_id[1] << 8) | (amd_vsdb->ieee_id[0]);
10719
10720                 if (ieeeId == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID &&
10721                                 amd_vsdb->version == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3) {
10722                         vsdb_info->replay_mode = (amd_vsdb->feature_caps & AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE) ? true : false;
10723                         vsdb_info->amd_vsdb_version = HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3;
10724                         DRM_DEBUG_KMS("Panel supports Replay Mode: %d\n", vsdb_info->replay_mode);
10725
10726                         return true;
10727                 }
10728                 j++;
10729         }
10730
10731         return false;
10732 }
10733
10734 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10735                 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10736 {
10737         u8 *edid_ext = NULL;
10738         int i;
10739         bool valid_vsdb_found = false;
10740
10741         /*----- drm_find_cea_extension() -----*/
10742         /* No EDID or EDID extensions */
10743         if (edid == NULL || edid->extensions == 0)
10744                 return -ENODEV;
10745
10746         /* Find CEA extension */
10747         for (i = 0; i < edid->extensions; i++) {
10748                 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
10749                 if (edid_ext[0] == CEA_EXT)
10750                         break;
10751         }
10752
10753         if (i == edid->extensions)
10754                 return -ENODEV;
10755
10756         /*----- cea_db_offsets() -----*/
10757         if (edid_ext[0] != CEA_EXT)
10758                 return -ENODEV;
10759
10760         valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
10761
10762         return valid_vsdb_found ? i : -ENODEV;
10763 }
10764
10765 /**
10766  * amdgpu_dm_update_freesync_caps - Update Freesync capabilities
10767  *
10768  * @connector: Connector to query.
10769  * @edid: EDID from monitor
10770  *
10771  * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep
10772  * track of some of the display information in the internal data struct used by
10773  * amdgpu_dm. This function checks which type of connector we need to set the
10774  * FreeSync parameters.
10775  */
10776 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
10777                                     struct edid *edid)
10778 {
10779         int i = 0;
10780         struct detailed_timing *timing;
10781         struct detailed_non_pixel *data;
10782         struct detailed_data_monitor_range *range;
10783         struct amdgpu_dm_connector *amdgpu_dm_connector =
10784                         to_amdgpu_dm_connector(connector);
10785         struct dm_connector_state *dm_con_state = NULL;
10786         struct dc_sink *sink;
10787
10788         struct drm_device *dev = connector->dev;
10789         struct amdgpu_device *adev = drm_to_adev(dev);
10790         struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
10791         bool freesync_capable = false;
10792         enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
10793
10794         if (!connector->state) {
10795                 DRM_ERROR("%s - Connector has no state", __func__);
10796                 goto update;
10797         }
10798
10799         sink = amdgpu_dm_connector->dc_sink ?
10800                 amdgpu_dm_connector->dc_sink :
10801                 amdgpu_dm_connector->dc_em_sink;
10802
10803         if (!edid || !sink) {
10804                 dm_con_state = to_dm_connector_state(connector->state);
10805
10806                 amdgpu_dm_connector->min_vfreq = 0;
10807                 amdgpu_dm_connector->max_vfreq = 0;
10808                 amdgpu_dm_connector->pixel_clock_mhz = 0;
10809                 connector->display_info.monitor_range.min_vfreq = 0;
10810                 connector->display_info.monitor_range.max_vfreq = 0;
10811                 freesync_capable = false;
10812
10813                 goto update;
10814         }
10815
10816         dm_con_state = to_dm_connector_state(connector->state);
10817
10818         if (!adev->dm.freesync_module)
10819                 goto update;
10820
10821         if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
10822                 || sink->sink_signal == SIGNAL_TYPE_EDP) {
10823                 bool edid_check_required = false;
10824
10825                 if (edid) {
10826                         edid_check_required = is_dp_capable_without_timing_msa(
10827                                                 adev->dm.dc,
10828                                                 amdgpu_dm_connector);
10829                 }
10830
10831                 if (edid_check_required == true && (edid->version > 1 ||
10832                    (edid->version == 1 && edid->revision > 1))) {
10833                         for (i = 0; i < 4; i++) {
10834
10835                                 timing  = &edid->detailed_timings[i];
10836                                 data    = &timing->data.other_data;
10837                                 range   = &data->data.range;
10838                                 /*
10839                                  * Check if monitor has continuous frequency mode
10840                                  */
10841                                 if (data->type != EDID_DETAIL_MONITOR_RANGE)
10842                                         continue;
10843                                 /*
10844                                  * Check for flag range limits only. If flag == 1 then
10845                                  * no additional timing information provided.
10846                                  * Default GTF, GTF Secondary curve and CVT are not
10847                                  * supported
10848                                  */
10849                                 if (range->flags != 1)
10850                                         continue;
10851
10852                                 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
10853                                 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
10854                                 amdgpu_dm_connector->pixel_clock_mhz =
10855                                         range->pixel_clock_mhz * 10;
10856
10857                                 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
10858                                 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
10859
10860                                 break;
10861                         }
10862
10863                         if (amdgpu_dm_connector->max_vfreq -
10864                             amdgpu_dm_connector->min_vfreq > 10) {
10865
10866                                 freesync_capable = true;
10867                         }
10868                 }
10869                 parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10870
10871                 if (vsdb_info.replay_mode) {
10872                         amdgpu_dm_connector->vsdb_info.replay_mode = vsdb_info.replay_mode;
10873                         amdgpu_dm_connector->vsdb_info.amd_vsdb_version = vsdb_info.amd_vsdb_version;
10874                         amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP;
10875                 }
10876
10877         } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
10878                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10879                 if (i >= 0 && vsdb_info.freesync_supported) {
10880                         timing  = &edid->detailed_timings[i];
10881                         data    = &timing->data.other_data;
10882
10883                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10884                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10885                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10886                                 freesync_capable = true;
10887
10888                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10889                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10890                 }
10891         }
10892
10893         as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link);
10894
10895         if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
10896                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10897                 if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) {
10898
10899                         amdgpu_dm_connector->pack_sdp_v1_3 = true;
10900                         amdgpu_dm_connector->as_type = as_type;
10901                         amdgpu_dm_connector->vsdb_info = vsdb_info;
10902
10903                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10904                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10905                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10906                                 freesync_capable = true;
10907
10908                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10909                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10910                 }
10911         }
10912
10913 update:
10914         if (dm_con_state)
10915                 dm_con_state->freesync_capable = freesync_capable;
10916
10917         if (connector->vrr_capable_property)
10918                 drm_connector_set_vrr_capable_property(connector,
10919                                                        freesync_capable);
10920 }
10921
10922 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
10923 {
10924         struct amdgpu_device *adev = drm_to_adev(dev);
10925         struct dc *dc = adev->dm.dc;
10926         int i;
10927
10928         mutex_lock(&adev->dm.dc_lock);
10929         if (dc->current_state) {
10930                 for (i = 0; i < dc->current_state->stream_count; ++i)
10931                         dc->current_state->streams[i]
10932                                 ->triggered_crtc_reset.enabled =
10933                                 adev->dm.force_timing_sync;
10934
10935                 dm_enable_per_frame_crtc_master_sync(dc->current_state);
10936                 dc_trigger_sync(dc, dc->current_state);
10937         }
10938         mutex_unlock(&adev->dm.dc_lock);
10939 }
10940
10941 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
10942                        u32 value, const char *func_name)
10943 {
10944 #ifdef DM_CHECK_ADDR_0
10945         if (address == 0) {
10946                 drm_err(adev_to_drm(ctx->driver_context),
10947                         "invalid register write. address = 0");
10948                 return;
10949         }
10950 #endif
10951         cgs_write_register(ctx->cgs_device, address, value);
10952         trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
10953 }
10954
10955 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
10956                           const char *func_name)
10957 {
10958         u32 value;
10959 #ifdef DM_CHECK_ADDR_0
10960         if (address == 0) {
10961                 drm_err(adev_to_drm(ctx->driver_context),
10962                         "invalid register read; address = 0\n");
10963                 return 0;
10964         }
10965 #endif
10966
10967         if (ctx->dmub_srv &&
10968             ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
10969             !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
10970                 ASSERT(false);
10971                 return 0;
10972         }
10973
10974         value = cgs_read_register(ctx->cgs_device, address);
10975
10976         trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
10977
10978         return value;
10979 }
10980
10981 int amdgpu_dm_process_dmub_aux_transfer_sync(
10982                 struct dc_context *ctx,
10983                 unsigned int link_index,
10984                 struct aux_payload *payload,
10985                 enum aux_return_code_type *operation_result)
10986 {
10987         struct amdgpu_device *adev = ctx->driver_context;
10988         struct dmub_notification *p_notify = adev->dm.dmub_notify;
10989         int ret = -1;
10990
10991         mutex_lock(&adev->dm.dpia_aux_lock);
10992         if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) {
10993                 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
10994                 goto out;
10995         }
10996
10997         if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10998                 DRM_ERROR("wait_for_completion_timeout timeout!");
10999                 *operation_result = AUX_RET_ERROR_TIMEOUT;
11000                 goto out;
11001         }
11002
11003         if (p_notify->result != AUX_RET_SUCCESS) {
11004                 /*
11005                  * Transient states before tunneling is enabled could
11006                  * lead to this error. We can ignore this for now.
11007                  */
11008                 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) {
11009                         DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n",
11010                                         payload->address, payload->length,
11011                                         p_notify->result);
11012                 }
11013                 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
11014                 goto out;
11015         }
11016
11017
11018         payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
11019         if (!payload->write && p_notify->aux_reply.length &&
11020                         (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) {
11021
11022                 if (payload->length != p_notify->aux_reply.length) {
11023                         DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n",
11024                                 p_notify->aux_reply.length,
11025                                         payload->address, payload->length);
11026                         *operation_result = AUX_RET_ERROR_INVALID_REPLY;
11027                         goto out;
11028                 }
11029
11030                 memcpy(payload->data, p_notify->aux_reply.data,
11031                                 p_notify->aux_reply.length);
11032         }
11033
11034         /* success */
11035         ret = p_notify->aux_reply.length;
11036         *operation_result = p_notify->result;
11037 out:
11038         reinit_completion(&adev->dm.dmub_aux_transfer_done);
11039         mutex_unlock(&adev->dm.dpia_aux_lock);
11040         return ret;
11041 }
11042
11043 int amdgpu_dm_process_dmub_set_config_sync(
11044                 struct dc_context *ctx,
11045                 unsigned int link_index,
11046                 struct set_config_cmd_payload *payload,
11047                 enum set_config_status *operation_result)
11048 {
11049         struct amdgpu_device *adev = ctx->driver_context;
11050         bool is_cmd_complete;
11051         int ret;
11052
11053         mutex_lock(&adev->dm.dpia_aux_lock);
11054         is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc,
11055                         link_index, payload, adev->dm.dmub_notify);
11056
11057         if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
11058                 ret = 0;
11059                 *operation_result = adev->dm.dmub_notify->sc_status;
11060         } else {
11061                 DRM_ERROR("wait_for_completion_timeout timeout!");
11062                 ret = -1;
11063                 *operation_result = SET_CONFIG_UNKNOWN_ERROR;
11064         }
11065
11066         if (!is_cmd_complete)
11067                 reinit_completion(&adev->dm.dmub_aux_transfer_done);
11068         mutex_unlock(&adev->dm.dpia_aux_lock);
11069         return ret;
11070 }
11071
11072 bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
11073 {
11074         return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type);
11075 }
11076
11077 bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
11078 {
11079         return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type);
11080 }