2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #ifndef __KFD_TOPOLOGY_H__
24 #define __KFD_TOPOLOGY_H__
26 #include <linux/types.h>
27 #include <linux/list.h>
30 #define KFD_TOPOLOGY_PUBLIC_NAME_SIZE 32
32 #define HSA_CAP_HOT_PLUGGABLE 0x00000001
33 #define HSA_CAP_ATS_PRESENT 0x00000002
34 #define HSA_CAP_SHARED_WITH_GRAPHICS 0x00000004
35 #define HSA_CAP_QUEUE_SIZE_POW2 0x00000008
36 #define HSA_CAP_QUEUE_SIZE_32BIT 0x00000010
37 #define HSA_CAP_QUEUE_IDLE_EVENT 0x00000020
38 #define HSA_CAP_VA_LIMIT 0x00000040
39 #define HSA_CAP_WATCH_POINTS_SUPPORTED 0x00000080
40 #define HSA_CAP_WATCH_POINTS_TOTALBITS_MASK 0x00000f00
41 #define HSA_CAP_WATCH_POINTS_TOTALBITS_SHIFT 8
42 #define HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK 0x00003000
43 #define HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT 12
45 #define HSA_CAP_DOORBELL_TYPE_PRE_1_0 0x0
46 #define HSA_CAP_DOORBELL_TYPE_1_0 0x1
47 #define HSA_CAP_DOORBELL_TYPE_2_0 0x2
48 #define HSA_CAP_AQL_QUEUE_DOUBLE_MAP 0x00004000
50 #define HSA_CAP_RESERVED_WAS_SRAM_EDCSUPPORTED 0x00080000 /* Old buggy user mode depends on this being 0 */
51 #define HSA_CAP_MEM_EDCSUPPORTED 0x00100000
52 #define HSA_CAP_RASEVENTNOTIFY 0x00200000
53 #define HSA_CAP_ASIC_REVISION_MASK 0x03c00000
54 #define HSA_CAP_ASIC_REVISION_SHIFT 22
55 #define HSA_CAP_SRAM_EDCSUPPORTED 0x04000000
56 #define HSA_CAP_SVMAPI_SUPPORTED 0x08000000
57 #define HSA_CAP_FLAGS_COHERENTHOSTACCESS 0x10000000
58 #define HSA_CAP_RESERVED 0xe00f8000
60 struct kfd_node_properties {
62 uint32_t cpu_cores_count;
64 uint32_t mem_banks_count;
65 uint32_t caches_count;
66 uint32_t io_links_count;
67 uint32_t cpu_core_id_base;
68 uint32_t simd_id_base;
70 uint32_t max_waves_per_simd;
71 uint32_t lds_size_in_kb;
72 uint32_t gds_size_in_kb;
74 uint32_t wave_front_size;
76 uint32_t simd_arrays_per_engine;
77 uint32_t cu_per_simd_array;
79 uint32_t max_slots_scratch_cu;
81 uint32_t gfx_target_version;
86 uint32_t max_engine_clk_fcompute;
87 uint32_t max_engine_clk_ccompute;
88 int32_t drm_render_minor;
89 uint32_t num_sdma_engines;
90 uint32_t num_sdma_xgmi_engines;
91 uint32_t num_sdma_queues_per_engine;
92 uint32_t num_cp_queues;
93 char name[KFD_TOPOLOGY_PUBLIC_NAME_SIZE];
96 #define HSA_MEM_HEAP_TYPE_SYSTEM 0
97 #define HSA_MEM_HEAP_TYPE_FB_PUBLIC 1
98 #define HSA_MEM_HEAP_TYPE_FB_PRIVATE 2
99 #define HSA_MEM_HEAP_TYPE_GPU_GDS 3
100 #define HSA_MEM_HEAP_TYPE_GPU_LDS 4
101 #define HSA_MEM_HEAP_TYPE_GPU_SCRATCH 5
103 #define HSA_MEM_FLAGS_HOT_PLUGGABLE 0x00000001
104 #define HSA_MEM_FLAGS_NON_VOLATILE 0x00000002
105 #define HSA_MEM_FLAGS_RESERVED 0xfffffffc
107 struct kfd_mem_properties {
108 struct list_head list;
110 uint64_t size_in_bytes;
113 uint32_t mem_clk_max;
115 struct kobject *kobj;
116 struct attribute attr;
119 #define HSA_CACHE_TYPE_DATA 0x00000001
120 #define HSA_CACHE_TYPE_INSTRUCTION 0x00000002
121 #define HSA_CACHE_TYPE_CPU 0x00000004
122 #define HSA_CACHE_TYPE_HSACU 0x00000008
123 #define HSA_CACHE_TYPE_RESERVED 0xfffffff0
125 struct kfd_cache_properties {
126 struct list_head list;
127 uint32_t processor_id_low;
128 uint32_t cache_level;
130 uint32_t cacheline_size;
131 uint32_t cachelines_per_tag;
132 uint32_t cache_assoc;
133 uint32_t cache_latency;
135 uint8_t sibling_map[CRAT_SIBLINGMAP_SIZE];
137 struct kobject *kobj;
138 struct attribute attr;
141 struct kfd_iolink_properties {
142 struct list_head list;
143 uint32_t iolink_type;
149 uint32_t min_latency;
150 uint32_t max_latency;
151 uint32_t min_bandwidth;
152 uint32_t max_bandwidth;
153 uint32_t rec_transfer_size;
156 struct kobject *kobj;
157 struct attribute attr;
160 struct kfd_perf_properties {
161 struct list_head list;
163 uint32_t max_concurrent;
164 struct attribute_group *attr_group;
167 struct kfd_topology_device {
168 struct list_head list;
170 uint32_t proximity_domain;
171 struct kfd_node_properties node_props;
172 struct list_head mem_props;
173 uint32_t cache_count;
174 struct list_head cache_props;
175 uint32_t io_link_count;
176 struct list_head io_link_props;
177 struct list_head perf_props;
179 struct kobject *kobj_node;
180 struct kobject *kobj_mem;
181 struct kobject *kobj_cache;
182 struct kobject *kobj_iolink;
183 struct kobject *kobj_perf;
184 struct attribute attr_gpuid;
185 struct attribute attr_name;
186 struct attribute attr_props;
187 uint8_t oem_id[CRAT_OEMID_LENGTH];
188 uint8_t oem_table_id[CRAT_OEMTABLEID_LENGTH];
189 uint32_t oem_revision;
192 struct kfd_system_properties {
193 uint32_t num_devices; /* Number of H-NUMA nodes */
194 uint32_t generation_count;
195 uint64_t platform_oem;
196 uint64_t platform_id;
197 uint64_t platform_rev;
198 struct kobject *kobj_topology;
199 struct kobject *kobj_nodes;
200 struct attribute attr_genid;
201 struct attribute attr_props;
204 struct kfd_topology_device *kfd_create_topology_device(
205 struct list_head *device_list);
206 void kfd_release_topology_device_list(struct list_head *device_list);
208 #endif /* __KFD_TOPOLOGY_H__ */