2 * Copyright 2014 Advanced Micro Devices, Inc.
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #ifndef F32_MES_PM4_PACKETS_H
25 #define F32_MES_PM4_PACKETS_H
27 #ifndef PM4_MES_HEADER_DEFINED
28 #define PM4_MES_HEADER_DEFINED
29 union PM4_MES_TYPE_3_HEADER {
31 uint32_t reserved1 : 8; /* < reserved */
32 uint32_t opcode : 8; /* < IT opcode */
33 uint32_t count : 14;/* < Number of DWORDS - 1 in the
36 uint32_t type : 2; /* < packet identifier
37 * It should be 3 for type 3 packets
42 #endif /* PM4_MES_HEADER_DEFINED */
44 /*--------------------MES_SET_RESOURCES--------------------*/
46 #ifndef PM4_MES_SET_RESOURCES_DEFINED
47 #define PM4_MES_SET_RESOURCES_DEFINED
48 enum mes_set_resources_queue_type_enum {
49 queue_type__mes_set_resources__kernel_interface_queue_kiq = 0,
50 queue_type__mes_set_resources__hsa_interface_queue_hiq = 1,
51 queue_type__mes_set_resources__hsa_debug_interface_queue = 4
55 struct pm4_mes_set_resources {
57 union PM4_MES_TYPE_3_HEADER header; /* header */
63 uint32_t vmid_mask:16;
64 uint32_t unmap_latency:8;
66 enum mes_set_resources_queue_type_enum queue_type:3;
71 uint32_t queue_mask_lo;
72 uint32_t queue_mask_hi;
79 uint32_t reserved2:16;
86 uint32_t gds_heap_base:6;
88 uint32_t gds_heap_size:6;
89 uint32_t reserved4:15;
97 /*--------------------MES_RUN_LIST--------------------*/
99 #ifndef PM4_MES_RUN_LIST_DEFINED
100 #define PM4_MES_RUN_LIST_DEFINED
102 struct pm4_mes_runlist {
104 union PM4_MES_TYPE_3_HEADER header; /* header */
110 uint32_t reserved1:2;
111 uint32_t ib_base_lo:30;
118 uint32_t ib_base_hi:16;
119 uint32_t reserved2:16;
128 uint32_t offload_polling:1;
129 uint32_t reserved2:1;
131 uint32_t process_cnt:4;
132 uint32_t reserved3:4;
140 /*--------------------MES_MAP_PROCESS--------------------*/
142 #ifndef PM4_MES_MAP_PROCESS_DEFINED
143 #define PM4_MES_MAP_PROCESS_DEFINED
145 struct pm4_mes_map_process {
147 union PM4_MES_TYPE_3_HEADER header; /* header */
154 uint32_t reserved1:8;
155 uint32_t diq_enable:1;
156 uint32_t process_quantum:7;
163 uint32_t page_table_base:28;
164 uint32_t reserved3:4;
171 uint32_t sh_mem_bases;
172 uint32_t sh_mem_config;
173 uint32_t sh_mem_ape1_base;
174 uint32_t sh_mem_ape1_limit;
176 uint32_t sh_hidden_private_base_vmid;
181 uint32_t gds_addr_lo;
182 uint32_t gds_addr_hi;
187 uint32_t reserved4:2;
189 uint32_t reserved5:4;
191 uint32_t num_queues:10;
196 uint32_t completion_signal_lo;
197 uint32_t completion_signal_hi;
203 /*--------------------MES_MAP_QUEUES--------------------*/
205 #ifndef PM4_MES_MAP_QUEUES_VI_DEFINED
206 #define PM4_MES_MAP_QUEUES_VI_DEFINED
207 enum mes_map_queues_queue_sel_vi_enum {
208 queue_sel__mes_map_queues__map_to_specified_queue_slots_vi = 0,
209 queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi = 1
212 enum mes_map_queues_queue_type_vi_enum {
213 queue_type__mes_map_queues__normal_compute_vi = 0,
214 queue_type__mes_map_queues__debug_interface_queue_vi = 1,
215 queue_type__mes_map_queues__normal_latency_static_queue_vi = 2,
216 queue_type__mes_map_queues__low_latency_static_queue_vi = 3
219 enum mes_map_queues_engine_sel_vi_enum {
220 engine_sel__mes_map_queues__compute_vi = 0,
221 engine_sel__mes_map_queues__sdma0_vi = 2,
222 engine_sel__mes_map_queues__sdma1_vi = 3
226 struct pm4_mes_map_queues {
228 union PM4_MES_TYPE_3_HEADER header; /* header */
234 uint32_t reserved1:4;
235 enum mes_map_queues_queue_sel_vi_enum queue_sel:2;
236 uint32_t reserved2:15;
237 enum mes_map_queues_queue_type_vi_enum queue_type:3;
238 uint32_t reserved3:2;
239 enum mes_map_queues_engine_sel_vi_enum engine_sel:3;
240 uint32_t num_queues:3;
247 uint32_t reserved3:1;
248 uint32_t check_disable:1;
249 uint32_t doorbell_offset:21;
250 uint32_t reserved4:3;
256 uint32_t mqd_addr_lo;
257 uint32_t mqd_addr_hi;
258 uint32_t wptr_addr_lo;
259 uint32_t wptr_addr_hi;
263 /*--------------------MES_QUERY_STATUS--------------------*/
265 #ifndef PM4_MES_QUERY_STATUS_DEFINED
266 #define PM4_MES_QUERY_STATUS_DEFINED
267 enum mes_query_status_interrupt_sel_enum {
268 interrupt_sel__mes_query_status__completion_status = 0,
269 interrupt_sel__mes_query_status__process_status = 1,
270 interrupt_sel__mes_query_status__queue_status = 2
273 enum mes_query_status_command_enum {
274 command__mes_query_status__interrupt_only = 0,
275 command__mes_query_status__fence_only_immediate = 1,
276 command__mes_query_status__fence_only_after_write_ack = 2,
277 command__mes_query_status__fence_wait_for_write_ack_send_interrupt = 3
280 enum mes_query_status_engine_sel_enum {
281 engine_sel__mes_query_status__compute = 0,
282 engine_sel__mes_query_status__sdma0_queue = 2,
283 engine_sel__mes_query_status__sdma1_queue = 3
286 struct pm4_mes_query_status {
288 union PM4_MES_TYPE_3_HEADER header; /* header */
294 uint32_t context_id:28;
295 enum mes_query_status_interrupt_sel_enum
297 enum mes_query_status_command_enum command:2;
305 uint32_t reserved1:16;
308 uint32_t reserved2:2;
309 uint32_t doorbell_offset:21;
310 uint32_t reserved3:2;
311 enum mes_query_status_engine_sel_enum engine_sel:3;
312 uint32_t reserved4:4;
324 /*--------------------MES_UNMAP_QUEUES--------------------*/
326 #ifndef PM4_MES_UNMAP_QUEUES_DEFINED
327 #define PM4_MES_UNMAP_QUEUES_DEFINED
328 enum mes_unmap_queues_action_enum {
329 action__mes_unmap_queues__preempt_queues = 0,
330 action__mes_unmap_queues__reset_queues = 1,
331 action__mes_unmap_queues__disable_process_queues = 2,
332 action__mes_unmap_queues__reserved = 3
335 enum mes_unmap_queues_queue_sel_enum {
336 queue_sel__mes_unmap_queues__perform_request_on_specified_queues = 0,
337 queue_sel__mes_unmap_queues__perform_request_on_pasid_queues = 1,
338 queue_sel__mes_unmap_queues__unmap_all_queues = 2,
339 queue_sel__mes_unmap_queues__unmap_all_non_static_queues = 3
342 enum mes_unmap_queues_engine_sel_enum {
343 engine_sel__mes_unmap_queues__compute = 0,
344 engine_sel__mes_unmap_queues__sdma0 = 2,
345 engine_sel__mes_unmap_queues__sdmal = 3
348 struct pm4_mes_unmap_queues {
350 union PM4_MES_TYPE_3_HEADER header; /* header */
356 enum mes_unmap_queues_action_enum action:2;
357 uint32_t reserved1:2;
358 enum mes_unmap_queues_queue_sel_enum queue_sel:2;
359 uint32_t reserved2:20;
360 enum mes_unmap_queues_engine_sel_enum engine_sel:3;
361 uint32_t num_queues:3;
369 uint32_t reserved3:16;
372 uint32_t reserved4:2;
373 uint32_t doorbell_offset0:21;
374 uint32_t reserved5:9;
381 uint32_t reserved6:2;
382 uint32_t doorbell_offset1:21;
383 uint32_t reserved7:9;
390 uint32_t reserved8:2;
391 uint32_t doorbell_offset2:21;
392 uint32_t reserved9:9;
399 uint32_t reserved10:2;
400 uint32_t doorbell_offset3:21;
401 uint32_t reserved11:9;
408 #ifndef PM4_MEC_RELEASE_MEM_DEFINED
409 #define PM4_MEC_RELEASE_MEM_DEFINED
410 enum RELEASE_MEM_event_index_enum {
411 event_index___release_mem__end_of_pipe = 5,
412 event_index___release_mem__shader_done = 6
415 enum RELEASE_MEM_cache_policy_enum {
416 cache_policy___release_mem__lru = 0,
417 cache_policy___release_mem__stream = 1,
418 cache_policy___release_mem__bypass = 2
421 enum RELEASE_MEM_dst_sel_enum {
422 dst_sel___release_mem__memory_controller = 0,
423 dst_sel___release_mem__tc_l2 = 1,
424 dst_sel___release_mem__queue_write_pointer_register = 2,
425 dst_sel___release_mem__queue_write_pointer_poll_mask_bit = 3
428 enum RELEASE_MEM_int_sel_enum {
429 int_sel___release_mem__none = 0,
430 int_sel___release_mem__send_interrupt_only = 1,
431 int_sel___release_mem__send_interrupt_after_write_confirm = 2,
432 int_sel___release_mem__send_data_after_write_confirm = 3
435 enum RELEASE_MEM_data_sel_enum {
436 data_sel___release_mem__none = 0,
437 data_sel___release_mem__send_32_bit_low = 1,
438 data_sel___release_mem__send_64_bit_data = 2,
439 data_sel___release_mem__send_gpu_clock_counter = 3,
440 data_sel___release_mem__send_cp_perfcounter_hi_lo = 4,
441 data_sel___release_mem__store_gds_data_to_memory = 5
444 struct pm4_mec_release_mem {
446 union PM4_MES_TYPE_3_HEADER header; /*header */
447 unsigned int ordinal1;
452 unsigned int event_type:6;
453 unsigned int reserved1:2;
454 enum RELEASE_MEM_event_index_enum event_index:4;
455 unsigned int tcl1_vol_action_ena:1;
456 unsigned int tc_vol_action_ena:1;
457 unsigned int reserved2:1;
458 unsigned int tc_wb_action_ena:1;
459 unsigned int tcl1_action_ena:1;
460 unsigned int tc_action_ena:1;
461 unsigned int reserved3:6;
463 enum RELEASE_MEM_cache_policy_enum cache_policy:2;
464 unsigned int reserved4:5;
466 unsigned int ordinal2;
471 unsigned int reserved5:16;
472 enum RELEASE_MEM_dst_sel_enum dst_sel:2;
473 unsigned int reserved6:6;
474 enum RELEASE_MEM_int_sel_enum int_sel:3;
475 unsigned int reserved7:2;
476 enum RELEASE_MEM_data_sel_enum data_sel:3;
478 unsigned int ordinal3;
483 unsigned int reserved8:2;
484 unsigned int address_lo_32b:30;
487 unsigned int reserved9:3;
488 unsigned int address_lo_64b:29;
490 unsigned int ordinal4;
493 unsigned int address_hi;
495 unsigned int data_lo;
497 unsigned int data_hi;
502 CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014