2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #ifndef KFD_PM4_HEADERS_H_
25 #define KFD_PM4_HEADERS_H_
27 #ifndef PM4_MES_HEADER_DEFINED
28 #define PM4_MES_HEADER_DEFINED
29 union PM4_MES_TYPE_3_HEADER {
35 /* number of DWORDs - 1 in the information body */
37 /* packet identifier. It should be 3 for type 3 packets */
42 #endif /* PM4_MES_HEADER_DEFINED */
45 /*--------------------MES_MAP_PROCESS-------------------- */
47 #ifndef PM4_MES_MAP_PROCESS_DEFINED
48 #define PM4_MES_MAP_PROCESS_DEFINED
50 struct pm4_map_process {
52 union PM4_MES_TYPE_3_HEADER header; /* header */
60 uint32_t diq_enable:1;
61 uint32_t process_quantum:7;
68 uint32_t page_table_base:28;
74 uint32_t sh_mem_bases;
75 uint32_t sh_mem_ape1_base;
76 uint32_t sh_mem_ape1_limit;
77 uint32_t sh_mem_config;
88 uint32_t num_queues:10;
96 #ifndef PM4_MES_MAP_PROCESS_DEFINED_KV_SCRATCH
97 #define PM4_MES_MAP_PROCESS_DEFINED_KV_SCRATCH
99 struct pm4_map_process_scratch_kv {
101 union PM4_MES_TYPE_3_HEADER header; /* header */
108 uint32_t reserved1:8;
109 uint32_t diq_enable:1;
110 uint32_t process_quantum:7;
117 uint32_t page_table_base:28;
118 uint32_t reserved2:4;
124 uint32_t sh_mem_bases;
125 uint32_t sh_mem_config;
126 uint32_t sh_mem_ape1_base;
127 uint32_t sh_mem_ape1_limit;
128 uint32_t sh_hidden_private_base_vmid;
131 uint32_t gds_addr_lo;
132 uint32_t gds_addr_hi;
137 uint32_t reserved6:2;
139 uint32_t reserved7:4;
141 uint32_t num_queues:10;
146 uint32_t completion_signal_lo32;
147 uint32_t completion_signal_hi32;
152 CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014
155 #endif /* KFD_PM4_HEADERS_H_ */