2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/ratelimit.h>
25 #include <linux/printk.h>
26 #include <linux/slab.h>
27 #include <linux/list.h>
28 #include <linux/types.h>
29 #include <linux/bitops.h>
30 #include <linux/sched.h>
32 #include "kfd_device_queue_manager.h"
33 #include "kfd_mqd_manager.h"
35 #include "kfd_kernel_queue.h"
36 #include "amdgpu_amdkfd.h"
38 /* Size of the per-pipe EOP queue */
39 #define CIK_HPD_EOP_BYTES_LOG2 11
40 #define CIK_HPD_EOP_BYTES (1U << CIK_HPD_EOP_BYTES_LOG2)
42 static int set_pasid_vmid_mapping(struct device_queue_manager *dqm,
43 unsigned int pasid, unsigned int vmid);
45 static int execute_queues_cpsch(struct device_queue_manager *dqm,
46 enum kfd_unmap_queues_filter filter,
47 uint32_t filter_param);
48 static int unmap_queues_cpsch(struct device_queue_manager *dqm,
49 enum kfd_unmap_queues_filter filter,
50 uint32_t filter_param);
52 static int map_queues_cpsch(struct device_queue_manager *dqm);
54 static void deallocate_sdma_queue(struct device_queue_manager *dqm,
57 static inline void deallocate_hqd(struct device_queue_manager *dqm,
59 static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q);
60 static int allocate_sdma_queue(struct device_queue_manager *dqm,
62 static void kfd_process_hw_exception(struct work_struct *work);
65 enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum kfd_queue_type type)
67 if (type == KFD_QUEUE_TYPE_SDMA || type == KFD_QUEUE_TYPE_SDMA_XGMI)
68 return KFD_MQD_TYPE_SDMA;
69 return KFD_MQD_TYPE_CP;
72 static bool is_pipe_enabled(struct device_queue_manager *dqm, int mec, int pipe)
75 int pipe_offset = mec * dqm->dev->shared_resources.num_pipe_per_mec
76 + pipe * dqm->dev->shared_resources.num_queue_per_pipe;
78 /* queue is available for KFD usage if bit is 1 */
79 for (i = 0; i < dqm->dev->shared_resources.num_queue_per_pipe; ++i)
80 if (test_bit(pipe_offset + i,
81 dqm->dev->shared_resources.queue_bitmap))
86 unsigned int get_queues_num(struct device_queue_manager *dqm)
88 return bitmap_weight(dqm->dev->shared_resources.queue_bitmap,
92 unsigned int get_queues_per_pipe(struct device_queue_manager *dqm)
94 return dqm->dev->shared_resources.num_queue_per_pipe;
97 unsigned int get_pipes_per_mec(struct device_queue_manager *dqm)
99 return dqm->dev->shared_resources.num_pipe_per_mec;
102 static unsigned int get_num_sdma_engines(struct device_queue_manager *dqm)
104 return dqm->dev->device_info->num_sdma_engines;
107 static unsigned int get_num_xgmi_sdma_engines(struct device_queue_manager *dqm)
109 return dqm->dev->device_info->num_xgmi_sdma_engines;
112 unsigned int get_num_sdma_queues(struct device_queue_manager *dqm)
114 return dqm->dev->device_info->num_sdma_engines
115 * dqm->dev->device_info->num_sdma_queues_per_engine;
118 unsigned int get_num_xgmi_sdma_queues(struct device_queue_manager *dqm)
120 return dqm->dev->device_info->num_xgmi_sdma_engines
121 * dqm->dev->device_info->num_sdma_queues_per_engine;
124 void program_sh_mem_settings(struct device_queue_manager *dqm,
125 struct qcm_process_device *qpd)
127 return dqm->dev->kfd2kgd->program_sh_mem_settings(
128 dqm->dev->kgd, qpd->vmid,
130 qpd->sh_mem_ape1_base,
131 qpd->sh_mem_ape1_limit,
135 static int allocate_doorbell(struct qcm_process_device *qpd, struct queue *q)
137 struct kfd_dev *dev = qpd->dqm->dev;
139 if (!KFD_IS_SOC15(dev->device_info->asic_family)) {
140 /* On pre-SOC15 chips we need to use the queue ID to
141 * preserve the user mode ABI.
143 q->doorbell_id = q->properties.queue_id;
144 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
145 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
146 /* For SDMA queues on SOC15 with 8-byte doorbell, use static
147 * doorbell assignments based on the engine and queue id.
148 * The doobell index distance between RLC (2*i) and (2*i+1)
149 * for a SDMA engine is 512.
151 uint32_t *idx_offset =
152 dev->shared_resources.sdma_doorbell_idx;
154 q->doorbell_id = idx_offset[q->properties.sdma_engine_id]
155 + (q->properties.sdma_queue_id & 1)
156 * KFD_QUEUE_DOORBELL_MIRROR_OFFSET
157 + (q->properties.sdma_queue_id >> 1);
159 /* For CP queues on SOC15 reserve a free doorbell ID */
162 found = find_first_zero_bit(qpd->doorbell_bitmap,
163 KFD_MAX_NUM_OF_QUEUES_PER_PROCESS);
164 if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) {
165 pr_debug("No doorbells available");
168 set_bit(found, qpd->doorbell_bitmap);
169 q->doorbell_id = found;
172 q->properties.doorbell_off =
173 kfd_get_doorbell_dw_offset_in_bar(dev, q->process,
179 static void deallocate_doorbell(struct qcm_process_device *qpd,
183 struct kfd_dev *dev = qpd->dqm->dev;
185 if (!KFD_IS_SOC15(dev->device_info->asic_family) ||
186 q->properties.type == KFD_QUEUE_TYPE_SDMA ||
187 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
190 old = test_and_clear_bit(q->doorbell_id, qpd->doorbell_bitmap);
194 static int allocate_vmid(struct device_queue_manager *dqm,
195 struct qcm_process_device *qpd,
198 int allocated_vmid = -1, i;
200 for (i = dqm->dev->vm_info.first_vmid_kfd;
201 i <= dqm->dev->vm_info.last_vmid_kfd; i++) {
202 if (!dqm->vmid_pasid[i]) {
208 if (allocated_vmid < 0) {
209 pr_err("no more vmid to allocate\n");
213 pr_debug("vmid allocated: %d\n", allocated_vmid);
215 dqm->vmid_pasid[allocated_vmid] = q->process->pasid;
217 set_pasid_vmid_mapping(dqm, q->process->pasid, allocated_vmid);
219 qpd->vmid = allocated_vmid;
220 q->properties.vmid = allocated_vmid;
222 program_sh_mem_settings(dqm, qpd);
224 /* qpd->page_table_base is set earlier when register_process()
225 * is called, i.e. when the first queue is created.
227 dqm->dev->kfd2kgd->set_vm_context_page_table_base(dqm->dev->kgd,
229 qpd->page_table_base);
230 /* invalidate the VM context after pasid and vmid mapping is set up */
231 kfd_flush_tlb(qpd_to_pdd(qpd));
233 if (dqm->dev->kfd2kgd->set_scratch_backing_va)
234 dqm->dev->kfd2kgd->set_scratch_backing_va(dqm->dev->kgd,
235 qpd->sh_hidden_private_base, qpd->vmid);
240 static int flush_texture_cache_nocpsch(struct kfd_dev *kdev,
241 struct qcm_process_device *qpd)
243 const struct packet_manager_funcs *pmf = qpd->dqm->packets.pmf;
249 ret = pmf->release_mem(qpd->ib_base, (uint32_t *)qpd->ib_kaddr);
253 return amdgpu_amdkfd_submit_ib(kdev->kgd, KGD_ENGINE_MEC1, qpd->vmid,
254 qpd->ib_base, (uint32_t *)qpd->ib_kaddr,
255 pmf->release_mem_size / sizeof(uint32_t));
258 static void deallocate_vmid(struct device_queue_manager *dqm,
259 struct qcm_process_device *qpd,
262 /* On GFX v7, CP doesn't flush TC at dequeue */
263 if (q->device->device_info->asic_family == CHIP_HAWAII)
264 if (flush_texture_cache_nocpsch(q->device, qpd))
265 pr_err("Failed to flush TC\n");
267 kfd_flush_tlb(qpd_to_pdd(qpd));
269 /* Release the vmid mapping */
270 set_pasid_vmid_mapping(dqm, 0, qpd->vmid);
271 dqm->vmid_pasid[qpd->vmid] = 0;
274 q->properties.vmid = 0;
277 static int create_queue_nocpsch(struct device_queue_manager *dqm,
279 struct qcm_process_device *qpd)
281 struct mqd_manager *mqd_mgr;
288 if (dqm->total_queue_count >= max_num_of_queues_per_device) {
289 pr_warn("Can't create new usermode queue because %d queues were already created\n",
290 dqm->total_queue_count);
295 if (list_empty(&qpd->queues_list)) {
296 retval = allocate_vmid(dqm, qpd, q);
300 q->properties.vmid = qpd->vmid;
302 * Eviction state logic: mark all queues as evicted, even ones
303 * not currently active. Restoring inactive queues later only
304 * updates the is_evicted flag but is a no-op otherwise.
306 q->properties.is_evicted = !!qpd->evicted;
308 q->properties.tba_addr = qpd->tba_addr;
309 q->properties.tma_addr = qpd->tma_addr;
311 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
312 q->properties.type)];
313 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) {
314 retval = allocate_hqd(dqm, q);
316 goto deallocate_vmid;
317 pr_debug("Loading mqd to hqd on pipe %d, queue %d\n",
319 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
320 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
321 retval = allocate_sdma_queue(dqm, q);
323 goto deallocate_vmid;
324 dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
327 retval = allocate_doorbell(qpd, q);
329 goto out_deallocate_hqd;
331 /* Temporarily release dqm lock to avoid a circular lock dependency */
333 q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties);
336 if (!q->mqd_mem_obj) {
338 goto out_deallocate_doorbell;
340 mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj,
341 &q->gart_mqd_addr, &q->properties);
342 if (q->properties.is_active) {
343 if (!dqm->sched_running) {
344 WARN_ONCE(1, "Load non-HWS mqd while stopped\n");
345 goto add_queue_to_list;
348 if (WARN(q->process->mm != current->mm,
349 "should only run in user thread"))
352 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe,
353 q->queue, &q->properties, current->mm);
359 list_add(&q->list, &qpd->queues_list);
361 if (q->properties.is_active)
364 if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
365 dqm->sdma_queue_count++;
366 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
367 dqm->xgmi_sdma_queue_count++;
370 * Unconditionally increment this counter, regardless of the queue's
371 * type or whether the queue is active.
373 dqm->total_queue_count++;
374 pr_debug("Total of %d queues are accountable so far\n",
375 dqm->total_queue_count);
379 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
380 out_deallocate_doorbell:
381 deallocate_doorbell(qpd, q);
383 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE)
384 deallocate_hqd(dqm, q);
385 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
386 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
387 deallocate_sdma_queue(dqm, q);
389 if (list_empty(&qpd->queues_list))
390 deallocate_vmid(dqm, qpd, q);
396 static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q)
403 for (pipe = dqm->next_pipe_to_allocate, i = 0;
404 i < get_pipes_per_mec(dqm);
405 pipe = ((pipe + 1) % get_pipes_per_mec(dqm)), ++i) {
407 if (!is_pipe_enabled(dqm, 0, pipe))
410 if (dqm->allocated_queues[pipe] != 0) {
411 bit = ffs(dqm->allocated_queues[pipe]) - 1;
412 dqm->allocated_queues[pipe] &= ~(1 << bit);
423 pr_debug("hqd slot - pipe %d, queue %d\n", q->pipe, q->queue);
424 /* horizontal hqd allocation */
425 dqm->next_pipe_to_allocate = (pipe + 1) % get_pipes_per_mec(dqm);
430 static inline void deallocate_hqd(struct device_queue_manager *dqm,
433 dqm->allocated_queues[q->pipe] |= (1 << q->queue);
436 /* Access to DQM has to be locked before calling destroy_queue_nocpsch_locked
437 * to avoid asynchronized access
439 static int destroy_queue_nocpsch_locked(struct device_queue_manager *dqm,
440 struct qcm_process_device *qpd,
444 struct mqd_manager *mqd_mgr;
446 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
447 q->properties.type)];
449 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) {
450 deallocate_hqd(dqm, q);
451 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
452 dqm->sdma_queue_count--;
453 deallocate_sdma_queue(dqm, q);
454 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
455 dqm->xgmi_sdma_queue_count--;
456 deallocate_sdma_queue(dqm, q);
458 pr_debug("q->properties.type %d is invalid\n",
462 dqm->total_queue_count--;
464 deallocate_doorbell(qpd, q);
466 if (!dqm->sched_running) {
467 WARN_ONCE(1, "Destroy non-HWS queue while stopped\n");
471 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
472 KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
473 KFD_UNMAP_LATENCY_MS,
475 if (retval == -ETIME)
476 qpd->reset_wavefronts = true;
478 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
481 if (list_empty(&qpd->queues_list)) {
482 if (qpd->reset_wavefronts) {
483 pr_warn("Resetting wave fronts (nocpsch) on dev %p\n",
485 /* dbgdev_wave_reset_wavefronts has to be called before
486 * deallocate_vmid(), i.e. when vmid is still in use.
488 dbgdev_wave_reset_wavefronts(dqm->dev,
490 qpd->reset_wavefronts = false;
493 deallocate_vmid(dqm, qpd, q);
496 if (q->properties.is_active)
502 static int destroy_queue_nocpsch(struct device_queue_manager *dqm,
503 struct qcm_process_device *qpd,
509 retval = destroy_queue_nocpsch_locked(dqm, qpd, q);
515 static int update_queue(struct device_queue_manager *dqm, struct queue *q)
518 struct mqd_manager *mqd_mgr;
519 struct kfd_process_device *pdd;
520 bool prev_active = false;
523 pdd = kfd_get_process_device_data(q->device, q->process);
528 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
529 q->properties.type)];
531 /* Save previous activity state for counters */
532 prev_active = q->properties.is_active;
534 /* Make sure the queue is unmapped before updating the MQD */
535 if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) {
536 retval = unmap_queues_cpsch(dqm,
537 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
539 pr_err("unmap queue failed\n");
542 } else if (prev_active &&
543 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
544 q->properties.type == KFD_QUEUE_TYPE_SDMA ||
545 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
547 if (!dqm->sched_running) {
548 WARN_ONCE(1, "Update non-HWS queue while stopped\n");
552 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
553 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN,
554 KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
556 pr_err("destroy mqd failed\n");
561 mqd_mgr->update_mqd(mqd_mgr, q->mqd, &q->properties);
564 * check active state vs. the previous state and modify
565 * counter accordingly. map_queues_cpsch uses the
566 * dqm->queue_count to determine whether a new runlist must be
569 if (q->properties.is_active && !prev_active)
571 else if (!q->properties.is_active && prev_active)
574 if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS)
575 retval = map_queues_cpsch(dqm);
576 else if (q->properties.is_active &&
577 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
578 q->properties.type == KFD_QUEUE_TYPE_SDMA ||
579 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
580 if (WARN(q->process->mm != current->mm,
581 "should only run in user thread"))
584 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd,
586 &q->properties, current->mm);
594 static int evict_process_queues_nocpsch(struct device_queue_manager *dqm,
595 struct qcm_process_device *qpd)
598 struct mqd_manager *mqd_mgr;
599 struct kfd_process_device *pdd;
603 if (qpd->evicted++ > 0) /* already evicted, do nothing */
606 pdd = qpd_to_pdd(qpd);
607 pr_info_ratelimited("Evicting PASID 0x%x queues\n",
608 pdd->process->pasid);
610 /* Mark all queues as evicted. Deactivate all active queues on
613 list_for_each_entry(q, &qpd->queues_list, list) {
614 q->properties.is_evicted = true;
615 if (!q->properties.is_active)
618 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
619 q->properties.type)];
620 q->properties.is_active = false;
623 if (WARN_ONCE(!dqm->sched_running, "Evict when stopped\n"))
626 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
627 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN,
628 KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
630 /* Return the first error, but keep going to
631 * maintain a consistent eviction state
641 static int evict_process_queues_cpsch(struct device_queue_manager *dqm,
642 struct qcm_process_device *qpd)
645 struct kfd_process_device *pdd;
649 if (qpd->evicted++ > 0) /* already evicted, do nothing */
652 pdd = qpd_to_pdd(qpd);
653 pr_info_ratelimited("Evicting PASID 0x%x queues\n",
654 pdd->process->pasid);
656 /* Mark all queues as evicted. Deactivate all active queues on
659 list_for_each_entry(q, &qpd->queues_list, list) {
660 q->properties.is_evicted = true;
661 if (!q->properties.is_active)
664 q->properties.is_active = false;
667 retval = execute_queues_cpsch(dqm,
669 KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES :
670 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
677 static int restore_process_queues_nocpsch(struct device_queue_manager *dqm,
678 struct qcm_process_device *qpd)
680 struct mm_struct *mm = NULL;
682 struct mqd_manager *mqd_mgr;
683 struct kfd_process_device *pdd;
687 pdd = qpd_to_pdd(qpd);
688 /* Retrieve PD base */
689 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->vm);
692 if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */
694 if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */
699 pr_info_ratelimited("Restoring PASID 0x%x queues\n",
700 pdd->process->pasid);
702 /* Update PD Base in QPD */
703 qpd->page_table_base = pd_base;
704 pr_debug("Updated PD address to 0x%llx\n", pd_base);
706 if (!list_empty(&qpd->queues_list)) {
707 dqm->dev->kfd2kgd->set_vm_context_page_table_base(
710 qpd->page_table_base);
714 /* Take a safe reference to the mm_struct, which may otherwise
715 * disappear even while the kfd_process is still referenced.
717 mm = get_task_mm(pdd->process->lead_thread);
723 /* Remove the eviction flags. Activate queues that are not
724 * inactive for other reasons.
726 list_for_each_entry(q, &qpd->queues_list, list) {
727 q->properties.is_evicted = false;
728 if (!QUEUE_IS_ACTIVE(q->properties))
731 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
732 q->properties.type)];
733 q->properties.is_active = true;
736 if (WARN_ONCE(!dqm->sched_running, "Restore when stopped\n"))
739 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe,
740 q->queue, &q->properties, mm);
742 /* Return the first error, but keep going to
743 * maintain a consistent eviction state
755 static int restore_process_queues_cpsch(struct device_queue_manager *dqm,
756 struct qcm_process_device *qpd)
759 struct kfd_process_device *pdd;
763 pdd = qpd_to_pdd(qpd);
764 /* Retrieve PD base */
765 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->vm);
768 if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */
770 if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */
775 pr_info_ratelimited("Restoring PASID 0x%x queues\n",
776 pdd->process->pasid);
778 /* Update PD Base in QPD */
779 qpd->page_table_base = pd_base;
780 pr_debug("Updated PD address to 0x%llx\n", pd_base);
782 /* activate all active queues on the qpd */
783 list_for_each_entry(q, &qpd->queues_list, list) {
784 q->properties.is_evicted = false;
785 if (!QUEUE_IS_ACTIVE(q->properties))
788 q->properties.is_active = true;
791 retval = execute_queues_cpsch(dqm,
792 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
799 static int register_process(struct device_queue_manager *dqm,
800 struct qcm_process_device *qpd)
802 struct device_process_node *n;
803 struct kfd_process_device *pdd;
807 n = kzalloc(sizeof(*n), GFP_KERNEL);
813 pdd = qpd_to_pdd(qpd);
814 /* Retrieve PD base */
815 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->vm);
818 list_add(&n->list, &dqm->queues);
820 /* Update PD Base in QPD */
821 qpd->page_table_base = pd_base;
822 pr_debug("Updated PD address to 0x%llx\n", pd_base);
824 retval = dqm->asic_ops.update_qpd(dqm, qpd);
826 dqm->processes_count++;
830 /* Outside the DQM lock because under the DQM lock we can't do
831 * reclaim or take other locks that others hold while reclaiming.
833 kfd_inc_compute_active(dqm->dev);
838 static int unregister_process(struct device_queue_manager *dqm,
839 struct qcm_process_device *qpd)
842 struct device_process_node *cur, *next;
844 pr_debug("qpd->queues_list is %s\n",
845 list_empty(&qpd->queues_list) ? "empty" : "not empty");
850 list_for_each_entry_safe(cur, next, &dqm->queues, list) {
851 if (qpd == cur->qpd) {
852 list_del(&cur->list);
854 dqm->processes_count--;
858 /* qpd not found in dqm list */
863 /* Outside the DQM lock because under the DQM lock we can't do
864 * reclaim or take other locks that others hold while reclaiming.
867 kfd_dec_compute_active(dqm->dev);
873 set_pasid_vmid_mapping(struct device_queue_manager *dqm, unsigned int pasid,
876 return dqm->dev->kfd2kgd->set_pasid_vmid_mapping(
877 dqm->dev->kgd, pasid, vmid);
880 static void init_interrupts(struct device_queue_manager *dqm)
884 for (i = 0 ; i < get_pipes_per_mec(dqm) ; i++)
885 if (is_pipe_enabled(dqm, 0, i))
886 dqm->dev->kfd2kgd->init_interrupts(dqm->dev->kgd, i);
889 static int initialize_nocpsch(struct device_queue_manager *dqm)
893 pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm));
895 dqm->allocated_queues = kcalloc(get_pipes_per_mec(dqm),
896 sizeof(unsigned int), GFP_KERNEL);
897 if (!dqm->allocated_queues)
900 mutex_init(&dqm->lock_hidden);
901 INIT_LIST_HEAD(&dqm->queues);
902 dqm->queue_count = dqm->next_pipe_to_allocate = 0;
903 dqm->sdma_queue_count = 0;
904 dqm->xgmi_sdma_queue_count = 0;
906 for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) {
907 int pipe_offset = pipe * get_queues_per_pipe(dqm);
909 for (queue = 0; queue < get_queues_per_pipe(dqm); queue++)
910 if (test_bit(pipe_offset + queue,
911 dqm->dev->shared_resources.queue_bitmap))
912 dqm->allocated_queues[pipe] |= 1 << queue;
915 memset(dqm->vmid_pasid, 0, sizeof(dqm->vmid_pasid));
917 dqm->sdma_bitmap = ~0ULL >> (64 - get_num_sdma_queues(dqm));
918 dqm->xgmi_sdma_bitmap = ~0ULL >> (64 - get_num_xgmi_sdma_queues(dqm));
923 static void uninitialize(struct device_queue_manager *dqm)
927 WARN_ON(dqm->queue_count > 0 || dqm->processes_count > 0);
929 kfree(dqm->allocated_queues);
930 for (i = 0 ; i < KFD_MQD_TYPE_MAX ; i++)
931 kfree(dqm->mqd_mgrs[i]);
932 mutex_destroy(&dqm->lock_hidden);
935 static int start_nocpsch(struct device_queue_manager *dqm)
937 init_interrupts(dqm);
939 if (dqm->dev->device_info->asic_family == CHIP_HAWAII)
940 return pm_init(&dqm->packets, dqm);
941 dqm->sched_running = true;
946 static int stop_nocpsch(struct device_queue_manager *dqm)
948 if (dqm->dev->device_info->asic_family == CHIP_HAWAII)
949 pm_uninit(&dqm->packets, false);
950 dqm->sched_running = false;
955 static void pre_reset(struct device_queue_manager *dqm)
958 dqm->is_resetting = true;
962 static int allocate_sdma_queue(struct device_queue_manager *dqm,
967 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
968 if (dqm->sdma_bitmap == 0)
970 bit = __ffs64(dqm->sdma_bitmap);
971 dqm->sdma_bitmap &= ~(1ULL << bit);
973 q->properties.sdma_engine_id = q->sdma_id %
974 get_num_sdma_engines(dqm);
975 q->properties.sdma_queue_id = q->sdma_id /
976 get_num_sdma_engines(dqm);
977 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
978 if (dqm->xgmi_sdma_bitmap == 0)
980 bit = __ffs64(dqm->xgmi_sdma_bitmap);
981 dqm->xgmi_sdma_bitmap &= ~(1ULL << bit);
983 /* sdma_engine_id is sdma id including
984 * both PCIe-optimized SDMAs and XGMI-
985 * optimized SDMAs. The calculation below
986 * assumes the first N engines are always
987 * PCIe-optimized ones
989 q->properties.sdma_engine_id = get_num_sdma_engines(dqm) +
990 q->sdma_id % get_num_xgmi_sdma_engines(dqm);
991 q->properties.sdma_queue_id = q->sdma_id /
992 get_num_xgmi_sdma_engines(dqm);
995 pr_debug("SDMA engine id: %d\n", q->properties.sdma_engine_id);
996 pr_debug("SDMA queue id: %d\n", q->properties.sdma_queue_id);
1001 static void deallocate_sdma_queue(struct device_queue_manager *dqm,
1004 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
1005 if (q->sdma_id >= get_num_sdma_queues(dqm))
1007 dqm->sdma_bitmap |= (1ULL << q->sdma_id);
1008 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
1009 if (q->sdma_id >= get_num_xgmi_sdma_queues(dqm))
1011 dqm->xgmi_sdma_bitmap |= (1ULL << q->sdma_id);
1016 * Device Queue Manager implementation for cp scheduler
1019 static int set_sched_resources(struct device_queue_manager *dqm)
1022 struct scheduling_resources res;
1024 res.vmid_mask = dqm->dev->shared_resources.compute_vmid_bitmap;
1027 for (i = 0; i < KGD_MAX_QUEUES; ++i) {
1028 mec = (i / dqm->dev->shared_resources.num_queue_per_pipe)
1029 / dqm->dev->shared_resources.num_pipe_per_mec;
1031 if (!test_bit(i, dqm->dev->shared_resources.queue_bitmap))
1034 /* only acquire queues from the first MEC */
1038 /* This situation may be hit in the future if a new HW
1039 * generation exposes more than 64 queues. If so, the
1040 * definition of res.queue_mask needs updating
1042 if (WARN_ON(i >= (sizeof(res.queue_mask)*8))) {
1043 pr_err("Invalid queue enabled by amdgpu: %d\n", i);
1047 res.queue_mask |= (1ull << i);
1049 res.gws_mask = ~0ull;
1050 res.oac_mask = res.gds_heap_base = res.gds_heap_size = 0;
1052 pr_debug("Scheduling resources:\n"
1053 "vmid mask: 0x%8X\n"
1054 "queue mask: 0x%8llX\n",
1055 res.vmid_mask, res.queue_mask);
1057 return pm_send_set_resources(&dqm->packets, &res);
1060 static int initialize_cpsch(struct device_queue_manager *dqm)
1062 pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm));
1064 mutex_init(&dqm->lock_hidden);
1065 INIT_LIST_HEAD(&dqm->queues);
1066 dqm->queue_count = dqm->processes_count = 0;
1067 dqm->sdma_queue_count = 0;
1068 dqm->xgmi_sdma_queue_count = 0;
1069 dqm->active_runlist = false;
1070 dqm->sdma_bitmap = ~0ULL >> (64 - get_num_sdma_queues(dqm));
1071 dqm->xgmi_sdma_bitmap = ~0ULL >> (64 - get_num_xgmi_sdma_queues(dqm));
1073 INIT_WORK(&dqm->hw_exception_work, kfd_process_hw_exception);
1078 static int start_cpsch(struct device_queue_manager *dqm)
1084 retval = pm_init(&dqm->packets, dqm);
1086 goto fail_packet_manager_init;
1088 retval = set_sched_resources(dqm);
1090 goto fail_set_sched_resources;
1092 pr_debug("Allocating fence memory\n");
1094 /* allocate fence memory on the gart */
1095 retval = kfd_gtt_sa_allocate(dqm->dev, sizeof(*dqm->fence_addr),
1099 goto fail_allocate_vidmem;
1101 dqm->fence_addr = dqm->fence_mem->cpu_ptr;
1102 dqm->fence_gpu_addr = dqm->fence_mem->gpu_addr;
1104 init_interrupts(dqm);
1107 /* clear hang status when driver try to start the hw scheduler */
1108 dqm->is_hws_hang = false;
1109 dqm->is_resetting = false;
1110 dqm->sched_running = true;
1111 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
1115 fail_allocate_vidmem:
1116 fail_set_sched_resources:
1117 pm_uninit(&dqm->packets, false);
1118 fail_packet_manager_init:
1122 static int stop_cpsch(struct device_queue_manager *dqm)
1127 if (!dqm->is_hws_hang)
1128 unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
1129 hanging = dqm->is_hws_hang || dqm->is_resetting;
1130 dqm->sched_running = false;
1133 kfd_gtt_sa_free(dqm->dev, dqm->fence_mem);
1134 pm_uninit(&dqm->packets, hanging);
1139 static int create_kernel_queue_cpsch(struct device_queue_manager *dqm,
1140 struct kernel_queue *kq,
1141 struct qcm_process_device *qpd)
1144 if (dqm->total_queue_count >= max_num_of_queues_per_device) {
1145 pr_warn("Can't create new kernel queue because %d queues were already created\n",
1146 dqm->total_queue_count);
1152 * Unconditionally increment this counter, regardless of the queue's
1153 * type or whether the queue is active.
1155 dqm->total_queue_count++;
1156 pr_debug("Total of %d queues are accountable so far\n",
1157 dqm->total_queue_count);
1159 list_add(&kq->list, &qpd->priv_queue_list);
1161 qpd->is_debug = true;
1162 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
1168 static void destroy_kernel_queue_cpsch(struct device_queue_manager *dqm,
1169 struct kernel_queue *kq,
1170 struct qcm_process_device *qpd)
1173 list_del(&kq->list);
1175 qpd->is_debug = false;
1176 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
1178 * Unconditionally decrement this counter, regardless of the queue's
1181 dqm->total_queue_count--;
1182 pr_debug("Total of %d queues are accountable so far\n",
1183 dqm->total_queue_count);
1187 static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q,
1188 struct qcm_process_device *qpd)
1191 struct mqd_manager *mqd_mgr;
1193 if (dqm->total_queue_count >= max_num_of_queues_per_device) {
1194 pr_warn("Can't create new usermode queue because %d queues were already created\n",
1195 dqm->total_queue_count);
1200 if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
1201 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
1203 retval = allocate_sdma_queue(dqm, q);
1209 retval = allocate_doorbell(qpd, q);
1211 goto out_deallocate_sdma_queue;
1213 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
1214 q->properties.type)];
1216 if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
1217 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
1218 dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
1219 q->properties.tba_addr = qpd->tba_addr;
1220 q->properties.tma_addr = qpd->tma_addr;
1221 q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties);
1222 if (!q->mqd_mem_obj) {
1224 goto out_deallocate_doorbell;
1229 * Eviction state logic: mark all queues as evicted, even ones
1230 * not currently active. Restoring inactive queues later only
1231 * updates the is_evicted flag but is a no-op otherwise.
1233 q->properties.is_evicted = !!qpd->evicted;
1234 mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj,
1235 &q->gart_mqd_addr, &q->properties);
1237 list_add(&q->list, &qpd->queues_list);
1239 if (q->properties.is_active) {
1241 retval = execute_queues_cpsch(dqm,
1242 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
1245 if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
1246 dqm->sdma_queue_count++;
1247 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
1248 dqm->xgmi_sdma_queue_count++;
1250 * Unconditionally increment this counter, regardless of the queue's
1251 * type or whether the queue is active.
1253 dqm->total_queue_count++;
1255 pr_debug("Total of %d queues are accountable so far\n",
1256 dqm->total_queue_count);
1261 out_deallocate_doorbell:
1262 deallocate_doorbell(qpd, q);
1263 out_deallocate_sdma_queue:
1264 if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
1265 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
1267 deallocate_sdma_queue(dqm, q);
1274 int amdkfd_fence_wait_timeout(unsigned int *fence_addr,
1275 unsigned int fence_value,
1276 unsigned int timeout_ms)
1278 unsigned long end_jiffies = msecs_to_jiffies(timeout_ms) + jiffies;
1280 while (*fence_addr != fence_value) {
1281 if (time_after(jiffies, end_jiffies)) {
1282 pr_err("qcm fence wait loop timeout expired\n");
1283 /* In HWS case, this is used to halt the driver thread
1284 * in order not to mess up CP states before doing
1285 * scandumps for FW debugging.
1287 while (halt_if_hws_hang)
1298 static int unmap_sdma_queues(struct device_queue_manager *dqm)
1302 for (i = 0; i < dqm->dev->device_info->num_sdma_engines +
1303 dqm->dev->device_info->num_xgmi_sdma_engines; i++) {
1304 retval = pm_send_unmap_queue(&dqm->packets, KFD_QUEUE_TYPE_SDMA,
1305 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, false, i);
1312 /* dqm->lock mutex has to be locked before calling this function */
1313 static int map_queues_cpsch(struct device_queue_manager *dqm)
1317 if (!dqm->sched_running)
1319 if (dqm->queue_count <= 0 || dqm->processes_count <= 0)
1321 if (dqm->active_runlist)
1324 retval = pm_send_runlist(&dqm->packets, &dqm->queues);
1325 pr_debug("%s sent runlist\n", __func__);
1327 pr_err("failed to execute runlist\n");
1330 dqm->active_runlist = true;
1335 /* dqm->lock mutex has to be locked before calling this function */
1336 static int unmap_queues_cpsch(struct device_queue_manager *dqm,
1337 enum kfd_unmap_queues_filter filter,
1338 uint32_t filter_param)
1342 if (!dqm->sched_running)
1344 if (dqm->is_hws_hang)
1346 if (!dqm->active_runlist)
1349 pr_debug("Before destroying queues, sdma queue count is : %u, xgmi sdma queue count is : %u\n",
1350 dqm->sdma_queue_count, dqm->xgmi_sdma_queue_count);
1352 if (dqm->sdma_queue_count > 0 || dqm->xgmi_sdma_queue_count)
1353 unmap_sdma_queues(dqm);
1355 retval = pm_send_unmap_queue(&dqm->packets, KFD_QUEUE_TYPE_COMPUTE,
1356 filter, filter_param, false, 0);
1360 *dqm->fence_addr = KFD_FENCE_INIT;
1361 pm_send_query_status(&dqm->packets, dqm->fence_gpu_addr,
1362 KFD_FENCE_COMPLETED);
1363 /* should be timed out */
1364 retval = amdkfd_fence_wait_timeout(dqm->fence_addr, KFD_FENCE_COMPLETED,
1365 queue_preemption_timeout_ms);
1367 pr_err("The cp might be in an unrecoverable state due to an unsuccessful queues preemption\n");
1368 dqm->is_hws_hang = true;
1369 /* It's possible we're detecting a HWS hang in the
1370 * middle of a GPU reset. No need to schedule another
1371 * reset in this case.
1373 if (!dqm->is_resetting)
1374 schedule_work(&dqm->hw_exception_work);
1378 pm_release_ib(&dqm->packets);
1379 dqm->active_runlist = false;
1384 /* dqm->lock mutex has to be locked before calling this function */
1385 static int execute_queues_cpsch(struct device_queue_manager *dqm,
1386 enum kfd_unmap_queues_filter filter,
1387 uint32_t filter_param)
1391 if (dqm->is_hws_hang)
1393 retval = unmap_queues_cpsch(dqm, filter, filter_param);
1397 return map_queues_cpsch(dqm);
1400 static int destroy_queue_cpsch(struct device_queue_manager *dqm,
1401 struct qcm_process_device *qpd,
1405 struct mqd_manager *mqd_mgr;
1409 /* remove queue from list to prevent rescheduling after preemption */
1412 if (qpd->is_debug) {
1414 * error, currently we do not allow to destroy a queue
1415 * of a currently debugged process
1418 goto failed_try_destroy_debugged_queue;
1422 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
1423 q->properties.type)];
1425 deallocate_doorbell(qpd, q);
1427 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
1428 dqm->sdma_queue_count--;
1429 deallocate_sdma_queue(dqm, q);
1430 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
1431 dqm->xgmi_sdma_queue_count--;
1432 deallocate_sdma_queue(dqm, q);
1437 if (q->properties.is_active) {
1439 retval = execute_queues_cpsch(dqm,
1440 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
1441 if (retval == -ETIME)
1442 qpd->reset_wavefronts = true;
1446 * Unconditionally decrement this counter, regardless of the queue's
1449 dqm->total_queue_count--;
1450 pr_debug("Total of %d queues are accountable so far\n",
1451 dqm->total_queue_count);
1455 /* Do free_mqd after dqm_unlock(dqm) to avoid circular locking */
1456 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
1460 failed_try_destroy_debugged_queue:
1467 * Low bits must be 0000/FFFF as required by HW, high bits must be 0 to
1468 * stay in user mode.
1470 #define APE1_FIXED_BITS_MASK 0xFFFF80000000FFFFULL
1471 /* APE1 limit is inclusive and 64K aligned. */
1472 #define APE1_LIMIT_ALIGNMENT 0xFFFF
1474 static bool set_cache_memory_policy(struct device_queue_manager *dqm,
1475 struct qcm_process_device *qpd,
1476 enum cache_policy default_policy,
1477 enum cache_policy alternate_policy,
1478 void __user *alternate_aperture_base,
1479 uint64_t alternate_aperture_size)
1483 if (!dqm->asic_ops.set_cache_memory_policy)
1488 if (alternate_aperture_size == 0) {
1489 /* base > limit disables APE1 */
1490 qpd->sh_mem_ape1_base = 1;
1491 qpd->sh_mem_ape1_limit = 0;
1494 * In FSA64, APE1_Base[63:0] = { 16{SH_MEM_APE1_BASE[31]},
1495 * SH_MEM_APE1_BASE[31:0], 0x0000 }
1496 * APE1_Limit[63:0] = { 16{SH_MEM_APE1_LIMIT[31]},
1497 * SH_MEM_APE1_LIMIT[31:0], 0xFFFF }
1498 * Verify that the base and size parameters can be
1499 * represented in this format and convert them.
1500 * Additionally restrict APE1 to user-mode addresses.
1503 uint64_t base = (uintptr_t)alternate_aperture_base;
1504 uint64_t limit = base + alternate_aperture_size - 1;
1506 if (limit <= base || (base & APE1_FIXED_BITS_MASK) != 0 ||
1507 (limit & APE1_FIXED_BITS_MASK) != APE1_LIMIT_ALIGNMENT) {
1512 qpd->sh_mem_ape1_base = base >> 16;
1513 qpd->sh_mem_ape1_limit = limit >> 16;
1516 retval = dqm->asic_ops.set_cache_memory_policy(
1521 alternate_aperture_base,
1522 alternate_aperture_size);
1524 if ((dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) && (qpd->vmid != 0))
1525 program_sh_mem_settings(dqm, qpd);
1527 pr_debug("sh_mem_config: 0x%x, ape1_base: 0x%x, ape1_limit: 0x%x\n",
1528 qpd->sh_mem_config, qpd->sh_mem_ape1_base,
1529 qpd->sh_mem_ape1_limit);
1536 static int set_trap_handler(struct device_queue_manager *dqm,
1537 struct qcm_process_device *qpd,
1543 if (dqm->dev->cwsr_enabled) {
1544 /* Jump from CWSR trap handler to user trap */
1545 tma = (uint64_t *)(qpd->cwsr_kaddr + KFD_CWSR_TMA_OFFSET);
1549 qpd->tba_addr = tba_addr;
1550 qpd->tma_addr = tma_addr;
1556 static int process_termination_nocpsch(struct device_queue_manager *dqm,
1557 struct qcm_process_device *qpd)
1559 struct queue *q, *next;
1560 struct device_process_node *cur, *next_dpn;
1566 /* Clear all user mode queues */
1567 list_for_each_entry_safe(q, next, &qpd->queues_list, list) {
1570 ret = destroy_queue_nocpsch_locked(dqm, qpd, q);
1575 /* Unregister process */
1576 list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) {
1577 if (qpd == cur->qpd) {
1578 list_del(&cur->list);
1580 dqm->processes_count--;
1588 /* Outside the DQM lock because under the DQM lock we can't do
1589 * reclaim or take other locks that others hold while reclaiming.
1592 kfd_dec_compute_active(dqm->dev);
1597 static int get_wave_state(struct device_queue_manager *dqm,
1599 void __user *ctl_stack,
1600 u32 *ctl_stack_used_size,
1601 u32 *save_area_used_size)
1603 struct mqd_manager *mqd_mgr;
1608 if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE ||
1609 q->properties.is_active || !q->device->cwsr_enabled) {
1614 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP];
1616 if (!mqd_mgr->get_wave_state) {
1621 r = mqd_mgr->get_wave_state(mqd_mgr, q->mqd, ctl_stack,
1622 ctl_stack_used_size, save_area_used_size);
1629 static int process_termination_cpsch(struct device_queue_manager *dqm,
1630 struct qcm_process_device *qpd)
1633 struct queue *q, *next;
1634 struct kernel_queue *kq, *kq_next;
1635 struct mqd_manager *mqd_mgr;
1636 struct device_process_node *cur, *next_dpn;
1637 enum kfd_unmap_queues_filter filter =
1638 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES;
1645 /* Clean all kernel queues */
1646 list_for_each_entry_safe(kq, kq_next, &qpd->priv_queue_list, list) {
1647 list_del(&kq->list);
1649 qpd->is_debug = false;
1650 dqm->total_queue_count--;
1651 filter = KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES;
1654 /* Clear all user mode queues */
1655 list_for_each_entry(q, &qpd->queues_list, list) {
1656 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
1657 dqm->sdma_queue_count--;
1658 deallocate_sdma_queue(dqm, q);
1659 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
1660 dqm->xgmi_sdma_queue_count--;
1661 deallocate_sdma_queue(dqm, q);
1664 if (q->properties.is_active)
1667 dqm->total_queue_count--;
1670 /* Unregister process */
1671 list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) {
1672 if (qpd == cur->qpd) {
1673 list_del(&cur->list);
1675 dqm->processes_count--;
1681 retval = execute_queues_cpsch(dqm, filter, 0);
1682 if ((!dqm->is_hws_hang) && (retval || qpd->reset_wavefronts)) {
1683 pr_warn("Resetting wave fronts (cpsch) on dev %p\n", dqm->dev);
1684 dbgdev_wave_reset_wavefronts(dqm->dev, qpd->pqm->process);
1685 qpd->reset_wavefronts = false;
1690 /* Outside the DQM lock because under the DQM lock we can't do
1691 * reclaim or take other locks that others hold while reclaiming.
1694 kfd_dec_compute_active(dqm->dev);
1696 /* Lastly, free mqd resources.
1697 * Do free_mqd() after dqm_unlock to avoid circular locking.
1699 list_for_each_entry_safe(q, next, &qpd->queues_list, list) {
1700 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
1701 q->properties.type)];
1704 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
1710 static int init_mqd_managers(struct device_queue_manager *dqm)
1713 struct mqd_manager *mqd_mgr;
1715 for (i = 0; i < KFD_MQD_TYPE_MAX; i++) {
1716 mqd_mgr = dqm->asic_ops.mqd_manager_init(i, dqm->dev);
1718 pr_err("mqd manager [%d] initialization failed\n", i);
1721 dqm->mqd_mgrs[i] = mqd_mgr;
1727 for (j = 0; j < i; j++) {
1728 kfree(dqm->mqd_mgrs[j]);
1729 dqm->mqd_mgrs[j] = NULL;
1735 /* Allocate one hiq mqd (HWS) and all SDMA mqd in a continuous trunk*/
1736 static int allocate_hiq_sdma_mqd(struct device_queue_manager *dqm)
1739 struct kfd_dev *dev = dqm->dev;
1740 struct kfd_mem_obj *mem_obj = &dqm->hiq_sdma_mqd;
1741 uint32_t size = dqm->mqd_mgrs[KFD_MQD_TYPE_SDMA]->mqd_size *
1742 (dev->device_info->num_sdma_engines +
1743 dev->device_info->num_xgmi_sdma_engines) *
1744 dev->device_info->num_sdma_queues_per_engine +
1745 dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size;
1747 retval = amdgpu_amdkfd_alloc_gtt_mem(dev->kgd, size,
1748 &(mem_obj->gtt_mem), &(mem_obj->gpu_addr),
1749 (void *)&(mem_obj->cpu_ptr), true);
1754 struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev)
1756 struct device_queue_manager *dqm;
1758 pr_debug("Loading device queue manager\n");
1760 dqm = kzalloc(sizeof(*dqm), GFP_KERNEL);
1764 switch (dev->device_info->asic_family) {
1765 /* HWS is not available on Hawaii. */
1767 /* HWS depends on CWSR for timely dequeue. CWSR is not
1768 * available on Tonga.
1770 * FIXME: This argument also applies to Kaveri.
1773 dqm->sched_policy = KFD_SCHED_POLICY_NO_HWS;
1776 dqm->sched_policy = sched_policy;
1781 switch (dqm->sched_policy) {
1782 case KFD_SCHED_POLICY_HWS:
1783 case KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION:
1784 /* initialize dqm for cp scheduling */
1785 dqm->ops.create_queue = create_queue_cpsch;
1786 dqm->ops.initialize = initialize_cpsch;
1787 dqm->ops.start = start_cpsch;
1788 dqm->ops.stop = stop_cpsch;
1789 dqm->ops.pre_reset = pre_reset;
1790 dqm->ops.destroy_queue = destroy_queue_cpsch;
1791 dqm->ops.update_queue = update_queue;
1792 dqm->ops.register_process = register_process;
1793 dqm->ops.unregister_process = unregister_process;
1794 dqm->ops.uninitialize = uninitialize;
1795 dqm->ops.create_kernel_queue = create_kernel_queue_cpsch;
1796 dqm->ops.destroy_kernel_queue = destroy_kernel_queue_cpsch;
1797 dqm->ops.set_cache_memory_policy = set_cache_memory_policy;
1798 dqm->ops.set_trap_handler = set_trap_handler;
1799 dqm->ops.process_termination = process_termination_cpsch;
1800 dqm->ops.evict_process_queues = evict_process_queues_cpsch;
1801 dqm->ops.restore_process_queues = restore_process_queues_cpsch;
1802 dqm->ops.get_wave_state = get_wave_state;
1804 case KFD_SCHED_POLICY_NO_HWS:
1805 /* initialize dqm for no cp scheduling */
1806 dqm->ops.start = start_nocpsch;
1807 dqm->ops.stop = stop_nocpsch;
1808 dqm->ops.pre_reset = pre_reset;
1809 dqm->ops.create_queue = create_queue_nocpsch;
1810 dqm->ops.destroy_queue = destroy_queue_nocpsch;
1811 dqm->ops.update_queue = update_queue;
1812 dqm->ops.register_process = register_process;
1813 dqm->ops.unregister_process = unregister_process;
1814 dqm->ops.initialize = initialize_nocpsch;
1815 dqm->ops.uninitialize = uninitialize;
1816 dqm->ops.set_cache_memory_policy = set_cache_memory_policy;
1817 dqm->ops.set_trap_handler = set_trap_handler;
1818 dqm->ops.process_termination = process_termination_nocpsch;
1819 dqm->ops.evict_process_queues = evict_process_queues_nocpsch;
1820 dqm->ops.restore_process_queues =
1821 restore_process_queues_nocpsch;
1822 dqm->ops.get_wave_state = get_wave_state;
1825 pr_err("Invalid scheduling policy %d\n", dqm->sched_policy);
1829 switch (dev->device_info->asic_family) {
1831 device_queue_manager_init_vi(&dqm->asic_ops);
1835 device_queue_manager_init_cik(&dqm->asic_ops);
1839 device_queue_manager_init_cik_hawaii(&dqm->asic_ops);
1844 case CHIP_POLARIS10:
1845 case CHIP_POLARIS11:
1846 case CHIP_POLARIS12:
1848 device_queue_manager_init_vi_tonga(&dqm->asic_ops);
1857 device_queue_manager_init_v9(&dqm->asic_ops);
1862 device_queue_manager_init_v10_navi10(&dqm->asic_ops);
1865 WARN(1, "Unexpected ASIC family %u",
1866 dev->device_info->asic_family);
1870 if (init_mqd_managers(dqm))
1873 if (allocate_hiq_sdma_mqd(dqm)) {
1874 pr_err("Failed to allocate hiq sdma mqd trunk buffer\n");
1878 if (!dqm->ops.initialize(dqm))
1886 static void deallocate_hiq_sdma_mqd(struct kfd_dev *dev,
1887 struct kfd_mem_obj *mqd)
1889 WARN(!mqd, "No hiq sdma mqd trunk to free");
1891 amdgpu_amdkfd_free_gtt_mem(dev->kgd, mqd->gtt_mem);
1894 void device_queue_manager_uninit(struct device_queue_manager *dqm)
1896 dqm->ops.uninitialize(dqm);
1897 deallocate_hiq_sdma_mqd(dqm->dev, &dqm->hiq_sdma_mqd);
1901 int kfd_process_vm_fault(struct device_queue_manager *dqm,
1904 struct kfd_process_device *pdd;
1905 struct kfd_process *p = kfd_lookup_process_by_pasid(pasid);
1910 pdd = kfd_get_process_device_data(dqm->dev, p);
1912 ret = dqm->ops.evict_process_queues(dqm, &pdd->qpd);
1913 kfd_unref_process(p);
1918 static void kfd_process_hw_exception(struct work_struct *work)
1920 struct device_queue_manager *dqm = container_of(work,
1921 struct device_queue_manager, hw_exception_work);
1922 amdgpu_amdkfd_gpu_reset(dqm->dev->kgd);
1925 #if defined(CONFIG_DEBUG_FS)
1927 static void seq_reg_dump(struct seq_file *m,
1928 uint32_t (*dump)[2], uint32_t n_regs)
1932 for (i = 0, count = 0; i < n_regs; i++) {
1934 dump[i-1][0] + sizeof(uint32_t) != dump[i][0]) {
1935 seq_printf(m, "%s %08x: %08x",
1937 dump[i][0], dump[i][1]);
1940 seq_printf(m, " %08x", dump[i][1]);
1948 int dqm_debugfs_hqds(struct seq_file *m, void *data)
1950 struct device_queue_manager *dqm = data;
1951 uint32_t (*dump)[2], n_regs;
1955 if (!dqm->sched_running) {
1956 seq_printf(m, " Device is stopped\n");
1961 r = dqm->dev->kfd2kgd->hqd_dump(dqm->dev->kgd,
1962 KFD_CIK_HIQ_PIPE, KFD_CIK_HIQ_QUEUE,
1965 seq_printf(m, " HIQ on MEC %d Pipe %d Queue %d\n",
1966 KFD_CIK_HIQ_PIPE/get_pipes_per_mec(dqm)+1,
1967 KFD_CIK_HIQ_PIPE%get_pipes_per_mec(dqm),
1969 seq_reg_dump(m, dump, n_regs);
1974 for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) {
1975 int pipe_offset = pipe * get_queues_per_pipe(dqm);
1977 for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) {
1978 if (!test_bit(pipe_offset + queue,
1979 dqm->dev->shared_resources.queue_bitmap))
1982 r = dqm->dev->kfd2kgd->hqd_dump(
1983 dqm->dev->kgd, pipe, queue, &dump, &n_regs);
1987 seq_printf(m, " CP Pipe %d, Queue %d\n",
1989 seq_reg_dump(m, dump, n_regs);
1995 for (pipe = 0; pipe < get_num_sdma_engines(dqm) +
1996 get_num_xgmi_sdma_engines(dqm); pipe++) {
1998 queue < dqm->dev->device_info->num_sdma_queues_per_engine;
2000 r = dqm->dev->kfd2kgd->hqd_sdma_dump(
2001 dqm->dev->kgd, pipe, queue, &dump, &n_regs);
2005 seq_printf(m, " SDMA Engine %d, RLC %d\n",
2007 seq_reg_dump(m, dump, n_regs);
2016 int dqm_debugfs_execute_queues(struct device_queue_manager *dqm)
2021 dqm->active_runlist = true;
2022 r = execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);