drivers/gpu/drm/amd/amdkfd/kfd_device.c

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 /*
   3  * Copyright 2014-2022 Advanced Micro Devices, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <linux/bsearch.h>
  25 #include <linux/pci.h>
  26 #include <linux/slab.h>
  27 #include "kfd_priv.h"
  28 #include "kfd_device_queue_manager.h"
  29 #include "kfd_pm4_headers_vi.h"
  30 #include "kfd_pm4_headers_aldebaran.h"
  31 #include "cwsr_trap_handler.h"
  32 #include "kfd_iommu.h"
  33 #include "amdgpu_amdkfd.h"
  34 #include "kfd_smi_events.h"
  35 #include "kfd_migrate.h"
  36 #include "amdgpu.h"
  37
  38 #define MQD_SIZE_ALIGNED 768
  39
  40 /*
  41  * kfd_locked is used to lock the kfd driver during suspend or reset
  42  * once locked, kfd driver will stop any further GPU execution.
  43  * create process (open) will return -EAGAIN.
  44  */
  45 static atomic_t kfd_locked = ATOMIC_INIT(0);
  46
  47 #ifdef CONFIG_DRM_AMDGPU_CIK
  48 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd;
  49 #endif
  50 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd;
  51 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd;
  52 extern const struct kfd2kgd_calls arcturus_kfd2kgd;
  53 extern const struct kfd2kgd_calls aldebaran_kfd2kgd;
  54 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd;
  55 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd;
  56 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd;
  57
  58 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
  59                                 unsigned int chunk_size);
  60 static void kfd_gtt_sa_fini(struct kfd_dev *kfd);
  61
  62 static int kfd_resume(struct kfd_dev *kfd);
  63
  64 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd)
  65 {
  66         uint32_t sdma_version = kfd->adev->ip_versions[SDMA0_HWIP][0];
  67
  68         switch (sdma_version) {
  69         case IP_VERSION(4, 0, 0):/* VEGA10 */
  70         case IP_VERSION(4, 0, 1):/* VEGA12 */
  71         case IP_VERSION(4, 1, 0):/* RAVEN */
  72         case IP_VERSION(4, 1, 1):/* RAVEN */
  73         case IP_VERSION(4, 1, 2):/* RENOIR */
  74         case IP_VERSION(5, 2, 1):/* VANGOGH */
  75         case IP_VERSION(5, 2, 3):/* YELLOW_CARP */
  76         case IP_VERSION(5, 2, 6):/* GC 10.3.6 */
  77         case IP_VERSION(5, 2, 7):/* GC 10.3.7 */
  78                 kfd->device_info.num_sdma_queues_per_engine = 2;
  79                 break;
  80         case IP_VERSION(4, 2, 0):/* VEGA20 */
  81         case IP_VERSION(4, 2, 2):/* ARCTURUS */
  82         case IP_VERSION(4, 4, 0):/* ALDEBARAN */
  83         case IP_VERSION(5, 0, 0):/* NAVI10 */
  84         case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */
  85         case IP_VERSION(5, 0, 2):/* NAVI14 */
  86         case IP_VERSION(5, 0, 5):/* NAVI12 */
  87         case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */
  88         case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */
  89         case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */
  90         case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */
  91         case IP_VERSION(6, 0, 0):
  92         case IP_VERSION(6, 0, 1):
  93         case IP_VERSION(6, 0, 2):
  94         case IP_VERSION(6, 0, 3):
  95                 kfd->device_info.num_sdma_queues_per_engine = 8;
  96                 break;
  97         default:
  98                 dev_warn(kfd_device,
  99                         "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n",
 100                         sdma_version);
 101                 kfd->device_info.num_sdma_queues_per_engine = 8;
 102         }
 103
 104         switch (sdma_version) {
 105         case IP_VERSION(6, 0, 0):
 106         case IP_VERSION(6, 0, 2):
 107         case IP_VERSION(6, 0, 3):
 108                 /* Reserve 1 for paging and 1 for gfx */
 109                 kfd->device_info.num_reserved_sdma_queues_per_engine = 2;
 110                 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */
 111                 kfd->device_info.reserved_sdma_queues_bitmap = 0xFULL;
 112                 break;
 113         case IP_VERSION(6, 0, 1):
 114                 /* Reserve 1 for paging and 1 for gfx */
 115                 kfd->device_info.num_reserved_sdma_queues_per_engine = 2;
 116                 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-0 queue-1; ... */
 117                 kfd->device_info.reserved_sdma_queues_bitmap = 0x3ULL;
 118                 break;
 119         default:
 120                 break;
 121         }
 122 }
 123
 124 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd)
 125 {
 126         uint32_t gc_version = KFD_GC_VERSION(kfd);
 127
 128         switch (gc_version) {
 129         case IP_VERSION(9, 0, 1): /* VEGA10 */
 130         case IP_VERSION(9, 1, 0): /* RAVEN */
 131         case IP_VERSION(9, 2, 1): /* VEGA12 */
 132         case IP_VERSION(9, 2, 2): /* RAVEN */
 133         case IP_VERSION(9, 3, 0): /* RENOIR */
 134         case IP_VERSION(9, 4, 0): /* VEGA20 */
 135         case IP_VERSION(9, 4, 1): /* ARCTURUS */
 136         case IP_VERSION(9, 4, 2): /* ALDEBARAN */
 137         case IP_VERSION(10, 3, 1): /* VANGOGH */
 138         case IP_VERSION(10, 3, 3): /* YELLOW_CARP */
 139         case IP_VERSION(10, 3, 6): /* GC 10.3.6 */
 140         case IP_VERSION(10, 3, 7): /* GC 10.3.7 */
 141         case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */
 142         case IP_VERSION(10, 1, 4):
 143         case IP_VERSION(10, 1, 10): /* NAVI10 */
 144         case IP_VERSION(10, 1, 2): /* NAVI12 */
 145         case IP_VERSION(10, 1, 1): /* NAVI14 */
 146         case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */
 147         case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */
 148         case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */
 149         case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */
 150                 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9;
 151                 break;
 152         case IP_VERSION(11, 0, 0):
 153         case IP_VERSION(11, 0, 1):
 154         case IP_VERSION(11, 0, 2):
 155         case IP_VERSION(11, 0, 3):
 156                 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11;
 157                 break;
 158         default:
 159                 dev_warn(kfd_device, "v9 event interrupt handler is set due to "
 160                         "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version);
 161                 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9;
 162         }
 163 }
 164
 165 static void kfd_device_info_init(struct kfd_dev *kfd,
 166                                  bool vf, uint32_t gfx_target_version)
 167 {
 168         uint32_t gc_version = KFD_GC_VERSION(kfd);
 169         uint32_t asic_type = kfd->adev->asic_type;
 170
 171         kfd->device_info.max_pasid_bits = 16;
 172         kfd->device_info.max_no_of_hqd = 24;
 173         kfd->device_info.num_of_watch_points = 4;
 174         kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED;
 175         kfd->device_info.gfx_target_version = gfx_target_version;
 176
 177         if (KFD_IS_SOC15(kfd)) {
 178                 kfd->device_info.doorbell_size = 8;
 179                 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t);
 180                 kfd->device_info.supports_cwsr = true;
 181
 182                 kfd_device_info_set_sdma_info(kfd);
 183
 184                 kfd_device_info_set_event_interrupt_class(kfd);
 185
 186                 /* Raven */
 187                 if (gc_version == IP_VERSION(9, 1, 0) ||
 188                     gc_version == IP_VERSION(9, 2, 2))
 189                         kfd->device_info.needs_iommu_device = true;
 190
 191                 if (gc_version < IP_VERSION(11, 0, 0)) {
 192                         /* Navi2x+, Navi1x+ */
 193                         if (gc_version == IP_VERSION(10, 3, 6))
 194                                 kfd->device_info.no_atomic_fw_version = 14;
 195                         else if (gc_version == IP_VERSION(10, 3, 7))
 196                                 kfd->device_info.no_atomic_fw_version = 3;
 197                         else if (gc_version >= IP_VERSION(10, 3, 0))
 198                                 kfd->device_info.no_atomic_fw_version = 92;
 199                         else if (gc_version >= IP_VERSION(10, 1, 1))
 200                                 kfd->device_info.no_atomic_fw_version = 145;
 201
 202                         /* Navi1x+ */
 203                         if (gc_version >= IP_VERSION(10, 1, 1))
 204                                 kfd->device_info.needs_pci_atomics = true;
 205                 }
 206         } else {
 207                 kfd->device_info.doorbell_size = 4;
 208                 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t);
 209                 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik;
 210                 kfd->device_info.num_sdma_queues_per_engine = 2;
 211
 212                 if (asic_type != CHIP_KAVERI &&
 213                     asic_type != CHIP_HAWAII &&
 214                     asic_type != CHIP_TONGA)
 215                         kfd->device_info.supports_cwsr = true;
 216
 217                 if (asic_type == CHIP_KAVERI ||
 218                     asic_type == CHIP_CARRIZO)
 219                         kfd->device_info.needs_iommu_device = true;
 220
 221                 if (asic_type != CHIP_HAWAII && !vf)
 222                         kfd->device_info.needs_pci_atomics = true;
 223         }
 224 }
 225
 226 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf)
 227 {
 228         struct kfd_dev *kfd = NULL;
 229         const struct kfd2kgd_calls *f2g = NULL;
 230         struct pci_dev *pdev = adev->pdev;
 231         uint32_t gfx_target_version = 0;
 232
 233         switch (adev->asic_type) {
 234 #ifdef KFD_SUPPORT_IOMMU_V2
 235 #ifdef CONFIG_DRM_AMDGPU_CIK
 236         case CHIP_KAVERI:
 237                 gfx_target_version = 70000;
 238                 if (!vf)
 239                         f2g = &gfx_v7_kfd2kgd;
 240                 break;
 241 #endif
 242         case CHIP_CARRIZO:
 243                 gfx_target_version = 80001;
 244                 if (!vf)
 245                         f2g = &gfx_v8_kfd2kgd;
 246                 break;
 247 #endif
 248 #ifdef CONFIG_DRM_AMDGPU_CIK
 249         case CHIP_HAWAII:
 250                 gfx_target_version = 70001;
 251                 if (!amdgpu_exp_hw_support)
 252                         pr_info(
 253         "KFD support on Hawaii is experimental. See modparam exp_hw_support\n"
 254                                 );
 255                 else if (!vf)
 256                         f2g = &gfx_v7_kfd2kgd;
 257                 break;
 258 #endif
 259         case CHIP_TONGA:
 260                 gfx_target_version = 80002;
 261                 if (!vf)
 262                         f2g = &gfx_v8_kfd2kgd;
 263                 break;
 264         case CHIP_FIJI:
 265                 gfx_target_version = 80003;
 266                 f2g = &gfx_v8_kfd2kgd;
 267                 break;
 268         case CHIP_POLARIS10:
 269                 gfx_target_version = 80003;
 270                 f2g = &gfx_v8_kfd2kgd;
 271                 break;
 272         case CHIP_POLARIS11:
 273                 gfx_target_version = 80003;
 274                 if (!vf)
 275                         f2g = &gfx_v8_kfd2kgd;
 276                 break;
 277         case CHIP_POLARIS12:
 278                 gfx_target_version = 80003;
 279                 if (!vf)
 280                         f2g = &gfx_v8_kfd2kgd;
 281                 break;
 282         case CHIP_VEGAM:
 283                 gfx_target_version = 80003;
 284                 if (!vf)
 285                         f2g = &gfx_v8_kfd2kgd;
 286                 break;
 287         default:
 288                 switch (adev->ip_versions[GC_HWIP][0]) {
 289                 /* Vega 10 */
 290                 case IP_VERSION(9, 0, 1):
 291                         gfx_target_version = 90000;
 292                         f2g = &gfx_v9_kfd2kgd;
 293                         break;
 294 #ifdef KFD_SUPPORT_IOMMU_V2
 295                 /* Raven */
 296                 case IP_VERSION(9, 1, 0):
 297                 case IP_VERSION(9, 2, 2):
 298                         gfx_target_version = 90002;
 299                         if (!vf)
 300                                 f2g = &gfx_v9_kfd2kgd;
 301                         break;
 302 #endif
 303                 /* Vega12 */
 304                 case IP_VERSION(9, 2, 1):
 305                         gfx_target_version = 90004;
 306                         if (!vf)
 307                                 f2g = &gfx_v9_kfd2kgd;
 308                         break;
 309                 /* Renoir */
 310                 case IP_VERSION(9, 3, 0):
 311                         gfx_target_version = 90012;
 312                         if (!vf)
 313                                 f2g = &gfx_v9_kfd2kgd;
 314                         break;
 315                 /* Vega20 */
 316                 case IP_VERSION(9, 4, 0):
 317                         gfx_target_version = 90006;
 318                         if (!vf)
 319                                 f2g = &gfx_v9_kfd2kgd;
 320                         break;
 321                 /* Arcturus */
 322                 case IP_VERSION(9, 4, 1):
 323                         gfx_target_version = 90008;
 324                         f2g = &arcturus_kfd2kgd;
 325                         break;
 326                 /* Aldebaran */
 327                 case IP_VERSION(9, 4, 2):
 328                         gfx_target_version = 90010;
 329                         f2g = &aldebaran_kfd2kgd;
 330                         break;
 331                 /* Navi10 */
 332                 case IP_VERSION(10, 1, 10):
 333                         gfx_target_version = 100100;
 334                         if (!vf)
 335                                 f2g = &gfx_v10_kfd2kgd;
 336                         break;
 337                 /* Navi12 */
 338                 case IP_VERSION(10, 1, 2):
 339                         gfx_target_version = 100101;
 340                         f2g = &gfx_v10_kfd2kgd;
 341                         break;
 342                 /* Navi14 */
 343                 case IP_VERSION(10, 1, 1):
 344                         gfx_target_version = 100102;
 345                         if (!vf)
 346                                 f2g = &gfx_v10_kfd2kgd;
 347                         break;
 348                 /* Cyan Skillfish */
 349                 case IP_VERSION(10, 1, 3):
 350                 case IP_VERSION(10, 1, 4):
 351                         gfx_target_version = 100103;
 352                         if (!vf)
 353                                 f2g = &gfx_v10_kfd2kgd;
 354                         break;
 355                 /* Sienna Cichlid */
 356                 case IP_VERSION(10, 3, 0):
 357                         gfx_target_version = 100300;
 358                         f2g = &gfx_v10_3_kfd2kgd;
 359                         break;
 360                 /* Navy Flounder */
 361                 case IP_VERSION(10, 3, 2):
 362                         gfx_target_version = 100301;
 363                         f2g = &gfx_v10_3_kfd2kgd;
 364                         break;
 365                 /* Van Gogh */
 366                 case IP_VERSION(10, 3, 1):
 367                         gfx_target_version = 100303;
 368                         if (!vf)
 369                                 f2g = &gfx_v10_3_kfd2kgd;
 370                         break;
 371                 /* Dimgrey Cavefish */
 372                 case IP_VERSION(10, 3, 4):
 373                         gfx_target_version = 100302;
 374                         f2g = &gfx_v10_3_kfd2kgd;
 375                         break;
 376                 /* Beige Goby */
 377                 case IP_VERSION(10, 3, 5):
 378                         gfx_target_version = 100304;
 379                         f2g = &gfx_v10_3_kfd2kgd;
 380                         break;
 381                 /* Yellow Carp */
 382                 case IP_VERSION(10, 3, 3):
 383                         gfx_target_version = 100305;
 384                         if (!vf)
 385                                 f2g = &gfx_v10_3_kfd2kgd;
 386                         break;
 387                 case IP_VERSION(10, 3, 6):
 388                 case IP_VERSION(10, 3, 7):
 389                         gfx_target_version = 100306;
 390                         if (!vf)
 391                                 f2g = &gfx_v10_3_kfd2kgd;
 392                         break;
 393                 case IP_VERSION(11, 0, 0):
 394                         gfx_target_version = 110000;
 395                         f2g = &gfx_v11_kfd2kgd;
 396                         break;
 397                 case IP_VERSION(11, 0, 1):
 398                         gfx_target_version = 110003;
 399                         f2g = &gfx_v11_kfd2kgd;
 400                         break;
 401                 case IP_VERSION(11, 0, 2):
 402                         gfx_target_version = 110002;
 403                         f2g = &gfx_v11_kfd2kgd;
 404                         break;
 405                 case IP_VERSION(11, 0, 3):
 406                         /* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */
 407                         gfx_target_version = 110001;
 408                         f2g = &gfx_v11_kfd2kgd;
 409                         break;
 410                 default:
 411                         break;
 412                 }
 413                 break;
 414         }
 415
 416         if (!f2g) {
 417                 if (adev->ip_versions[GC_HWIP][0])
 418                         dev_err(kfd_device, "GC IP %06x %s not supported in kfd\n",
 419                                 adev->ip_versions[GC_HWIP][0], vf ? "VF" : "");
 420                 else
 421                         dev_err(kfd_device, "%s %s not supported in kfd\n",
 422                                 amdgpu_asic_name[adev->asic_type], vf ? "VF" : "");
 423                 return NULL;
 424         }
 425
 426         kfd = kzalloc(sizeof(*kfd), GFP_KERNEL);
 427         if (!kfd)
 428                 return NULL;
 429
 430         kfd->adev = adev;
 431         kfd_device_info_init(kfd, vf, gfx_target_version);
 432         kfd->pdev = pdev;
 433         kfd->init_complete = false;
 434         kfd->kfd2kgd = f2g;
 435         atomic_set(&kfd->compute_profile, 0);
 436
 437         mutex_init(&kfd->doorbell_mutex);
 438         memset(&kfd->doorbell_available_index, 0,
 439                 sizeof(kfd->doorbell_available_index));
 440
 441         atomic_set(&kfd->sram_ecc_flag, 0);
 442
 443         ida_init(&kfd->doorbell_ida);
 444
 445         return kfd;
 446 }
 447
 448 static void kfd_cwsr_init(struct kfd_dev *kfd)
 449 {
 450         if (cwsr_enable && kfd->device_info.supports_cwsr) {
 451                 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) {
 452                         BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE);
 453                         kfd->cwsr_isa = cwsr_trap_gfx8_hex;
 454                         kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex);
 455                 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) {
 456                         BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE);
 457                         kfd->cwsr_isa = cwsr_trap_arcturus_hex;
 458                         kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex);
 459                 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) {
 460                         BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) > PAGE_SIZE);
 461                         kfd->cwsr_isa = cwsr_trap_aldebaran_hex;
 462                         kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex);
 463                 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) {
 464                         BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE);
 465                         kfd->cwsr_isa = cwsr_trap_gfx9_hex;
 466                         kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex);
 467                 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) {
 468                         BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE);
 469                         kfd->cwsr_isa = cwsr_trap_nv1x_hex;
 470                         kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex);
 471                 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) {
 472                         BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE);
 473                         kfd->cwsr_isa = cwsr_trap_gfx10_hex;
 474                         kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex);
 475                 } else {
 476                         BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE);
 477                         kfd->cwsr_isa = cwsr_trap_gfx11_hex;
 478                         kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex);
 479                 }
 480
 481                 kfd->cwsr_enabled = true;
 482         }
 483 }
 484
 485 static int kfd_gws_init(struct kfd_dev *kfd)
 486 {
 487         int ret = 0;
 488
 489         if (kfd->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS)
 490                 return 0;
 491
 492         if (hws_gws_support || (KFD_IS_SOC15(kfd) &&
 493                 ((KFD_GC_VERSION(kfd) == IP_VERSION(9, 0, 1)
 494                         && kfd->mec2_fw_version >= 0x81b3) ||
 495                 (KFD_GC_VERSION(kfd) <= IP_VERSION(9, 4, 0)
 496                         && kfd->mec2_fw_version >= 0x1b3)  ||
 497                 (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)
 498                         && kfd->mec2_fw_version >= 0x30)   ||
 499                 (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)
 500                         && kfd->mec2_fw_version >= 0x28))))
 501                 ret = amdgpu_amdkfd_alloc_gws(kfd->adev,
 502                                 kfd->adev->gds.gws_size, &kfd->gws);
 503
 504         return ret;
 505 }
 506
 507 static void kfd_smi_init(struct kfd_dev *dev)
 508 {
 509         INIT_LIST_HEAD(&dev->smi_clients);
 510         spin_lock_init(&dev->smi_lock);
 511 }
 512
 513 bool kgd2kfd_device_init(struct kfd_dev *kfd,
 514                          struct drm_device *ddev,
 515                          const struct kgd2kfd_shared_resources *gpu_resources)
 516 {
 517         unsigned int size, map_process_packet_size;
 518
 519         kfd->ddev = ddev;
 520         kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev,
 521                         KGD_ENGINE_MEC1);
 522         kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev,
 523                         KGD_ENGINE_MEC2);
 524         kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev,
 525                         KGD_ENGINE_SDMA1);
 526         kfd->shared_resources = *gpu_resources;
 527
 528         kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1;
 529         kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1;
 530         kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd
 531                         - kfd->vm_info.first_vmid_kfd + 1;
 532
 533         /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps.
 534          * 32 and 64-bit requests are possible and must be
 535          * supported.
 536          */
 537         kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev);
 538         if (!kfd->pci_atomic_requested &&
 539             kfd->device_info.needs_pci_atomics &&
 540             (!kfd->device_info.no_atomic_fw_version ||
 541              kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) {
 542                 dev_info(kfd_device,
 543                          "skipped device %x:%x, PCI rejects atomics %d<%d\n",
 544                          kfd->pdev->vendor, kfd->pdev->device,
 545                          kfd->mec_fw_version,
 546                          kfd->device_info.no_atomic_fw_version);
 547                 return false;
 548         }
 549
 550         /* Verify module parameters regarding mapped process number*/
 551         if (hws_max_conc_proc >= 0)
 552                 kfd->max_proc_per_quantum = min((u32)hws_max_conc_proc, kfd->vm_info.vmid_num_kfd);
 553         else
 554                 kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd;
 555
 556         /* calculate max size of mqds needed for queues */
 557         size = max_num_of_queues_per_device *
 558                         kfd->device_info.mqd_size_aligned;
 559
 560         /*
 561          * calculate max size of runlist packet.
 562          * There can be only 2 packets at once
 563          */
 564         map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ?
 565                                 sizeof(struct pm4_mes_map_process_aldebaran) :
 566                                 sizeof(struct pm4_mes_map_process);
 567         size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size +
 568                 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues)
 569                 + sizeof(struct pm4_mes_runlist)) * 2;
 570
 571         /* Add size of HIQ & DIQ */
 572         size += KFD_KERNEL_QUEUE_SIZE * 2;
 573
 574         /* add another 512KB for all other allocations on gart (HPD, fences) */
 575         size += 512 * 1024;
 576
 577         if (amdgpu_amdkfd_alloc_gtt_mem(
 578                         kfd->adev, size, &kfd->gtt_mem,
 579                         &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr,
 580                         false)) {
 581                 dev_err(kfd_device, "Could not allocate %d bytes\n", size);
 582                 goto alloc_gtt_mem_failure;
 583         }
 584
 585         dev_info(kfd_device, "Allocated %d bytes on gart\n", size);
 586
 587         /* Initialize GTT sa with 512 byte chunk size */
 588         if (kfd_gtt_sa_init(kfd, size, 512) != 0) {
 589                 dev_err(kfd_device, "Error initializing gtt sub-allocator\n");
 590                 goto kfd_gtt_sa_init_error;
 591         }
 592
 593         if (kfd_doorbell_init(kfd)) {
 594                 dev_err(kfd_device,
 595                         "Error initializing doorbell aperture\n");
 596                 goto kfd_doorbell_error;
 597         }
 598
 599         if (amdgpu_use_xgmi_p2p)
 600                 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id;
 601
 602         kfd->noretry = kfd->adev->gmc.noretry;
 603
 604         if (kfd_interrupt_init(kfd)) {
 605                 dev_err(kfd_device, "Error initializing interrupts\n");
 606                 goto kfd_interrupt_error;
 607         }
 608
 609         kfd->dqm = device_queue_manager_init(kfd);
 610         if (!kfd->dqm) {
 611                 dev_err(kfd_device, "Error initializing queue manager\n");
 612                 goto device_queue_manager_error;
 613         }
 614
 615         /* If supported on this device, allocate global GWS that is shared
 616          * by all KFD processes
 617          */
 618         if (kfd_gws_init(kfd)) {
 619                 dev_err(kfd_device, "Could not allocate %d gws\n",
 620                         kfd->adev->gds.gws_size);
 621                 goto gws_error;
 622         }
 623
 624         /* If CRAT is broken, won't set iommu enabled */
 625         kfd_double_confirm_iommu_support(kfd);
 626
 627         if (kfd_iommu_device_init(kfd)) {
 628                 kfd->use_iommu_v2 = false;
 629                 dev_err(kfd_device, "Error initializing iommuv2\n");
 630                 goto device_iommu_error;
 631         }
 632
 633         kfd_cwsr_init(kfd);
 634
 635         svm_migrate_init(kfd->adev);
 636
 637         if (kgd2kfd_resume_iommu(kfd))
 638                 goto device_iommu_error;
 639
 640         if (kfd_resume(kfd))
 641                 goto kfd_resume_error;
 642
 643         amdgpu_amdkfd_get_local_mem_info(kfd->adev, &kfd->local_mem_info);
 644
 645         if (kfd_topology_add_device(kfd)) {
 646                 dev_err(kfd_device, "Error adding device to topology\n");
 647                 goto kfd_topology_add_device_error;
 648         }
 649
 650         kfd_smi_init(kfd);
 651
 652         kfd->init_complete = true;
 653         dev_info(kfd_device, "added device %x:%x\n", kfd->pdev->vendor,
 654                  kfd->pdev->device);
 655
 656         pr_debug("Starting kfd with the following scheduling policy %d\n",
 657                 kfd->dqm->sched_policy);
 658
 659         goto out;
 660
 661 kfd_topology_add_device_error:
 662 kfd_resume_error:
 663 device_iommu_error:
 664 gws_error:
 665         device_queue_manager_uninit(kfd->dqm);
 666 device_queue_manager_error:
 667         kfd_interrupt_exit(kfd);
 668 kfd_interrupt_error:
 669         kfd_doorbell_fini(kfd);
 670 kfd_doorbell_error:
 671         kfd_gtt_sa_fini(kfd);
 672 kfd_gtt_sa_init_error:
 673         amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem);
 674 alloc_gtt_mem_failure:
 675         if (kfd->gws)
 676                 amdgpu_amdkfd_free_gws(kfd->adev, kfd->gws);
 677         dev_err(kfd_device,
 678                 "device %x:%x NOT added due to errors\n",
 679                 kfd->pdev->vendor, kfd->pdev->device);
 680 out:
 681         return kfd->init_complete;
 682 }
 683
 684 void kgd2kfd_device_exit(struct kfd_dev *kfd)
 685 {
 686         if (kfd->init_complete) {
 687                 device_queue_manager_uninit(kfd->dqm);
 688                 kfd_interrupt_exit(kfd);
 689                 kfd_topology_remove_device(kfd);
 690                 kfd_doorbell_fini(kfd);
 691                 ida_destroy(&kfd->doorbell_ida);
 692                 kfd_gtt_sa_fini(kfd);
 693                 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem);
 694                 if (kfd->gws)
 695                         amdgpu_amdkfd_free_gws(kfd->adev, kfd->gws);
 696         }
 697
 698         kfree(kfd);
 699 }
 700
 701 int kgd2kfd_pre_reset(struct kfd_dev *kfd)
 702 {
 703         if (!kfd->init_complete)
 704                 return 0;
 705
 706         kfd_smi_event_update_gpu_reset(kfd, false);
 707
 708         kfd->dqm->ops.pre_reset(kfd->dqm);
 709
 710         kgd2kfd_suspend(kfd, false);
 711
 712         kfd_signal_reset_event(kfd);
 713         return 0;
 714 }
 715
 716 /*
 717  * Fix me. KFD won't be able to resume existing process for now.
 718  * We will keep all existing process in a evicted state and
 719  * wait the process to be terminated.
 720  */
 721
 722 int kgd2kfd_post_reset(struct kfd_dev *kfd)
 723 {
 724         int ret;
 725
 726         if (!kfd->init_complete)
 727                 return 0;
 728
 729         ret = kfd_resume(kfd);
 730         if (ret)
 731                 return ret;
 732         atomic_dec(&kfd_locked);
 733
 734         atomic_set(&kfd->sram_ecc_flag, 0);
 735
 736         kfd_smi_event_update_gpu_reset(kfd, true);
 737
 738         return 0;
 739 }
 740
 741 bool kfd_is_locked(void)
 742 {
 743         return  (atomic_read(&kfd_locked) > 0);
 744 }
 745
 746 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)
 747 {
 748         if (!kfd->init_complete)
 749                 return;
 750
 751         /* for runtime suspend, skip locking kfd */
 752         if (!run_pm) {
 753                 /* For first KFD device suspend all the KFD processes */
 754                 if (atomic_inc_return(&kfd_locked) == 1)
 755                         kfd_suspend_all_processes();
 756         }
 757
 758         kfd->dqm->ops.stop(kfd->dqm);
 759         kfd_iommu_suspend(kfd);
 760 }
 761
 762 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)
 763 {
 764         int ret, count;
 765
 766         if (!kfd->init_complete)
 767                 return 0;
 768
 769         ret = kfd_resume(kfd);
 770         if (ret)
 771                 return ret;
 772
 773         /* for runtime resume, skip unlocking kfd */
 774         if (!run_pm) {
 775                 count = atomic_dec_return(&kfd_locked);
 776                 WARN_ONCE(count < 0, "KFD suspend / resume ref. error");
 777                 if (count == 0)
 778                         ret = kfd_resume_all_processes();
 779         }
 780
 781         return ret;
 782 }
 783
 784 int kgd2kfd_resume_iommu(struct kfd_dev *kfd)
 785 {
 786         int err = 0;
 787
 788         err = kfd_iommu_resume(kfd);
 789         if (err)
 790                 dev_err(kfd_device,
 791                         "Failed to resume IOMMU for device %x:%x\n",
 792                         kfd->pdev->vendor, kfd->pdev->device);
 793         return err;
 794 }
 795
 796 static int kfd_resume(struct kfd_dev *kfd)
 797 {
 798         int err = 0;
 799
 800         err = kfd->dqm->ops.start(kfd->dqm);
 801         if (err)
 802                 dev_err(kfd_device,
 803                         "Error starting queue manager for device %x:%x\n",
 804                         kfd->pdev->vendor, kfd->pdev->device);
 805
 806         return err;
 807 }
 808
 809 static inline void kfd_queue_work(struct workqueue_struct *wq,
 810                                   struct work_struct *work)
 811 {
 812         int cpu, new_cpu;
 813
 814         cpu = new_cpu = smp_processor_id();
 815         do {
 816                 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids;
 817                 if (cpu_to_node(new_cpu) == numa_node_id())
 818                         break;
 819         } while (cpu != new_cpu);
 820
 821         queue_work_on(new_cpu, wq, work);
 822 }
 823
 824 /* This is called directly from KGD at ISR. */
 825 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
 826 {
 827         uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE];
 828         bool is_patched = false;
 829         unsigned long flags;
 830
 831         if (!kfd->init_complete)
 832                 return;
 833
 834         if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) {
 835                 dev_err_once(kfd_device, "Ring entry too small\n");
 836                 return;
 837         }
 838
 839         spin_lock_irqsave(&kfd->interrupt_lock, flags);
 840
 841         if (kfd->interrupts_active
 842             && interrupt_is_wanted(kfd, ih_ring_entry,
 843                                    patched_ihre, &is_patched)
 844             && enqueue_ih_ring_entry(kfd,
 845                                      is_patched ? patched_ihre : ih_ring_entry))
 846                 kfd_queue_work(kfd->ih_wq, &kfd->interrupt_work);
 847
 848         spin_unlock_irqrestore(&kfd->interrupt_lock, flags);
 849 }
 850
 851 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger)
 852 {
 853         struct kfd_process *p;
 854         int r;
 855
 856         /* Because we are called from arbitrary context (workqueue) as opposed
 857          * to process context, kfd_process could attempt to exit while we are
 858          * running so the lookup function increments the process ref count.
 859          */
 860         p = kfd_lookup_process_by_mm(mm);
 861         if (!p)
 862                 return -ESRCH;
 863
 864         WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid);
 865         r = kfd_process_evict_queues(p, trigger);
 866
 867         kfd_unref_process(p);
 868         return r;
 869 }
 870
 871 int kgd2kfd_resume_mm(struct mm_struct *mm)
 872 {
 873         struct kfd_process *p;
 874         int r;
 875
 876         /* Because we are called from arbitrary context (workqueue) as opposed
 877          * to process context, kfd_process could attempt to exit while we are
 878          * running so the lookup function increments the process ref count.
 879          */
 880         p = kfd_lookup_process_by_mm(mm);
 881         if (!p)
 882                 return -ESRCH;
 883
 884         r = kfd_process_restore_queues(p);
 885
 886         kfd_unref_process(p);
 887         return r;
 888 }
 889
 890 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will
 891  *   prepare for safe eviction of KFD BOs that belong to the specified
 892  *   process.
 893  *
 894  * @mm: mm_struct that identifies the specified KFD process
 895  * @fence: eviction fence attached to KFD process BOs
 896  *
 897  */
 898 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
 899                                                struct dma_fence *fence)
 900 {
 901         struct kfd_process *p;
 902         unsigned long active_time;
 903         unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS);
 904
 905         if (!fence)
 906                 return -EINVAL;
 907
 908         if (dma_fence_is_signaled(fence))
 909                 return 0;
 910
 911         p = kfd_lookup_process_by_mm(mm);
 912         if (!p)
 913                 return -ENODEV;
 914
 915         if (fence->seqno == p->last_eviction_seqno)
 916                 goto out;
 917
 918         p->last_eviction_seqno = fence->seqno;
 919
 920         /* Avoid KFD process starvation. Wait for at least
 921          * PROCESS_ACTIVE_TIME_MS before evicting the process again
 922          */
 923         active_time = get_jiffies_64() - p->last_restore_timestamp;
 924         if (delay_jiffies > active_time)
 925                 delay_jiffies -= active_time;
 926         else
 927                 delay_jiffies = 0;
 928
 929         /* During process initialization eviction_work.dwork is initialized
 930          * to kfd_evict_bo_worker
 931          */
 932         WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies",
 933              p->lead_thread->pid, delay_jiffies);
 934         schedule_delayed_work(&p->eviction_work, delay_jiffies);
 935 out:
 936         kfd_unref_process(p);
 937         return 0;
 938 }
 939
 940 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
 941                                 unsigned int chunk_size)
 942 {
 943         if (WARN_ON(buf_size < chunk_size))
 944                 return -EINVAL;
 945         if (WARN_ON(buf_size == 0))
 946                 return -EINVAL;
 947         if (WARN_ON(chunk_size == 0))
 948                 return -EINVAL;
 949
 950         kfd->gtt_sa_chunk_size = chunk_size;
 951         kfd->gtt_sa_num_of_chunks = buf_size / chunk_size;
 952
 953         kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks,
 954                                            GFP_KERNEL);
 955         if (!kfd->gtt_sa_bitmap)
 956                 return -ENOMEM;
 957
 958         pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n",
 959                         kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap);
 960
 961         mutex_init(&kfd->gtt_sa_lock);
 962
 963         return 0;
 964 }
 965
 966 static void kfd_gtt_sa_fini(struct kfd_dev *kfd)
 967 {
 968         mutex_destroy(&kfd->gtt_sa_lock);
 969         bitmap_free(kfd->gtt_sa_bitmap);
 970 }
 971
 972 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr,
 973                                                 unsigned int bit_num,
 974                                                 unsigned int chunk_size)
 975 {
 976         return start_addr + bit_num * chunk_size;
 977 }
 978
 979 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr,
 980                                                 unsigned int bit_num,
 981                                                 unsigned int chunk_size)
 982 {
 983         return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size);
 984 }
 985
 986 int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size,
 987                         struct kfd_mem_obj **mem_obj)
 988 {
 989         unsigned int found, start_search, cur_size;
 990
 991         if (size == 0)
 992                 return -EINVAL;
 993
 994         if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size)
 995                 return -ENOMEM;
 996
 997         *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
 998         if (!(*mem_obj))
 999                 return -ENOMEM;
1000
1001         pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size);
1002
1003         start_search = 0;
1004
1005         mutex_lock(&kfd->gtt_sa_lock);
1006
1007 kfd_gtt_restart_search:
1008         /* Find the first chunk that is free */
1009         found = find_next_zero_bit(kfd->gtt_sa_bitmap,
1010                                         kfd->gtt_sa_num_of_chunks,
1011                                         start_search);
1012
1013         pr_debug("Found = %d\n", found);
1014
1015         /* If there wasn't any free chunk, bail out */
1016         if (found == kfd->gtt_sa_num_of_chunks)
1017                 goto kfd_gtt_no_free_chunk;
1018
1019         /* Update fields of mem_obj */
1020         (*mem_obj)->range_start = found;
1021         (*mem_obj)->range_end = found;
1022         (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr(
1023                                         kfd->gtt_start_gpu_addr,
1024                                         found,
1025                                         kfd->gtt_sa_chunk_size);
1026         (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr(
1027                                         kfd->gtt_start_cpu_ptr,
1028                                         found,
1029                                         kfd->gtt_sa_chunk_size);
1030
1031         pr_debug("gpu_addr = %p, cpu_addr = %p\n",
1032                         (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr);
1033
1034         /* If we need only one chunk, mark it as allocated and get out */
1035         if (size <= kfd->gtt_sa_chunk_size) {
1036                 pr_debug("Single bit\n");
1037                 __set_bit(found, kfd->gtt_sa_bitmap);
1038                 goto kfd_gtt_out;
1039         }
1040
1041         /* Otherwise, try to see if we have enough contiguous chunks */
1042         cur_size = size - kfd->gtt_sa_chunk_size;
1043         do {
1044                 (*mem_obj)->range_end =
1045                         find_next_zero_bit(kfd->gtt_sa_bitmap,
1046                                         kfd->gtt_sa_num_of_chunks, ++found);
1047                 /*
1048                  * If next free chunk is not contiguous than we need to
1049                  * restart our search from the last free chunk we found (which
1050                  * wasn't contiguous to the previous ones
1051                  */
1052                 if ((*mem_obj)->range_end != found) {
1053                         start_search = found;
1054                         goto kfd_gtt_restart_search;
1055                 }
1056
1057                 /*
1058                  * If we reached end of buffer, bail out with error
1059                  */
1060                 if (found == kfd->gtt_sa_num_of_chunks)
1061                         goto kfd_gtt_no_free_chunk;
1062
1063                 /* Check if we don't need another chunk */
1064                 if (cur_size <= kfd->gtt_sa_chunk_size)
1065                         cur_size = 0;
1066                 else
1067                         cur_size -= kfd->gtt_sa_chunk_size;
1068
1069         } while (cur_size > 0);
1070
1071         pr_debug("range_start = %d, range_end = %d\n",
1072                 (*mem_obj)->range_start, (*mem_obj)->range_end);
1073
1074         /* Mark the chunks as allocated */
1075         bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start,
1076                    (*mem_obj)->range_end - (*mem_obj)->range_start + 1);
1077
1078 kfd_gtt_out:
1079         mutex_unlock(&kfd->gtt_sa_lock);
1080         return 0;
1081
1082 kfd_gtt_no_free_chunk:
1083         pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj);
1084         mutex_unlock(&kfd->gtt_sa_lock);
1085         kfree(*mem_obj);
1086         return -ENOMEM;
1087 }
1088
1089 int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj)
1090 {
1091         /* Act like kfree when trying to free a NULL object */
1092         if (!mem_obj)
1093                 return 0;
1094
1095         pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n",
1096                         mem_obj, mem_obj->range_start, mem_obj->range_end);
1097
1098         mutex_lock(&kfd->gtt_sa_lock);
1099
1100         /* Mark the chunks as free */
1101         bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start,
1102                      mem_obj->range_end - mem_obj->range_start + 1);
1103
1104         mutex_unlock(&kfd->gtt_sa_lock);
1105
1106         kfree(mem_obj);
1107         return 0;
1108 }
1109
1110 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
1111 {
1112         if (kfd)
1113                 atomic_inc(&kfd->sram_ecc_flag);
1114 }
1115
1116 void kfd_inc_compute_active(struct kfd_dev *kfd)
1117 {
1118         if (atomic_inc_return(&kfd->compute_profile) == 1)
1119                 amdgpu_amdkfd_set_compute_idle(kfd->adev, false);
1120 }
1121
1122 void kfd_dec_compute_active(struct kfd_dev *kfd)
1123 {
1124         int count = atomic_dec_return(&kfd->compute_profile);
1125
1126         if (count == 0)
1127                 amdgpu_amdkfd_set_compute_idle(kfd->adev, true);
1128         WARN_ONCE(count < 0, "Compute profile ref. count error");
1129 }
1130
1131 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask)
1132 {
1133         if (kfd && kfd->init_complete)
1134                 kfd_smi_event_update_thermal_throttling(kfd, throttle_bitmask);
1135 }
1136
1137 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and
1138  * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA.
1139  * When the device has more than two engines, we reserve two for PCIe to enable
1140  * full-duplex and the rest are used as XGMI.
1141  */
1142 unsigned int kfd_get_num_sdma_engines(struct kfd_dev *kdev)
1143 {
1144         /* If XGMI is not supported, all SDMA engines are PCIe */
1145         if (!kdev->adev->gmc.xgmi.supported)
1146                 return kdev->adev->sdma.num_instances;
1147
1148         return min(kdev->adev->sdma.num_instances, 2);
1149 }
1150
1151 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_dev *kdev)
1152 {
1153         /* After reserved for PCIe, the rest of engines are XGMI */
1154         return kdev->adev->sdma.num_instances - kfd_get_num_sdma_engines(kdev);
1155 }
1156
1157 #if defined(CONFIG_DEBUG_FS)
1158
1159 /* This function will send a package to HIQ to hang the HWS
1160  * which will trigger a GPU reset and bring the HWS back to normal state
1161  */
1162 int kfd_debugfs_hang_hws(struct kfd_dev *dev)
1163 {
1164         if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) {
1165                 pr_err("HWS is not enabled");
1166                 return -EINVAL;
1167         }
1168
1169         return dqm_debugfs_hang_hws(dev->dqm);
1170 }
1171
1172 #endif