drivers/gpu/drm/amd/amdkfd/kfd_device.c

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 /*
   3  * Copyright 2014-2022 Advanced Micro Devices, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <linux/bsearch.h>
  25 #include <linux/pci.h>
  26 #include <linux/slab.h>
  27 #include "kfd_priv.h"
  28 #include "kfd_device_queue_manager.h"
  29 #include "kfd_pm4_headers_vi.h"
  30 #include "kfd_pm4_headers_aldebaran.h"
  31 #include "cwsr_trap_handler.h"
  32 #include "kfd_iommu.h"
  33 #include "amdgpu_amdkfd.h"
  34 #include "kfd_smi_events.h"
  35 #include "kfd_migrate.h"
  36 #include "amdgpu.h"
  37
  38 #define MQD_SIZE_ALIGNED 768
  39
  40 /*
  41  * kfd_locked is used to lock the kfd driver during suspend or reset
  42  * once locked, kfd driver will stop any further GPU execution.
  43  * create process (open) will return -EAGAIN.
  44  */
  45 static atomic_t kfd_locked = ATOMIC_INIT(0);
  46
  47 #ifdef CONFIG_DRM_AMDGPU_CIK
  48 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd;
  49 #endif
  50 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd;
  51 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd;
  52 extern const struct kfd2kgd_calls arcturus_kfd2kgd;
  53 extern const struct kfd2kgd_calls aldebaran_kfd2kgd;
  54 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd;
  55 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd;
  56 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd;
  57
  58 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
  59                                 unsigned int chunk_size);
  60 static void kfd_gtt_sa_fini(struct kfd_dev *kfd);
  61
  62 static int kfd_resume(struct kfd_dev *kfd);
  63
  64 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd)
  65 {
  66         uint32_t sdma_version = kfd->adev->ip_versions[SDMA0_HWIP][0];
  67
  68         switch (sdma_version) {
  69         case IP_VERSION(4, 0, 0):/* VEGA10 */
  70         case IP_VERSION(4, 0, 1):/* VEGA12 */
  71         case IP_VERSION(4, 1, 0):/* RAVEN */
  72         case IP_VERSION(4, 1, 1):/* RAVEN */
  73         case IP_VERSION(4, 1, 2):/* RENOIR */
  74         case IP_VERSION(5, 2, 1):/* VANGOGH */
  75         case IP_VERSION(5, 2, 3):/* YELLOW_CARP */
  76         case IP_VERSION(5, 2, 6):/* GC 10.3.6 */
  77         case IP_VERSION(5, 2, 7):/* GC 10.3.7 */
  78                 kfd->device_info.num_sdma_queues_per_engine = 2;
  79                 break;
  80         case IP_VERSION(4, 2, 0):/* VEGA20 */
  81         case IP_VERSION(4, 2, 2):/* ARCTURUS */
  82         case IP_VERSION(4, 4, 0):/* ALDEBARAN */
  83         case IP_VERSION(5, 0, 0):/* NAVI10 */
  84         case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */
  85         case IP_VERSION(5, 0, 2):/* NAVI14 */
  86         case IP_VERSION(5, 0, 5):/* NAVI12 */
  87         case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */
  88         case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */
  89         case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */
  90         case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */
  91         case IP_VERSION(6, 0, 0):
  92         case IP_VERSION(6, 0, 1):
  93         case IP_VERSION(6, 0, 2):
  94         case IP_VERSION(6, 0, 3):
  95                 kfd->device_info.num_sdma_queues_per_engine = 8;
  96                 break;
  97         default:
  98                 dev_warn(kfd_device,
  99                         "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n",
 100                         sdma_version);
 101                 kfd->device_info.num_sdma_queues_per_engine = 8;
 102         }
 103
 104         switch (sdma_version) {
 105         case IP_VERSION(6, 0, 0):
 106         case IP_VERSION(6, 0, 2):
 107         case IP_VERSION(6, 0, 3):
 108                 /* Reserve 1 for paging and 1 for gfx */
 109                 kfd->device_info.num_reserved_sdma_queues_per_engine = 2;
 110                 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */
 111                 kfd->device_info.reserved_sdma_queues_bitmap = 0xFULL;
 112                 break;
 113         case IP_VERSION(6, 0, 1):
 114                 /* Reserve 1 for paging and 1 for gfx */
 115                 kfd->device_info.num_reserved_sdma_queues_per_engine = 2;
 116                 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-0 queue-1; ... */
 117                 kfd->device_info.reserved_sdma_queues_bitmap = 0x3ULL;
 118                 break;
 119         default:
 120                 break;
 121         }
 122 }
 123
 124 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd)
 125 {
 126         uint32_t gc_version = KFD_GC_VERSION(kfd);
 127
 128         switch (gc_version) {
 129         case IP_VERSION(9, 0, 1): /* VEGA10 */
 130         case IP_VERSION(9, 1, 0): /* RAVEN */
 131         case IP_VERSION(9, 2, 1): /* VEGA12 */
 132         case IP_VERSION(9, 2, 2): /* RAVEN */
 133         case IP_VERSION(9, 3, 0): /* RENOIR */
 134         case IP_VERSION(9, 4, 0): /* VEGA20 */
 135         case IP_VERSION(9, 4, 1): /* ARCTURUS */
 136         case IP_VERSION(9, 4, 2): /* ALDEBARAN */
 137         case IP_VERSION(10, 3, 1): /* VANGOGH */
 138         case IP_VERSION(10, 3, 3): /* YELLOW_CARP */
 139         case IP_VERSION(10, 3, 6): /* GC 10.3.6 */
 140         case IP_VERSION(10, 3, 7): /* GC 10.3.7 */
 141         case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */
 142         case IP_VERSION(10, 1, 4):
 143         case IP_VERSION(10, 1, 10): /* NAVI10 */
 144         case IP_VERSION(10, 1, 2): /* NAVI12 */
 145         case IP_VERSION(10, 1, 1): /* NAVI14 */
 146         case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */
 147         case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */
 148         case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */
 149         case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */
 150                 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9;
 151                 break;
 152         case IP_VERSION(11, 0, 0):
 153         case IP_VERSION(11, 0, 1):
 154         case IP_VERSION(11, 0, 2):
 155         case IP_VERSION(11, 0, 3):
 156                 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11;
 157                 break;
 158         default:
 159                 dev_warn(kfd_device, "v9 event interrupt handler is set due to "
 160                         "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version);
 161                 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9;
 162         }
 163 }
 164
 165 static void kfd_device_info_init(struct kfd_dev *kfd,
 166                                  bool vf, uint32_t gfx_target_version)
 167 {
 168         uint32_t gc_version = KFD_GC_VERSION(kfd);
 169         uint32_t asic_type = kfd->adev->asic_type;
 170
 171         kfd->device_info.max_pasid_bits = 16;
 172         kfd->device_info.max_no_of_hqd = 24;
 173         kfd->device_info.num_of_watch_points = 4;
 174         kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED;
 175         kfd->device_info.gfx_target_version = gfx_target_version;
 176
 177         if (KFD_IS_SOC15(kfd)) {
 178                 kfd->device_info.doorbell_size = 8;
 179                 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t);
 180                 kfd->device_info.supports_cwsr = true;
 181
 182                 kfd_device_info_set_sdma_info(kfd);
 183
 184                 kfd_device_info_set_event_interrupt_class(kfd);
 185
 186                 /* Raven */
 187                 if (gc_version == IP_VERSION(9, 1, 0) ||
 188                     gc_version == IP_VERSION(9, 2, 2))
 189                         kfd->device_info.needs_iommu_device = true;
 190
 191                 if (gc_version < IP_VERSION(11, 0, 0)) {
 192                         /* Navi2x+, Navi1x+ */
 193                         if (gc_version == IP_VERSION(10, 3, 6))
 194                                 kfd->device_info.no_atomic_fw_version = 14;
 195                         else if (gc_version == IP_VERSION(10, 3, 7))
 196                                 kfd->device_info.no_atomic_fw_version = 3;
 197                         else if (gc_version >= IP_VERSION(10, 3, 0))
 198                                 kfd->device_info.no_atomic_fw_version = 92;
 199                         else if (gc_version >= IP_VERSION(10, 1, 1))
 200                                 kfd->device_info.no_atomic_fw_version = 145;
 201
 202                         /* Navi1x+ */
 203                         if (gc_version >= IP_VERSION(10, 1, 1))
 204                                 kfd->device_info.needs_pci_atomics = true;
 205                 }
 206         } else {
 207                 kfd->device_info.doorbell_size = 4;
 208                 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t);
 209                 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik;
 210                 kfd->device_info.num_sdma_queues_per_engine = 2;
 211
 212                 if (asic_type != CHIP_KAVERI &&
 213                     asic_type != CHIP_HAWAII &&
 214                     asic_type != CHIP_TONGA)
 215                         kfd->device_info.supports_cwsr = true;
 216
 217                 if (asic_type == CHIP_KAVERI ||
 218                     asic_type == CHIP_CARRIZO)
 219                         kfd->device_info.needs_iommu_device = true;
 220
 221                 if (asic_type != CHIP_HAWAII && !vf)
 222                         kfd->device_info.needs_pci_atomics = true;
 223         }
 224 }
 225
 226 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf)
 227 {
 228         struct kfd_dev *kfd = NULL;
 229         const struct kfd2kgd_calls *f2g = NULL;
 230         uint32_t gfx_target_version = 0;
 231
 232         switch (adev->asic_type) {
 233 #ifdef KFD_SUPPORT_IOMMU_V2
 234 #ifdef CONFIG_DRM_AMDGPU_CIK
 235         case CHIP_KAVERI:
 236                 gfx_target_version = 70000;
 237                 if (!vf)
 238                         f2g = &gfx_v7_kfd2kgd;
 239                 break;
 240 #endif
 241         case CHIP_CARRIZO:
 242                 gfx_target_version = 80001;
 243                 if (!vf)
 244                         f2g = &gfx_v8_kfd2kgd;
 245                 break;
 246 #endif
 247 #ifdef CONFIG_DRM_AMDGPU_CIK
 248         case CHIP_HAWAII:
 249                 gfx_target_version = 70001;
 250                 if (!amdgpu_exp_hw_support)
 251                         pr_info(
 252         "KFD support on Hawaii is experimental. See modparam exp_hw_support\n"
 253                                 );
 254                 else if (!vf)
 255                         f2g = &gfx_v7_kfd2kgd;
 256                 break;
 257 #endif
 258         case CHIP_TONGA:
 259                 gfx_target_version = 80002;
 260                 if (!vf)
 261                         f2g = &gfx_v8_kfd2kgd;
 262                 break;
 263         case CHIP_FIJI:
 264                 gfx_target_version = 80003;
 265                 f2g = &gfx_v8_kfd2kgd;
 266                 break;
 267         case CHIP_POLARIS10:
 268                 gfx_target_version = 80003;
 269                 f2g = &gfx_v8_kfd2kgd;
 270                 break;
 271         case CHIP_POLARIS11:
 272                 gfx_target_version = 80003;
 273                 if (!vf)
 274                         f2g = &gfx_v8_kfd2kgd;
 275                 break;
 276         case CHIP_POLARIS12:
 277                 gfx_target_version = 80003;
 278                 if (!vf)
 279                         f2g = &gfx_v8_kfd2kgd;
 280                 break;
 281         case CHIP_VEGAM:
 282                 gfx_target_version = 80003;
 283                 if (!vf)
 284                         f2g = &gfx_v8_kfd2kgd;
 285                 break;
 286         default:
 287                 switch (adev->ip_versions[GC_HWIP][0]) {
 288                 /* Vega 10 */
 289                 case IP_VERSION(9, 0, 1):
 290                         gfx_target_version = 90000;
 291                         f2g = &gfx_v9_kfd2kgd;
 292                         break;
 293 #ifdef KFD_SUPPORT_IOMMU_V2
 294                 /* Raven */
 295                 case IP_VERSION(9, 1, 0):
 296                 case IP_VERSION(9, 2, 2):
 297                         gfx_target_version = 90002;
 298                         if (!vf)
 299                                 f2g = &gfx_v9_kfd2kgd;
 300                         break;
 301 #endif
 302                 /* Vega12 */
 303                 case IP_VERSION(9, 2, 1):
 304                         gfx_target_version = 90004;
 305                         if (!vf)
 306                                 f2g = &gfx_v9_kfd2kgd;
 307                         break;
 308                 /* Renoir */
 309                 case IP_VERSION(9, 3, 0):
 310                         gfx_target_version = 90012;
 311                         if (!vf)
 312                                 f2g = &gfx_v9_kfd2kgd;
 313                         break;
 314                 /* Vega20 */
 315                 case IP_VERSION(9, 4, 0):
 316                         gfx_target_version = 90006;
 317                         if (!vf)
 318                                 f2g = &gfx_v9_kfd2kgd;
 319                         break;
 320                 /* Arcturus */
 321                 case IP_VERSION(9, 4, 1):
 322                         gfx_target_version = 90008;
 323                         f2g = &arcturus_kfd2kgd;
 324                         break;
 325                 /* Aldebaran */
 326                 case IP_VERSION(9, 4, 2):
 327                         gfx_target_version = 90010;
 328                         f2g = &aldebaran_kfd2kgd;
 329                         break;
 330                 /* Navi10 */
 331                 case IP_VERSION(10, 1, 10):
 332                         gfx_target_version = 100100;
 333                         if (!vf)
 334                                 f2g = &gfx_v10_kfd2kgd;
 335                         break;
 336                 /* Navi12 */
 337                 case IP_VERSION(10, 1, 2):
 338                         gfx_target_version = 100101;
 339                         f2g = &gfx_v10_kfd2kgd;
 340                         break;
 341                 /* Navi14 */
 342                 case IP_VERSION(10, 1, 1):
 343                         gfx_target_version = 100102;
 344                         if (!vf)
 345                                 f2g = &gfx_v10_kfd2kgd;
 346                         break;
 347                 /* Cyan Skillfish */
 348                 case IP_VERSION(10, 1, 3):
 349                 case IP_VERSION(10, 1, 4):
 350                         gfx_target_version = 100103;
 351                         if (!vf)
 352                                 f2g = &gfx_v10_kfd2kgd;
 353                         break;
 354                 /* Sienna Cichlid */
 355                 case IP_VERSION(10, 3, 0):
 356                         gfx_target_version = 100300;
 357                         f2g = &gfx_v10_3_kfd2kgd;
 358                         break;
 359                 /* Navy Flounder */
 360                 case IP_VERSION(10, 3, 2):
 361                         gfx_target_version = 100301;
 362                         f2g = &gfx_v10_3_kfd2kgd;
 363                         break;
 364                 /* Van Gogh */
 365                 case IP_VERSION(10, 3, 1):
 366                         gfx_target_version = 100303;
 367                         if (!vf)
 368                                 f2g = &gfx_v10_3_kfd2kgd;
 369                         break;
 370                 /* Dimgrey Cavefish */
 371                 case IP_VERSION(10, 3, 4):
 372                         gfx_target_version = 100302;
 373                         f2g = &gfx_v10_3_kfd2kgd;
 374                         break;
 375                 /* Beige Goby */
 376                 case IP_VERSION(10, 3, 5):
 377                         gfx_target_version = 100304;
 378                         f2g = &gfx_v10_3_kfd2kgd;
 379                         break;
 380                 /* Yellow Carp */
 381                 case IP_VERSION(10, 3, 3):
 382                         gfx_target_version = 100305;
 383                         if (!vf)
 384                                 f2g = &gfx_v10_3_kfd2kgd;
 385                         break;
 386                 case IP_VERSION(10, 3, 6):
 387                 case IP_VERSION(10, 3, 7):
 388                         gfx_target_version = 100306;
 389                         if (!vf)
 390                                 f2g = &gfx_v10_3_kfd2kgd;
 391                         break;
 392                 case IP_VERSION(11, 0, 0):
 393                         gfx_target_version = 110000;
 394                         f2g = &gfx_v11_kfd2kgd;
 395                         break;
 396                 case IP_VERSION(11, 0, 1):
 397                         gfx_target_version = 110003;
 398                         f2g = &gfx_v11_kfd2kgd;
 399                         break;
 400                 case IP_VERSION(11, 0, 2):
 401                         gfx_target_version = 110002;
 402                         f2g = &gfx_v11_kfd2kgd;
 403                         break;
 404                 case IP_VERSION(11, 0, 3):
 405                         /* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */
 406                         gfx_target_version = 110001;
 407                         f2g = &gfx_v11_kfd2kgd;
 408                         break;
 409                 default:
 410                         break;
 411                 }
 412                 break;
 413         }
 414
 415         if (!f2g) {
 416                 if (adev->ip_versions[GC_HWIP][0])
 417                         dev_err(kfd_device, "GC IP %06x %s not supported in kfd\n",
 418                                 adev->ip_versions[GC_HWIP][0], vf ? "VF" : "");
 419                 else
 420                         dev_err(kfd_device, "%s %s not supported in kfd\n",
 421                                 amdgpu_asic_name[adev->asic_type], vf ? "VF" : "");
 422                 return NULL;
 423         }
 424
 425         kfd = kzalloc(sizeof(*kfd), GFP_KERNEL);
 426         if (!kfd)
 427                 return NULL;
 428
 429         kfd->adev = adev;
 430         kfd_device_info_init(kfd, vf, gfx_target_version);
 431         kfd->init_complete = false;
 432         kfd->kfd2kgd = f2g;
 433         atomic_set(&kfd->compute_profile, 0);
 434
 435         mutex_init(&kfd->doorbell_mutex);
 436         memset(&kfd->doorbell_available_index, 0,
 437                 sizeof(kfd->doorbell_available_index));
 438
 439         atomic_set(&kfd->sram_ecc_flag, 0);
 440
 441         ida_init(&kfd->doorbell_ida);
 442
 443         return kfd;
 444 }
 445
 446 static void kfd_cwsr_init(struct kfd_dev *kfd)
 447 {
 448         if (cwsr_enable && kfd->device_info.supports_cwsr) {
 449                 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) {
 450                         BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE);
 451                         kfd->cwsr_isa = cwsr_trap_gfx8_hex;
 452                         kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex);
 453                 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) {
 454                         BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE);
 455                         kfd->cwsr_isa = cwsr_trap_arcturus_hex;
 456                         kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex);
 457                 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) {
 458                         BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) > PAGE_SIZE);
 459                         kfd->cwsr_isa = cwsr_trap_aldebaran_hex;
 460                         kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex);
 461                 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) {
 462                         BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE);
 463                         kfd->cwsr_isa = cwsr_trap_gfx9_hex;
 464                         kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex);
 465                 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) {
 466                         BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE);
 467                         kfd->cwsr_isa = cwsr_trap_nv1x_hex;
 468                         kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex);
 469                 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) {
 470                         BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE);
 471                         kfd->cwsr_isa = cwsr_trap_gfx10_hex;
 472                         kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex);
 473                 } else {
 474                         BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE);
 475                         kfd->cwsr_isa = cwsr_trap_gfx11_hex;
 476                         kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex);
 477                 }
 478
 479                 kfd->cwsr_enabled = true;
 480         }
 481 }
 482
 483 static int kfd_gws_init(struct kfd_dev *kfd)
 484 {
 485         int ret = 0;
 486
 487         if (kfd->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS)
 488                 return 0;
 489
 490         if (hws_gws_support || (KFD_IS_SOC15(kfd) &&
 491                 ((KFD_GC_VERSION(kfd) == IP_VERSION(9, 0, 1)
 492                         && kfd->mec2_fw_version >= 0x81b3) ||
 493                 (KFD_GC_VERSION(kfd) <= IP_VERSION(9, 4, 0)
 494                         && kfd->mec2_fw_version >= 0x1b3)  ||
 495                 (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)
 496                         && kfd->mec2_fw_version >= 0x30)   ||
 497                 (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)
 498                         && kfd->mec2_fw_version >= 0x28) ||
 499                 (KFD_GC_VERSION(kfd) >= IP_VERSION(10, 3, 0)
 500                         && KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)
 501                         && kfd->mec2_fw_version >= 0x6b))))
 502                 ret = amdgpu_amdkfd_alloc_gws(kfd->adev,
 503                                 kfd->adev->gds.gws_size, &kfd->gws);
 504
 505         return ret;
 506 }
 507
 508 static void kfd_smi_init(struct kfd_dev *dev)
 509 {
 510         INIT_LIST_HEAD(&dev->smi_clients);
 511         spin_lock_init(&dev->smi_lock);
 512 }
 513
 514 bool kgd2kfd_device_init(struct kfd_dev *kfd,
 515                          const struct kgd2kfd_shared_resources *gpu_resources)
 516 {
 517         unsigned int size, map_process_packet_size;
 518
 519         kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev,
 520                         KGD_ENGINE_MEC1);
 521         kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev,
 522                         KGD_ENGINE_MEC2);
 523         kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev,
 524                         KGD_ENGINE_SDMA1);
 525         kfd->shared_resources = *gpu_resources;
 526
 527         kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1;
 528         kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1;
 529         kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd
 530                         - kfd->vm_info.first_vmid_kfd + 1;
 531
 532         /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps.
 533          * 32 and 64-bit requests are possible and must be
 534          * supported.
 535          */
 536         kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev);
 537         if (!kfd->pci_atomic_requested &&
 538             kfd->device_info.needs_pci_atomics &&
 539             (!kfd->device_info.no_atomic_fw_version ||
 540              kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) {
 541                 dev_info(kfd_device,
 542                          "skipped device %x:%x, PCI rejects atomics %d<%d\n",
 543                          kfd->adev->pdev->vendor, kfd->adev->pdev->device,
 544                          kfd->mec_fw_version,
 545                          kfd->device_info.no_atomic_fw_version);
 546                 return false;
 547         }
 548
 549         /* Verify module parameters regarding mapped process number*/
 550         if (hws_max_conc_proc >= 0)
 551                 kfd->max_proc_per_quantum = min((u32)hws_max_conc_proc, kfd->vm_info.vmid_num_kfd);
 552         else
 553                 kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd;
 554
 555         /* calculate max size of mqds needed for queues */
 556         size = max_num_of_queues_per_device *
 557                         kfd->device_info.mqd_size_aligned;
 558
 559         /*
 560          * calculate max size of runlist packet.
 561          * There can be only 2 packets at once
 562          */
 563         map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ?
 564                                 sizeof(struct pm4_mes_map_process_aldebaran) :
 565                                 sizeof(struct pm4_mes_map_process);
 566         size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size +
 567                 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues)
 568                 + sizeof(struct pm4_mes_runlist)) * 2;
 569
 570         /* Add size of HIQ & DIQ */
 571         size += KFD_KERNEL_QUEUE_SIZE * 2;
 572
 573         /* add another 512KB for all other allocations on gart (HPD, fences) */
 574         size += 512 * 1024;
 575
 576         if (amdgpu_amdkfd_alloc_gtt_mem(
 577                         kfd->adev, size, &kfd->gtt_mem,
 578                         &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr,
 579                         false)) {
 580                 dev_err(kfd_device, "Could not allocate %d bytes\n", size);
 581                 goto alloc_gtt_mem_failure;
 582         }
 583
 584         dev_info(kfd_device, "Allocated %d bytes on gart\n", size);
 585
 586         /* Initialize GTT sa with 512 byte chunk size */
 587         if (kfd_gtt_sa_init(kfd, size, 512) != 0) {
 588                 dev_err(kfd_device, "Error initializing gtt sub-allocator\n");
 589                 goto kfd_gtt_sa_init_error;
 590         }
 591
 592         if (kfd_doorbell_init(kfd)) {
 593                 dev_err(kfd_device,
 594                         "Error initializing doorbell aperture\n");
 595                 goto kfd_doorbell_error;
 596         }
 597
 598         if (amdgpu_use_xgmi_p2p)
 599                 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id;
 600
 601         kfd->noretry = kfd->adev->gmc.noretry;
 602
 603         if (kfd_interrupt_init(kfd)) {
 604                 dev_err(kfd_device, "Error initializing interrupts\n");
 605                 goto kfd_interrupt_error;
 606         }
 607
 608         kfd->dqm = device_queue_manager_init(kfd);
 609         if (!kfd->dqm) {
 610                 dev_err(kfd_device, "Error initializing queue manager\n");
 611                 goto device_queue_manager_error;
 612         }
 613
 614         /* If supported on this device, allocate global GWS that is shared
 615          * by all KFD processes
 616          */
 617         if (kfd_gws_init(kfd)) {
 618                 dev_err(kfd_device, "Could not allocate %d gws\n",
 619                         kfd->adev->gds.gws_size);
 620                 goto gws_error;
 621         }
 622
 623         /* If CRAT is broken, won't set iommu enabled */
 624         kfd_double_confirm_iommu_support(kfd);
 625
 626         if (kfd_iommu_device_init(kfd)) {
 627                 kfd->use_iommu_v2 = false;
 628                 dev_err(kfd_device, "Error initializing iommuv2\n");
 629                 goto device_iommu_error;
 630         }
 631
 632         kfd_cwsr_init(kfd);
 633
 634         svm_migrate_init(kfd->adev);
 635
 636         if (kgd2kfd_resume_iommu(kfd))
 637                 goto device_iommu_error;
 638
 639         if (kfd_resume(kfd))
 640                 goto kfd_resume_error;
 641
 642         amdgpu_amdkfd_get_local_mem_info(kfd->adev, &kfd->local_mem_info);
 643
 644         if (kfd_topology_add_device(kfd)) {
 645                 dev_err(kfd_device, "Error adding device to topology\n");
 646                 goto kfd_topology_add_device_error;
 647         }
 648
 649         kfd_smi_init(kfd);
 650
 651         kfd->init_complete = true;
 652         dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor,
 653                  kfd->adev->pdev->device);
 654
 655         pr_debug("Starting kfd with the following scheduling policy %d\n",
 656                 kfd->dqm->sched_policy);
 657
 658         goto out;
 659
 660 kfd_topology_add_device_error:
 661 kfd_resume_error:
 662 device_iommu_error:
 663 gws_error:
 664         device_queue_manager_uninit(kfd->dqm);
 665 device_queue_manager_error:
 666         kfd_interrupt_exit(kfd);
 667 kfd_interrupt_error:
 668         kfd_doorbell_fini(kfd);
 669 kfd_doorbell_error:
 670         kfd_gtt_sa_fini(kfd);
 671 kfd_gtt_sa_init_error:
 672         amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem);
 673 alloc_gtt_mem_failure:
 674         if (kfd->gws)
 675                 amdgpu_amdkfd_free_gws(kfd->adev, kfd->gws);
 676         dev_err(kfd_device,
 677                 "device %x:%x NOT added due to errors\n",
 678                 kfd->adev->pdev->vendor, kfd->adev->pdev->device);
 679 out:
 680         return kfd->init_complete;
 681 }
 682
 683 void kgd2kfd_device_exit(struct kfd_dev *kfd)
 684 {
 685         if (kfd->init_complete) {
 686                 device_queue_manager_uninit(kfd->dqm);
 687                 kfd_interrupt_exit(kfd);
 688                 kfd_topology_remove_device(kfd);
 689                 kfd_doorbell_fini(kfd);
 690                 ida_destroy(&kfd->doorbell_ida);
 691                 kfd_gtt_sa_fini(kfd);
 692                 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem);
 693                 if (kfd->gws)
 694                         amdgpu_amdkfd_free_gws(kfd->adev, kfd->gws);
 695         }
 696
 697         kfree(kfd);
 698 }
 699
 700 int kgd2kfd_pre_reset(struct kfd_dev *kfd)
 701 {
 702         if (!kfd->init_complete)
 703                 return 0;
 704
 705         kfd_smi_event_update_gpu_reset(kfd, false);
 706
 707         kfd->dqm->ops.pre_reset(kfd->dqm);
 708
 709         kgd2kfd_suspend(kfd, false);
 710
 711         kfd_signal_reset_event(kfd);
 712         return 0;
 713 }
 714
 715 /*
 716  * Fix me. KFD won't be able to resume existing process for now.
 717  * We will keep all existing process in a evicted state and
 718  * wait the process to be terminated.
 719  */
 720
 721 int kgd2kfd_post_reset(struct kfd_dev *kfd)
 722 {
 723         int ret;
 724
 725         if (!kfd->init_complete)
 726                 return 0;
 727
 728         ret = kfd_resume(kfd);
 729         if (ret)
 730                 return ret;
 731         atomic_dec(&kfd_locked);
 732
 733         atomic_set(&kfd->sram_ecc_flag, 0);
 734
 735         kfd_smi_event_update_gpu_reset(kfd, true);
 736
 737         return 0;
 738 }
 739
 740 bool kfd_is_locked(void)
 741 {
 742         return  (atomic_read(&kfd_locked) > 0);
 743 }
 744
 745 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)
 746 {
 747         if (!kfd->init_complete)
 748                 return;
 749
 750         /* for runtime suspend, skip locking kfd */
 751         if (!run_pm) {
 752                 /* For first KFD device suspend all the KFD processes */
 753                 if (atomic_inc_return(&kfd_locked) == 1)
 754                         kfd_suspend_all_processes();
 755         }
 756
 757         kfd->dqm->ops.stop(kfd->dqm);
 758         kfd_iommu_suspend(kfd);
 759 }
 760
 761 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)
 762 {
 763         int ret, count;
 764
 765         if (!kfd->init_complete)
 766                 return 0;
 767
 768         ret = kfd_resume(kfd);
 769         if (ret)
 770                 return ret;
 771
 772         /* for runtime resume, skip unlocking kfd */
 773         if (!run_pm) {
 774                 count = atomic_dec_return(&kfd_locked);
 775                 WARN_ONCE(count < 0, "KFD suspend / resume ref. error");
 776                 if (count == 0)
 777                         ret = kfd_resume_all_processes();
 778         }
 779
 780         return ret;
 781 }
 782
 783 int kgd2kfd_resume_iommu(struct kfd_dev *kfd)
 784 {
 785         int err = 0;
 786
 787         err = kfd_iommu_resume(kfd);
 788         if (err)
 789                 dev_err(kfd_device,
 790                         "Failed to resume IOMMU for device %x:%x\n",
 791                         kfd->adev->pdev->vendor, kfd->adev->pdev->device);
 792         return err;
 793 }
 794
 795 static int kfd_resume(struct kfd_dev *kfd)
 796 {
 797         int err = 0;
 798
 799         err = kfd->dqm->ops.start(kfd->dqm);
 800         if (err)
 801                 dev_err(kfd_device,
 802                         "Error starting queue manager for device %x:%x\n",
 803                         kfd->adev->pdev->vendor, kfd->adev->pdev->device);
 804
 805         return err;
 806 }
 807
 808 static inline void kfd_queue_work(struct workqueue_struct *wq,
 809                                   struct work_struct *work)
 810 {
 811         int cpu, new_cpu;
 812
 813         cpu = new_cpu = smp_processor_id();
 814         do {
 815                 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids;
 816                 if (cpu_to_node(new_cpu) == numa_node_id())
 817                         break;
 818         } while (cpu != new_cpu);
 819
 820         queue_work_on(new_cpu, wq, work);
 821 }
 822
 823 /* This is called directly from KGD at ISR. */
 824 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
 825 {
 826         uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE];
 827         bool is_patched = false;
 828         unsigned long flags;
 829
 830         if (!kfd->init_complete)
 831                 return;
 832
 833         if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) {
 834                 dev_err_once(kfd_device, "Ring entry too small\n");
 835                 return;
 836         }
 837
 838         spin_lock_irqsave(&kfd->interrupt_lock, flags);
 839
 840         if (kfd->interrupts_active
 841             && interrupt_is_wanted(kfd, ih_ring_entry,
 842                                    patched_ihre, &is_patched)
 843             && enqueue_ih_ring_entry(kfd,
 844                                      is_patched ? patched_ihre : ih_ring_entry))
 845                 kfd_queue_work(kfd->ih_wq, &kfd->interrupt_work);
 846
 847         spin_unlock_irqrestore(&kfd->interrupt_lock, flags);
 848 }
 849
 850 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger)
 851 {
 852         struct kfd_process *p;
 853         int r;
 854
 855         /* Because we are called from arbitrary context (workqueue) as opposed
 856          * to process context, kfd_process could attempt to exit while we are
 857          * running so the lookup function increments the process ref count.
 858          */
 859         p = kfd_lookup_process_by_mm(mm);
 860         if (!p)
 861                 return -ESRCH;
 862
 863         WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid);
 864         r = kfd_process_evict_queues(p, trigger);
 865
 866         kfd_unref_process(p);
 867         return r;
 868 }
 869
 870 int kgd2kfd_resume_mm(struct mm_struct *mm)
 871 {
 872         struct kfd_process *p;
 873         int r;
 874
 875         /* Because we are called from arbitrary context (workqueue) as opposed
 876          * to process context, kfd_process could attempt to exit while we are
 877          * running so the lookup function increments the process ref count.
 878          */
 879         p = kfd_lookup_process_by_mm(mm);
 880         if (!p)
 881                 return -ESRCH;
 882
 883         r = kfd_process_restore_queues(p);
 884
 885         kfd_unref_process(p);
 886         return r;
 887 }
 888
 889 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will
 890  *   prepare for safe eviction of KFD BOs that belong to the specified
 891  *   process.
 892  *
 893  * @mm: mm_struct that identifies the specified KFD process
 894  * @fence: eviction fence attached to KFD process BOs
 895  *
 896  */
 897 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
 898                                                struct dma_fence *fence)
 899 {
 900         struct kfd_process *p;
 901         unsigned long active_time;
 902         unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS);
 903
 904         if (!fence)
 905                 return -EINVAL;
 906
 907         if (dma_fence_is_signaled(fence))
 908                 return 0;
 909
 910         p = kfd_lookup_process_by_mm(mm);
 911         if (!p)
 912                 return -ENODEV;
 913
 914         if (fence->seqno == p->last_eviction_seqno)
 915                 goto out;
 916
 917         p->last_eviction_seqno = fence->seqno;
 918
 919         /* Avoid KFD process starvation. Wait for at least
 920          * PROCESS_ACTIVE_TIME_MS before evicting the process again
 921          */
 922         active_time = get_jiffies_64() - p->last_restore_timestamp;
 923         if (delay_jiffies > active_time)
 924                 delay_jiffies -= active_time;
 925         else
 926                 delay_jiffies = 0;
 927
 928         /* During process initialization eviction_work.dwork is initialized
 929          * to kfd_evict_bo_worker
 930          */
 931         WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies",
 932              p->lead_thread->pid, delay_jiffies);
 933         schedule_delayed_work(&p->eviction_work, delay_jiffies);
 934 out:
 935         kfd_unref_process(p);
 936         return 0;
 937 }
 938
 939 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
 940                                 unsigned int chunk_size)
 941 {
 942         if (WARN_ON(buf_size < chunk_size))
 943                 return -EINVAL;
 944         if (WARN_ON(buf_size == 0))
 945                 return -EINVAL;
 946         if (WARN_ON(chunk_size == 0))
 947                 return -EINVAL;
 948
 949         kfd->gtt_sa_chunk_size = chunk_size;
 950         kfd->gtt_sa_num_of_chunks = buf_size / chunk_size;
 951
 952         kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks,
 953                                            GFP_KERNEL);
 954         if (!kfd->gtt_sa_bitmap)
 955                 return -ENOMEM;
 956
 957         pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n",
 958                         kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap);
 959
 960         mutex_init(&kfd->gtt_sa_lock);
 961
 962         return 0;
 963 }
 964
 965 static void kfd_gtt_sa_fini(struct kfd_dev *kfd)
 966 {
 967         mutex_destroy(&kfd->gtt_sa_lock);
 968         bitmap_free(kfd->gtt_sa_bitmap);
 969 }
 970
 971 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr,
 972                                                 unsigned int bit_num,
 973                                                 unsigned int chunk_size)
 974 {
 975         return start_addr + bit_num * chunk_size;
 976 }
 977
 978 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr,
 979                                                 unsigned int bit_num,
 980                                                 unsigned int chunk_size)
 981 {
 982         return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size);
 983 }
 984
 985 int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size,
 986                         struct kfd_mem_obj **mem_obj)
 987 {
 988         unsigned int found, start_search, cur_size;
 989
 990         if (size == 0)
 991                 return -EINVAL;
 992
 993         if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size)
 994                 return -ENOMEM;
 995
 996         *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
 997         if (!(*mem_obj))
 998                 return -ENOMEM;
 999
1000         pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size);
1001
1002         start_search = 0;
1003
1004         mutex_lock(&kfd->gtt_sa_lock);
1005
1006 kfd_gtt_restart_search:
1007         /* Find the first chunk that is free */
1008         found = find_next_zero_bit(kfd->gtt_sa_bitmap,
1009                                         kfd->gtt_sa_num_of_chunks,
1010                                         start_search);
1011
1012         pr_debug("Found = %d\n", found);
1013
1014         /* If there wasn't any free chunk, bail out */
1015         if (found == kfd->gtt_sa_num_of_chunks)
1016                 goto kfd_gtt_no_free_chunk;
1017
1018         /* Update fields of mem_obj */
1019         (*mem_obj)->range_start = found;
1020         (*mem_obj)->range_end = found;
1021         (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr(
1022                                         kfd->gtt_start_gpu_addr,
1023                                         found,
1024                                         kfd->gtt_sa_chunk_size);
1025         (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr(
1026                                         kfd->gtt_start_cpu_ptr,
1027                                         found,
1028                                         kfd->gtt_sa_chunk_size);
1029
1030         pr_debug("gpu_addr = %p, cpu_addr = %p\n",
1031                         (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr);
1032
1033         /* If we need only one chunk, mark it as allocated and get out */
1034         if (size <= kfd->gtt_sa_chunk_size) {
1035                 pr_debug("Single bit\n");
1036                 __set_bit(found, kfd->gtt_sa_bitmap);
1037                 goto kfd_gtt_out;
1038         }
1039
1040         /* Otherwise, try to see if we have enough contiguous chunks */
1041         cur_size = size - kfd->gtt_sa_chunk_size;
1042         do {
1043                 (*mem_obj)->range_end =
1044                         find_next_zero_bit(kfd->gtt_sa_bitmap,
1045                                         kfd->gtt_sa_num_of_chunks, ++found);
1046                 /*
1047                  * If next free chunk is not contiguous than we need to
1048                  * restart our search from the last free chunk we found (which
1049                  * wasn't contiguous to the previous ones
1050                  */
1051                 if ((*mem_obj)->range_end != found) {
1052                         start_search = found;
1053                         goto kfd_gtt_restart_search;
1054                 }
1055
1056                 /*
1057                  * If we reached end of buffer, bail out with error
1058                  */
1059                 if (found == kfd->gtt_sa_num_of_chunks)
1060                         goto kfd_gtt_no_free_chunk;
1061
1062                 /* Check if we don't need another chunk */
1063                 if (cur_size <= kfd->gtt_sa_chunk_size)
1064                         cur_size = 0;
1065                 else
1066                         cur_size -= kfd->gtt_sa_chunk_size;
1067
1068         } while (cur_size > 0);
1069
1070         pr_debug("range_start = %d, range_end = %d\n",
1071                 (*mem_obj)->range_start, (*mem_obj)->range_end);
1072
1073         /* Mark the chunks as allocated */
1074         bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start,
1075                    (*mem_obj)->range_end - (*mem_obj)->range_start + 1);
1076
1077 kfd_gtt_out:
1078         mutex_unlock(&kfd->gtt_sa_lock);
1079         return 0;
1080
1081 kfd_gtt_no_free_chunk:
1082         pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj);
1083         mutex_unlock(&kfd->gtt_sa_lock);
1084         kfree(*mem_obj);
1085         return -ENOMEM;
1086 }
1087
1088 int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj)
1089 {
1090         /* Act like kfree when trying to free a NULL object */
1091         if (!mem_obj)
1092                 return 0;
1093
1094         pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n",
1095                         mem_obj, mem_obj->range_start, mem_obj->range_end);
1096
1097         mutex_lock(&kfd->gtt_sa_lock);
1098
1099         /* Mark the chunks as free */
1100         bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start,
1101                      mem_obj->range_end - mem_obj->range_start + 1);
1102
1103         mutex_unlock(&kfd->gtt_sa_lock);
1104
1105         kfree(mem_obj);
1106         return 0;
1107 }
1108
1109 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
1110 {
1111         if (kfd)
1112                 atomic_inc(&kfd->sram_ecc_flag);
1113 }
1114
1115 void kfd_inc_compute_active(struct kfd_dev *kfd)
1116 {
1117         if (atomic_inc_return(&kfd->compute_profile) == 1)
1118                 amdgpu_amdkfd_set_compute_idle(kfd->adev, false);
1119 }
1120
1121 void kfd_dec_compute_active(struct kfd_dev *kfd)
1122 {
1123         int count = atomic_dec_return(&kfd->compute_profile);
1124
1125         if (count == 0)
1126                 amdgpu_amdkfd_set_compute_idle(kfd->adev, true);
1127         WARN_ONCE(count < 0, "Compute profile ref. count error");
1128 }
1129
1130 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask)
1131 {
1132         if (kfd && kfd->init_complete)
1133                 kfd_smi_event_update_thermal_throttling(kfd, throttle_bitmask);
1134 }
1135
1136 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and
1137  * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA.
1138  * When the device has more than two engines, we reserve two for PCIe to enable
1139  * full-duplex and the rest are used as XGMI.
1140  */
1141 unsigned int kfd_get_num_sdma_engines(struct kfd_dev *kdev)
1142 {
1143         /* If XGMI is not supported, all SDMA engines are PCIe */
1144         if (!kdev->adev->gmc.xgmi.supported)
1145                 return kdev->adev->sdma.num_instances;
1146
1147         return min(kdev->adev->sdma.num_instances, 2);
1148 }
1149
1150 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_dev *kdev)
1151 {
1152         /* After reserved for PCIe, the rest of engines are XGMI */
1153         return kdev->adev->sdma.num_instances - kfd_get_num_sdma_engines(kdev);
1154 }
1155
1156 #if defined(CONFIG_DEBUG_FS)
1157
1158 /* This function will send a package to HIQ to hang the HWS
1159  * which will trigger a GPU reset and bring the HWS back to normal state
1160  */
1161 int kfd_debugfs_hang_hws(struct kfd_dev *dev)
1162 {
1163         if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) {
1164                 pr_err("HWS is not enabled");
1165                 return -EINVAL;
1166         }
1167
1168         return dqm_debugfs_hang_hws(dev->dqm);
1169 }
1170
1171 #endif