2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 SQ_CMD_VMID_OFFSET = 28,
28 ADDRESS_WATCH_CNTL_OFFSET = 24
32 PRIV_QUEUE_SYNC_TIME_MS = 200
35 /* CONTEXT reg space definition */
37 CONTEXT_REG_BASE = 0xA000,
38 CONTEXT_REG_END = 0xA400,
39 CONTEXT_REG_SIZE = CONTEXT_REG_END - CONTEXT_REG_BASE
42 /* USER CONFIG reg space definition */
44 USERCONFIG_REG_BASE = 0xC000,
45 USERCONFIG_REG_END = 0x10000,
46 USERCONFIG_REG_SIZE = USERCONFIG_REG_END - USERCONFIG_REG_BASE
49 /* CONFIG reg space definition */
51 AMD_CONFIG_REG_BASE = 0x2000, /* in dwords */
52 AMD_CONFIG_REG_END = 0x2B00,
53 AMD_CONFIG_REG_SIZE = AMD_CONFIG_REG_END - AMD_CONFIG_REG_BASE
56 /* SH reg space definition */
60 SH_REG_SIZE = SH_REG_END - SH_REG_BASE
63 /* SQ_CMD definitions */
67 SQ_IND_CMD_CMD_NULL = 0x00000000,
68 SQ_IND_CMD_CMD_HALT = 0x00000001,
69 SQ_IND_CMD_CMD_RESUME = 0x00000002,
70 SQ_IND_CMD_CMD_KILL = 0x00000003,
71 SQ_IND_CMD_CMD_DEBUG = 0x00000004,
72 SQ_IND_CMD_CMD_TRAP = 0x00000005,
75 enum SQ_IND_CMD_MODE {
76 SQ_IND_CMD_MODE_SINGLE = 0x00000000,
77 SQ_IND_CMD_MODE_BROADCAST = 0x00000001,
78 SQ_IND_CMD_MODE_BROADCAST_QUEUE = 0x00000002,
79 SQ_IND_CMD_MODE_BROADCAST_PIPE = 0x00000003,
80 SQ_IND_CMD_MODE_BROADCAST_ME = 0x00000004,
83 union SQ_IND_INDEX_BITS {
89 uint32_t force_read:1;
90 uint32_t read_timeout:1;
100 union SQ_IND_CMD_BITS {
114 uint32_t check_vmid:1;
129 union SQ_IND_DATA_BITS {
138 union GRBM_GFX_INDEX_BITS {
140 uint32_t instance_index:8;
144 uint32_t sh_broadcast_writes:1;
145 uint32_t instance_broadcast_writes:1;
146 uint32_t se_broadcast_writes:1;
153 union TCP_WATCH_ADDR_H_BITS {
164 union TCP_WATCH_ADDR_L_BITS {
175 QUEUESTATE__INVALID = 0, /* so by default we'll get invalid state */
176 QUEUESTATE__ACTIVE_COMPLETION_PENDING,
180 union ULARGE_INTEGER {
185 unsigned long long quad_part;
189 #define KFD_CIK_VMID_START_OFFSET (8)
190 #define KFD_CIK_VMID_END_OFFSET (KFD_CIK_VMID_START_OFFSET + (8))
193 void kfd_dbgdev_init(struct kfd_dbgdev *pdbgdev, struct kfd_dev *pdev,
194 enum DBGDEV_TYPE type);
196 union TCP_WATCH_CNTL_BITS {
210 ADDRESS_WATCH_REG_CNTL_ATC_BIT = 0x10000000UL,
211 ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK = 0x00FFFFFF,
212 ADDRESS_WATCH_REG_ADDLOW_MASK_EXTENSION = 0x03000000,
213 /* extend the mask to 26 bits in order to match the low address field */
214 ADDRESS_WATCH_REG_ADDLOW_SHIFT = 6,
215 ADDRESS_WATCH_REG_ADDHIGH_MASK = 0xFFFF
219 MAX_TRAPID = 8, /* 3 bits in the bitfield. */
220 MAX_WATCH_ADDRESSES = 4
224 ADDRESS_WATCH_REG_ADDR_HI = 0,
225 ADDRESS_WATCH_REG_ADDR_LO,
226 ADDRESS_WATCH_REG_CNTL,
227 ADDRESS_WATCH_REG_MAX
230 #endif /* KFD_DBGDEV_H_ */