1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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24 #ifndef KFD_CRAT_H_INCLUDED
25 #define KFD_CRAT_H_INCLUDED
27 #include <linux/types.h>
32 * 4CC signature value for the CRAT ACPI table
35 #define CRAT_SIGNATURE "CRAT"
38 * Component Resource Association Table (CRAT)
41 #define CRAT_OEMID_LENGTH 6
42 #define CRAT_OEMTABLEID_LENGTH 8
43 #define CRAT_RESERVED_LENGTH 6
45 #define CRAT_OEMID_64BIT_MASK ((1ULL << (CRAT_OEMID_LENGTH * 8)) - 1)
47 /* Compute Unit flags */
48 #define COMPUTE_UNIT_CPU (1 << 0) /* Create Virtual CRAT for CPU */
49 #define COMPUTE_UNIT_GPU (1 << 1) /* Create Virtual CRAT for GPU */
56 uint8_t oem_id[CRAT_OEMID_LENGTH];
57 uint8_t oem_table_id[CRAT_OEMTABLEID_LENGTH];
58 uint32_t oem_revision;
60 uint32_t creator_revision;
61 uint32_t total_entries;
63 uint8_t reserved[CRAT_RESERVED_LENGTH];
67 * The header structure is immediately followed by total_entries of the
72 * The currently defined subtype entries in the CRAT
74 #define CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY 0
75 #define CRAT_SUBTYPE_MEMORY_AFFINITY 1
76 #define CRAT_SUBTYPE_CACHE_AFFINITY 2
77 #define CRAT_SUBTYPE_TLB_AFFINITY 3
78 #define CRAT_SUBTYPE_CCOMPUTE_AFFINITY 4
79 #define CRAT_SUBTYPE_IOLINK_AFFINITY 5
80 #define CRAT_SUBTYPE_MAX 6
83 * Do not change the value of CRAT_SIBLINGMAP_SIZE from 32
84 * as it breaks the ABI.
86 #define CRAT_SIBLINGMAP_SIZE 32
89 * ComputeUnit Affinity structure and definitions
91 #define CRAT_CU_FLAGS_ENABLED 0x00000001
92 #define CRAT_CU_FLAGS_HOT_PLUGGABLE 0x00000002
93 #define CRAT_CU_FLAGS_CPU_PRESENT 0x00000004
94 #define CRAT_CU_FLAGS_GPU_PRESENT 0x00000008
95 #define CRAT_CU_FLAGS_IOMMU_PRESENT 0x00000010
96 #define CRAT_CU_FLAGS_RESERVED 0xffffffe0
98 #define CRAT_COMPUTEUNIT_RESERVED_LENGTH 4
100 struct crat_subtype_computeunit {
105 uint32_t proximity_domain;
106 uint32_t processor_id_low;
107 uint16_t num_cpu_cores;
108 uint16_t num_simd_cores;
109 uint16_t max_waves_simd;
111 uint16_t hsa_capability;
112 uint16_t lds_size_in_kb;
113 uint8_t wave_front_size;
115 uint16_t micro_engine_id;
117 uint8_t num_cu_per_array;
118 uint8_t num_simd_per_cu;
119 uint8_t max_slots_scatch_cu;
120 uint8_t reserved2[CRAT_COMPUTEUNIT_RESERVED_LENGTH];
124 * HSA Memory Affinity structure and definitions
126 #define CRAT_MEM_FLAGS_ENABLED 0x00000001
127 #define CRAT_MEM_FLAGS_HOT_PLUGGABLE 0x00000002
128 #define CRAT_MEM_FLAGS_NON_VOLATILE 0x00000004
129 #define CRAT_MEM_FLAGS_RESERVED 0xfffffff8
131 #define CRAT_MEMORY_RESERVED_LENGTH 8
133 struct crat_subtype_memory {
138 uint32_t proximity_domain;
139 uint32_t base_addr_low;
140 uint32_t base_addr_high;
142 uint32_t length_high;
144 uint8_t visibility_type; /* for virtual (dGPU) CRAT */
145 uint8_t reserved2[CRAT_MEMORY_RESERVED_LENGTH - 1];
149 * HSA Cache Affinity structure and definitions
151 #define CRAT_CACHE_FLAGS_ENABLED 0x00000001
152 #define CRAT_CACHE_FLAGS_DATA_CACHE 0x00000002
153 #define CRAT_CACHE_FLAGS_INST_CACHE 0x00000004
154 #define CRAT_CACHE_FLAGS_CPU_CACHE 0x00000008
155 #define CRAT_CACHE_FLAGS_SIMD_CACHE 0x00000010
156 #define CRAT_CACHE_FLAGS_RESERVED 0xffffffe0
158 #define CRAT_CACHE_RESERVED_LENGTH 8
160 struct crat_subtype_cache {
165 uint32_t processor_id_low;
166 uint8_t sibling_map[CRAT_SIBLINGMAP_SIZE];
169 uint8_t lines_per_tag;
170 uint16_t cache_line_size;
171 uint8_t associativity;
172 uint8_t cache_properties;
173 uint16_t cache_latency;
174 uint8_t reserved2[CRAT_CACHE_RESERVED_LENGTH];
178 * HSA TLB Affinity structure and definitions
180 #define CRAT_TLB_FLAGS_ENABLED 0x00000001
181 #define CRAT_TLB_FLAGS_DATA_TLB 0x00000002
182 #define CRAT_TLB_FLAGS_INST_TLB 0x00000004
183 #define CRAT_TLB_FLAGS_CPU_TLB 0x00000008
184 #define CRAT_TLB_FLAGS_SIMD_TLB 0x00000010
185 #define CRAT_TLB_FLAGS_RESERVED 0xffffffe0
187 #define CRAT_TLB_RESERVED_LENGTH 4
189 struct crat_subtype_tlb {
194 uint32_t processor_id_low;
195 uint8_t sibling_map[CRAT_SIBLINGMAP_SIZE];
197 uint8_t data_tlb_associativity_2mb;
198 uint8_t data_tlb_size_2mb;
199 uint8_t instruction_tlb_associativity_2mb;
200 uint8_t instruction_tlb_size_2mb;
201 uint8_t data_tlb_associativity_4k;
202 uint8_t data_tlb_size_4k;
203 uint8_t instruction_tlb_associativity_4k;
204 uint8_t instruction_tlb_size_4k;
205 uint8_t data_tlb_associativity_1gb;
206 uint8_t data_tlb_size_1gb;
207 uint8_t instruction_tlb_associativity_1gb;
208 uint8_t instruction_tlb_size_1gb;
209 uint8_t reserved2[CRAT_TLB_RESERVED_LENGTH];
213 * HSA CCompute/APU Affinity structure and definitions
215 #define CRAT_CCOMPUTE_FLAGS_ENABLED 0x00000001
216 #define CRAT_CCOMPUTE_FLAGS_RESERVED 0xfffffffe
218 #define CRAT_CCOMPUTE_RESERVED_LENGTH 16
220 struct crat_subtype_ccompute {
225 uint32_t processor_id_low;
226 uint8_t sibling_map[CRAT_SIBLINGMAP_SIZE];
228 uint8_t reserved2[CRAT_CCOMPUTE_RESERVED_LENGTH];
232 * HSA IO Link Affinity structure and definitions
234 #define CRAT_IOLINK_FLAGS_ENABLED (1 << 0)
235 #define CRAT_IOLINK_FLAGS_NON_COHERENT (1 << 1)
236 #define CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT (1 << 2)
237 #define CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT (1 << 3)
238 #define CRAT_IOLINK_FLAGS_NO_PEER_TO_PEER_DMA (1 << 4)
239 #define CRAT_IOLINK_FLAGS_BI_DIRECTIONAL (1 << 31)
240 #define CRAT_IOLINK_FLAGS_RESERVED_MASK 0x7fffffe0
245 #define CRAT_IOLINK_TYPE_UNDEFINED 0
246 #define CRAT_IOLINK_TYPE_HYPERTRANSPORT 1
247 #define CRAT_IOLINK_TYPE_PCIEXPRESS 2
248 #define CRAT_IOLINK_TYPE_AMBA 3
249 #define CRAT_IOLINK_TYPE_MIPI 4
250 #define CRAT_IOLINK_TYPE_QPI_1_1 5
251 #define CRAT_IOLINK_TYPE_RESERVED1 6
252 #define CRAT_IOLINK_TYPE_RESERVED2 7
253 #define CRAT_IOLINK_TYPE_RAPID_IO 8
254 #define CRAT_IOLINK_TYPE_INFINIBAND 9
255 #define CRAT_IOLINK_TYPE_RESERVED3 10
256 #define CRAT_IOLINK_TYPE_XGMI 11
257 #define CRAT_IOLINK_TYPE_XGOP 12
258 #define CRAT_IOLINK_TYPE_GZ 13
259 #define CRAT_IOLINK_TYPE_ETHERNET_RDMA 14
260 #define CRAT_IOLINK_TYPE_RDMA_OTHER 15
261 #define CRAT_IOLINK_TYPE_OTHER 16
262 #define CRAT_IOLINK_TYPE_MAX 255
264 #define CRAT_IOLINK_RESERVED_LENGTH 24
266 struct crat_subtype_iolink {
271 uint32_t proximity_domain_from;
272 uint32_t proximity_domain_to;
273 uint8_t io_interface_type;
274 uint8_t version_major;
275 uint16_t version_minor;
276 uint32_t minimum_latency;
277 uint32_t maximum_latency;
278 uint32_t minimum_bandwidth_mbs;
279 uint32_t maximum_bandwidth_mbs;
280 uint32_t recommended_transfer_size;
281 uint8_t reserved2[CRAT_IOLINK_RESERVED_LENGTH - 1];
286 * HSA generic sub-type header
289 #define CRAT_SUBTYPE_FLAGS_ENABLED 0x00000001
291 struct crat_subtype_generic {
302 /* Static table to describe GPU Cache information */
303 struct kfd_gpu_cache_info {
305 uint32_t cache_level;
306 uint32_t cache_line_size;
308 /* Indicates how many Compute Units share this cache
309 * within a SA. Value = 1 indicates the cache is not shared
311 uint32_t num_cu_shared;
313 int kfd_get_gpu_cache_info(struct kfd_node *kdev, struct kfd_gpu_cache_info **pcache_info);
315 void kfd_destroy_crat_image(void *crat_image);
316 int kfd_parse_crat_table(void *crat_image, struct list_head *device_list,
317 uint32_t proximity_domain);
318 int kfd_create_crat_image_virtual(void **crat_image, size_t *size,
319 int flags, struct kfd_node *kdev,
320 uint32_t proximity_domain);
322 #endif /* KFD_CRAT_H_INCLUDED */