1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/device.h>
25 #include <linux/export.h>
26 #include <linux/err.h>
28 #include <linux/file.h>
29 #include <linux/sched.h>
30 #include <linux/slab.h>
31 #include <linux/uaccess.h>
32 #include <linux/compat.h>
33 #include <uapi/linux/kfd_ioctl.h>
34 #include <linux/time.h>
36 #include <linux/mman.h>
37 #include <linux/ptrace.h>
38 #include <linux/dma-buf.h>
39 #include <linux/fdtable.h>
40 #include <linux/processor.h>
42 #include "kfd_device_queue_manager.h"
44 #include "amdgpu_amdkfd.h"
45 #include "kfd_smi_events.h"
46 #include "amdgpu_dma_buf.h"
47 #include "kfd_debug.h"
49 static long kfd_ioctl(struct file *, unsigned int, unsigned long);
50 static int kfd_open(struct inode *, struct file *);
51 static int kfd_release(struct inode *, struct file *);
52 static int kfd_mmap(struct file *, struct vm_area_struct *);
54 static const char kfd_dev_name[] = "kfd";
56 static const struct file_operations kfd_fops = {
58 .unlocked_ioctl = kfd_ioctl,
59 .compat_ioctl = compat_ptr_ioctl,
61 .release = kfd_release,
65 static int kfd_char_dev_major = -1;
66 static struct class *kfd_class;
67 struct device *kfd_device;
69 static inline struct kfd_process_device *kfd_lock_pdd_by_id(struct kfd_process *p, __u32 gpu_id)
71 struct kfd_process_device *pdd;
73 mutex_lock(&p->mutex);
74 pdd = kfd_process_device_data_by_id(p, gpu_id);
79 mutex_unlock(&p->mutex);
83 static inline void kfd_unlock_pdd(struct kfd_process_device *pdd)
85 mutex_unlock(&pdd->process->mutex);
88 int kfd_chardev_init(void)
92 kfd_char_dev_major = register_chrdev(0, kfd_dev_name, &kfd_fops);
93 err = kfd_char_dev_major;
95 goto err_register_chrdev;
97 kfd_class = class_create(THIS_MODULE, kfd_dev_name);
98 err = PTR_ERR(kfd_class);
99 if (IS_ERR(kfd_class))
100 goto err_class_create;
102 kfd_device = device_create(kfd_class, NULL,
103 MKDEV(kfd_char_dev_major, 0),
105 err = PTR_ERR(kfd_device);
106 if (IS_ERR(kfd_device))
107 goto err_device_create;
112 class_destroy(kfd_class);
114 unregister_chrdev(kfd_char_dev_major, kfd_dev_name);
119 void kfd_chardev_exit(void)
121 device_destroy(kfd_class, MKDEV(kfd_char_dev_major, 0));
122 class_destroy(kfd_class);
123 unregister_chrdev(kfd_char_dev_major, kfd_dev_name);
128 static int kfd_open(struct inode *inode, struct file *filep)
130 struct kfd_process *process;
131 bool is_32bit_user_mode;
133 if (iminor(inode) != 0)
136 is_32bit_user_mode = in_compat_syscall();
138 if (is_32bit_user_mode) {
140 "Process %d (32-bit) failed to open /dev/kfd\n"
141 "32-bit processes are not supported by amdkfd\n",
146 process = kfd_create_process(current);
148 return PTR_ERR(process);
150 if (kfd_process_init_cwsr_apu(process, filep)) {
151 kfd_unref_process(process);
155 /* filep now owns the reference returned by kfd_create_process */
156 filep->private_data = process;
158 dev_dbg(kfd_device, "process %d opened, compat mode (32 bit) - %d\n",
159 process->pasid, process->is_32bit_user_mode);
164 static int kfd_release(struct inode *inode, struct file *filep)
166 struct kfd_process *process = filep->private_data;
169 kfd_unref_process(process);
174 static int kfd_ioctl_get_version(struct file *filep, struct kfd_process *p,
177 struct kfd_ioctl_get_version_args *args = data;
179 args->major_version = KFD_IOCTL_MAJOR_VERSION;
180 args->minor_version = KFD_IOCTL_MINOR_VERSION;
185 static int set_queue_properties_from_user(struct queue_properties *q_properties,
186 struct kfd_ioctl_create_queue_args *args)
189 * Repurpose queue percentage to accommodate new features:
190 * bit 0-7: queue percentage
191 * bit 8-15: pm4_target_xcc
193 if ((args->queue_percentage & 0xFF) > KFD_MAX_QUEUE_PERCENTAGE) {
194 pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n");
198 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) {
199 pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n");
203 if ((args->ring_base_address) &&
204 (!access_ok((const void __user *) args->ring_base_address,
205 sizeof(uint64_t)))) {
206 pr_err("Can't access ring base address\n");
210 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) {
211 pr_err("Ring size must be a power of 2 or 0\n");
215 if (!access_ok((const void __user *) args->read_pointer_address,
217 pr_err("Can't access read pointer\n");
221 if (!access_ok((const void __user *) args->write_pointer_address,
223 pr_err("Can't access write pointer\n");
227 if (args->eop_buffer_address &&
228 !access_ok((const void __user *) args->eop_buffer_address,
230 pr_debug("Can't access eop buffer");
234 if (args->ctx_save_restore_address &&
235 !access_ok((const void __user *) args->ctx_save_restore_address,
237 pr_debug("Can't access ctx save restore buffer");
241 q_properties->is_interop = false;
242 q_properties->is_gws = false;
243 q_properties->queue_percent = args->queue_percentage & 0xFF;
244 /* bit 8-15 are repurposed to be PM4 target XCC */
245 q_properties->pm4_target_xcc = (args->queue_percentage >> 8) & 0xFF;
246 q_properties->priority = args->queue_priority;
247 q_properties->queue_address = args->ring_base_address;
248 q_properties->queue_size = args->ring_size;
249 q_properties->read_ptr = (uint32_t *) args->read_pointer_address;
250 q_properties->write_ptr = (uint32_t *) args->write_pointer_address;
251 q_properties->eop_ring_buffer_address = args->eop_buffer_address;
252 q_properties->eop_ring_buffer_size = args->eop_buffer_size;
253 q_properties->ctx_save_restore_area_address =
254 args->ctx_save_restore_address;
255 q_properties->ctx_save_restore_area_size = args->ctx_save_restore_size;
256 q_properties->ctl_stack_size = args->ctl_stack_size;
257 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE ||
258 args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL)
259 q_properties->type = KFD_QUEUE_TYPE_COMPUTE;
260 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA)
261 q_properties->type = KFD_QUEUE_TYPE_SDMA;
262 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA_XGMI)
263 q_properties->type = KFD_QUEUE_TYPE_SDMA_XGMI;
267 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL)
268 q_properties->format = KFD_QUEUE_FORMAT_AQL;
270 q_properties->format = KFD_QUEUE_FORMAT_PM4;
272 pr_debug("Queue Percentage: %d, %d\n",
273 q_properties->queue_percent, args->queue_percentage);
275 pr_debug("Queue Priority: %d, %d\n",
276 q_properties->priority, args->queue_priority);
278 pr_debug("Queue Address: 0x%llX, 0x%llX\n",
279 q_properties->queue_address, args->ring_base_address);
281 pr_debug("Queue Size: 0x%llX, %u\n",
282 q_properties->queue_size, args->ring_size);
284 pr_debug("Queue r/w Pointers: %px, %px\n",
285 q_properties->read_ptr,
286 q_properties->write_ptr);
288 pr_debug("Queue Format: %d\n", q_properties->format);
290 pr_debug("Queue EOP: 0x%llX\n", q_properties->eop_ring_buffer_address);
292 pr_debug("Queue CTX save area: 0x%llX\n",
293 q_properties->ctx_save_restore_area_address);
298 static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p,
301 struct kfd_ioctl_create_queue_args *args = data;
302 struct kfd_node *dev;
304 unsigned int queue_id;
305 struct kfd_process_device *pdd;
306 struct queue_properties q_properties;
307 uint32_t doorbell_offset_in_process = 0;
308 struct amdgpu_bo *wptr_bo = NULL;
310 memset(&q_properties, 0, sizeof(struct queue_properties));
312 pr_debug("Creating queue ioctl\n");
314 err = set_queue_properties_from_user(&q_properties, args);
318 pr_debug("Looking for gpu id 0x%x\n", args->gpu_id);
320 mutex_lock(&p->mutex);
322 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
324 pr_debug("Could not find gpu id 0x%x\n", args->gpu_id);
330 pdd = kfd_bind_process_to_device(dev, p);
333 goto err_bind_process;
336 if (!pdd->doorbell_index &&
337 kfd_alloc_process_doorbells(dev->kfd, &pdd->doorbell_index) < 0) {
339 goto err_alloc_doorbells;
342 /* Starting with GFX11, wptr BOs must be mapped to GART for MES to determine work
343 * on unmapped queues for usermode queue oversubscription (no aggregated doorbell)
345 if (dev->kfd->shared_resources.enable_mes &&
346 ((dev->adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK)
347 >> AMDGPU_MES_API_VERSION_SHIFT) >= 2) {
348 struct amdgpu_bo_va_mapping *wptr_mapping;
349 struct amdgpu_vm *wptr_vm;
351 wptr_vm = drm_priv_to_vm(pdd->drm_priv);
352 err = amdgpu_bo_reserve(wptr_vm->root.bo, false);
354 goto err_wptr_map_gart;
356 wptr_mapping = amdgpu_vm_bo_lookup_mapping(
357 wptr_vm, args->write_pointer_address >> PAGE_SHIFT);
358 amdgpu_bo_unreserve(wptr_vm->root.bo);
360 pr_err("Failed to lookup wptr bo\n");
362 goto err_wptr_map_gart;
365 wptr_bo = wptr_mapping->bo_va->base.bo;
366 if (wptr_bo->tbo.base.size > PAGE_SIZE) {
367 pr_err("Requested GART mapping for wptr bo larger than one page\n");
369 goto err_wptr_map_gart;
372 err = amdgpu_amdkfd_map_gtt_bo_to_gart(dev->adev, wptr_bo);
374 pr_err("Failed to map wptr bo to GART\n");
375 goto err_wptr_map_gart;
379 pr_debug("Creating queue for PASID 0x%x on gpu 0x%x\n",
383 err = pqm_create_queue(&p->pqm, dev, filep, &q_properties, &queue_id, wptr_bo,
384 NULL, NULL, NULL, &doorbell_offset_in_process);
386 goto err_create_queue;
388 args->queue_id = queue_id;
391 /* Return gpu_id as doorbell offset for mmap usage */
392 args->doorbell_offset = KFD_MMAP_TYPE_DOORBELL;
393 args->doorbell_offset |= KFD_MMAP_GPU_ID(args->gpu_id);
394 if (KFD_IS_SOC15(dev))
395 /* On SOC15 ASICs, include the doorbell offset within the
396 * process doorbell frame, which is 2 pages.
398 args->doorbell_offset |= doorbell_offset_in_process;
400 mutex_unlock(&p->mutex);
402 pr_debug("Queue id %d was created successfully\n", args->queue_id);
404 pr_debug("Ring buffer address == 0x%016llX\n",
405 args->ring_base_address);
407 pr_debug("Read ptr address == 0x%016llX\n",
408 args->read_pointer_address);
410 pr_debug("Write ptr address == 0x%016llX\n",
411 args->write_pointer_address);
417 amdgpu_amdkfd_free_gtt_mem(dev->adev, wptr_bo);
422 mutex_unlock(&p->mutex);
426 static int kfd_ioctl_destroy_queue(struct file *filp, struct kfd_process *p,
430 struct kfd_ioctl_destroy_queue_args *args = data;
432 pr_debug("Destroying queue id %d for pasid 0x%x\n",
436 mutex_lock(&p->mutex);
438 retval = pqm_destroy_queue(&p->pqm, args->queue_id);
440 mutex_unlock(&p->mutex);
444 static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p,
448 struct kfd_ioctl_update_queue_args *args = data;
449 struct queue_properties properties;
452 * Repurpose queue percentage to accommodate new features:
453 * bit 0-7: queue percentage
454 * bit 8-15: pm4_target_xcc
456 if ((args->queue_percentage & 0xFF) > KFD_MAX_QUEUE_PERCENTAGE) {
457 pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n");
461 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) {
462 pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n");
466 if ((args->ring_base_address) &&
467 (!access_ok((const void __user *) args->ring_base_address,
468 sizeof(uint64_t)))) {
469 pr_err("Can't access ring base address\n");
473 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) {
474 pr_err("Ring size must be a power of 2 or 0\n");
478 properties.queue_address = args->ring_base_address;
479 properties.queue_size = args->ring_size;
480 properties.queue_percent = args->queue_percentage & 0xFF;
481 /* bit 8-15 are repurposed to be PM4 target XCC */
482 properties.pm4_target_xcc = (args->queue_percentage >> 8) & 0xFF;
483 properties.priority = args->queue_priority;
485 pr_debug("Updating queue id %d for pasid 0x%x\n",
486 args->queue_id, p->pasid);
488 mutex_lock(&p->mutex);
490 retval = pqm_update_queue_properties(&p->pqm, args->queue_id, &properties);
492 mutex_unlock(&p->mutex);
497 static int kfd_ioctl_set_cu_mask(struct file *filp, struct kfd_process *p,
501 const int max_num_cus = 1024;
502 struct kfd_ioctl_set_cu_mask_args *args = data;
503 struct mqd_update_info minfo = {0};
504 uint32_t __user *cu_mask_ptr = (uint32_t __user *)args->cu_mask_ptr;
505 size_t cu_mask_size = sizeof(uint32_t) * (args->num_cu_mask / 32);
507 if ((args->num_cu_mask % 32) != 0) {
508 pr_debug("num_cu_mask 0x%x must be a multiple of 32",
513 minfo.cu_mask.count = args->num_cu_mask;
514 if (minfo.cu_mask.count == 0) {
515 pr_debug("CU mask cannot be 0");
519 /* To prevent an unreasonably large CU mask size, set an arbitrary
520 * limit of max_num_cus bits. We can then just drop any CU mask bits
521 * past max_num_cus bits and just use the first max_num_cus bits.
523 if (minfo.cu_mask.count > max_num_cus) {
524 pr_debug("CU mask cannot be greater than 1024 bits");
525 minfo.cu_mask.count = max_num_cus;
526 cu_mask_size = sizeof(uint32_t) * (max_num_cus/32);
529 minfo.cu_mask.ptr = kzalloc(cu_mask_size, GFP_KERNEL);
530 if (!minfo.cu_mask.ptr)
533 retval = copy_from_user(minfo.cu_mask.ptr, cu_mask_ptr, cu_mask_size);
535 pr_debug("Could not copy CU mask from userspace");
540 mutex_lock(&p->mutex);
542 retval = pqm_update_mqd(&p->pqm, args->queue_id, &minfo);
544 mutex_unlock(&p->mutex);
547 kfree(minfo.cu_mask.ptr);
551 static int kfd_ioctl_get_queue_wave_state(struct file *filep,
552 struct kfd_process *p, void *data)
554 struct kfd_ioctl_get_queue_wave_state_args *args = data;
557 mutex_lock(&p->mutex);
559 r = pqm_get_wave_state(&p->pqm, args->queue_id,
560 (void __user *)args->ctl_stack_address,
561 &args->ctl_stack_used_size,
562 &args->save_area_used_size);
564 mutex_unlock(&p->mutex);
569 static int kfd_ioctl_set_memory_policy(struct file *filep,
570 struct kfd_process *p, void *data)
572 struct kfd_ioctl_set_memory_policy_args *args = data;
574 struct kfd_process_device *pdd;
575 enum cache_policy default_policy, alternate_policy;
577 if (args->default_policy != KFD_IOC_CACHE_POLICY_COHERENT
578 && args->default_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) {
582 if (args->alternate_policy != KFD_IOC_CACHE_POLICY_COHERENT
583 && args->alternate_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) {
587 mutex_lock(&p->mutex);
588 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
590 pr_debug("Could not find gpu id 0x%x\n", args->gpu_id);
595 pdd = kfd_bind_process_to_device(pdd->dev, p);
601 default_policy = (args->default_policy == KFD_IOC_CACHE_POLICY_COHERENT)
602 ? cache_policy_coherent : cache_policy_noncoherent;
605 (args->alternate_policy == KFD_IOC_CACHE_POLICY_COHERENT)
606 ? cache_policy_coherent : cache_policy_noncoherent;
608 if (!pdd->dev->dqm->ops.set_cache_memory_policy(pdd->dev->dqm,
612 (void __user *)args->alternate_aperture_base,
613 args->alternate_aperture_size))
618 mutex_unlock(&p->mutex);
623 static int kfd_ioctl_set_trap_handler(struct file *filep,
624 struct kfd_process *p, void *data)
626 struct kfd_ioctl_set_trap_handler_args *args = data;
628 struct kfd_process_device *pdd;
630 mutex_lock(&p->mutex);
632 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
638 pdd = kfd_bind_process_to_device(pdd->dev, p);
644 kfd_process_set_trap_handler(&pdd->qpd, args->tba_addr, args->tma_addr);
648 mutex_unlock(&p->mutex);
653 static int kfd_ioctl_dbg_register(struct file *filep,
654 struct kfd_process *p, void *data)
659 static int kfd_ioctl_dbg_unregister(struct file *filep,
660 struct kfd_process *p, void *data)
665 static int kfd_ioctl_dbg_address_watch(struct file *filep,
666 struct kfd_process *p, void *data)
671 /* Parse and generate fixed size data structure for wave control */
672 static int kfd_ioctl_dbg_wave_control(struct file *filep,
673 struct kfd_process *p, void *data)
678 static int kfd_ioctl_get_clock_counters(struct file *filep,
679 struct kfd_process *p, void *data)
681 struct kfd_ioctl_get_clock_counters_args *args = data;
682 struct kfd_process_device *pdd;
684 mutex_lock(&p->mutex);
685 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
686 mutex_unlock(&p->mutex);
688 /* Reading GPU clock counter from KGD */
689 args->gpu_clock_counter = amdgpu_amdkfd_get_gpu_clock_counter(pdd->dev->adev);
691 /* Node without GPU resource */
692 args->gpu_clock_counter = 0;
694 /* No access to rdtsc. Using raw monotonic time */
695 args->cpu_clock_counter = ktime_get_raw_ns();
696 args->system_clock_counter = ktime_get_boottime_ns();
698 /* Since the counter is in nano-seconds we use 1GHz frequency */
699 args->system_clock_freq = 1000000000;
705 static int kfd_ioctl_get_process_apertures(struct file *filp,
706 struct kfd_process *p, void *data)
708 struct kfd_ioctl_get_process_apertures_args *args = data;
709 struct kfd_process_device_apertures *pAperture;
712 dev_dbg(kfd_device, "get apertures for PASID 0x%x", p->pasid);
714 args->num_of_nodes = 0;
716 mutex_lock(&p->mutex);
717 /* Run over all pdd of the process */
718 for (i = 0; i < p->n_pdds; i++) {
719 struct kfd_process_device *pdd = p->pdds[i];
722 &args->process_apertures[args->num_of_nodes];
723 pAperture->gpu_id = pdd->dev->id;
724 pAperture->lds_base = pdd->lds_base;
725 pAperture->lds_limit = pdd->lds_limit;
726 pAperture->gpuvm_base = pdd->gpuvm_base;
727 pAperture->gpuvm_limit = pdd->gpuvm_limit;
728 pAperture->scratch_base = pdd->scratch_base;
729 pAperture->scratch_limit = pdd->scratch_limit;
732 "node id %u\n", args->num_of_nodes);
734 "gpu id %u\n", pdd->dev->id);
736 "lds_base %llX\n", pdd->lds_base);
738 "lds_limit %llX\n", pdd->lds_limit);
740 "gpuvm_base %llX\n", pdd->gpuvm_base);
742 "gpuvm_limit %llX\n", pdd->gpuvm_limit);
744 "scratch_base %llX\n", pdd->scratch_base);
746 "scratch_limit %llX\n", pdd->scratch_limit);
748 if (++args->num_of_nodes >= NUM_OF_SUPPORTED_GPUS)
751 mutex_unlock(&p->mutex);
756 static int kfd_ioctl_get_process_apertures_new(struct file *filp,
757 struct kfd_process *p, void *data)
759 struct kfd_ioctl_get_process_apertures_new_args *args = data;
760 struct kfd_process_device_apertures *pa;
764 dev_dbg(kfd_device, "get apertures for PASID 0x%x", p->pasid);
766 if (args->num_of_nodes == 0) {
767 /* Return number of nodes, so that user space can alloacate
770 mutex_lock(&p->mutex);
771 args->num_of_nodes = p->n_pdds;
775 /* Fill in process-aperture information for all available
776 * nodes, but not more than args->num_of_nodes as that is
777 * the amount of memory allocated by user
779 pa = kzalloc((sizeof(struct kfd_process_device_apertures) *
780 args->num_of_nodes), GFP_KERNEL);
784 mutex_lock(&p->mutex);
787 args->num_of_nodes = 0;
792 /* Run over all pdd of the process */
793 for (i = 0; i < min(p->n_pdds, args->num_of_nodes); i++) {
794 struct kfd_process_device *pdd = p->pdds[i];
796 pa[i].gpu_id = pdd->dev->id;
797 pa[i].lds_base = pdd->lds_base;
798 pa[i].lds_limit = pdd->lds_limit;
799 pa[i].gpuvm_base = pdd->gpuvm_base;
800 pa[i].gpuvm_limit = pdd->gpuvm_limit;
801 pa[i].scratch_base = pdd->scratch_base;
802 pa[i].scratch_limit = pdd->scratch_limit;
805 "gpu id %u\n", pdd->dev->id);
807 "lds_base %llX\n", pdd->lds_base);
809 "lds_limit %llX\n", pdd->lds_limit);
811 "gpuvm_base %llX\n", pdd->gpuvm_base);
813 "gpuvm_limit %llX\n", pdd->gpuvm_limit);
815 "scratch_base %llX\n", pdd->scratch_base);
817 "scratch_limit %llX\n", pdd->scratch_limit);
819 mutex_unlock(&p->mutex);
821 args->num_of_nodes = i;
823 (void __user *)args->kfd_process_device_apertures_ptr,
825 (i * sizeof(struct kfd_process_device_apertures)));
827 return ret ? -EFAULT : 0;
830 mutex_unlock(&p->mutex);
834 static int kfd_ioctl_create_event(struct file *filp, struct kfd_process *p,
837 struct kfd_ioctl_create_event_args *args = data;
840 /* For dGPUs the event page is allocated in user mode. The
841 * handle is passed to KFD with the first call to this IOCTL
842 * through the event_page_offset field.
844 if (args->event_page_offset) {
845 mutex_lock(&p->mutex);
846 err = kfd_kmap_event_page(p, args->event_page_offset);
847 mutex_unlock(&p->mutex);
852 err = kfd_event_create(filp, p, args->event_type,
853 args->auto_reset != 0, args->node_id,
854 &args->event_id, &args->event_trigger_data,
855 &args->event_page_offset,
856 &args->event_slot_index);
858 pr_debug("Created event (id:0x%08x) (%s)\n", args->event_id, __func__);
862 static int kfd_ioctl_destroy_event(struct file *filp, struct kfd_process *p,
865 struct kfd_ioctl_destroy_event_args *args = data;
867 return kfd_event_destroy(p, args->event_id);
870 static int kfd_ioctl_set_event(struct file *filp, struct kfd_process *p,
873 struct kfd_ioctl_set_event_args *args = data;
875 return kfd_set_event(p, args->event_id);
878 static int kfd_ioctl_reset_event(struct file *filp, struct kfd_process *p,
881 struct kfd_ioctl_reset_event_args *args = data;
883 return kfd_reset_event(p, args->event_id);
886 static int kfd_ioctl_wait_events(struct file *filp, struct kfd_process *p,
889 struct kfd_ioctl_wait_events_args *args = data;
891 return kfd_wait_on_events(p, args->num_events,
892 (void __user *)args->events_ptr,
893 (args->wait_for_all != 0),
894 &args->timeout, &args->wait_result);
896 static int kfd_ioctl_set_scratch_backing_va(struct file *filep,
897 struct kfd_process *p, void *data)
899 struct kfd_ioctl_set_scratch_backing_va_args *args = data;
900 struct kfd_process_device *pdd;
901 struct kfd_node *dev;
904 mutex_lock(&p->mutex);
905 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
912 pdd = kfd_bind_process_to_device(dev, p);
915 goto bind_process_to_device_fail;
918 pdd->qpd.sh_hidden_private_base = args->va_addr;
920 mutex_unlock(&p->mutex);
922 if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS &&
923 pdd->qpd.vmid != 0 && dev->kfd2kgd->set_scratch_backing_va)
924 dev->kfd2kgd->set_scratch_backing_va(
925 dev->adev, args->va_addr, pdd->qpd.vmid);
929 bind_process_to_device_fail:
931 mutex_unlock(&p->mutex);
935 static int kfd_ioctl_get_tile_config(struct file *filep,
936 struct kfd_process *p, void *data)
938 struct kfd_ioctl_get_tile_config_args *args = data;
939 struct kfd_process_device *pdd;
940 struct tile_config config;
943 mutex_lock(&p->mutex);
944 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
945 mutex_unlock(&p->mutex);
949 amdgpu_amdkfd_get_tile_config(pdd->dev->adev, &config);
951 args->gb_addr_config = config.gb_addr_config;
952 args->num_banks = config.num_banks;
953 args->num_ranks = config.num_ranks;
955 if (args->num_tile_configs > config.num_tile_configs)
956 args->num_tile_configs = config.num_tile_configs;
957 err = copy_to_user((void __user *)args->tile_config_ptr,
958 config.tile_config_ptr,
959 args->num_tile_configs * sizeof(uint32_t));
961 args->num_tile_configs = 0;
965 if (args->num_macro_tile_configs > config.num_macro_tile_configs)
966 args->num_macro_tile_configs =
967 config.num_macro_tile_configs;
968 err = copy_to_user((void __user *)args->macro_tile_config_ptr,
969 config.macro_tile_config_ptr,
970 args->num_macro_tile_configs * sizeof(uint32_t));
972 args->num_macro_tile_configs = 0;
979 static int kfd_ioctl_acquire_vm(struct file *filep, struct kfd_process *p,
982 struct kfd_ioctl_acquire_vm_args *args = data;
983 struct kfd_process_device *pdd;
984 struct file *drm_file;
987 drm_file = fget(args->drm_fd);
991 mutex_lock(&p->mutex);
992 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
999 ret = pdd->drm_file == drm_file ? 0 : -EBUSY;
1003 ret = kfd_process_device_init_vm(pdd, drm_file);
1007 /* On success, the PDD keeps the drm_file reference */
1008 mutex_unlock(&p->mutex);
1015 mutex_unlock(&p->mutex);
1020 bool kfd_dev_is_large_bar(struct kfd_node *dev)
1022 if (debug_largebar) {
1023 pr_debug("Simulate large-bar allocation on non large-bar machine\n");
1027 if (dev->kfd->use_iommu_v2)
1030 if (dev->local_mem_info.local_mem_size_private == 0 &&
1031 dev->local_mem_info.local_mem_size_public > 0)
1034 if (dev->local_mem_info.local_mem_size_public == 0 &&
1035 dev->kfd->adev->gmc.is_app_apu) {
1036 pr_debug("APP APU, Consider like a large bar system\n");
1043 static int kfd_ioctl_get_available_memory(struct file *filep,
1044 struct kfd_process *p, void *data)
1046 struct kfd_ioctl_get_available_memory_args *args = data;
1047 struct kfd_process_device *pdd = kfd_lock_pdd_by_id(p, args->gpu_id);
1051 args->available = amdgpu_amdkfd_get_available_memory(pdd->dev->adev,
1053 kfd_unlock_pdd(pdd);
1057 static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep,
1058 struct kfd_process *p, void *data)
1060 struct kfd_ioctl_alloc_memory_of_gpu_args *args = data;
1061 struct kfd_process_device *pdd;
1063 struct kfd_node *dev;
1066 uint64_t offset = args->mmap_offset;
1067 uint32_t flags = args->flags;
1069 if (args->size == 0)
1072 #if IS_ENABLED(CONFIG_HSA_AMD_SVM)
1073 /* Flush pending deferred work to avoid racing with deferred actions
1074 * from previous memory map changes (e.g. munmap).
1076 svm_range_list_lock_and_flush_work(&p->svms, current->mm);
1077 mutex_lock(&p->svms.lock);
1078 mmap_write_unlock(current->mm);
1079 if (interval_tree_iter_first(&p->svms.objects,
1080 args->va_addr >> PAGE_SHIFT,
1081 (args->va_addr + args->size - 1) >> PAGE_SHIFT)) {
1082 pr_err("Address: 0x%llx already allocated by SVM\n",
1084 mutex_unlock(&p->svms.lock);
1088 /* When register user buffer check if it has been registered by svm by
1089 * buffer cpu virtual address.
1091 if ((flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) &&
1092 interval_tree_iter_first(&p->svms.objects,
1093 args->mmap_offset >> PAGE_SHIFT,
1094 (args->mmap_offset + args->size - 1) >> PAGE_SHIFT)) {
1095 pr_err("User Buffer Address: 0x%llx already allocated by SVM\n",
1097 mutex_unlock(&p->svms.lock);
1101 mutex_unlock(&p->svms.lock);
1103 mutex_lock(&p->mutex);
1104 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
1112 if ((flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) &&
1113 (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) &&
1114 !kfd_dev_is_large_bar(dev)) {
1115 pr_err("Alloc host visible vram on small bar is not allowed\n");
1120 pdd = kfd_bind_process_to_device(dev, p);
1126 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) {
1127 if (args->size != kfd_doorbell_process_slice(dev->kfd)) {
1131 offset = kfd_get_process_doorbells(pdd);
1136 } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) {
1137 if (args->size != PAGE_SIZE) {
1141 offset = dev->adev->rmmio_remap.bus_addr;
1148 err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
1149 dev->adev, args->va_addr, args->size,
1150 pdd->drm_priv, (struct kgd_mem **) &mem, &offset,
1156 idr_handle = kfd_process_device_create_obj_handle(pdd, mem);
1157 if (idr_handle < 0) {
1162 /* Update the VRAM usage count */
1163 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
1164 uint64_t size = args->size;
1166 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM)
1168 WRITE_ONCE(pdd->vram_usage, pdd->vram_usage + PAGE_ALIGN(size));
1171 mutex_unlock(&p->mutex);
1173 args->handle = MAKE_HANDLE(args->gpu_id, idr_handle);
1174 args->mmap_offset = offset;
1176 /* MMIO is mapped through kfd device
1177 * Generate a kfd mmap offset
1179 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)
1180 args->mmap_offset = KFD_MMAP_TYPE_MMIO
1181 | KFD_MMAP_GPU_ID(args->gpu_id);
1186 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev, (struct kgd_mem *)mem,
1187 pdd->drm_priv, NULL);
1191 mutex_unlock(&p->mutex);
1195 static int kfd_ioctl_free_memory_of_gpu(struct file *filep,
1196 struct kfd_process *p, void *data)
1198 struct kfd_ioctl_free_memory_of_gpu_args *args = data;
1199 struct kfd_process_device *pdd;
1204 mutex_lock(&p->mutex);
1206 * Safeguard to prevent user space from freeing signal BO.
1207 * It will be freed at process termination.
1209 if (p->signal_handle && (p->signal_handle == args->handle)) {
1210 pr_err("Free signal BO is not allowed\n");
1215 pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle));
1217 pr_err("Process device data doesn't exist\n");
1222 mem = kfd_process_device_translate_handle(
1223 pdd, GET_IDR_HANDLE(args->handle));
1229 ret = amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev,
1230 (struct kgd_mem *)mem, pdd->drm_priv, &size);
1232 /* If freeing the buffer failed, leave the handle in place for
1233 * clean-up during process tear-down.
1236 kfd_process_device_remove_obj_handle(
1237 pdd, GET_IDR_HANDLE(args->handle));
1239 WRITE_ONCE(pdd->vram_usage, pdd->vram_usage - size);
1243 mutex_unlock(&p->mutex);
1247 static int kfd_ioctl_map_memory_to_gpu(struct file *filep,
1248 struct kfd_process *p, void *data)
1250 struct kfd_ioctl_map_memory_to_gpu_args *args = data;
1251 struct kfd_process_device *pdd, *peer_pdd;
1253 struct kfd_node *dev;
1256 uint32_t *devices_arr = NULL;
1258 if (!args->n_devices) {
1259 pr_debug("Device IDs array empty\n");
1262 if (args->n_success > args->n_devices) {
1263 pr_debug("n_success exceeds n_devices\n");
1267 devices_arr = kmalloc_array(args->n_devices, sizeof(*devices_arr),
1272 err = copy_from_user(devices_arr,
1273 (void __user *)args->device_ids_array_ptr,
1274 args->n_devices * sizeof(*devices_arr));
1277 goto copy_from_user_failed;
1280 mutex_lock(&p->mutex);
1281 pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle));
1284 goto get_process_device_data_failed;
1288 pdd = kfd_bind_process_to_device(dev, p);
1291 goto bind_process_to_device_failed;
1294 mem = kfd_process_device_translate_handle(pdd,
1295 GET_IDR_HANDLE(args->handle));
1298 goto get_mem_obj_from_handle_failed;
1301 for (i = args->n_success; i < args->n_devices; i++) {
1302 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]);
1304 pr_debug("Getting device by id failed for 0x%x\n",
1307 goto get_mem_obj_from_handle_failed;
1310 peer_pdd = kfd_bind_process_to_device(peer_pdd->dev, p);
1311 if (IS_ERR(peer_pdd)) {
1312 err = PTR_ERR(peer_pdd);
1313 goto get_mem_obj_from_handle_failed;
1316 err = amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
1317 peer_pdd->dev->adev, (struct kgd_mem *)mem,
1318 peer_pdd->drm_priv);
1320 struct pci_dev *pdev = peer_pdd->dev->adev->pdev;
1322 dev_err(dev->adev->dev,
1323 "Failed to map peer:%04x:%02x:%02x.%d mem_domain:%d\n",
1324 pci_domain_nr(pdev->bus),
1326 PCI_SLOT(pdev->devfn),
1327 PCI_FUNC(pdev->devfn),
1328 ((struct kgd_mem *)mem)->domain);
1329 goto map_memory_to_gpu_failed;
1331 args->n_success = i+1;
1334 err = amdgpu_amdkfd_gpuvm_sync_memory(dev->adev, (struct kgd_mem *) mem, true);
1336 pr_debug("Sync memory failed, wait interrupted by user signal\n");
1337 goto sync_memory_failed;
1340 mutex_unlock(&p->mutex);
1342 /* Flush TLBs after waiting for the page table updates to complete */
1343 for (i = 0; i < args->n_devices; i++) {
1344 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]);
1345 if (WARN_ON_ONCE(!peer_pdd))
1347 kfd_flush_tlb(peer_pdd, TLB_FLUSH_LEGACY);
1353 get_process_device_data_failed:
1354 bind_process_to_device_failed:
1355 get_mem_obj_from_handle_failed:
1356 map_memory_to_gpu_failed:
1358 mutex_unlock(&p->mutex);
1359 copy_from_user_failed:
1365 static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep,
1366 struct kfd_process *p, void *data)
1368 struct kfd_ioctl_unmap_memory_from_gpu_args *args = data;
1369 struct kfd_process_device *pdd, *peer_pdd;
1372 uint32_t *devices_arr = NULL, i;
1375 if (!args->n_devices) {
1376 pr_debug("Device IDs array empty\n");
1379 if (args->n_success > args->n_devices) {
1380 pr_debug("n_success exceeds n_devices\n");
1384 devices_arr = kmalloc_array(args->n_devices, sizeof(*devices_arr),
1389 err = copy_from_user(devices_arr,
1390 (void __user *)args->device_ids_array_ptr,
1391 args->n_devices * sizeof(*devices_arr));
1394 goto copy_from_user_failed;
1397 mutex_lock(&p->mutex);
1398 pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle));
1401 goto bind_process_to_device_failed;
1404 mem = kfd_process_device_translate_handle(pdd,
1405 GET_IDR_HANDLE(args->handle));
1408 goto get_mem_obj_from_handle_failed;
1411 for (i = args->n_success; i < args->n_devices; i++) {
1412 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]);
1415 goto get_mem_obj_from_handle_failed;
1417 err = amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
1418 peer_pdd->dev->adev, (struct kgd_mem *)mem, peer_pdd->drm_priv);
1420 pr_err("Failed to unmap from gpu %d/%d\n",
1421 i, args->n_devices);
1422 goto unmap_memory_from_gpu_failed;
1424 args->n_success = i+1;
1427 flush_tlb = kfd_flush_tlb_after_unmap(pdd->dev->kfd);
1429 err = amdgpu_amdkfd_gpuvm_sync_memory(pdd->dev->adev,
1430 (struct kgd_mem *) mem, true);
1432 pr_debug("Sync memory failed, wait interrupted by user signal\n");
1433 goto sync_memory_failed;
1436 mutex_unlock(&p->mutex);
1439 /* Flush TLBs after waiting for the page table updates to complete */
1440 for (i = 0; i < args->n_devices; i++) {
1441 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]);
1442 if (WARN_ON_ONCE(!peer_pdd))
1444 kfd_flush_tlb(peer_pdd, TLB_FLUSH_HEAVYWEIGHT);
1451 bind_process_to_device_failed:
1452 get_mem_obj_from_handle_failed:
1453 unmap_memory_from_gpu_failed:
1455 mutex_unlock(&p->mutex);
1456 copy_from_user_failed:
1461 static int kfd_ioctl_alloc_queue_gws(struct file *filep,
1462 struct kfd_process *p, void *data)
1465 struct kfd_ioctl_alloc_queue_gws_args *args = data;
1467 struct kfd_node *dev;
1469 mutex_lock(&p->mutex);
1470 q = pqm_get_user_queue(&p->pqm, args->queue_id);
1484 if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) {
1489 if (!kfd_dbg_has_gws_support(dev) && p->debug_trap_enabled) {
1494 retval = pqm_set_gws(&p->pqm, args->queue_id, args->num_gws ? dev->gws : NULL);
1495 mutex_unlock(&p->mutex);
1497 args->first_gws = 0;
1501 mutex_unlock(&p->mutex);
1505 static int kfd_ioctl_get_dmabuf_info(struct file *filep,
1506 struct kfd_process *p, void *data)
1508 struct kfd_ioctl_get_dmabuf_info_args *args = data;
1509 struct kfd_node *dev = NULL;
1510 struct amdgpu_device *dmabuf_adev;
1511 void *metadata_buffer = NULL;
1517 /* Find a KFD GPU device that supports the get_dmabuf_info query */
1518 for (i = 0; kfd_topology_enum_kfd_devices(i, &dev) == 0; i++)
1524 if (args->metadata_ptr) {
1525 metadata_buffer = kzalloc(args->metadata_size, GFP_KERNEL);
1526 if (!metadata_buffer)
1530 /* Get dmabuf info from KGD */
1531 r = amdgpu_amdkfd_get_dmabuf_info(dev->adev, args->dmabuf_fd,
1532 &dmabuf_adev, &args->size,
1533 metadata_buffer, args->metadata_size,
1534 &args->metadata_size, &flags, &xcp_id);
1539 args->gpu_id = dmabuf_adev->kfd.dev->nodes[xcp_id]->id;
1541 args->gpu_id = dmabuf_adev->kfd.dev->nodes[0]->id;
1542 args->flags = flags;
1544 /* Copy metadata buffer to user mode */
1545 if (metadata_buffer) {
1546 r = copy_to_user((void __user *)args->metadata_ptr,
1547 metadata_buffer, args->metadata_size);
1553 kfree(metadata_buffer);
1558 static int kfd_ioctl_import_dmabuf(struct file *filep,
1559 struct kfd_process *p, void *data)
1561 struct kfd_ioctl_import_dmabuf_args *args = data;
1562 struct kfd_process_device *pdd;
1563 struct dma_buf *dmabuf;
1569 dmabuf = dma_buf_get(args->dmabuf_fd);
1571 return PTR_ERR(dmabuf);
1573 mutex_lock(&p->mutex);
1574 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
1580 pdd = kfd_bind_process_to_device(pdd->dev, p);
1586 r = amdgpu_amdkfd_gpuvm_import_dmabuf(pdd->dev->adev, dmabuf,
1587 args->va_addr, pdd->drm_priv,
1588 (struct kgd_mem **)&mem, &size,
1593 idr_handle = kfd_process_device_create_obj_handle(pdd, mem);
1594 if (idr_handle < 0) {
1599 mutex_unlock(&p->mutex);
1600 dma_buf_put(dmabuf);
1602 args->handle = MAKE_HANDLE(args->gpu_id, idr_handle);
1607 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, (struct kgd_mem *)mem,
1608 pdd->drm_priv, NULL);
1610 mutex_unlock(&p->mutex);
1611 dma_buf_put(dmabuf);
1615 static int kfd_ioctl_export_dmabuf(struct file *filep,
1616 struct kfd_process *p, void *data)
1618 struct kfd_ioctl_export_dmabuf_args *args = data;
1619 struct kfd_process_device *pdd;
1620 struct dma_buf *dmabuf;
1621 struct kfd_node *dev;
1625 dev = kfd_device_by_id(GET_GPU_ID(args->handle));
1629 mutex_lock(&p->mutex);
1631 pdd = kfd_get_process_device_data(dev, p);
1637 mem = kfd_process_device_translate_handle(pdd,
1638 GET_IDR_HANDLE(args->handle));
1644 ret = amdgpu_amdkfd_gpuvm_export_dmabuf(mem, &dmabuf);
1645 mutex_unlock(&p->mutex);
1649 ret = dma_buf_fd(dmabuf, args->flags);
1651 dma_buf_put(dmabuf);
1654 /* dma_buf_fd assigns the reference count to the fd, no need to
1655 * put the reference here.
1657 args->dmabuf_fd = ret;
1662 mutex_unlock(&p->mutex);
1667 /* Handle requests for watching SMI events */
1668 static int kfd_ioctl_smi_events(struct file *filep,
1669 struct kfd_process *p, void *data)
1671 struct kfd_ioctl_smi_events_args *args = data;
1672 struct kfd_process_device *pdd;
1674 mutex_lock(&p->mutex);
1676 pdd = kfd_process_device_data_by_id(p, args->gpuid);
1677 mutex_unlock(&p->mutex);
1681 return kfd_smi_event_open(pdd->dev, &args->anon_fd);
1684 #if IS_ENABLED(CONFIG_HSA_AMD_SVM)
1686 static int kfd_ioctl_set_xnack_mode(struct file *filep,
1687 struct kfd_process *p, void *data)
1689 struct kfd_ioctl_set_xnack_mode_args *args = data;
1692 mutex_lock(&p->mutex);
1693 if (args->xnack_enabled >= 0) {
1694 if (!list_empty(&p->pqm.queues)) {
1695 pr_debug("Process has user queues running\n");
1700 if (p->xnack_enabled == args->xnack_enabled)
1703 if (args->xnack_enabled && !kfd_process_xnack_mode(p, true)) {
1708 r = svm_range_switch_xnack_reserve_mem(p, args->xnack_enabled);
1710 args->xnack_enabled = p->xnack_enabled;
1714 mutex_unlock(&p->mutex);
1719 static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data)
1721 struct kfd_ioctl_svm_args *args = data;
1724 pr_debug("start 0x%llx size 0x%llx op 0x%x nattr 0x%x\n",
1725 args->start_addr, args->size, args->op, args->nattr);
1727 if ((args->start_addr & ~PAGE_MASK) || (args->size & ~PAGE_MASK))
1729 if (!args->start_addr || !args->size)
1732 r = svm_ioctl(p, args->op, args->start_addr, args->size, args->nattr,
1738 static int kfd_ioctl_set_xnack_mode(struct file *filep,
1739 struct kfd_process *p, void *data)
1743 static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data)
1749 static int criu_checkpoint_process(struct kfd_process *p,
1750 uint8_t __user *user_priv_data,
1751 uint64_t *priv_offset)
1753 struct kfd_criu_process_priv_data process_priv;
1756 memset(&process_priv, 0, sizeof(process_priv));
1758 process_priv.version = KFD_CRIU_PRIV_VERSION;
1759 /* For CR, we don't consider negative xnack mode which is used for
1760 * querying without changing it, here 0 simply means disabled and 1
1761 * means enabled so retry for finding a valid PTE.
1763 process_priv.xnack_mode = p->xnack_enabled ? 1 : 0;
1765 ret = copy_to_user(user_priv_data + *priv_offset,
1766 &process_priv, sizeof(process_priv));
1769 pr_err("Failed to copy process information to user\n");
1773 *priv_offset += sizeof(process_priv);
1777 static int criu_checkpoint_devices(struct kfd_process *p,
1778 uint32_t num_devices,
1779 uint8_t __user *user_addr,
1780 uint8_t __user *user_priv_data,
1781 uint64_t *priv_offset)
1783 struct kfd_criu_device_priv_data *device_priv = NULL;
1784 struct kfd_criu_device_bucket *device_buckets = NULL;
1787 device_buckets = kvzalloc(num_devices * sizeof(*device_buckets), GFP_KERNEL);
1788 if (!device_buckets) {
1793 device_priv = kvzalloc(num_devices * sizeof(*device_priv), GFP_KERNEL);
1799 for (i = 0; i < num_devices; i++) {
1800 struct kfd_process_device *pdd = p->pdds[i];
1802 device_buckets[i].user_gpu_id = pdd->user_gpu_id;
1803 device_buckets[i].actual_gpu_id = pdd->dev->id;
1806 * priv_data does not contain useful information for now and is reserved for
1807 * future use, so we do not set its contents.
1811 ret = copy_to_user(user_addr, device_buckets, num_devices * sizeof(*device_buckets));
1813 pr_err("Failed to copy device information to user\n");
1818 ret = copy_to_user(user_priv_data + *priv_offset,
1820 num_devices * sizeof(*device_priv));
1822 pr_err("Failed to copy device information to user\n");
1825 *priv_offset += num_devices * sizeof(*device_priv);
1828 kvfree(device_buckets);
1829 kvfree(device_priv);
1833 static uint32_t get_process_num_bos(struct kfd_process *p)
1835 uint32_t num_of_bos = 0;
1838 /* Run over all PDDs of the process */
1839 for (i = 0; i < p->n_pdds; i++) {
1840 struct kfd_process_device *pdd = p->pdds[i];
1844 idr_for_each_entry(&pdd->alloc_idr, mem, id) {
1845 struct kgd_mem *kgd_mem = (struct kgd_mem *)mem;
1847 if ((uint64_t)kgd_mem->va > pdd->gpuvm_base)
1854 static int criu_get_prime_handle(struct drm_gem_object *gobj, int flags,
1857 struct dma_buf *dmabuf;
1860 dmabuf = amdgpu_gem_prime_export(gobj, flags);
1861 if (IS_ERR(dmabuf)) {
1862 ret = PTR_ERR(dmabuf);
1863 pr_err("dmabuf export failed for the BO\n");
1867 ret = dma_buf_fd(dmabuf, flags);
1869 pr_err("dmabuf create fd failed, ret:%d\n", ret);
1870 goto out_free_dmabuf;
1877 dma_buf_put(dmabuf);
1881 static int criu_checkpoint_bos(struct kfd_process *p,
1883 uint8_t __user *user_bos,
1884 uint8_t __user *user_priv_data,
1885 uint64_t *priv_offset)
1887 struct kfd_criu_bo_bucket *bo_buckets;
1888 struct kfd_criu_bo_priv_data *bo_privs;
1889 int ret = 0, pdd_index, bo_index = 0, id;
1892 bo_buckets = kvzalloc(num_bos * sizeof(*bo_buckets), GFP_KERNEL);
1896 bo_privs = kvzalloc(num_bos * sizeof(*bo_privs), GFP_KERNEL);
1902 for (pdd_index = 0; pdd_index < p->n_pdds; pdd_index++) {
1903 struct kfd_process_device *pdd = p->pdds[pdd_index];
1904 struct amdgpu_bo *dumper_bo;
1905 struct kgd_mem *kgd_mem;
1907 idr_for_each_entry(&pdd->alloc_idr, mem, id) {
1908 struct kfd_criu_bo_bucket *bo_bucket;
1909 struct kfd_criu_bo_priv_data *bo_priv;
1917 kgd_mem = (struct kgd_mem *)mem;
1918 dumper_bo = kgd_mem->bo;
1920 if ((uint64_t)kgd_mem->va <= pdd->gpuvm_base)
1923 bo_bucket = &bo_buckets[bo_index];
1924 bo_priv = &bo_privs[bo_index];
1926 bo_bucket->gpu_id = pdd->user_gpu_id;
1927 bo_bucket->addr = (uint64_t)kgd_mem->va;
1928 bo_bucket->size = amdgpu_bo_size(dumper_bo);
1929 bo_bucket->alloc_flags = (uint32_t)kgd_mem->alloc_flags;
1930 bo_priv->idr_handle = id;
1932 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
1933 ret = amdgpu_ttm_tt_get_userptr(&dumper_bo->tbo,
1934 &bo_priv->user_addr);
1936 pr_err("Failed to obtain user address for user-pointer bo\n");
1940 if (bo_bucket->alloc_flags
1941 & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) {
1942 ret = criu_get_prime_handle(&dumper_bo->tbo.base,
1943 bo_bucket->alloc_flags &
1944 KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? DRM_RDWR : 0,
1945 &bo_bucket->dmabuf_fd);
1949 bo_bucket->dmabuf_fd = KFD_INVALID_FD;
1952 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL)
1953 bo_bucket->offset = KFD_MMAP_TYPE_DOORBELL |
1954 KFD_MMAP_GPU_ID(pdd->dev->id);
1955 else if (bo_bucket->alloc_flags &
1956 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)
1957 bo_bucket->offset = KFD_MMAP_TYPE_MMIO |
1958 KFD_MMAP_GPU_ID(pdd->dev->id);
1960 bo_bucket->offset = amdgpu_bo_mmap_offset(dumper_bo);
1962 for (i = 0; i < p->n_pdds; i++) {
1963 if (amdgpu_amdkfd_bo_mapped_to_dev(p->pdds[i]->dev->adev, kgd_mem))
1964 bo_priv->mapped_gpuids[dev_idx++] = p->pdds[i]->user_gpu_id;
1967 pr_debug("bo_size = 0x%llx, bo_addr = 0x%llx bo_offset = 0x%llx\n"
1968 "gpu_id = 0x%x alloc_flags = 0x%x idr_handle = 0x%x",
1973 bo_bucket->alloc_flags,
1974 bo_priv->idr_handle);
1979 ret = copy_to_user(user_bos, bo_buckets, num_bos * sizeof(*bo_buckets));
1981 pr_err("Failed to copy BO information to user\n");
1986 ret = copy_to_user(user_priv_data + *priv_offset, bo_privs, num_bos * sizeof(*bo_privs));
1988 pr_err("Failed to copy BO priv information to user\n");
1993 *priv_offset += num_bos * sizeof(*bo_privs);
1996 while (ret && bo_index--) {
1997 if (bo_buckets[bo_index].alloc_flags
1998 & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT))
1999 close_fd(bo_buckets[bo_index].dmabuf_fd);
2007 static int criu_get_process_object_info(struct kfd_process *p,
2008 uint32_t *num_devices,
2010 uint32_t *num_objects,
2011 uint64_t *objs_priv_size)
2013 uint64_t queues_priv_data_size, svm_priv_data_size, priv_size;
2014 uint32_t num_queues, num_events, num_svm_ranges;
2017 *num_devices = p->n_pdds;
2018 *num_bos = get_process_num_bos(p);
2020 ret = kfd_process_get_queue_info(p, &num_queues, &queues_priv_data_size);
2024 num_events = kfd_get_num_events(p);
2026 ret = svm_range_get_info(p, &num_svm_ranges, &svm_priv_data_size);
2030 *num_objects = num_queues + num_events + num_svm_ranges;
2032 if (objs_priv_size) {
2033 priv_size = sizeof(struct kfd_criu_process_priv_data);
2034 priv_size += *num_devices * sizeof(struct kfd_criu_device_priv_data);
2035 priv_size += *num_bos * sizeof(struct kfd_criu_bo_priv_data);
2036 priv_size += queues_priv_data_size;
2037 priv_size += num_events * sizeof(struct kfd_criu_event_priv_data);
2038 priv_size += svm_priv_data_size;
2039 *objs_priv_size = priv_size;
2044 static int criu_checkpoint(struct file *filep,
2045 struct kfd_process *p,
2046 struct kfd_ioctl_criu_args *args)
2049 uint32_t num_devices, num_bos, num_objects;
2050 uint64_t priv_size, priv_offset = 0, bo_priv_offset;
2052 if (!args->devices || !args->bos || !args->priv_data)
2055 mutex_lock(&p->mutex);
2058 pr_err("No pdd for given process\n");
2063 /* Confirm all process queues are evicted */
2064 if (!p->queues_paused) {
2065 pr_err("Cannot dump process when queues are not in evicted state\n");
2066 /* CRIU plugin did not call op PROCESS_INFO before checkpointing */
2071 ret = criu_get_process_object_info(p, &num_devices, &num_bos, &num_objects, &priv_size);
2075 if (num_devices != args->num_devices ||
2076 num_bos != args->num_bos ||
2077 num_objects != args->num_objects ||
2078 priv_size != args->priv_data_size) {
2084 /* each function will store private data inside priv_data and adjust priv_offset */
2085 ret = criu_checkpoint_process(p, (uint8_t __user *)args->priv_data, &priv_offset);
2089 ret = criu_checkpoint_devices(p, num_devices, (uint8_t __user *)args->devices,
2090 (uint8_t __user *)args->priv_data, &priv_offset);
2094 /* Leave room for BOs in the private data. They need to be restored
2095 * before events, but we checkpoint them last to simplify the error
2098 bo_priv_offset = priv_offset;
2099 priv_offset += num_bos * sizeof(struct kfd_criu_bo_priv_data);
2102 ret = kfd_criu_checkpoint_queues(p, (uint8_t __user *)args->priv_data,
2107 ret = kfd_criu_checkpoint_events(p, (uint8_t __user *)args->priv_data,
2112 ret = kfd_criu_checkpoint_svm(p, (uint8_t __user *)args->priv_data, &priv_offset);
2117 /* This must be the last thing in this function that can fail.
2118 * Otherwise we leak dmabuf file descriptors.
2120 ret = criu_checkpoint_bos(p, num_bos, (uint8_t __user *)args->bos,
2121 (uint8_t __user *)args->priv_data, &bo_priv_offset);
2124 mutex_unlock(&p->mutex);
2126 pr_err("Failed to dump CRIU ret:%d\n", ret);
2128 pr_debug("CRIU dump ret:%d\n", ret);
2133 static int criu_restore_process(struct kfd_process *p,
2134 struct kfd_ioctl_criu_args *args,
2135 uint64_t *priv_offset,
2136 uint64_t max_priv_data_size)
2139 struct kfd_criu_process_priv_data process_priv;
2141 if (*priv_offset + sizeof(process_priv) > max_priv_data_size)
2144 ret = copy_from_user(&process_priv,
2145 (void __user *)(args->priv_data + *priv_offset),
2146 sizeof(process_priv));
2148 pr_err("Failed to copy process private information from user\n");
2152 *priv_offset += sizeof(process_priv);
2154 if (process_priv.version != KFD_CRIU_PRIV_VERSION) {
2155 pr_err("Invalid CRIU API version (checkpointed:%d current:%d)\n",
2156 process_priv.version, KFD_CRIU_PRIV_VERSION);
2160 pr_debug("Setting XNACK mode\n");
2161 if (process_priv.xnack_mode && !kfd_process_xnack_mode(p, true)) {
2162 pr_err("xnack mode cannot be set\n");
2166 pr_debug("set xnack mode: %d\n", process_priv.xnack_mode);
2167 p->xnack_enabled = process_priv.xnack_mode;
2174 static int criu_restore_devices(struct kfd_process *p,
2175 struct kfd_ioctl_criu_args *args,
2176 uint64_t *priv_offset,
2177 uint64_t max_priv_data_size)
2179 struct kfd_criu_device_bucket *device_buckets;
2180 struct kfd_criu_device_priv_data *device_privs;
2184 if (args->num_devices != p->n_pdds)
2187 if (*priv_offset + (args->num_devices * sizeof(*device_privs)) > max_priv_data_size)
2190 device_buckets = kmalloc_array(args->num_devices, sizeof(*device_buckets), GFP_KERNEL);
2191 if (!device_buckets)
2194 ret = copy_from_user(device_buckets, (void __user *)args->devices,
2195 args->num_devices * sizeof(*device_buckets));
2197 pr_err("Failed to copy devices buckets from user\n");
2202 for (i = 0; i < args->num_devices; i++) {
2203 struct kfd_node *dev;
2204 struct kfd_process_device *pdd;
2205 struct file *drm_file;
2207 /* device private data is not currently used */
2209 if (!device_buckets[i].user_gpu_id) {
2210 pr_err("Invalid user gpu_id\n");
2215 dev = kfd_device_by_id(device_buckets[i].actual_gpu_id);
2217 pr_err("Failed to find device with gpu_id = %x\n",
2218 device_buckets[i].actual_gpu_id);
2223 pdd = kfd_get_process_device_data(dev, p);
2225 pr_err("Failed to get pdd for gpu_id = %x\n",
2226 device_buckets[i].actual_gpu_id);
2230 pdd->user_gpu_id = device_buckets[i].user_gpu_id;
2232 drm_file = fget(device_buckets[i].drm_fd);
2234 pr_err("Invalid render node file descriptor sent from plugin (%d)\n",
2235 device_buckets[i].drm_fd);
2240 if (pdd->drm_file) {
2245 /* create the vm using render nodes for kfd pdd */
2246 if (kfd_process_device_init_vm(pdd, drm_file)) {
2247 pr_err("could not init vm for given pdd\n");
2248 /* On success, the PDD keeps the drm_file reference */
2254 * pdd now already has the vm bound to render node so below api won't create a new
2255 * exclusive kfd mapping but use existing one with renderDXXX but is still needed
2256 * for iommu v2 binding and runtime pm.
2258 pdd = kfd_bind_process_to_device(dev, p);
2264 if (!pdd->doorbell_index &&
2265 kfd_alloc_process_doorbells(pdd->dev->kfd, &pdd->doorbell_index) < 0) {
2272 * We are not copying device private data from user as we are not using the data for now,
2273 * but we still adjust for its private data.
2275 *priv_offset += args->num_devices * sizeof(*device_privs);
2278 kfree(device_buckets);
2282 static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd,
2283 struct kfd_criu_bo_bucket *bo_bucket,
2284 struct kfd_criu_bo_priv_data *bo_priv,
2285 struct kgd_mem **kgd_mem)
2289 const bool criu_resume = true;
2292 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) {
2293 if (bo_bucket->size !=
2294 kfd_doorbell_process_slice(pdd->dev->kfd))
2297 offset = kfd_get_process_doorbells(pdd);
2300 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) {
2301 /* MMIO BOs need remapped bus address */
2302 if (bo_bucket->size != PAGE_SIZE) {
2303 pr_err("Invalid page size\n");
2306 offset = pdd->dev->adev->rmmio_remap.bus_addr;
2308 pr_err("amdgpu_amdkfd_get_mmio_remap_phys_addr failed\n");
2311 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
2312 offset = bo_priv->user_addr;
2315 ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(pdd->dev->adev, bo_bucket->addr,
2316 bo_bucket->size, pdd->drm_priv, kgd_mem,
2317 &offset, bo_bucket->alloc_flags, criu_resume);
2319 pr_err("Could not create the BO\n");
2322 pr_debug("New BO created: size:0x%llx addr:0x%llx offset:0x%llx\n",
2323 bo_bucket->size, bo_bucket->addr, offset);
2325 /* Restore previous IDR handle */
2326 pr_debug("Restoring old IDR handle for the BO");
2327 idr_handle = idr_alloc(&pdd->alloc_idr, *kgd_mem, bo_priv->idr_handle,
2328 bo_priv->idr_handle + 1, GFP_KERNEL);
2330 if (idr_handle < 0) {
2331 pr_err("Could not allocate idr\n");
2332 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, *kgd_mem, pdd->drm_priv,
2337 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL)
2338 bo_bucket->restored_offset = KFD_MMAP_TYPE_DOORBELL | KFD_MMAP_GPU_ID(pdd->dev->id);
2339 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) {
2340 bo_bucket->restored_offset = KFD_MMAP_TYPE_MMIO | KFD_MMAP_GPU_ID(pdd->dev->id);
2341 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
2342 bo_bucket->restored_offset = offset;
2343 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
2344 bo_bucket->restored_offset = offset;
2345 /* Update the VRAM usage count */
2346 WRITE_ONCE(pdd->vram_usage, pdd->vram_usage + bo_bucket->size);
2351 static int criu_restore_bo(struct kfd_process *p,
2352 struct kfd_criu_bo_bucket *bo_bucket,
2353 struct kfd_criu_bo_priv_data *bo_priv)
2355 struct kfd_process_device *pdd;
2356 struct kgd_mem *kgd_mem;
2360 pr_debug("Restoring BO size:0x%llx addr:0x%llx gpu_id:0x%x flags:0x%x idr_handle:0x%x\n",
2361 bo_bucket->size, bo_bucket->addr, bo_bucket->gpu_id, bo_bucket->alloc_flags,
2362 bo_priv->idr_handle);
2364 pdd = kfd_process_device_data_by_id(p, bo_bucket->gpu_id);
2366 pr_err("Failed to get pdd\n");
2370 ret = criu_restore_memory_of_gpu(pdd, bo_bucket, bo_priv, &kgd_mem);
2374 /* now map these BOs to GPU/s */
2375 for (j = 0; j < p->n_pdds; j++) {
2376 struct kfd_node *peer;
2377 struct kfd_process_device *peer_pdd;
2379 if (!bo_priv->mapped_gpuids[j])
2382 peer_pdd = kfd_process_device_data_by_id(p, bo_priv->mapped_gpuids[j]);
2386 peer = peer_pdd->dev;
2388 peer_pdd = kfd_bind_process_to_device(peer, p);
2389 if (IS_ERR(peer_pdd))
2390 return PTR_ERR(peer_pdd);
2392 ret = amdgpu_amdkfd_gpuvm_map_memory_to_gpu(peer->adev, kgd_mem,
2393 peer_pdd->drm_priv);
2395 pr_err("Failed to map to gpu %d/%d\n", j, p->n_pdds);
2400 pr_debug("map memory was successful for the BO\n");
2401 /* create the dmabuf object and export the bo */
2402 if (bo_bucket->alloc_flags
2403 & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) {
2404 ret = criu_get_prime_handle(&kgd_mem->bo->tbo.base, DRM_RDWR,
2405 &bo_bucket->dmabuf_fd);
2409 bo_bucket->dmabuf_fd = KFD_INVALID_FD;
2415 static int criu_restore_bos(struct kfd_process *p,
2416 struct kfd_ioctl_criu_args *args,
2417 uint64_t *priv_offset,
2418 uint64_t max_priv_data_size)
2420 struct kfd_criu_bo_bucket *bo_buckets = NULL;
2421 struct kfd_criu_bo_priv_data *bo_privs = NULL;
2425 if (*priv_offset + (args->num_bos * sizeof(*bo_privs)) > max_priv_data_size)
2428 /* Prevent MMU notifications until stage-4 IOCTL (CRIU_RESUME) is received */
2429 amdgpu_amdkfd_block_mmu_notifications(p->kgd_process_info);
2431 bo_buckets = kvmalloc_array(args->num_bos, sizeof(*bo_buckets), GFP_KERNEL);
2435 ret = copy_from_user(bo_buckets, (void __user *)args->bos,
2436 args->num_bos * sizeof(*bo_buckets));
2438 pr_err("Failed to copy BOs information from user\n");
2443 bo_privs = kvmalloc_array(args->num_bos, sizeof(*bo_privs), GFP_KERNEL);
2449 ret = copy_from_user(bo_privs, (void __user *)args->priv_data + *priv_offset,
2450 args->num_bos * sizeof(*bo_privs));
2452 pr_err("Failed to copy BOs information from user\n");
2456 *priv_offset += args->num_bos * sizeof(*bo_privs);
2458 /* Create and map new BOs */
2459 for (; i < args->num_bos; i++) {
2460 ret = criu_restore_bo(p, &bo_buckets[i], &bo_privs[i]);
2462 pr_debug("Failed to restore BO[%d] ret%d\n", i, ret);
2467 /* Copy only the buckets back so user can read bo_buckets[N].restored_offset */
2468 ret = copy_to_user((void __user *)args->bos,
2470 (args->num_bos * sizeof(*bo_buckets)));
2475 while (ret && i--) {
2476 if (bo_buckets[i].alloc_flags
2477 & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT))
2478 close_fd(bo_buckets[i].dmabuf_fd);
2485 static int criu_restore_objects(struct file *filep,
2486 struct kfd_process *p,
2487 struct kfd_ioctl_criu_args *args,
2488 uint64_t *priv_offset,
2489 uint64_t max_priv_data_size)
2494 BUILD_BUG_ON(offsetof(struct kfd_criu_queue_priv_data, object_type));
2495 BUILD_BUG_ON(offsetof(struct kfd_criu_event_priv_data, object_type));
2496 BUILD_BUG_ON(offsetof(struct kfd_criu_svm_range_priv_data, object_type));
2498 for (i = 0; i < args->num_objects; i++) {
2499 uint32_t object_type;
2501 if (*priv_offset + sizeof(object_type) > max_priv_data_size) {
2502 pr_err("Invalid private data size\n");
2506 ret = get_user(object_type, (uint32_t __user *)(args->priv_data + *priv_offset));
2508 pr_err("Failed to copy private information from user\n");
2512 switch (object_type) {
2513 case KFD_CRIU_OBJECT_TYPE_QUEUE:
2514 ret = kfd_criu_restore_queue(p, (uint8_t __user *)args->priv_data,
2515 priv_offset, max_priv_data_size);
2519 case KFD_CRIU_OBJECT_TYPE_EVENT:
2520 ret = kfd_criu_restore_event(filep, p, (uint8_t __user *)args->priv_data,
2521 priv_offset, max_priv_data_size);
2525 case KFD_CRIU_OBJECT_TYPE_SVM_RANGE:
2526 ret = kfd_criu_restore_svm(p, (uint8_t __user *)args->priv_data,
2527 priv_offset, max_priv_data_size);
2532 pr_err("Invalid object type:%u at index:%d\n", object_type, i);
2541 static int criu_restore(struct file *filep,
2542 struct kfd_process *p,
2543 struct kfd_ioctl_criu_args *args)
2545 uint64_t priv_offset = 0;
2548 pr_debug("CRIU restore (num_devices:%u num_bos:%u num_objects:%u priv_data_size:%llu)\n",
2549 args->num_devices, args->num_bos, args->num_objects, args->priv_data_size);
2551 if (!args->bos || !args->devices || !args->priv_data || !args->priv_data_size ||
2552 !args->num_devices || !args->num_bos)
2555 mutex_lock(&p->mutex);
2558 * Set the process to evicted state to avoid running any new queues before all the memory
2559 * mappings are ready.
2561 ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_CRIU_RESTORE);
2565 /* Each function will adjust priv_offset based on how many bytes they consumed */
2566 ret = criu_restore_process(p, args, &priv_offset, args->priv_data_size);
2570 ret = criu_restore_devices(p, args, &priv_offset, args->priv_data_size);
2574 ret = criu_restore_bos(p, args, &priv_offset, args->priv_data_size);
2578 ret = criu_restore_objects(filep, p, args, &priv_offset, args->priv_data_size);
2582 if (priv_offset != args->priv_data_size) {
2583 pr_err("Invalid private data size\n");
2588 mutex_unlock(&p->mutex);
2590 pr_err("Failed to restore CRIU ret:%d\n", ret);
2592 pr_debug("CRIU restore successful\n");
2597 static int criu_unpause(struct file *filep,
2598 struct kfd_process *p,
2599 struct kfd_ioctl_criu_args *args)
2603 mutex_lock(&p->mutex);
2605 if (!p->queues_paused) {
2606 mutex_unlock(&p->mutex);
2610 ret = kfd_process_restore_queues(p);
2612 pr_err("Failed to unpause queues ret:%d\n", ret);
2614 p->queues_paused = false;
2616 mutex_unlock(&p->mutex);
2621 static int criu_resume(struct file *filep,
2622 struct kfd_process *p,
2623 struct kfd_ioctl_criu_args *args)
2625 struct kfd_process *target = NULL;
2626 struct pid *pid = NULL;
2629 pr_debug("Inside %s, target pid for criu restore: %d\n", __func__,
2632 pid = find_get_pid(args->pid);
2634 pr_err("Cannot find pid info for %i\n", args->pid);
2638 pr_debug("calling kfd_lookup_process_by_pid\n");
2639 target = kfd_lookup_process_by_pid(pid);
2644 pr_debug("Cannot find process info for %i\n", args->pid);
2648 mutex_lock(&target->mutex);
2649 ret = kfd_criu_resume_svm(target);
2651 pr_err("kfd_criu_resume_svm failed for %i\n", args->pid);
2655 ret = amdgpu_amdkfd_criu_resume(target->kgd_process_info);
2657 pr_err("amdgpu_amdkfd_criu_resume failed for %i\n", args->pid);
2660 mutex_unlock(&target->mutex);
2662 kfd_unref_process(target);
2666 static int criu_process_info(struct file *filep,
2667 struct kfd_process *p,
2668 struct kfd_ioctl_criu_args *args)
2672 mutex_lock(&p->mutex);
2675 pr_err("No pdd for given process\n");
2680 ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_CRIU_CHECKPOINT);
2684 p->queues_paused = true;
2686 args->pid = task_pid_nr_ns(p->lead_thread,
2687 task_active_pid_ns(p->lead_thread));
2689 ret = criu_get_process_object_info(p, &args->num_devices, &args->num_bos,
2690 &args->num_objects, &args->priv_data_size);
2694 dev_dbg(kfd_device, "Num of devices:%u bos:%u objects:%u priv_data_size:%lld\n",
2695 args->num_devices, args->num_bos, args->num_objects,
2696 args->priv_data_size);
2700 kfd_process_restore_queues(p);
2701 p->queues_paused = false;
2703 mutex_unlock(&p->mutex);
2707 static int kfd_ioctl_criu(struct file *filep, struct kfd_process *p, void *data)
2709 struct kfd_ioctl_criu_args *args = data;
2712 dev_dbg(kfd_device, "CRIU operation: %d\n", args->op);
2714 case KFD_CRIU_OP_PROCESS_INFO:
2715 ret = criu_process_info(filep, p, args);
2717 case KFD_CRIU_OP_CHECKPOINT:
2718 ret = criu_checkpoint(filep, p, args);
2720 case KFD_CRIU_OP_UNPAUSE:
2721 ret = criu_unpause(filep, p, args);
2723 case KFD_CRIU_OP_RESTORE:
2724 ret = criu_restore(filep, p, args);
2726 case KFD_CRIU_OP_RESUME:
2727 ret = criu_resume(filep, p, args);
2730 dev_dbg(kfd_device, "Unsupported CRIU operation:%d\n", args->op);
2736 dev_dbg(kfd_device, "CRIU operation:%d err:%d\n", args->op, ret);
2741 static int runtime_enable(struct kfd_process *p, uint64_t r_debug,
2742 bool enable_ttmp_setup)
2746 if (p->is_runtime_retry)
2749 if (p->runtime_info.runtime_state != DEBUG_RUNTIME_STATE_DISABLED)
2752 for (i = 0; i < p->n_pdds; i++) {
2753 struct kfd_process_device *pdd = p->pdds[i];
2755 if (pdd->qpd.queue_count)
2759 p->runtime_info.runtime_state = DEBUG_RUNTIME_STATE_ENABLED;
2760 p->runtime_info.r_debug = r_debug;
2761 p->runtime_info.ttmp_setup = enable_ttmp_setup;
2763 if (p->runtime_info.ttmp_setup) {
2764 for (i = 0; i < p->n_pdds; i++) {
2765 struct kfd_process_device *pdd = p->pdds[i];
2767 if (!kfd_dbg_is_rlc_restore_supported(pdd->dev)) {
2768 amdgpu_gfx_off_ctrl(pdd->dev->adev, false);
2769 pdd->dev->kfd2kgd->enable_debug_trap(
2772 pdd->dev->vm_info.last_vmid_kfd);
2773 } else if (kfd_dbg_is_per_vmid_supported(pdd->dev)) {
2774 pdd->spi_dbg_override = pdd->dev->kfd2kgd->enable_debug_trap(
2783 if (p->debug_trap_enabled) {
2784 if (!p->is_runtime_retry) {
2785 kfd_dbg_trap_activate(p);
2786 kfd_dbg_ev_raise(KFD_EC_MASK(EC_PROCESS_RUNTIME),
2787 p, NULL, 0, false, NULL, 0);
2790 mutex_unlock(&p->mutex);
2791 ret = down_interruptible(&p->runtime_enable_sema);
2792 mutex_lock(&p->mutex);
2794 p->is_runtime_retry = !!ret;
2800 static int runtime_disable(struct kfd_process *p)
2803 bool was_enabled = p->runtime_info.runtime_state == DEBUG_RUNTIME_STATE_ENABLED;
2805 p->runtime_info.runtime_state = DEBUG_RUNTIME_STATE_DISABLED;
2806 p->runtime_info.r_debug = 0;
2808 if (p->debug_trap_enabled) {
2810 kfd_dbg_trap_deactivate(p, false, 0);
2812 if (!p->is_runtime_retry)
2813 kfd_dbg_ev_raise(KFD_EC_MASK(EC_PROCESS_RUNTIME),
2814 p, NULL, 0, false, NULL, 0);
2816 mutex_unlock(&p->mutex);
2817 ret = down_interruptible(&p->runtime_enable_sema);
2818 mutex_lock(&p->mutex);
2820 p->is_runtime_retry = !!ret;
2825 if (was_enabled && p->runtime_info.ttmp_setup) {
2826 for (i = 0; i < p->n_pdds; i++) {
2827 struct kfd_process_device *pdd = p->pdds[i];
2829 if (!kfd_dbg_is_rlc_restore_supported(pdd->dev))
2830 amdgpu_gfx_off_ctrl(pdd->dev->adev, true);
2834 p->runtime_info.ttmp_setup = false;
2836 /* disable ttmp setup */
2837 for (i = 0; i < p->n_pdds; i++) {
2838 struct kfd_process_device *pdd = p->pdds[i];
2840 if (kfd_dbg_is_per_vmid_supported(pdd->dev)) {
2841 pdd->spi_dbg_override =
2842 pdd->dev->kfd2kgd->disable_debug_trap(
2845 pdd->dev->vm_info.last_vmid_kfd);
2847 if (!pdd->dev->kfd->shared_resources.enable_mes)
2848 debug_refresh_runlist(pdd->dev->dqm);
2850 kfd_dbg_set_mes_debug_mode(pdd);
2857 static int kfd_ioctl_runtime_enable(struct file *filep, struct kfd_process *p, void *data)
2859 struct kfd_ioctl_runtime_enable_args *args = data;
2862 mutex_lock(&p->mutex);
2864 if (args->mode_mask & KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK)
2865 r = runtime_enable(p, args->r_debug,
2866 !!(args->mode_mask & KFD_RUNTIME_ENABLE_MODE_TTMP_SAVE_MASK));
2868 r = runtime_disable(p);
2870 mutex_unlock(&p->mutex);
2875 static int kfd_ioctl_set_debug_trap(struct file *filep, struct kfd_process *p, void *data)
2877 struct kfd_ioctl_dbg_trap_args *args = data;
2878 struct task_struct *thread = NULL;
2879 struct mm_struct *mm = NULL;
2880 struct pid *pid = NULL;
2881 struct kfd_process *target = NULL;
2884 if (sched_policy == KFD_SCHED_POLICY_NO_HWS) {
2885 pr_err("Debugging does not support sched_policy %i", sched_policy);
2889 pid = find_get_pid(args->pid);
2891 pr_debug("Cannot find pid info for %i\n", args->pid);
2896 thread = get_pid_task(pid, PIDTYPE_PID);
2902 mm = get_task_mm(thread);
2908 if (args->op == KFD_IOC_DBG_TRAP_ENABLE) {
2909 bool create_process;
2912 create_process = thread && thread != current && ptrace_parent(thread) == current;
2915 target = create_process ? kfd_create_process(thread) :
2916 kfd_lookup_process_by_pid(pid);
2918 target = kfd_lookup_process_by_pid(pid);
2922 pr_debug("Cannot find process PID %i to debug\n", args->pid);
2927 /* Check if target is still PTRACED. */
2929 if (target != p && args->op != KFD_IOC_DBG_TRAP_DISABLE
2930 && ptrace_parent(target->lead_thread) != current) {
2931 pr_err("PID %i is not PTRACED and cannot be debugged\n", args->pid);
2939 mutex_lock(&target->mutex);
2941 if (args->op != KFD_IOC_DBG_TRAP_ENABLE && !target->debug_trap_enabled) {
2942 pr_err("PID %i not debug enabled for op %i\n", args->pid, args->op);
2947 if (target->runtime_info.runtime_state != DEBUG_RUNTIME_STATE_ENABLED &&
2948 (args->op == KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE ||
2949 args->op == KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE ||
2950 args->op == KFD_IOC_DBG_TRAP_SUSPEND_QUEUES ||
2951 args->op == KFD_IOC_DBG_TRAP_RESUME_QUEUES ||
2952 args->op == KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH ||
2953 args->op == KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH ||
2954 args->op == KFD_IOC_DBG_TRAP_SET_FLAGS)) {
2960 case KFD_IOC_DBG_TRAP_ENABLE:
2962 target->debugger_process = p;
2964 r = kfd_dbg_trap_enable(target,
2965 args->enable.dbg_fd,
2966 (void __user *)args->enable.rinfo_ptr,
2967 &args->enable.rinfo_size);
2969 target->exception_enable_mask = args->enable.exception_mask;
2971 pr_warn("Debug functions limited\n");
2973 case KFD_IOC_DBG_TRAP_DISABLE:
2974 r = kfd_dbg_trap_disable(target);
2976 case KFD_IOC_DBG_TRAP_SEND_RUNTIME_EVENT:
2977 r = kfd_dbg_send_exception_to_runtime(target,
2978 args->send_runtime_event.gpu_id,
2979 args->send_runtime_event.queue_id,
2980 args->send_runtime_event.exception_mask);
2982 case KFD_IOC_DBG_TRAP_SET_EXCEPTIONS_ENABLED:
2983 kfd_dbg_set_enabled_debug_exception_mask(target,
2984 args->set_exceptions_enabled.exception_mask);
2986 case KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE:
2987 case KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE:
2988 case KFD_IOC_DBG_TRAP_SUSPEND_QUEUES:
2989 case KFD_IOC_DBG_TRAP_RESUME_QUEUES:
2990 case KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH:
2991 case KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH:
2992 case KFD_IOC_DBG_TRAP_SET_FLAGS:
2993 case KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT:
2994 case KFD_IOC_DBG_TRAP_QUERY_EXCEPTION_INFO:
2995 case KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT:
2996 case KFD_IOC_DBG_TRAP_GET_DEVICE_SNAPSHOT:
2997 pr_warn("Debug op %i not supported yet\n", args->op);
3001 pr_err("Invalid option: %i\n", args->op);
3006 mutex_unlock(&target->mutex);
3010 put_task_struct(thread);
3019 kfd_unref_process(target);
3024 #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \
3025 [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \
3026 .cmd_drv = 0, .name = #ioctl}
3029 static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = {
3030 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_VERSION,
3031 kfd_ioctl_get_version, 0),
3033 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_QUEUE,
3034 kfd_ioctl_create_queue, 0),
3036 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_QUEUE,
3037 kfd_ioctl_destroy_queue, 0),
3039 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_MEMORY_POLICY,
3040 kfd_ioctl_set_memory_policy, 0),
3042 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_CLOCK_COUNTERS,
3043 kfd_ioctl_get_clock_counters, 0),
3045 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES,
3046 kfd_ioctl_get_process_apertures, 0),
3048 AMDKFD_IOCTL_DEF(AMDKFD_IOC_UPDATE_QUEUE,
3049 kfd_ioctl_update_queue, 0),
3051 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_EVENT,
3052 kfd_ioctl_create_event, 0),
3054 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_EVENT,
3055 kfd_ioctl_destroy_event, 0),
3057 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_EVENT,
3058 kfd_ioctl_set_event, 0),
3060 AMDKFD_IOCTL_DEF(AMDKFD_IOC_RESET_EVENT,
3061 kfd_ioctl_reset_event, 0),
3063 AMDKFD_IOCTL_DEF(AMDKFD_IOC_WAIT_EVENTS,
3064 kfd_ioctl_wait_events, 0),
3066 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_REGISTER_DEPRECATED,
3067 kfd_ioctl_dbg_register, 0),
3069 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_UNREGISTER_DEPRECATED,
3070 kfd_ioctl_dbg_unregister, 0),
3072 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_ADDRESS_WATCH_DEPRECATED,
3073 kfd_ioctl_dbg_address_watch, 0),
3075 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_WAVE_CONTROL_DEPRECATED,
3076 kfd_ioctl_dbg_wave_control, 0),
3078 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_SCRATCH_BACKING_VA,
3079 kfd_ioctl_set_scratch_backing_va, 0),
3081 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_TILE_CONFIG,
3082 kfd_ioctl_get_tile_config, 0),
3084 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_TRAP_HANDLER,
3085 kfd_ioctl_set_trap_handler, 0),
3087 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES_NEW,
3088 kfd_ioctl_get_process_apertures_new, 0),
3090 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ACQUIRE_VM,
3091 kfd_ioctl_acquire_vm, 0),
3093 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ALLOC_MEMORY_OF_GPU,
3094 kfd_ioctl_alloc_memory_of_gpu, 0),
3096 AMDKFD_IOCTL_DEF(AMDKFD_IOC_FREE_MEMORY_OF_GPU,
3097 kfd_ioctl_free_memory_of_gpu, 0),
3099 AMDKFD_IOCTL_DEF(AMDKFD_IOC_MAP_MEMORY_TO_GPU,
3100 kfd_ioctl_map_memory_to_gpu, 0),
3102 AMDKFD_IOCTL_DEF(AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU,
3103 kfd_ioctl_unmap_memory_from_gpu, 0),
3105 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_CU_MASK,
3106 kfd_ioctl_set_cu_mask, 0),
3108 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_QUEUE_WAVE_STATE,
3109 kfd_ioctl_get_queue_wave_state, 0),
3111 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_DMABUF_INFO,
3112 kfd_ioctl_get_dmabuf_info, 0),
3114 AMDKFD_IOCTL_DEF(AMDKFD_IOC_IMPORT_DMABUF,
3115 kfd_ioctl_import_dmabuf, 0),
3117 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ALLOC_QUEUE_GWS,
3118 kfd_ioctl_alloc_queue_gws, 0),
3120 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SMI_EVENTS,
3121 kfd_ioctl_smi_events, 0),
3123 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SVM, kfd_ioctl_svm, 0),
3125 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_XNACK_MODE,
3126 kfd_ioctl_set_xnack_mode, 0),
3128 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CRIU_OP,
3129 kfd_ioctl_criu, KFD_IOC_FLAG_CHECKPOINT_RESTORE),
3131 AMDKFD_IOCTL_DEF(AMDKFD_IOC_AVAILABLE_MEMORY,
3132 kfd_ioctl_get_available_memory, 0),
3134 AMDKFD_IOCTL_DEF(AMDKFD_IOC_EXPORT_DMABUF,
3135 kfd_ioctl_export_dmabuf, 0),
3137 AMDKFD_IOCTL_DEF(AMDKFD_IOC_RUNTIME_ENABLE,
3138 kfd_ioctl_runtime_enable, 0),
3140 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_TRAP,
3141 kfd_ioctl_set_debug_trap, 0),
3144 #define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls)
3146 static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
3148 struct kfd_process *process;
3149 amdkfd_ioctl_t *func;
3150 const struct amdkfd_ioctl_desc *ioctl = NULL;
3151 unsigned int nr = _IOC_NR(cmd);
3152 char stack_kdata[128];
3154 unsigned int usize, asize;
3155 int retcode = -EINVAL;
3156 bool ptrace_attached = false;
3158 if (nr >= AMDKFD_CORE_IOCTL_COUNT)
3161 if ((nr >= AMDKFD_COMMAND_START) && (nr < AMDKFD_COMMAND_END)) {
3164 ioctl = &amdkfd_ioctls[nr];
3166 amdkfd_size = _IOC_SIZE(ioctl->cmd);
3167 usize = asize = _IOC_SIZE(cmd);
3168 if (amdkfd_size > asize)
3169 asize = amdkfd_size;
3175 dev_dbg(kfd_device, "ioctl cmd 0x%x (#0x%x), arg 0x%lx\n", cmd, nr, arg);
3177 /* Get the process struct from the filep. Only the process
3178 * that opened /dev/kfd can use the file descriptor. Child
3179 * processes need to create their own KFD device context.
3181 process = filep->private_data;
3184 if ((ioctl->flags & KFD_IOC_FLAG_CHECKPOINT_RESTORE) &&
3185 ptrace_parent(process->lead_thread) == current)
3186 ptrace_attached = true;
3189 if (process->lead_thread != current->group_leader
3190 && !ptrace_attached) {
3191 dev_dbg(kfd_device, "Using KFD FD in wrong process\n");
3196 /* Do not trust userspace, use our own definition */
3199 if (unlikely(!func)) {
3200 dev_dbg(kfd_device, "no function\n");
3206 * Versions of docker shipped in Ubuntu 18.xx and 20.xx do not support
3207 * CAP_CHECKPOINT_RESTORE, so we also allow access if CAP_SYS_ADMIN as CAP_SYS_ADMIN is a
3208 * more priviledged access.
3210 if (unlikely(ioctl->flags & KFD_IOC_FLAG_CHECKPOINT_RESTORE)) {
3211 if (!capable(CAP_CHECKPOINT_RESTORE) &&
3212 !capable(CAP_SYS_ADMIN)) {
3218 if (cmd & (IOC_IN | IOC_OUT)) {
3219 if (asize <= sizeof(stack_kdata)) {
3220 kdata = stack_kdata;
3222 kdata = kmalloc(asize, GFP_KERNEL);
3229 memset(kdata + usize, 0, asize - usize);
3233 if (copy_from_user(kdata, (void __user *)arg, usize) != 0) {
3237 } else if (cmd & IOC_OUT) {
3238 memset(kdata, 0, usize);
3241 retcode = func(filep, process, kdata);
3244 if (copy_to_user((void __user *)arg, kdata, usize) != 0)
3249 dev_dbg(kfd_device, "invalid ioctl: pid=%d, cmd=0x%02x, nr=0x%02x\n",
3250 task_pid_nr(current), cmd, nr);
3252 if (kdata != stack_kdata)
3256 dev_dbg(kfd_device, "ioctl cmd (#0x%x), arg 0x%lx, ret = %d\n",
3262 static int kfd_mmio_mmap(struct kfd_node *dev, struct kfd_process *process,
3263 struct vm_area_struct *vma)
3265 phys_addr_t address;
3267 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
3270 address = dev->adev->rmmio_remap.bus_addr;
3272 vm_flags_set(vma, VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_NORESERVE |
3273 VM_DONTDUMP | VM_PFNMAP);
3275 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
3277 pr_debug("pasid 0x%x mapping mmio page\n"
3278 " target user address == 0x%08llX\n"
3279 " physical address == 0x%08llX\n"
3280 " vm_flags == 0x%04lX\n"
3281 " size == 0x%04lX\n",
3282 process->pasid, (unsigned long long) vma->vm_start,
3283 address, vma->vm_flags, PAGE_SIZE);
3285 return io_remap_pfn_range(vma,
3287 address >> PAGE_SHIFT,
3293 static int kfd_mmap(struct file *filp, struct vm_area_struct *vma)
3295 struct kfd_process *process;
3296 struct kfd_node *dev = NULL;
3297 unsigned long mmap_offset;
3298 unsigned int gpu_id;
3300 process = kfd_get_process(current);
3301 if (IS_ERR(process))
3302 return PTR_ERR(process);
3304 mmap_offset = vma->vm_pgoff << PAGE_SHIFT;
3305 gpu_id = KFD_MMAP_GET_GPU_ID(mmap_offset);
3307 dev = kfd_device_by_id(gpu_id);
3309 switch (mmap_offset & KFD_MMAP_TYPE_MASK) {
3310 case KFD_MMAP_TYPE_DOORBELL:
3313 return kfd_doorbell_mmap(dev, process, vma);
3315 case KFD_MMAP_TYPE_EVENTS:
3316 return kfd_event_mmap(process, vma);
3318 case KFD_MMAP_TYPE_RESERVED_MEM:
3321 return kfd_reserved_mem_mmap(dev, process, vma);
3322 case KFD_MMAP_TYPE_MMIO:
3325 return kfd_mmio_mmap(dev, process, vma);