1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/device.h>
25 #include <linux/export.h>
26 #include <linux/err.h>
28 #include <linux/file.h>
29 #include <linux/sched.h>
30 #include <linux/slab.h>
31 #include <linux/uaccess.h>
32 #include <linux/compat.h>
33 #include <uapi/linux/kfd_ioctl.h>
34 #include <linux/time.h>
36 #include <linux/mman.h>
37 #include <linux/ptrace.h>
38 #include <linux/dma-buf.h>
39 #include <linux/fdtable.h>
40 #include <linux/processor.h>
42 #include "kfd_device_queue_manager.h"
44 #include "amdgpu_amdkfd.h"
45 #include "kfd_smi_events.h"
46 #include "amdgpu_dma_buf.h"
48 static long kfd_ioctl(struct file *, unsigned int, unsigned long);
49 static int kfd_open(struct inode *, struct file *);
50 static int kfd_release(struct inode *, struct file *);
51 static int kfd_mmap(struct file *, struct vm_area_struct *);
53 static const char kfd_dev_name[] = "kfd";
55 static const struct file_operations kfd_fops = {
57 .unlocked_ioctl = kfd_ioctl,
58 .compat_ioctl = compat_ptr_ioctl,
60 .release = kfd_release,
64 static int kfd_char_dev_major = -1;
65 static struct class *kfd_class;
66 struct device *kfd_device;
68 static inline struct kfd_process_device *kfd_lock_pdd_by_id(struct kfd_process *p, __u32 gpu_id)
70 struct kfd_process_device *pdd;
72 mutex_lock(&p->mutex);
73 pdd = kfd_process_device_data_by_id(p, gpu_id);
78 mutex_unlock(&p->mutex);
82 static inline void kfd_unlock_pdd(struct kfd_process_device *pdd)
84 mutex_unlock(&pdd->process->mutex);
87 int kfd_chardev_init(void)
91 kfd_char_dev_major = register_chrdev(0, kfd_dev_name, &kfd_fops);
92 err = kfd_char_dev_major;
94 goto err_register_chrdev;
96 kfd_class = class_create(THIS_MODULE, kfd_dev_name);
97 err = PTR_ERR(kfd_class);
98 if (IS_ERR(kfd_class))
99 goto err_class_create;
101 kfd_device = device_create(kfd_class, NULL,
102 MKDEV(kfd_char_dev_major, 0),
104 err = PTR_ERR(kfd_device);
105 if (IS_ERR(kfd_device))
106 goto err_device_create;
111 class_destroy(kfd_class);
113 unregister_chrdev(kfd_char_dev_major, kfd_dev_name);
118 void kfd_chardev_exit(void)
120 device_destroy(kfd_class, MKDEV(kfd_char_dev_major, 0));
121 class_destroy(kfd_class);
122 unregister_chrdev(kfd_char_dev_major, kfd_dev_name);
127 static int kfd_open(struct inode *inode, struct file *filep)
129 struct kfd_process *process;
130 bool is_32bit_user_mode;
132 if (iminor(inode) != 0)
135 is_32bit_user_mode = in_compat_syscall();
137 if (is_32bit_user_mode) {
139 "Process %d (32-bit) failed to open /dev/kfd\n"
140 "32-bit processes are not supported by amdkfd\n",
145 process = kfd_create_process(filep);
147 return PTR_ERR(process);
149 if (kfd_is_locked()) {
150 dev_dbg(kfd_device, "kfd is locked!\n"
151 "process %d unreferenced", process->pasid);
152 kfd_unref_process(process);
156 /* filep now owns the reference returned by kfd_create_process */
157 filep->private_data = process;
159 dev_dbg(kfd_device, "process %d opened, compat mode (32 bit) - %d\n",
160 process->pasid, process->is_32bit_user_mode);
165 static int kfd_release(struct inode *inode, struct file *filep)
167 struct kfd_process *process = filep->private_data;
170 kfd_unref_process(process);
175 static int kfd_ioctl_get_version(struct file *filep, struct kfd_process *p,
178 struct kfd_ioctl_get_version_args *args = data;
180 args->major_version = KFD_IOCTL_MAJOR_VERSION;
181 args->minor_version = KFD_IOCTL_MINOR_VERSION;
186 static int set_queue_properties_from_user(struct queue_properties *q_properties,
187 struct kfd_ioctl_create_queue_args *args)
189 if (args->queue_percentage > KFD_MAX_QUEUE_PERCENTAGE) {
190 pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n");
194 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) {
195 pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n");
199 if ((args->ring_base_address) &&
200 (!access_ok((const void __user *) args->ring_base_address,
201 sizeof(uint64_t)))) {
202 pr_err("Can't access ring base address\n");
206 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) {
207 pr_err("Ring size must be a power of 2 or 0\n");
211 if (!access_ok((const void __user *) args->read_pointer_address,
213 pr_err("Can't access read pointer\n");
217 if (!access_ok((const void __user *) args->write_pointer_address,
219 pr_err("Can't access write pointer\n");
223 if (args->eop_buffer_address &&
224 !access_ok((const void __user *) args->eop_buffer_address,
226 pr_debug("Can't access eop buffer");
230 if (args->ctx_save_restore_address &&
231 !access_ok((const void __user *) args->ctx_save_restore_address,
233 pr_debug("Can't access ctx save restore buffer");
237 q_properties->is_interop = false;
238 q_properties->is_gws = false;
239 q_properties->queue_percent = args->queue_percentage;
240 q_properties->priority = args->queue_priority;
241 q_properties->queue_address = args->ring_base_address;
242 q_properties->queue_size = args->ring_size;
243 q_properties->read_ptr = (uint32_t *) args->read_pointer_address;
244 q_properties->write_ptr = (uint32_t *) args->write_pointer_address;
245 q_properties->eop_ring_buffer_address = args->eop_buffer_address;
246 q_properties->eop_ring_buffer_size = args->eop_buffer_size;
247 q_properties->ctx_save_restore_area_address =
248 args->ctx_save_restore_address;
249 q_properties->ctx_save_restore_area_size = args->ctx_save_restore_size;
250 q_properties->ctl_stack_size = args->ctl_stack_size;
251 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE ||
252 args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL)
253 q_properties->type = KFD_QUEUE_TYPE_COMPUTE;
254 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA)
255 q_properties->type = KFD_QUEUE_TYPE_SDMA;
256 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA_XGMI)
257 q_properties->type = KFD_QUEUE_TYPE_SDMA_XGMI;
261 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL)
262 q_properties->format = KFD_QUEUE_FORMAT_AQL;
264 q_properties->format = KFD_QUEUE_FORMAT_PM4;
266 pr_debug("Queue Percentage: %d, %d\n",
267 q_properties->queue_percent, args->queue_percentage);
269 pr_debug("Queue Priority: %d, %d\n",
270 q_properties->priority, args->queue_priority);
272 pr_debug("Queue Address: 0x%llX, 0x%llX\n",
273 q_properties->queue_address, args->ring_base_address);
275 pr_debug("Queue Size: 0x%llX, %u\n",
276 q_properties->queue_size, args->ring_size);
278 pr_debug("Queue r/w Pointers: %px, %px\n",
279 q_properties->read_ptr,
280 q_properties->write_ptr);
282 pr_debug("Queue Format: %d\n", q_properties->format);
284 pr_debug("Queue EOP: 0x%llX\n", q_properties->eop_ring_buffer_address);
286 pr_debug("Queue CTX save area: 0x%llX\n",
287 q_properties->ctx_save_restore_area_address);
292 static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p,
295 struct kfd_ioctl_create_queue_args *args = data;
298 unsigned int queue_id;
299 struct kfd_process_device *pdd;
300 struct queue_properties q_properties;
301 uint32_t doorbell_offset_in_process = 0;
302 struct amdgpu_bo *wptr_bo = NULL;
304 memset(&q_properties, 0, sizeof(struct queue_properties));
306 pr_debug("Creating queue ioctl\n");
308 err = set_queue_properties_from_user(&q_properties, args);
312 pr_debug("Looking for gpu id 0x%x\n", args->gpu_id);
314 mutex_lock(&p->mutex);
316 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
318 pr_debug("Could not find gpu id 0x%x\n", args->gpu_id);
324 pdd = kfd_bind_process_to_device(dev, p);
327 goto err_bind_process;
330 if (!pdd->doorbell_index &&
331 kfd_alloc_process_doorbells(dev, &pdd->doorbell_index) < 0) {
333 goto err_alloc_doorbells;
336 /* Starting with GFX11, wptr BOs must be mapped to GART for MES to determine work
337 * on unmapped queues for usermode queue oversubscription (no aggregated doorbell)
339 if (dev->shared_resources.enable_mes &&
340 ((dev->adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK)
341 >> AMDGPU_MES_API_VERSION_SHIFT) >= 2) {
342 struct amdgpu_bo_va_mapping *wptr_mapping;
343 struct amdgpu_vm *wptr_vm;
345 wptr_vm = drm_priv_to_vm(pdd->drm_priv);
346 err = amdgpu_bo_reserve(wptr_vm->root.bo, false);
348 goto err_wptr_map_gart;
350 wptr_mapping = amdgpu_vm_bo_lookup_mapping(
351 wptr_vm, args->write_pointer_address >> PAGE_SHIFT);
352 amdgpu_bo_unreserve(wptr_vm->root.bo);
354 pr_err("Failed to lookup wptr bo\n");
356 goto err_wptr_map_gart;
359 wptr_bo = wptr_mapping->bo_va->base.bo;
360 if (wptr_bo->tbo.base.size > PAGE_SIZE) {
361 pr_err("Requested GART mapping for wptr bo larger than one page\n");
363 goto err_wptr_map_gart;
366 err = amdgpu_amdkfd_map_gtt_bo_to_gart(dev->adev, wptr_bo);
368 pr_err("Failed to map wptr bo to GART\n");
369 goto err_wptr_map_gart;
373 pr_debug("Creating queue for PASID 0x%x on gpu 0x%x\n",
377 err = pqm_create_queue(&p->pqm, dev, filep, &q_properties, &queue_id, wptr_bo,
378 NULL, NULL, NULL, &doorbell_offset_in_process);
380 goto err_create_queue;
382 args->queue_id = queue_id;
385 /* Return gpu_id as doorbell offset for mmap usage */
386 args->doorbell_offset = KFD_MMAP_TYPE_DOORBELL;
387 args->doorbell_offset |= KFD_MMAP_GPU_ID(args->gpu_id);
388 if (KFD_IS_SOC15(dev))
389 /* On SOC15 ASICs, include the doorbell offset within the
390 * process doorbell frame, which is 2 pages.
392 args->doorbell_offset |= doorbell_offset_in_process;
394 mutex_unlock(&p->mutex);
396 pr_debug("Queue id %d was created successfully\n", args->queue_id);
398 pr_debug("Ring buffer address == 0x%016llX\n",
399 args->ring_base_address);
401 pr_debug("Read ptr address == 0x%016llX\n",
402 args->read_pointer_address);
404 pr_debug("Write ptr address == 0x%016llX\n",
405 args->write_pointer_address);
411 amdgpu_amdkfd_free_gtt_mem(dev->adev, wptr_bo);
416 mutex_unlock(&p->mutex);
420 static int kfd_ioctl_destroy_queue(struct file *filp, struct kfd_process *p,
424 struct kfd_ioctl_destroy_queue_args *args = data;
426 pr_debug("Destroying queue id %d for pasid 0x%x\n",
430 mutex_lock(&p->mutex);
432 retval = pqm_destroy_queue(&p->pqm, args->queue_id);
434 mutex_unlock(&p->mutex);
438 static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p,
442 struct kfd_ioctl_update_queue_args *args = data;
443 struct queue_properties properties;
445 if (args->queue_percentage > KFD_MAX_QUEUE_PERCENTAGE) {
446 pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n");
450 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) {
451 pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n");
455 if ((args->ring_base_address) &&
456 (!access_ok((const void __user *) args->ring_base_address,
457 sizeof(uint64_t)))) {
458 pr_err("Can't access ring base address\n");
462 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) {
463 pr_err("Ring size must be a power of 2 or 0\n");
467 properties.queue_address = args->ring_base_address;
468 properties.queue_size = args->ring_size;
469 properties.queue_percent = args->queue_percentage;
470 properties.priority = args->queue_priority;
472 pr_debug("Updating queue id %d for pasid 0x%x\n",
473 args->queue_id, p->pasid);
475 mutex_lock(&p->mutex);
477 retval = pqm_update_queue_properties(&p->pqm, args->queue_id, &properties);
479 mutex_unlock(&p->mutex);
484 static int kfd_ioctl_set_cu_mask(struct file *filp, struct kfd_process *p,
488 const int max_num_cus = 1024;
489 struct kfd_ioctl_set_cu_mask_args *args = data;
490 struct mqd_update_info minfo = {0};
491 uint32_t __user *cu_mask_ptr = (uint32_t __user *)args->cu_mask_ptr;
492 size_t cu_mask_size = sizeof(uint32_t) * (args->num_cu_mask / 32);
494 if ((args->num_cu_mask % 32) != 0) {
495 pr_debug("num_cu_mask 0x%x must be a multiple of 32",
500 minfo.cu_mask.count = args->num_cu_mask;
501 if (minfo.cu_mask.count == 0) {
502 pr_debug("CU mask cannot be 0");
506 /* To prevent an unreasonably large CU mask size, set an arbitrary
507 * limit of max_num_cus bits. We can then just drop any CU mask bits
508 * past max_num_cus bits and just use the first max_num_cus bits.
510 if (minfo.cu_mask.count > max_num_cus) {
511 pr_debug("CU mask cannot be greater than 1024 bits");
512 minfo.cu_mask.count = max_num_cus;
513 cu_mask_size = sizeof(uint32_t) * (max_num_cus/32);
516 minfo.cu_mask.ptr = kzalloc(cu_mask_size, GFP_KERNEL);
517 if (!minfo.cu_mask.ptr)
520 retval = copy_from_user(minfo.cu_mask.ptr, cu_mask_ptr, cu_mask_size);
522 pr_debug("Could not copy CU mask from userspace");
527 minfo.update_flag = UPDATE_FLAG_CU_MASK;
529 mutex_lock(&p->mutex);
531 retval = pqm_update_mqd(&p->pqm, args->queue_id, &minfo);
533 mutex_unlock(&p->mutex);
536 kfree(minfo.cu_mask.ptr);
540 static int kfd_ioctl_get_queue_wave_state(struct file *filep,
541 struct kfd_process *p, void *data)
543 struct kfd_ioctl_get_queue_wave_state_args *args = data;
546 mutex_lock(&p->mutex);
548 r = pqm_get_wave_state(&p->pqm, args->queue_id,
549 (void __user *)args->ctl_stack_address,
550 &args->ctl_stack_used_size,
551 &args->save_area_used_size);
553 mutex_unlock(&p->mutex);
558 static int kfd_ioctl_set_memory_policy(struct file *filep,
559 struct kfd_process *p, void *data)
561 struct kfd_ioctl_set_memory_policy_args *args = data;
563 struct kfd_process_device *pdd;
564 enum cache_policy default_policy, alternate_policy;
566 if (args->default_policy != KFD_IOC_CACHE_POLICY_COHERENT
567 && args->default_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) {
571 if (args->alternate_policy != KFD_IOC_CACHE_POLICY_COHERENT
572 && args->alternate_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) {
576 mutex_lock(&p->mutex);
577 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
579 pr_debug("Could not find gpu id 0x%x\n", args->gpu_id);
584 pdd = kfd_bind_process_to_device(pdd->dev, p);
590 default_policy = (args->default_policy == KFD_IOC_CACHE_POLICY_COHERENT)
591 ? cache_policy_coherent : cache_policy_noncoherent;
594 (args->alternate_policy == KFD_IOC_CACHE_POLICY_COHERENT)
595 ? cache_policy_coherent : cache_policy_noncoherent;
597 if (!pdd->dev->dqm->ops.set_cache_memory_policy(pdd->dev->dqm,
601 (void __user *)args->alternate_aperture_base,
602 args->alternate_aperture_size))
607 mutex_unlock(&p->mutex);
612 static int kfd_ioctl_set_trap_handler(struct file *filep,
613 struct kfd_process *p, void *data)
615 struct kfd_ioctl_set_trap_handler_args *args = data;
617 struct kfd_process_device *pdd;
619 mutex_lock(&p->mutex);
621 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
627 pdd = kfd_bind_process_to_device(pdd->dev, p);
633 kfd_process_set_trap_handler(&pdd->qpd, args->tba_addr, args->tma_addr);
637 mutex_unlock(&p->mutex);
642 static int kfd_ioctl_dbg_register(struct file *filep,
643 struct kfd_process *p, void *data)
648 static int kfd_ioctl_dbg_unregister(struct file *filep,
649 struct kfd_process *p, void *data)
654 static int kfd_ioctl_dbg_address_watch(struct file *filep,
655 struct kfd_process *p, void *data)
660 /* Parse and generate fixed size data structure for wave control */
661 static int kfd_ioctl_dbg_wave_control(struct file *filep,
662 struct kfd_process *p, void *data)
667 static int kfd_ioctl_get_clock_counters(struct file *filep,
668 struct kfd_process *p, void *data)
670 struct kfd_ioctl_get_clock_counters_args *args = data;
671 struct kfd_process_device *pdd;
673 mutex_lock(&p->mutex);
674 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
675 mutex_unlock(&p->mutex);
677 /* Reading GPU clock counter from KGD */
678 args->gpu_clock_counter = amdgpu_amdkfd_get_gpu_clock_counter(pdd->dev->adev);
680 /* Node without GPU resource */
681 args->gpu_clock_counter = 0;
683 /* No access to rdtsc. Using raw monotonic time */
684 args->cpu_clock_counter = ktime_get_raw_ns();
685 args->system_clock_counter = ktime_get_boottime_ns();
687 /* Since the counter is in nano-seconds we use 1GHz frequency */
688 args->system_clock_freq = 1000000000;
694 static int kfd_ioctl_get_process_apertures(struct file *filp,
695 struct kfd_process *p, void *data)
697 struct kfd_ioctl_get_process_apertures_args *args = data;
698 struct kfd_process_device_apertures *pAperture;
701 dev_dbg(kfd_device, "get apertures for PASID 0x%x", p->pasid);
703 args->num_of_nodes = 0;
705 mutex_lock(&p->mutex);
706 /* Run over all pdd of the process */
707 for (i = 0; i < p->n_pdds; i++) {
708 struct kfd_process_device *pdd = p->pdds[i];
711 &args->process_apertures[args->num_of_nodes];
712 pAperture->gpu_id = pdd->dev->id;
713 pAperture->lds_base = pdd->lds_base;
714 pAperture->lds_limit = pdd->lds_limit;
715 pAperture->gpuvm_base = pdd->gpuvm_base;
716 pAperture->gpuvm_limit = pdd->gpuvm_limit;
717 pAperture->scratch_base = pdd->scratch_base;
718 pAperture->scratch_limit = pdd->scratch_limit;
721 "node id %u\n", args->num_of_nodes);
723 "gpu id %u\n", pdd->dev->id);
725 "lds_base %llX\n", pdd->lds_base);
727 "lds_limit %llX\n", pdd->lds_limit);
729 "gpuvm_base %llX\n", pdd->gpuvm_base);
731 "gpuvm_limit %llX\n", pdd->gpuvm_limit);
733 "scratch_base %llX\n", pdd->scratch_base);
735 "scratch_limit %llX\n", pdd->scratch_limit);
737 if (++args->num_of_nodes >= NUM_OF_SUPPORTED_GPUS)
740 mutex_unlock(&p->mutex);
745 static int kfd_ioctl_get_process_apertures_new(struct file *filp,
746 struct kfd_process *p, void *data)
748 struct kfd_ioctl_get_process_apertures_new_args *args = data;
749 struct kfd_process_device_apertures *pa;
753 dev_dbg(kfd_device, "get apertures for PASID 0x%x", p->pasid);
755 if (args->num_of_nodes == 0) {
756 /* Return number of nodes, so that user space can alloacate
759 mutex_lock(&p->mutex);
760 args->num_of_nodes = p->n_pdds;
764 /* Fill in process-aperture information for all available
765 * nodes, but not more than args->num_of_nodes as that is
766 * the amount of memory allocated by user
768 pa = kzalloc((sizeof(struct kfd_process_device_apertures) *
769 args->num_of_nodes), GFP_KERNEL);
773 mutex_lock(&p->mutex);
776 args->num_of_nodes = 0;
781 /* Run over all pdd of the process */
782 for (i = 0; i < min(p->n_pdds, args->num_of_nodes); i++) {
783 struct kfd_process_device *pdd = p->pdds[i];
785 pa[i].gpu_id = pdd->dev->id;
786 pa[i].lds_base = pdd->lds_base;
787 pa[i].lds_limit = pdd->lds_limit;
788 pa[i].gpuvm_base = pdd->gpuvm_base;
789 pa[i].gpuvm_limit = pdd->gpuvm_limit;
790 pa[i].scratch_base = pdd->scratch_base;
791 pa[i].scratch_limit = pdd->scratch_limit;
794 "gpu id %u\n", pdd->dev->id);
796 "lds_base %llX\n", pdd->lds_base);
798 "lds_limit %llX\n", pdd->lds_limit);
800 "gpuvm_base %llX\n", pdd->gpuvm_base);
802 "gpuvm_limit %llX\n", pdd->gpuvm_limit);
804 "scratch_base %llX\n", pdd->scratch_base);
806 "scratch_limit %llX\n", pdd->scratch_limit);
808 mutex_unlock(&p->mutex);
810 args->num_of_nodes = i;
812 (void __user *)args->kfd_process_device_apertures_ptr,
814 (i * sizeof(struct kfd_process_device_apertures)));
816 return ret ? -EFAULT : 0;
819 mutex_unlock(&p->mutex);
823 static int kfd_ioctl_create_event(struct file *filp, struct kfd_process *p,
826 struct kfd_ioctl_create_event_args *args = data;
829 /* For dGPUs the event page is allocated in user mode. The
830 * handle is passed to KFD with the first call to this IOCTL
831 * through the event_page_offset field.
833 if (args->event_page_offset) {
834 mutex_lock(&p->mutex);
835 err = kfd_kmap_event_page(p, args->event_page_offset);
836 mutex_unlock(&p->mutex);
841 err = kfd_event_create(filp, p, args->event_type,
842 args->auto_reset != 0, args->node_id,
843 &args->event_id, &args->event_trigger_data,
844 &args->event_page_offset,
845 &args->event_slot_index);
847 pr_debug("Created event (id:0x%08x) (%s)\n", args->event_id, __func__);
851 static int kfd_ioctl_destroy_event(struct file *filp, struct kfd_process *p,
854 struct kfd_ioctl_destroy_event_args *args = data;
856 return kfd_event_destroy(p, args->event_id);
859 static int kfd_ioctl_set_event(struct file *filp, struct kfd_process *p,
862 struct kfd_ioctl_set_event_args *args = data;
864 return kfd_set_event(p, args->event_id);
867 static int kfd_ioctl_reset_event(struct file *filp, struct kfd_process *p,
870 struct kfd_ioctl_reset_event_args *args = data;
872 return kfd_reset_event(p, args->event_id);
875 static int kfd_ioctl_wait_events(struct file *filp, struct kfd_process *p,
878 struct kfd_ioctl_wait_events_args *args = data;
880 return kfd_wait_on_events(p, args->num_events,
881 (void __user *)args->events_ptr,
882 (args->wait_for_all != 0),
883 &args->timeout, &args->wait_result);
885 static int kfd_ioctl_set_scratch_backing_va(struct file *filep,
886 struct kfd_process *p, void *data)
888 struct kfd_ioctl_set_scratch_backing_va_args *args = data;
889 struct kfd_process_device *pdd;
893 mutex_lock(&p->mutex);
894 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
901 pdd = kfd_bind_process_to_device(dev, p);
904 goto bind_process_to_device_fail;
907 pdd->qpd.sh_hidden_private_base = args->va_addr;
909 mutex_unlock(&p->mutex);
911 if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS &&
912 pdd->qpd.vmid != 0 && dev->kfd2kgd->set_scratch_backing_va)
913 dev->kfd2kgd->set_scratch_backing_va(
914 dev->adev, args->va_addr, pdd->qpd.vmid);
918 bind_process_to_device_fail:
920 mutex_unlock(&p->mutex);
924 static int kfd_ioctl_get_tile_config(struct file *filep,
925 struct kfd_process *p, void *data)
927 struct kfd_ioctl_get_tile_config_args *args = data;
928 struct kfd_process_device *pdd;
929 struct tile_config config;
932 mutex_lock(&p->mutex);
933 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
934 mutex_unlock(&p->mutex);
938 amdgpu_amdkfd_get_tile_config(pdd->dev->adev, &config);
940 args->gb_addr_config = config.gb_addr_config;
941 args->num_banks = config.num_banks;
942 args->num_ranks = config.num_ranks;
944 if (args->num_tile_configs > config.num_tile_configs)
945 args->num_tile_configs = config.num_tile_configs;
946 err = copy_to_user((void __user *)args->tile_config_ptr,
947 config.tile_config_ptr,
948 args->num_tile_configs * sizeof(uint32_t));
950 args->num_tile_configs = 0;
954 if (args->num_macro_tile_configs > config.num_macro_tile_configs)
955 args->num_macro_tile_configs =
956 config.num_macro_tile_configs;
957 err = copy_to_user((void __user *)args->macro_tile_config_ptr,
958 config.macro_tile_config_ptr,
959 args->num_macro_tile_configs * sizeof(uint32_t));
961 args->num_macro_tile_configs = 0;
968 static int kfd_ioctl_acquire_vm(struct file *filep, struct kfd_process *p,
971 struct kfd_ioctl_acquire_vm_args *args = data;
972 struct kfd_process_device *pdd;
973 struct file *drm_file;
976 drm_file = fget(args->drm_fd);
980 mutex_lock(&p->mutex);
981 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
988 ret = pdd->drm_file == drm_file ? 0 : -EBUSY;
992 ret = kfd_process_device_init_vm(pdd, drm_file);
996 /* On success, the PDD keeps the drm_file reference */
997 mutex_unlock(&p->mutex);
1004 mutex_unlock(&p->mutex);
1009 bool kfd_dev_is_large_bar(struct kfd_dev *dev)
1011 if (debug_largebar) {
1012 pr_debug("Simulate large-bar allocation on non large-bar machine\n");
1016 if (dev->use_iommu_v2)
1019 if (dev->local_mem_info.local_mem_size_private == 0 &&
1020 dev->local_mem_info.local_mem_size_public > 0)
1025 static int kfd_ioctl_get_available_memory(struct file *filep,
1026 struct kfd_process *p, void *data)
1028 struct kfd_ioctl_get_available_memory_args *args = data;
1029 struct kfd_process_device *pdd = kfd_lock_pdd_by_id(p, args->gpu_id);
1033 args->available = amdgpu_amdkfd_get_available_memory(pdd->dev->adev);
1034 kfd_unlock_pdd(pdd);
1038 static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep,
1039 struct kfd_process *p, void *data)
1041 struct kfd_ioctl_alloc_memory_of_gpu_args *args = data;
1042 struct kfd_process_device *pdd;
1044 struct kfd_dev *dev;
1047 uint64_t offset = args->mmap_offset;
1048 uint32_t flags = args->flags;
1050 if (args->size == 0)
1053 #if IS_ENABLED(CONFIG_HSA_AMD_SVM)
1054 /* Flush pending deferred work to avoid racing with deferred actions
1055 * from previous memory map changes (e.g. munmap).
1057 svm_range_list_lock_and_flush_work(&p->svms, current->mm);
1058 mutex_lock(&p->svms.lock);
1059 mmap_write_unlock(current->mm);
1060 if (interval_tree_iter_first(&p->svms.objects,
1061 args->va_addr >> PAGE_SHIFT,
1062 (args->va_addr + args->size - 1) >> PAGE_SHIFT)) {
1063 pr_err("Address: 0x%llx already allocated by SVM\n",
1065 mutex_unlock(&p->svms.lock);
1069 /* When register user buffer check if it has been registered by svm by
1070 * buffer cpu virtual address.
1072 if ((flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) &&
1073 interval_tree_iter_first(&p->svms.objects,
1074 args->mmap_offset >> PAGE_SHIFT,
1075 (args->mmap_offset + args->size - 1) >> PAGE_SHIFT)) {
1076 pr_err("User Buffer Address: 0x%llx already allocated by SVM\n",
1078 mutex_unlock(&p->svms.lock);
1082 mutex_unlock(&p->svms.lock);
1084 mutex_lock(&p->mutex);
1085 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
1093 if ((flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) &&
1094 (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) &&
1095 !kfd_dev_is_large_bar(dev)) {
1096 pr_err("Alloc host visible vram on small bar is not allowed\n");
1101 pdd = kfd_bind_process_to_device(dev, p);
1107 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) {
1108 if (args->size != kfd_doorbell_process_slice(dev)) {
1112 offset = kfd_get_process_doorbells(pdd);
1117 } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) {
1118 if (args->size != PAGE_SIZE) {
1122 offset = dev->adev->rmmio_remap.bus_addr;
1129 err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
1130 dev->adev, args->va_addr, args->size,
1131 pdd->drm_priv, (struct kgd_mem **) &mem, &offset,
1137 idr_handle = kfd_process_device_create_obj_handle(pdd, mem);
1138 if (idr_handle < 0) {
1143 /* Update the VRAM usage count */
1144 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
1145 uint64_t size = args->size;
1147 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM)
1149 WRITE_ONCE(pdd->vram_usage, pdd->vram_usage + PAGE_ALIGN(size));
1152 mutex_unlock(&p->mutex);
1154 args->handle = MAKE_HANDLE(args->gpu_id, idr_handle);
1155 args->mmap_offset = offset;
1157 /* MMIO is mapped through kfd device
1158 * Generate a kfd mmap offset
1160 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)
1161 args->mmap_offset = KFD_MMAP_TYPE_MMIO
1162 | KFD_MMAP_GPU_ID(args->gpu_id);
1167 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev, (struct kgd_mem *)mem,
1168 pdd->drm_priv, NULL);
1172 mutex_unlock(&p->mutex);
1176 static int kfd_ioctl_free_memory_of_gpu(struct file *filep,
1177 struct kfd_process *p, void *data)
1179 struct kfd_ioctl_free_memory_of_gpu_args *args = data;
1180 struct kfd_process_device *pdd;
1185 mutex_lock(&p->mutex);
1187 * Safeguard to prevent user space from freeing signal BO.
1188 * It will be freed at process termination.
1190 if (p->signal_handle && (p->signal_handle == args->handle)) {
1191 pr_err("Free signal BO is not allowed\n");
1196 pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle));
1198 pr_err("Process device data doesn't exist\n");
1203 mem = kfd_process_device_translate_handle(
1204 pdd, GET_IDR_HANDLE(args->handle));
1210 ret = amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev,
1211 (struct kgd_mem *)mem, pdd->drm_priv, &size);
1213 /* If freeing the buffer failed, leave the handle in place for
1214 * clean-up during process tear-down.
1217 kfd_process_device_remove_obj_handle(
1218 pdd, GET_IDR_HANDLE(args->handle));
1220 WRITE_ONCE(pdd->vram_usage, pdd->vram_usage - size);
1224 mutex_unlock(&p->mutex);
1228 static int kfd_ioctl_map_memory_to_gpu(struct file *filep,
1229 struct kfd_process *p, void *data)
1231 struct kfd_ioctl_map_memory_to_gpu_args *args = data;
1232 struct kfd_process_device *pdd, *peer_pdd;
1234 struct kfd_dev *dev;
1237 uint32_t *devices_arr = NULL;
1239 if (!args->n_devices) {
1240 pr_debug("Device IDs array empty\n");
1243 if (args->n_success > args->n_devices) {
1244 pr_debug("n_success exceeds n_devices\n");
1248 devices_arr = kmalloc_array(args->n_devices, sizeof(*devices_arr),
1253 err = copy_from_user(devices_arr,
1254 (void __user *)args->device_ids_array_ptr,
1255 args->n_devices * sizeof(*devices_arr));
1258 goto copy_from_user_failed;
1261 mutex_lock(&p->mutex);
1262 pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle));
1265 goto get_process_device_data_failed;
1269 pdd = kfd_bind_process_to_device(dev, p);
1272 goto bind_process_to_device_failed;
1275 mem = kfd_process_device_translate_handle(pdd,
1276 GET_IDR_HANDLE(args->handle));
1279 goto get_mem_obj_from_handle_failed;
1282 for (i = args->n_success; i < args->n_devices; i++) {
1283 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]);
1285 pr_debug("Getting device by id failed for 0x%x\n",
1288 goto get_mem_obj_from_handle_failed;
1291 peer_pdd = kfd_bind_process_to_device(peer_pdd->dev, p);
1292 if (IS_ERR(peer_pdd)) {
1293 err = PTR_ERR(peer_pdd);
1294 goto get_mem_obj_from_handle_failed;
1297 err = amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
1298 peer_pdd->dev->adev, (struct kgd_mem *)mem,
1299 peer_pdd->drm_priv);
1301 struct pci_dev *pdev = peer_pdd->dev->adev->pdev;
1303 dev_err(dev->adev->dev,
1304 "Failed to map peer:%04x:%02x:%02x.%d mem_domain:%d\n",
1305 pci_domain_nr(pdev->bus),
1307 PCI_SLOT(pdev->devfn),
1308 PCI_FUNC(pdev->devfn),
1309 ((struct kgd_mem *)mem)->domain);
1310 goto map_memory_to_gpu_failed;
1312 args->n_success = i+1;
1315 mutex_unlock(&p->mutex);
1317 err = amdgpu_amdkfd_gpuvm_sync_memory(dev->adev, (struct kgd_mem *) mem, true);
1319 pr_debug("Sync memory failed, wait interrupted by user signal\n");
1320 goto sync_memory_failed;
1323 /* Flush TLBs after waiting for the page table updates to complete */
1324 for (i = 0; i < args->n_devices; i++) {
1325 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]);
1326 if (WARN_ON_ONCE(!peer_pdd))
1328 kfd_flush_tlb(peer_pdd, TLB_FLUSH_LEGACY);
1334 get_process_device_data_failed:
1335 bind_process_to_device_failed:
1336 get_mem_obj_from_handle_failed:
1337 map_memory_to_gpu_failed:
1338 mutex_unlock(&p->mutex);
1339 copy_from_user_failed:
1346 static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep,
1347 struct kfd_process *p, void *data)
1349 struct kfd_ioctl_unmap_memory_from_gpu_args *args = data;
1350 struct kfd_process_device *pdd, *peer_pdd;
1353 uint32_t *devices_arr = NULL, i;
1355 if (!args->n_devices) {
1356 pr_debug("Device IDs array empty\n");
1359 if (args->n_success > args->n_devices) {
1360 pr_debug("n_success exceeds n_devices\n");
1364 devices_arr = kmalloc_array(args->n_devices, sizeof(*devices_arr),
1369 err = copy_from_user(devices_arr,
1370 (void __user *)args->device_ids_array_ptr,
1371 args->n_devices * sizeof(*devices_arr));
1374 goto copy_from_user_failed;
1377 mutex_lock(&p->mutex);
1378 pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle));
1381 goto bind_process_to_device_failed;
1384 mem = kfd_process_device_translate_handle(pdd,
1385 GET_IDR_HANDLE(args->handle));
1388 goto get_mem_obj_from_handle_failed;
1391 for (i = args->n_success; i < args->n_devices; i++) {
1392 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]);
1395 goto get_mem_obj_from_handle_failed;
1397 err = amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
1398 peer_pdd->dev->adev, (struct kgd_mem *)mem, peer_pdd->drm_priv);
1400 pr_err("Failed to unmap from gpu %d/%d\n",
1401 i, args->n_devices);
1402 goto unmap_memory_from_gpu_failed;
1404 args->n_success = i+1;
1406 mutex_unlock(&p->mutex);
1408 if (kfd_flush_tlb_after_unmap(pdd->dev)) {
1409 err = amdgpu_amdkfd_gpuvm_sync_memory(pdd->dev->adev,
1410 (struct kgd_mem *) mem, true);
1412 pr_debug("Sync memory failed, wait interrupted by user signal\n");
1413 goto sync_memory_failed;
1416 /* Flush TLBs after waiting for the page table updates to complete */
1417 for (i = 0; i < args->n_devices; i++) {
1418 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]);
1419 if (WARN_ON_ONCE(!peer_pdd))
1421 kfd_flush_tlb(peer_pdd, TLB_FLUSH_HEAVYWEIGHT);
1428 bind_process_to_device_failed:
1429 get_mem_obj_from_handle_failed:
1430 unmap_memory_from_gpu_failed:
1431 mutex_unlock(&p->mutex);
1432 copy_from_user_failed:
1438 static int kfd_ioctl_alloc_queue_gws(struct file *filep,
1439 struct kfd_process *p, void *data)
1442 struct kfd_ioctl_alloc_queue_gws_args *args = data;
1444 struct kfd_dev *dev;
1446 mutex_lock(&p->mutex);
1447 q = pqm_get_user_queue(&p->pqm, args->queue_id);
1461 if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) {
1466 retval = pqm_set_gws(&p->pqm, args->queue_id, args->num_gws ? dev->gws : NULL);
1467 mutex_unlock(&p->mutex);
1469 args->first_gws = 0;
1473 mutex_unlock(&p->mutex);
1477 static int kfd_ioctl_get_dmabuf_info(struct file *filep,
1478 struct kfd_process *p, void *data)
1480 struct kfd_ioctl_get_dmabuf_info_args *args = data;
1481 struct kfd_dev *dev = NULL;
1482 struct amdgpu_device *dmabuf_adev;
1483 void *metadata_buffer = NULL;
1488 /* Find a KFD GPU device that supports the get_dmabuf_info query */
1489 for (i = 0; kfd_topology_enum_kfd_devices(i, &dev) == 0; i++)
1495 if (args->metadata_ptr) {
1496 metadata_buffer = kzalloc(args->metadata_size, GFP_KERNEL);
1497 if (!metadata_buffer)
1501 /* Get dmabuf info from KGD */
1502 r = amdgpu_amdkfd_get_dmabuf_info(dev->adev, args->dmabuf_fd,
1503 &dmabuf_adev, &args->size,
1504 metadata_buffer, args->metadata_size,
1505 &args->metadata_size, &flags);
1509 /* Reverse-lookup gpu_id from kgd pointer */
1510 dev = kfd_device_by_adev(dmabuf_adev);
1515 args->gpu_id = dev->id;
1516 args->flags = flags;
1518 /* Copy metadata buffer to user mode */
1519 if (metadata_buffer) {
1520 r = copy_to_user((void __user *)args->metadata_ptr,
1521 metadata_buffer, args->metadata_size);
1527 kfree(metadata_buffer);
1532 static int kfd_ioctl_import_dmabuf(struct file *filep,
1533 struct kfd_process *p, void *data)
1535 struct kfd_ioctl_import_dmabuf_args *args = data;
1536 struct kfd_process_device *pdd;
1537 struct dma_buf *dmabuf;
1543 dmabuf = dma_buf_get(args->dmabuf_fd);
1545 return PTR_ERR(dmabuf);
1547 mutex_lock(&p->mutex);
1548 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
1554 pdd = kfd_bind_process_to_device(pdd->dev, p);
1560 r = amdgpu_amdkfd_gpuvm_import_dmabuf(pdd->dev->adev, dmabuf,
1561 args->va_addr, pdd->drm_priv,
1562 (struct kgd_mem **)&mem, &size,
1567 idr_handle = kfd_process_device_create_obj_handle(pdd, mem);
1568 if (idr_handle < 0) {
1573 mutex_unlock(&p->mutex);
1574 dma_buf_put(dmabuf);
1576 args->handle = MAKE_HANDLE(args->gpu_id, idr_handle);
1581 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, (struct kgd_mem *)mem,
1582 pdd->drm_priv, NULL);
1584 mutex_unlock(&p->mutex);
1585 dma_buf_put(dmabuf);
1589 /* Handle requests for watching SMI events */
1590 static int kfd_ioctl_smi_events(struct file *filep,
1591 struct kfd_process *p, void *data)
1593 struct kfd_ioctl_smi_events_args *args = data;
1594 struct kfd_process_device *pdd;
1596 mutex_lock(&p->mutex);
1598 pdd = kfd_process_device_data_by_id(p, args->gpuid);
1599 mutex_unlock(&p->mutex);
1603 return kfd_smi_event_open(pdd->dev, &args->anon_fd);
1606 #if IS_ENABLED(CONFIG_HSA_AMD_SVM)
1608 static int kfd_ioctl_set_xnack_mode(struct file *filep,
1609 struct kfd_process *p, void *data)
1611 struct kfd_ioctl_set_xnack_mode_args *args = data;
1614 mutex_lock(&p->mutex);
1615 if (args->xnack_enabled >= 0) {
1616 if (!list_empty(&p->pqm.queues)) {
1617 pr_debug("Process has user queues running\n");
1622 if (p->xnack_enabled == args->xnack_enabled)
1625 if (args->xnack_enabled && !kfd_process_xnack_mode(p, true)) {
1630 r = svm_range_switch_xnack_reserve_mem(p, args->xnack_enabled);
1632 args->xnack_enabled = p->xnack_enabled;
1636 mutex_unlock(&p->mutex);
1641 static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data)
1643 struct kfd_ioctl_svm_args *args = data;
1646 pr_debug("start 0x%llx size 0x%llx op 0x%x nattr 0x%x\n",
1647 args->start_addr, args->size, args->op, args->nattr);
1649 if ((args->start_addr & ~PAGE_MASK) || (args->size & ~PAGE_MASK))
1651 if (!args->start_addr || !args->size)
1654 r = svm_ioctl(p, args->op, args->start_addr, args->size, args->nattr,
1660 static int kfd_ioctl_set_xnack_mode(struct file *filep,
1661 struct kfd_process *p, void *data)
1665 static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data)
1671 static int criu_checkpoint_process(struct kfd_process *p,
1672 uint8_t __user *user_priv_data,
1673 uint64_t *priv_offset)
1675 struct kfd_criu_process_priv_data process_priv;
1678 memset(&process_priv, 0, sizeof(process_priv));
1680 process_priv.version = KFD_CRIU_PRIV_VERSION;
1681 /* For CR, we don't consider negative xnack mode which is used for
1682 * querying without changing it, here 0 simply means disabled and 1
1683 * means enabled so retry for finding a valid PTE.
1685 process_priv.xnack_mode = p->xnack_enabled ? 1 : 0;
1687 ret = copy_to_user(user_priv_data + *priv_offset,
1688 &process_priv, sizeof(process_priv));
1691 pr_err("Failed to copy process information to user\n");
1695 *priv_offset += sizeof(process_priv);
1699 static int criu_checkpoint_devices(struct kfd_process *p,
1700 uint32_t num_devices,
1701 uint8_t __user *user_addr,
1702 uint8_t __user *user_priv_data,
1703 uint64_t *priv_offset)
1705 struct kfd_criu_device_priv_data *device_priv = NULL;
1706 struct kfd_criu_device_bucket *device_buckets = NULL;
1709 device_buckets = kvzalloc(num_devices * sizeof(*device_buckets), GFP_KERNEL);
1710 if (!device_buckets) {
1715 device_priv = kvzalloc(num_devices * sizeof(*device_priv), GFP_KERNEL);
1721 for (i = 0; i < num_devices; i++) {
1722 struct kfd_process_device *pdd = p->pdds[i];
1724 device_buckets[i].user_gpu_id = pdd->user_gpu_id;
1725 device_buckets[i].actual_gpu_id = pdd->dev->id;
1728 * priv_data does not contain useful information for now and is reserved for
1729 * future use, so we do not set its contents.
1733 ret = copy_to_user(user_addr, device_buckets, num_devices * sizeof(*device_buckets));
1735 pr_err("Failed to copy device information to user\n");
1740 ret = copy_to_user(user_priv_data + *priv_offset,
1742 num_devices * sizeof(*device_priv));
1744 pr_err("Failed to copy device information to user\n");
1747 *priv_offset += num_devices * sizeof(*device_priv);
1750 kvfree(device_buckets);
1751 kvfree(device_priv);
1755 static uint32_t get_process_num_bos(struct kfd_process *p)
1757 uint32_t num_of_bos = 0;
1760 /* Run over all PDDs of the process */
1761 for (i = 0; i < p->n_pdds; i++) {
1762 struct kfd_process_device *pdd = p->pdds[i];
1766 idr_for_each_entry(&pdd->alloc_idr, mem, id) {
1767 struct kgd_mem *kgd_mem = (struct kgd_mem *)mem;
1769 if ((uint64_t)kgd_mem->va > pdd->gpuvm_base)
1776 static int criu_get_prime_handle(struct drm_gem_object *gobj, int flags,
1779 struct dma_buf *dmabuf;
1782 dmabuf = amdgpu_gem_prime_export(gobj, flags);
1783 if (IS_ERR(dmabuf)) {
1784 ret = PTR_ERR(dmabuf);
1785 pr_err("dmabuf export failed for the BO\n");
1789 ret = dma_buf_fd(dmabuf, flags);
1791 pr_err("dmabuf create fd failed, ret:%d\n", ret);
1792 goto out_free_dmabuf;
1799 dma_buf_put(dmabuf);
1803 static int criu_checkpoint_bos(struct kfd_process *p,
1805 uint8_t __user *user_bos,
1806 uint8_t __user *user_priv_data,
1807 uint64_t *priv_offset)
1809 struct kfd_criu_bo_bucket *bo_buckets;
1810 struct kfd_criu_bo_priv_data *bo_privs;
1811 int ret = 0, pdd_index, bo_index = 0, id;
1814 bo_buckets = kvzalloc(num_bos * sizeof(*bo_buckets), GFP_KERNEL);
1818 bo_privs = kvzalloc(num_bos * sizeof(*bo_privs), GFP_KERNEL);
1824 for (pdd_index = 0; pdd_index < p->n_pdds; pdd_index++) {
1825 struct kfd_process_device *pdd = p->pdds[pdd_index];
1826 struct amdgpu_bo *dumper_bo;
1827 struct kgd_mem *kgd_mem;
1829 idr_for_each_entry(&pdd->alloc_idr, mem, id) {
1830 struct kfd_criu_bo_bucket *bo_bucket;
1831 struct kfd_criu_bo_priv_data *bo_priv;
1839 kgd_mem = (struct kgd_mem *)mem;
1840 dumper_bo = kgd_mem->bo;
1842 if ((uint64_t)kgd_mem->va <= pdd->gpuvm_base)
1845 bo_bucket = &bo_buckets[bo_index];
1846 bo_priv = &bo_privs[bo_index];
1848 bo_bucket->gpu_id = pdd->user_gpu_id;
1849 bo_bucket->addr = (uint64_t)kgd_mem->va;
1850 bo_bucket->size = amdgpu_bo_size(dumper_bo);
1851 bo_bucket->alloc_flags = (uint32_t)kgd_mem->alloc_flags;
1852 bo_priv->idr_handle = id;
1854 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
1855 ret = amdgpu_ttm_tt_get_userptr(&dumper_bo->tbo,
1856 &bo_priv->user_addr);
1858 pr_err("Failed to obtain user address for user-pointer bo\n");
1862 if (bo_bucket->alloc_flags
1863 & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) {
1864 ret = criu_get_prime_handle(&dumper_bo->tbo.base,
1865 bo_bucket->alloc_flags &
1866 KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? DRM_RDWR : 0,
1867 &bo_bucket->dmabuf_fd);
1871 bo_bucket->dmabuf_fd = KFD_INVALID_FD;
1874 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL)
1875 bo_bucket->offset = KFD_MMAP_TYPE_DOORBELL |
1876 KFD_MMAP_GPU_ID(pdd->dev->id);
1877 else if (bo_bucket->alloc_flags &
1878 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)
1879 bo_bucket->offset = KFD_MMAP_TYPE_MMIO |
1880 KFD_MMAP_GPU_ID(pdd->dev->id);
1882 bo_bucket->offset = amdgpu_bo_mmap_offset(dumper_bo);
1884 for (i = 0; i < p->n_pdds; i++) {
1885 if (amdgpu_amdkfd_bo_mapped_to_dev(p->pdds[i]->dev->adev, kgd_mem))
1886 bo_priv->mapped_gpuids[dev_idx++] = p->pdds[i]->user_gpu_id;
1889 pr_debug("bo_size = 0x%llx, bo_addr = 0x%llx bo_offset = 0x%llx\n"
1890 "gpu_id = 0x%x alloc_flags = 0x%x idr_handle = 0x%x",
1895 bo_bucket->alloc_flags,
1896 bo_priv->idr_handle);
1901 ret = copy_to_user(user_bos, bo_buckets, num_bos * sizeof(*bo_buckets));
1903 pr_err("Failed to copy BO information to user\n");
1908 ret = copy_to_user(user_priv_data + *priv_offset, bo_privs, num_bos * sizeof(*bo_privs));
1910 pr_err("Failed to copy BO priv information to user\n");
1915 *priv_offset += num_bos * sizeof(*bo_privs);
1918 while (ret && bo_index--) {
1919 if (bo_buckets[bo_index].alloc_flags
1920 & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT))
1921 close_fd(bo_buckets[bo_index].dmabuf_fd);
1929 static int criu_get_process_object_info(struct kfd_process *p,
1930 uint32_t *num_devices,
1932 uint32_t *num_objects,
1933 uint64_t *objs_priv_size)
1935 uint64_t queues_priv_data_size, svm_priv_data_size, priv_size;
1936 uint32_t num_queues, num_events, num_svm_ranges;
1939 *num_devices = p->n_pdds;
1940 *num_bos = get_process_num_bos(p);
1942 ret = kfd_process_get_queue_info(p, &num_queues, &queues_priv_data_size);
1946 num_events = kfd_get_num_events(p);
1948 ret = svm_range_get_info(p, &num_svm_ranges, &svm_priv_data_size);
1952 *num_objects = num_queues + num_events + num_svm_ranges;
1954 if (objs_priv_size) {
1955 priv_size = sizeof(struct kfd_criu_process_priv_data);
1956 priv_size += *num_devices * sizeof(struct kfd_criu_device_priv_data);
1957 priv_size += *num_bos * sizeof(struct kfd_criu_bo_priv_data);
1958 priv_size += queues_priv_data_size;
1959 priv_size += num_events * sizeof(struct kfd_criu_event_priv_data);
1960 priv_size += svm_priv_data_size;
1961 *objs_priv_size = priv_size;
1966 static int criu_checkpoint(struct file *filep,
1967 struct kfd_process *p,
1968 struct kfd_ioctl_criu_args *args)
1971 uint32_t num_devices, num_bos, num_objects;
1972 uint64_t priv_size, priv_offset = 0, bo_priv_offset;
1974 if (!args->devices || !args->bos || !args->priv_data)
1977 mutex_lock(&p->mutex);
1980 pr_err("No pdd for given process\n");
1985 /* Confirm all process queues are evicted */
1986 if (!p->queues_paused) {
1987 pr_err("Cannot dump process when queues are not in evicted state\n");
1988 /* CRIU plugin did not call op PROCESS_INFO before checkpointing */
1993 ret = criu_get_process_object_info(p, &num_devices, &num_bos, &num_objects, &priv_size);
1997 if (num_devices != args->num_devices ||
1998 num_bos != args->num_bos ||
1999 num_objects != args->num_objects ||
2000 priv_size != args->priv_data_size) {
2006 /* each function will store private data inside priv_data and adjust priv_offset */
2007 ret = criu_checkpoint_process(p, (uint8_t __user *)args->priv_data, &priv_offset);
2011 ret = criu_checkpoint_devices(p, num_devices, (uint8_t __user *)args->devices,
2012 (uint8_t __user *)args->priv_data, &priv_offset);
2016 /* Leave room for BOs in the private data. They need to be restored
2017 * before events, but we checkpoint them last to simplify the error
2020 bo_priv_offset = priv_offset;
2021 priv_offset += num_bos * sizeof(struct kfd_criu_bo_priv_data);
2024 ret = kfd_criu_checkpoint_queues(p, (uint8_t __user *)args->priv_data,
2029 ret = kfd_criu_checkpoint_events(p, (uint8_t __user *)args->priv_data,
2034 ret = kfd_criu_checkpoint_svm(p, (uint8_t __user *)args->priv_data, &priv_offset);
2039 /* This must be the last thing in this function that can fail.
2040 * Otherwise we leak dmabuf file descriptors.
2042 ret = criu_checkpoint_bos(p, num_bos, (uint8_t __user *)args->bos,
2043 (uint8_t __user *)args->priv_data, &bo_priv_offset);
2046 mutex_unlock(&p->mutex);
2048 pr_err("Failed to dump CRIU ret:%d\n", ret);
2050 pr_debug("CRIU dump ret:%d\n", ret);
2055 static int criu_restore_process(struct kfd_process *p,
2056 struct kfd_ioctl_criu_args *args,
2057 uint64_t *priv_offset,
2058 uint64_t max_priv_data_size)
2061 struct kfd_criu_process_priv_data process_priv;
2063 if (*priv_offset + sizeof(process_priv) > max_priv_data_size)
2066 ret = copy_from_user(&process_priv,
2067 (void __user *)(args->priv_data + *priv_offset),
2068 sizeof(process_priv));
2070 pr_err("Failed to copy process private information from user\n");
2074 *priv_offset += sizeof(process_priv);
2076 if (process_priv.version != KFD_CRIU_PRIV_VERSION) {
2077 pr_err("Invalid CRIU API version (checkpointed:%d current:%d)\n",
2078 process_priv.version, KFD_CRIU_PRIV_VERSION);
2082 pr_debug("Setting XNACK mode\n");
2083 if (process_priv.xnack_mode && !kfd_process_xnack_mode(p, true)) {
2084 pr_err("xnack mode cannot be set\n");
2088 pr_debug("set xnack mode: %d\n", process_priv.xnack_mode);
2089 p->xnack_enabled = process_priv.xnack_mode;
2096 static int criu_restore_devices(struct kfd_process *p,
2097 struct kfd_ioctl_criu_args *args,
2098 uint64_t *priv_offset,
2099 uint64_t max_priv_data_size)
2101 struct kfd_criu_device_bucket *device_buckets;
2102 struct kfd_criu_device_priv_data *device_privs;
2106 if (args->num_devices != p->n_pdds)
2109 if (*priv_offset + (args->num_devices * sizeof(*device_privs)) > max_priv_data_size)
2112 device_buckets = kmalloc_array(args->num_devices, sizeof(*device_buckets), GFP_KERNEL);
2113 if (!device_buckets)
2116 ret = copy_from_user(device_buckets, (void __user *)args->devices,
2117 args->num_devices * sizeof(*device_buckets));
2119 pr_err("Failed to copy devices buckets from user\n");
2124 for (i = 0; i < args->num_devices; i++) {
2125 struct kfd_dev *dev;
2126 struct kfd_process_device *pdd;
2127 struct file *drm_file;
2129 /* device private data is not currently used */
2131 if (!device_buckets[i].user_gpu_id) {
2132 pr_err("Invalid user gpu_id\n");
2137 dev = kfd_device_by_id(device_buckets[i].actual_gpu_id);
2139 pr_err("Failed to find device with gpu_id = %x\n",
2140 device_buckets[i].actual_gpu_id);
2145 pdd = kfd_get_process_device_data(dev, p);
2147 pr_err("Failed to get pdd for gpu_id = %x\n",
2148 device_buckets[i].actual_gpu_id);
2152 pdd->user_gpu_id = device_buckets[i].user_gpu_id;
2154 drm_file = fget(device_buckets[i].drm_fd);
2156 pr_err("Invalid render node file descriptor sent from plugin (%d)\n",
2157 device_buckets[i].drm_fd);
2162 if (pdd->drm_file) {
2167 /* create the vm using render nodes for kfd pdd */
2168 if (kfd_process_device_init_vm(pdd, drm_file)) {
2169 pr_err("could not init vm for given pdd\n");
2170 /* On success, the PDD keeps the drm_file reference */
2176 * pdd now already has the vm bound to render node so below api won't create a new
2177 * exclusive kfd mapping but use existing one with renderDXXX but is still needed
2178 * for iommu v2 binding and runtime pm.
2180 pdd = kfd_bind_process_to_device(dev, p);
2186 if (!pdd->doorbell_index &&
2187 kfd_alloc_process_doorbells(pdd->dev, &pdd->doorbell_index) < 0) {
2194 * We are not copying device private data from user as we are not using the data for now,
2195 * but we still adjust for its private data.
2197 *priv_offset += args->num_devices * sizeof(*device_privs);
2200 kfree(device_buckets);
2204 static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd,
2205 struct kfd_criu_bo_bucket *bo_bucket,
2206 struct kfd_criu_bo_priv_data *bo_priv,
2207 struct kgd_mem **kgd_mem)
2211 const bool criu_resume = true;
2214 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) {
2215 if (bo_bucket->size != kfd_doorbell_process_slice(pdd->dev))
2218 offset = kfd_get_process_doorbells(pdd);
2221 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) {
2222 /* MMIO BOs need remapped bus address */
2223 if (bo_bucket->size != PAGE_SIZE) {
2224 pr_err("Invalid page size\n");
2227 offset = pdd->dev->adev->rmmio_remap.bus_addr;
2229 pr_err("amdgpu_amdkfd_get_mmio_remap_phys_addr failed\n");
2232 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
2233 offset = bo_priv->user_addr;
2236 ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(pdd->dev->adev, bo_bucket->addr,
2237 bo_bucket->size, pdd->drm_priv, kgd_mem,
2238 &offset, bo_bucket->alloc_flags, criu_resume);
2240 pr_err("Could not create the BO\n");
2243 pr_debug("New BO created: size:0x%llx addr:0x%llx offset:0x%llx\n",
2244 bo_bucket->size, bo_bucket->addr, offset);
2246 /* Restore previous IDR handle */
2247 pr_debug("Restoring old IDR handle for the BO");
2248 idr_handle = idr_alloc(&pdd->alloc_idr, *kgd_mem, bo_priv->idr_handle,
2249 bo_priv->idr_handle + 1, GFP_KERNEL);
2251 if (idr_handle < 0) {
2252 pr_err("Could not allocate idr\n");
2253 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, *kgd_mem, pdd->drm_priv,
2258 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL)
2259 bo_bucket->restored_offset = KFD_MMAP_TYPE_DOORBELL | KFD_MMAP_GPU_ID(pdd->dev->id);
2260 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) {
2261 bo_bucket->restored_offset = KFD_MMAP_TYPE_MMIO | KFD_MMAP_GPU_ID(pdd->dev->id);
2262 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
2263 bo_bucket->restored_offset = offset;
2264 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
2265 bo_bucket->restored_offset = offset;
2266 /* Update the VRAM usage count */
2267 WRITE_ONCE(pdd->vram_usage, pdd->vram_usage + bo_bucket->size);
2272 static int criu_restore_bo(struct kfd_process *p,
2273 struct kfd_criu_bo_bucket *bo_bucket,
2274 struct kfd_criu_bo_priv_data *bo_priv)
2276 struct kfd_process_device *pdd;
2277 struct kgd_mem *kgd_mem;
2281 pr_debug("Restoring BO size:0x%llx addr:0x%llx gpu_id:0x%x flags:0x%x idr_handle:0x%x\n",
2282 bo_bucket->size, bo_bucket->addr, bo_bucket->gpu_id, bo_bucket->alloc_flags,
2283 bo_priv->idr_handle);
2285 pdd = kfd_process_device_data_by_id(p, bo_bucket->gpu_id);
2287 pr_err("Failed to get pdd\n");
2291 ret = criu_restore_memory_of_gpu(pdd, bo_bucket, bo_priv, &kgd_mem);
2295 /* now map these BOs to GPU/s */
2296 for (j = 0; j < p->n_pdds; j++) {
2297 struct kfd_dev *peer;
2298 struct kfd_process_device *peer_pdd;
2300 if (!bo_priv->mapped_gpuids[j])
2303 peer_pdd = kfd_process_device_data_by_id(p, bo_priv->mapped_gpuids[j]);
2307 peer = peer_pdd->dev;
2309 peer_pdd = kfd_bind_process_to_device(peer, p);
2310 if (IS_ERR(peer_pdd))
2311 return PTR_ERR(peer_pdd);
2313 ret = amdgpu_amdkfd_gpuvm_map_memory_to_gpu(peer->adev, kgd_mem,
2314 peer_pdd->drm_priv);
2316 pr_err("Failed to map to gpu %d/%d\n", j, p->n_pdds);
2321 pr_debug("map memory was successful for the BO\n");
2322 /* create the dmabuf object and export the bo */
2323 if (bo_bucket->alloc_flags
2324 & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) {
2325 ret = criu_get_prime_handle(&kgd_mem->bo->tbo.base, DRM_RDWR,
2326 &bo_bucket->dmabuf_fd);
2330 bo_bucket->dmabuf_fd = KFD_INVALID_FD;
2336 static int criu_restore_bos(struct kfd_process *p,
2337 struct kfd_ioctl_criu_args *args,
2338 uint64_t *priv_offset,
2339 uint64_t max_priv_data_size)
2341 struct kfd_criu_bo_bucket *bo_buckets = NULL;
2342 struct kfd_criu_bo_priv_data *bo_privs = NULL;
2346 if (*priv_offset + (args->num_bos * sizeof(*bo_privs)) > max_priv_data_size)
2349 /* Prevent MMU notifications until stage-4 IOCTL (CRIU_RESUME) is received */
2350 amdgpu_amdkfd_block_mmu_notifications(p->kgd_process_info);
2352 bo_buckets = kvmalloc_array(args->num_bos, sizeof(*bo_buckets), GFP_KERNEL);
2356 ret = copy_from_user(bo_buckets, (void __user *)args->bos,
2357 args->num_bos * sizeof(*bo_buckets));
2359 pr_err("Failed to copy BOs information from user\n");
2364 bo_privs = kvmalloc_array(args->num_bos, sizeof(*bo_privs), GFP_KERNEL);
2370 ret = copy_from_user(bo_privs, (void __user *)args->priv_data + *priv_offset,
2371 args->num_bos * sizeof(*bo_privs));
2373 pr_err("Failed to copy BOs information from user\n");
2377 *priv_offset += args->num_bos * sizeof(*bo_privs);
2379 /* Create and map new BOs */
2380 for (; i < args->num_bos; i++) {
2381 ret = criu_restore_bo(p, &bo_buckets[i], &bo_privs[i]);
2383 pr_debug("Failed to restore BO[%d] ret%d\n", i, ret);
2388 /* Copy only the buckets back so user can read bo_buckets[N].restored_offset */
2389 ret = copy_to_user((void __user *)args->bos,
2391 (args->num_bos * sizeof(*bo_buckets)));
2396 while (ret && i--) {
2397 if (bo_buckets[i].alloc_flags
2398 & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT))
2399 close_fd(bo_buckets[i].dmabuf_fd);
2406 static int criu_restore_objects(struct file *filep,
2407 struct kfd_process *p,
2408 struct kfd_ioctl_criu_args *args,
2409 uint64_t *priv_offset,
2410 uint64_t max_priv_data_size)
2415 BUILD_BUG_ON(offsetof(struct kfd_criu_queue_priv_data, object_type));
2416 BUILD_BUG_ON(offsetof(struct kfd_criu_event_priv_data, object_type));
2417 BUILD_BUG_ON(offsetof(struct kfd_criu_svm_range_priv_data, object_type));
2419 for (i = 0; i < args->num_objects; i++) {
2420 uint32_t object_type;
2422 if (*priv_offset + sizeof(object_type) > max_priv_data_size) {
2423 pr_err("Invalid private data size\n");
2427 ret = get_user(object_type, (uint32_t __user *)(args->priv_data + *priv_offset));
2429 pr_err("Failed to copy private information from user\n");
2433 switch (object_type) {
2434 case KFD_CRIU_OBJECT_TYPE_QUEUE:
2435 ret = kfd_criu_restore_queue(p, (uint8_t __user *)args->priv_data,
2436 priv_offset, max_priv_data_size);
2440 case KFD_CRIU_OBJECT_TYPE_EVENT:
2441 ret = kfd_criu_restore_event(filep, p, (uint8_t __user *)args->priv_data,
2442 priv_offset, max_priv_data_size);
2446 case KFD_CRIU_OBJECT_TYPE_SVM_RANGE:
2447 ret = kfd_criu_restore_svm(p, (uint8_t __user *)args->priv_data,
2448 priv_offset, max_priv_data_size);
2453 pr_err("Invalid object type:%u at index:%d\n", object_type, i);
2462 static int criu_restore(struct file *filep,
2463 struct kfd_process *p,
2464 struct kfd_ioctl_criu_args *args)
2466 uint64_t priv_offset = 0;
2469 pr_debug("CRIU restore (num_devices:%u num_bos:%u num_objects:%u priv_data_size:%llu)\n",
2470 args->num_devices, args->num_bos, args->num_objects, args->priv_data_size);
2472 if (!args->bos || !args->devices || !args->priv_data || !args->priv_data_size ||
2473 !args->num_devices || !args->num_bos)
2476 mutex_lock(&p->mutex);
2479 * Set the process to evicted state to avoid running any new queues before all the memory
2480 * mappings are ready.
2482 ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_CRIU_RESTORE);
2486 /* Each function will adjust priv_offset based on how many bytes they consumed */
2487 ret = criu_restore_process(p, args, &priv_offset, args->priv_data_size);
2491 ret = criu_restore_devices(p, args, &priv_offset, args->priv_data_size);
2495 ret = criu_restore_bos(p, args, &priv_offset, args->priv_data_size);
2499 ret = criu_restore_objects(filep, p, args, &priv_offset, args->priv_data_size);
2503 if (priv_offset != args->priv_data_size) {
2504 pr_err("Invalid private data size\n");
2509 mutex_unlock(&p->mutex);
2511 pr_err("Failed to restore CRIU ret:%d\n", ret);
2513 pr_debug("CRIU restore successful\n");
2518 static int criu_unpause(struct file *filep,
2519 struct kfd_process *p,
2520 struct kfd_ioctl_criu_args *args)
2524 mutex_lock(&p->mutex);
2526 if (!p->queues_paused) {
2527 mutex_unlock(&p->mutex);
2531 ret = kfd_process_restore_queues(p);
2533 pr_err("Failed to unpause queues ret:%d\n", ret);
2535 p->queues_paused = false;
2537 mutex_unlock(&p->mutex);
2542 static int criu_resume(struct file *filep,
2543 struct kfd_process *p,
2544 struct kfd_ioctl_criu_args *args)
2546 struct kfd_process *target = NULL;
2547 struct pid *pid = NULL;
2550 pr_debug("Inside %s, target pid for criu restore: %d\n", __func__,
2553 pid = find_get_pid(args->pid);
2555 pr_err("Cannot find pid info for %i\n", args->pid);
2559 pr_debug("calling kfd_lookup_process_by_pid\n");
2560 target = kfd_lookup_process_by_pid(pid);
2565 pr_debug("Cannot find process info for %i\n", args->pid);
2569 mutex_lock(&target->mutex);
2570 ret = kfd_criu_resume_svm(target);
2572 pr_err("kfd_criu_resume_svm failed for %i\n", args->pid);
2576 ret = amdgpu_amdkfd_criu_resume(target->kgd_process_info);
2578 pr_err("amdgpu_amdkfd_criu_resume failed for %i\n", args->pid);
2581 mutex_unlock(&target->mutex);
2583 kfd_unref_process(target);
2587 static int criu_process_info(struct file *filep,
2588 struct kfd_process *p,
2589 struct kfd_ioctl_criu_args *args)
2593 mutex_lock(&p->mutex);
2596 pr_err("No pdd for given process\n");
2601 ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_CRIU_CHECKPOINT);
2605 p->queues_paused = true;
2607 args->pid = task_pid_nr_ns(p->lead_thread,
2608 task_active_pid_ns(p->lead_thread));
2610 ret = criu_get_process_object_info(p, &args->num_devices, &args->num_bos,
2611 &args->num_objects, &args->priv_data_size);
2615 dev_dbg(kfd_device, "Num of devices:%u bos:%u objects:%u priv_data_size:%lld\n",
2616 args->num_devices, args->num_bos, args->num_objects,
2617 args->priv_data_size);
2621 kfd_process_restore_queues(p);
2622 p->queues_paused = false;
2624 mutex_unlock(&p->mutex);
2628 static int kfd_ioctl_criu(struct file *filep, struct kfd_process *p, void *data)
2630 struct kfd_ioctl_criu_args *args = data;
2633 dev_dbg(kfd_device, "CRIU operation: %d\n", args->op);
2635 case KFD_CRIU_OP_PROCESS_INFO:
2636 ret = criu_process_info(filep, p, args);
2638 case KFD_CRIU_OP_CHECKPOINT:
2639 ret = criu_checkpoint(filep, p, args);
2641 case KFD_CRIU_OP_UNPAUSE:
2642 ret = criu_unpause(filep, p, args);
2644 case KFD_CRIU_OP_RESTORE:
2645 ret = criu_restore(filep, p, args);
2647 case KFD_CRIU_OP_RESUME:
2648 ret = criu_resume(filep, p, args);
2651 dev_dbg(kfd_device, "Unsupported CRIU operation:%d\n", args->op);
2657 dev_dbg(kfd_device, "CRIU operation:%d err:%d\n", args->op, ret);
2662 #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \
2663 [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \
2664 .cmd_drv = 0, .name = #ioctl}
2667 static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = {
2668 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_VERSION,
2669 kfd_ioctl_get_version, 0),
2671 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_QUEUE,
2672 kfd_ioctl_create_queue, 0),
2674 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_QUEUE,
2675 kfd_ioctl_destroy_queue, 0),
2677 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_MEMORY_POLICY,
2678 kfd_ioctl_set_memory_policy, 0),
2680 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_CLOCK_COUNTERS,
2681 kfd_ioctl_get_clock_counters, 0),
2683 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES,
2684 kfd_ioctl_get_process_apertures, 0),
2686 AMDKFD_IOCTL_DEF(AMDKFD_IOC_UPDATE_QUEUE,
2687 kfd_ioctl_update_queue, 0),
2689 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_EVENT,
2690 kfd_ioctl_create_event, 0),
2692 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_EVENT,
2693 kfd_ioctl_destroy_event, 0),
2695 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_EVENT,
2696 kfd_ioctl_set_event, 0),
2698 AMDKFD_IOCTL_DEF(AMDKFD_IOC_RESET_EVENT,
2699 kfd_ioctl_reset_event, 0),
2701 AMDKFD_IOCTL_DEF(AMDKFD_IOC_WAIT_EVENTS,
2702 kfd_ioctl_wait_events, 0),
2704 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_REGISTER_DEPRECATED,
2705 kfd_ioctl_dbg_register, 0),
2707 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_UNREGISTER_DEPRECATED,
2708 kfd_ioctl_dbg_unregister, 0),
2710 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_ADDRESS_WATCH_DEPRECATED,
2711 kfd_ioctl_dbg_address_watch, 0),
2713 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_WAVE_CONTROL_DEPRECATED,
2714 kfd_ioctl_dbg_wave_control, 0),
2716 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_SCRATCH_BACKING_VA,
2717 kfd_ioctl_set_scratch_backing_va, 0),
2719 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_TILE_CONFIG,
2720 kfd_ioctl_get_tile_config, 0),
2722 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_TRAP_HANDLER,
2723 kfd_ioctl_set_trap_handler, 0),
2725 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES_NEW,
2726 kfd_ioctl_get_process_apertures_new, 0),
2728 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ACQUIRE_VM,
2729 kfd_ioctl_acquire_vm, 0),
2731 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ALLOC_MEMORY_OF_GPU,
2732 kfd_ioctl_alloc_memory_of_gpu, 0),
2734 AMDKFD_IOCTL_DEF(AMDKFD_IOC_FREE_MEMORY_OF_GPU,
2735 kfd_ioctl_free_memory_of_gpu, 0),
2737 AMDKFD_IOCTL_DEF(AMDKFD_IOC_MAP_MEMORY_TO_GPU,
2738 kfd_ioctl_map_memory_to_gpu, 0),
2740 AMDKFD_IOCTL_DEF(AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU,
2741 kfd_ioctl_unmap_memory_from_gpu, 0),
2743 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_CU_MASK,
2744 kfd_ioctl_set_cu_mask, 0),
2746 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_QUEUE_WAVE_STATE,
2747 kfd_ioctl_get_queue_wave_state, 0),
2749 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_DMABUF_INFO,
2750 kfd_ioctl_get_dmabuf_info, 0),
2752 AMDKFD_IOCTL_DEF(AMDKFD_IOC_IMPORT_DMABUF,
2753 kfd_ioctl_import_dmabuf, 0),
2755 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ALLOC_QUEUE_GWS,
2756 kfd_ioctl_alloc_queue_gws, 0),
2758 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SMI_EVENTS,
2759 kfd_ioctl_smi_events, 0),
2761 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SVM, kfd_ioctl_svm, 0),
2763 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_XNACK_MODE,
2764 kfd_ioctl_set_xnack_mode, 0),
2766 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CRIU_OP,
2767 kfd_ioctl_criu, KFD_IOC_FLAG_CHECKPOINT_RESTORE),
2769 AMDKFD_IOCTL_DEF(AMDKFD_IOC_AVAILABLE_MEMORY,
2770 kfd_ioctl_get_available_memory, 0),
2773 #define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls)
2775 static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
2777 struct kfd_process *process;
2778 amdkfd_ioctl_t *func;
2779 const struct amdkfd_ioctl_desc *ioctl = NULL;
2780 unsigned int nr = _IOC_NR(cmd);
2781 char stack_kdata[128];
2783 unsigned int usize, asize;
2784 int retcode = -EINVAL;
2785 bool ptrace_attached = false;
2787 if (nr >= AMDKFD_CORE_IOCTL_COUNT)
2790 if ((nr >= AMDKFD_COMMAND_START) && (nr < AMDKFD_COMMAND_END)) {
2793 ioctl = &amdkfd_ioctls[nr];
2795 amdkfd_size = _IOC_SIZE(ioctl->cmd);
2796 usize = asize = _IOC_SIZE(cmd);
2797 if (amdkfd_size > asize)
2798 asize = amdkfd_size;
2804 dev_dbg(kfd_device, "ioctl cmd 0x%x (#0x%x), arg 0x%lx\n", cmd, nr, arg);
2806 /* Get the process struct from the filep. Only the process
2807 * that opened /dev/kfd can use the file descriptor. Child
2808 * processes need to create their own KFD device context.
2810 process = filep->private_data;
2813 if ((ioctl->flags & KFD_IOC_FLAG_CHECKPOINT_RESTORE) &&
2814 ptrace_parent(process->lead_thread) == current)
2815 ptrace_attached = true;
2818 if (process->lead_thread != current->group_leader
2819 && !ptrace_attached) {
2820 dev_dbg(kfd_device, "Using KFD FD in wrong process\n");
2825 /* Do not trust userspace, use our own definition */
2828 if (unlikely(!func)) {
2829 dev_dbg(kfd_device, "no function\n");
2835 * Versions of docker shipped in Ubuntu 18.xx and 20.xx do not support
2836 * CAP_CHECKPOINT_RESTORE, so we also allow access if CAP_SYS_ADMIN as CAP_SYS_ADMIN is a
2837 * more priviledged access.
2839 if (unlikely(ioctl->flags & KFD_IOC_FLAG_CHECKPOINT_RESTORE)) {
2840 if (!capable(CAP_CHECKPOINT_RESTORE) &&
2841 !capable(CAP_SYS_ADMIN)) {
2847 if (cmd & (IOC_IN | IOC_OUT)) {
2848 if (asize <= sizeof(stack_kdata)) {
2849 kdata = stack_kdata;
2851 kdata = kmalloc(asize, GFP_KERNEL);
2858 memset(kdata + usize, 0, asize - usize);
2862 if (copy_from_user(kdata, (void __user *)arg, usize) != 0) {
2866 } else if (cmd & IOC_OUT) {
2867 memset(kdata, 0, usize);
2870 retcode = func(filep, process, kdata);
2873 if (copy_to_user((void __user *)arg, kdata, usize) != 0)
2878 dev_dbg(kfd_device, "invalid ioctl: pid=%d, cmd=0x%02x, nr=0x%02x\n",
2879 task_pid_nr(current), cmd, nr);
2881 if (kdata != stack_kdata)
2885 dev_dbg(kfd_device, "ioctl cmd (#0x%x), arg 0x%lx, ret = %d\n",
2891 static int kfd_mmio_mmap(struct kfd_dev *dev, struct kfd_process *process,
2892 struct vm_area_struct *vma)
2894 phys_addr_t address;
2896 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2899 address = dev->adev->rmmio_remap.bus_addr;
2901 vm_flags_set(vma, VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_NORESERVE |
2902 VM_DONTDUMP | VM_PFNMAP);
2904 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
2906 pr_debug("pasid 0x%x mapping mmio page\n"
2907 " target user address == 0x%08llX\n"
2908 " physical address == 0x%08llX\n"
2909 " vm_flags == 0x%04lX\n"
2910 " size == 0x%04lX\n",
2911 process->pasid, (unsigned long long) vma->vm_start,
2912 address, vma->vm_flags, PAGE_SIZE);
2914 return io_remap_pfn_range(vma,
2916 address >> PAGE_SHIFT,
2922 static int kfd_mmap(struct file *filp, struct vm_area_struct *vma)
2924 struct kfd_process *process;
2925 struct kfd_dev *dev = NULL;
2926 unsigned long mmap_offset;
2927 unsigned int gpu_id;
2929 process = kfd_get_process(current);
2930 if (IS_ERR(process))
2931 return PTR_ERR(process);
2933 mmap_offset = vma->vm_pgoff << PAGE_SHIFT;
2934 gpu_id = KFD_MMAP_GET_GPU_ID(mmap_offset);
2936 dev = kfd_device_by_id(gpu_id);
2938 switch (mmap_offset & KFD_MMAP_TYPE_MASK) {
2939 case KFD_MMAP_TYPE_DOORBELL:
2942 return kfd_doorbell_mmap(dev, process, vma);
2944 case KFD_MMAP_TYPE_EVENTS:
2945 return kfd_event_mmap(process, vma);
2947 case KFD_MMAP_TYPE_RESERVED_MEM:
2950 return kfd_reserved_mem_mmap(dev, process, vma);
2951 case KFD_MMAP_TYPE_MMIO:
2954 return kfd_mmio_mmap(dev, process, vma);