2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/device.h>
24 #include <linux/export.h>
25 #include <linux/err.h>
27 #include <linux/file.h>
28 #include <linux/sched.h>
29 #include <linux/slab.h>
30 #include <linux/uaccess.h>
31 #include <linux/compat.h>
32 #include <uapi/linux/kfd_ioctl.h>
33 #include <linux/time.h>
35 #include <linux/mman.h>
36 #include <linux/dma-buf.h>
37 #include <asm/processor.h>
39 #include "kfd_device_queue_manager.h"
40 #include "kfd_dbgmgr.h"
41 #include "amdgpu_amdkfd.h"
42 #include "kfd_smi_events.h"
44 static long kfd_ioctl(struct file *, unsigned int, unsigned long);
45 static int kfd_open(struct inode *, struct file *);
46 static int kfd_release(struct inode *, struct file *);
47 static int kfd_mmap(struct file *, struct vm_area_struct *);
49 static const char kfd_dev_name[] = "kfd";
51 static const struct file_operations kfd_fops = {
53 .unlocked_ioctl = kfd_ioctl,
54 .compat_ioctl = compat_ptr_ioctl,
56 .release = kfd_release,
60 static int kfd_char_dev_major = -1;
61 static struct class *kfd_class;
62 struct device *kfd_device;
64 int kfd_chardev_init(void)
68 kfd_char_dev_major = register_chrdev(0, kfd_dev_name, &kfd_fops);
69 err = kfd_char_dev_major;
71 goto err_register_chrdev;
73 kfd_class = class_create(THIS_MODULE, kfd_dev_name);
74 err = PTR_ERR(kfd_class);
75 if (IS_ERR(kfd_class))
76 goto err_class_create;
78 kfd_device = device_create(kfd_class, NULL,
79 MKDEV(kfd_char_dev_major, 0),
81 err = PTR_ERR(kfd_device);
82 if (IS_ERR(kfd_device))
83 goto err_device_create;
88 class_destroy(kfd_class);
90 unregister_chrdev(kfd_char_dev_major, kfd_dev_name);
95 void kfd_chardev_exit(void)
97 device_destroy(kfd_class, MKDEV(kfd_char_dev_major, 0));
98 class_destroy(kfd_class);
99 unregister_chrdev(kfd_char_dev_major, kfd_dev_name);
103 struct device *kfd_chardev(void)
109 static int kfd_open(struct inode *inode, struct file *filep)
111 struct kfd_process *process;
112 bool is_32bit_user_mode;
114 if (iminor(inode) != 0)
117 is_32bit_user_mode = in_compat_syscall();
119 if (is_32bit_user_mode) {
121 "Process %d (32-bit) failed to open /dev/kfd\n"
122 "32-bit processes are not supported by amdkfd\n",
127 process = kfd_create_process(filep);
129 return PTR_ERR(process);
131 if (kfd_is_locked()) {
132 dev_dbg(kfd_device, "kfd is locked!\n"
133 "process %d unreferenced", process->pasid);
134 kfd_unref_process(process);
138 /* filep now owns the reference returned by kfd_create_process */
139 filep->private_data = process;
141 dev_dbg(kfd_device, "process %d opened, compat mode (32 bit) - %d\n",
142 process->pasid, process->is_32bit_user_mode);
147 static int kfd_release(struct inode *inode, struct file *filep)
149 struct kfd_process *process = filep->private_data;
152 kfd_unref_process(process);
157 static int kfd_ioctl_get_version(struct file *filep, struct kfd_process *p,
160 struct kfd_ioctl_get_version_args *args = data;
162 args->major_version = KFD_IOCTL_MAJOR_VERSION;
163 args->minor_version = KFD_IOCTL_MINOR_VERSION;
168 static int set_queue_properties_from_user(struct queue_properties *q_properties,
169 struct kfd_ioctl_create_queue_args *args)
171 if (args->queue_percentage > KFD_MAX_QUEUE_PERCENTAGE) {
172 pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n");
176 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) {
177 pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n");
181 if ((args->ring_base_address) &&
182 (!access_ok((const void __user *) args->ring_base_address,
183 sizeof(uint64_t)))) {
184 pr_err("Can't access ring base address\n");
188 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) {
189 pr_err("Ring size must be a power of 2 or 0\n");
193 if (!access_ok((const void __user *) args->read_pointer_address,
195 pr_err("Can't access read pointer\n");
199 if (!access_ok((const void __user *) args->write_pointer_address,
201 pr_err("Can't access write pointer\n");
205 if (args->eop_buffer_address &&
206 !access_ok((const void __user *) args->eop_buffer_address,
208 pr_debug("Can't access eop buffer");
212 if (args->ctx_save_restore_address &&
213 !access_ok((const void __user *) args->ctx_save_restore_address,
215 pr_debug("Can't access ctx save restore buffer");
219 q_properties->is_interop = false;
220 q_properties->is_gws = false;
221 q_properties->queue_percent = args->queue_percentage;
222 q_properties->priority = args->queue_priority;
223 q_properties->queue_address = args->ring_base_address;
224 q_properties->queue_size = args->ring_size;
225 q_properties->read_ptr = (uint32_t *) args->read_pointer_address;
226 q_properties->write_ptr = (uint32_t *) args->write_pointer_address;
227 q_properties->eop_ring_buffer_address = args->eop_buffer_address;
228 q_properties->eop_ring_buffer_size = args->eop_buffer_size;
229 q_properties->ctx_save_restore_area_address =
230 args->ctx_save_restore_address;
231 q_properties->ctx_save_restore_area_size = args->ctx_save_restore_size;
232 q_properties->ctl_stack_size = args->ctl_stack_size;
233 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE ||
234 args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL)
235 q_properties->type = KFD_QUEUE_TYPE_COMPUTE;
236 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA)
237 q_properties->type = KFD_QUEUE_TYPE_SDMA;
238 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA_XGMI)
239 q_properties->type = KFD_QUEUE_TYPE_SDMA_XGMI;
243 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL)
244 q_properties->format = KFD_QUEUE_FORMAT_AQL;
246 q_properties->format = KFD_QUEUE_FORMAT_PM4;
248 pr_debug("Queue Percentage: %d, %d\n",
249 q_properties->queue_percent, args->queue_percentage);
251 pr_debug("Queue Priority: %d, %d\n",
252 q_properties->priority, args->queue_priority);
254 pr_debug("Queue Address: 0x%llX, 0x%llX\n",
255 q_properties->queue_address, args->ring_base_address);
257 pr_debug("Queue Size: 0x%llX, %u\n",
258 q_properties->queue_size, args->ring_size);
260 pr_debug("Queue r/w Pointers: %px, %px\n",
261 q_properties->read_ptr,
262 q_properties->write_ptr);
264 pr_debug("Queue Format: %d\n", q_properties->format);
266 pr_debug("Queue EOP: 0x%llX\n", q_properties->eop_ring_buffer_address);
268 pr_debug("Queue CTX save area: 0x%llX\n",
269 q_properties->ctx_save_restore_area_address);
274 static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p,
277 struct kfd_ioctl_create_queue_args *args = data;
280 unsigned int queue_id;
281 struct kfd_process_device *pdd;
282 struct queue_properties q_properties;
283 uint32_t doorbell_offset_in_process = 0;
285 memset(&q_properties, 0, sizeof(struct queue_properties));
287 pr_debug("Creating queue ioctl\n");
289 err = set_queue_properties_from_user(&q_properties, args);
293 pr_debug("Looking for gpu id 0x%x\n", args->gpu_id);
294 dev = kfd_device_by_id(args->gpu_id);
296 pr_debug("Could not find gpu id 0x%x\n", args->gpu_id);
300 mutex_lock(&p->mutex);
302 pdd = kfd_bind_process_to_device(dev, p);
305 goto err_bind_process;
308 pr_debug("Creating queue for PASID 0x%x on gpu 0x%x\n",
312 err = pqm_create_queue(&p->pqm, dev, filep, &q_properties, &queue_id,
313 &doorbell_offset_in_process);
315 goto err_create_queue;
317 args->queue_id = queue_id;
320 /* Return gpu_id as doorbell offset for mmap usage */
321 args->doorbell_offset = KFD_MMAP_TYPE_DOORBELL;
322 args->doorbell_offset |= KFD_MMAP_GPU_ID(args->gpu_id);
323 if (KFD_IS_SOC15(dev->device_info->asic_family))
324 /* On SOC15 ASICs, include the doorbell offset within the
325 * process doorbell frame, which is 2 pages.
327 args->doorbell_offset |= doorbell_offset_in_process;
329 mutex_unlock(&p->mutex);
331 pr_debug("Queue id %d was created successfully\n", args->queue_id);
333 pr_debug("Ring buffer address == 0x%016llX\n",
334 args->ring_base_address);
336 pr_debug("Read ptr address == 0x%016llX\n",
337 args->read_pointer_address);
339 pr_debug("Write ptr address == 0x%016llX\n",
340 args->write_pointer_address);
346 mutex_unlock(&p->mutex);
350 static int kfd_ioctl_destroy_queue(struct file *filp, struct kfd_process *p,
354 struct kfd_ioctl_destroy_queue_args *args = data;
356 pr_debug("Destroying queue id %d for pasid 0x%x\n",
360 mutex_lock(&p->mutex);
362 retval = pqm_destroy_queue(&p->pqm, args->queue_id);
364 mutex_unlock(&p->mutex);
368 static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p,
372 struct kfd_ioctl_update_queue_args *args = data;
373 struct queue_properties properties;
375 if (args->queue_percentage > KFD_MAX_QUEUE_PERCENTAGE) {
376 pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n");
380 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) {
381 pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n");
385 if ((args->ring_base_address) &&
386 (!access_ok((const void __user *) args->ring_base_address,
387 sizeof(uint64_t)))) {
388 pr_err("Can't access ring base address\n");
392 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) {
393 pr_err("Ring size must be a power of 2 or 0\n");
397 properties.queue_address = args->ring_base_address;
398 properties.queue_size = args->ring_size;
399 properties.queue_percent = args->queue_percentage;
400 properties.priority = args->queue_priority;
402 pr_debug("Updating queue id %d for pasid 0x%x\n",
403 args->queue_id, p->pasid);
405 mutex_lock(&p->mutex);
407 retval = pqm_update_queue(&p->pqm, args->queue_id, &properties);
409 mutex_unlock(&p->mutex);
414 static int kfd_ioctl_set_cu_mask(struct file *filp, struct kfd_process *p,
418 const int max_num_cus = 1024;
419 struct kfd_ioctl_set_cu_mask_args *args = data;
420 struct queue_properties properties;
421 uint32_t __user *cu_mask_ptr = (uint32_t __user *)args->cu_mask_ptr;
422 size_t cu_mask_size = sizeof(uint32_t) * (args->num_cu_mask / 32);
424 if ((args->num_cu_mask % 32) != 0) {
425 pr_debug("num_cu_mask 0x%x must be a multiple of 32",
430 properties.cu_mask_count = args->num_cu_mask;
431 if (properties.cu_mask_count == 0) {
432 pr_debug("CU mask cannot be 0");
436 /* To prevent an unreasonably large CU mask size, set an arbitrary
437 * limit of max_num_cus bits. We can then just drop any CU mask bits
438 * past max_num_cus bits and just use the first max_num_cus bits.
440 if (properties.cu_mask_count > max_num_cus) {
441 pr_debug("CU mask cannot be greater than 1024 bits");
442 properties.cu_mask_count = max_num_cus;
443 cu_mask_size = sizeof(uint32_t) * (max_num_cus/32);
446 properties.cu_mask = kzalloc(cu_mask_size, GFP_KERNEL);
447 if (!properties.cu_mask)
450 retval = copy_from_user(properties.cu_mask, cu_mask_ptr, cu_mask_size);
452 pr_debug("Could not copy CU mask from userspace");
453 kfree(properties.cu_mask);
457 mutex_lock(&p->mutex);
459 retval = pqm_set_cu_mask(&p->pqm, args->queue_id, &properties);
461 mutex_unlock(&p->mutex);
464 kfree(properties.cu_mask);
469 static int kfd_ioctl_get_queue_wave_state(struct file *filep,
470 struct kfd_process *p, void *data)
472 struct kfd_ioctl_get_queue_wave_state_args *args = data;
475 mutex_lock(&p->mutex);
477 r = pqm_get_wave_state(&p->pqm, args->queue_id,
478 (void __user *)args->ctl_stack_address,
479 &args->ctl_stack_used_size,
480 &args->save_area_used_size);
482 mutex_unlock(&p->mutex);
487 static int kfd_ioctl_set_memory_policy(struct file *filep,
488 struct kfd_process *p, void *data)
490 struct kfd_ioctl_set_memory_policy_args *args = data;
493 struct kfd_process_device *pdd;
494 enum cache_policy default_policy, alternate_policy;
496 if (args->default_policy != KFD_IOC_CACHE_POLICY_COHERENT
497 && args->default_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) {
501 if (args->alternate_policy != KFD_IOC_CACHE_POLICY_COHERENT
502 && args->alternate_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) {
506 dev = kfd_device_by_id(args->gpu_id);
510 mutex_lock(&p->mutex);
512 pdd = kfd_bind_process_to_device(dev, p);
518 default_policy = (args->default_policy == KFD_IOC_CACHE_POLICY_COHERENT)
519 ? cache_policy_coherent : cache_policy_noncoherent;
522 (args->alternate_policy == KFD_IOC_CACHE_POLICY_COHERENT)
523 ? cache_policy_coherent : cache_policy_noncoherent;
525 if (!dev->dqm->ops.set_cache_memory_policy(dev->dqm,
529 (void __user *)args->alternate_aperture_base,
530 args->alternate_aperture_size))
534 mutex_unlock(&p->mutex);
539 static int kfd_ioctl_set_trap_handler(struct file *filep,
540 struct kfd_process *p, void *data)
542 struct kfd_ioctl_set_trap_handler_args *args = data;
545 struct kfd_process_device *pdd;
547 dev = kfd_device_by_id(args->gpu_id);
551 mutex_lock(&p->mutex);
553 pdd = kfd_bind_process_to_device(dev, p);
559 kfd_process_set_trap_handler(&pdd->qpd, args->tba_addr, args->tma_addr);
562 mutex_unlock(&p->mutex);
567 static int kfd_ioctl_dbg_register(struct file *filep,
568 struct kfd_process *p, void *data)
570 struct kfd_ioctl_dbg_register_args *args = data;
572 struct kfd_dbgmgr *dbgmgr_ptr;
573 struct kfd_process_device *pdd;
577 dev = kfd_device_by_id(args->gpu_id);
581 if (dev->device_info->asic_family == CHIP_CARRIZO) {
582 pr_debug("kfd_ioctl_dbg_register not supported on CZ\n");
586 mutex_lock(&p->mutex);
587 mutex_lock(kfd_get_dbgmgr_mutex());
590 * make sure that we have pdd, if this the first queue created for
593 pdd = kfd_bind_process_to_device(dev, p);
595 status = PTR_ERR(pdd);
600 /* In case of a legal call, we have no dbgmgr yet */
601 create_ok = kfd_dbgmgr_create(&dbgmgr_ptr, dev);
603 status = kfd_dbgmgr_register(dbgmgr_ptr, p);
605 kfd_dbgmgr_destroy(dbgmgr_ptr);
607 dev->dbgmgr = dbgmgr_ptr;
610 pr_debug("debugger already registered\n");
615 mutex_unlock(kfd_get_dbgmgr_mutex());
616 mutex_unlock(&p->mutex);
621 static int kfd_ioctl_dbg_unregister(struct file *filep,
622 struct kfd_process *p, void *data)
624 struct kfd_ioctl_dbg_unregister_args *args = data;
628 dev = kfd_device_by_id(args->gpu_id);
629 if (!dev || !dev->dbgmgr)
632 if (dev->device_info->asic_family == CHIP_CARRIZO) {
633 pr_debug("kfd_ioctl_dbg_unregister not supported on CZ\n");
637 mutex_lock(kfd_get_dbgmgr_mutex());
639 status = kfd_dbgmgr_unregister(dev->dbgmgr, p);
641 kfd_dbgmgr_destroy(dev->dbgmgr);
645 mutex_unlock(kfd_get_dbgmgr_mutex());
651 * Parse and generate variable size data structure for address watch.
652 * Total size of the buffer and # watch points is limited in order
653 * to prevent kernel abuse. (no bearing to the much smaller HW limitation
654 * which is enforced by dbgdev module)
655 * please also note that the watch address itself are not "copied from user",
656 * since it be set into the HW in user mode values.
659 static int kfd_ioctl_dbg_address_watch(struct file *filep,
660 struct kfd_process *p, void *data)
662 struct kfd_ioctl_dbg_address_watch_args *args = data;
664 struct dbg_address_watch_info aw_info;
665 unsigned char *args_buff;
667 void __user *cmd_from_user;
668 uint64_t watch_mask_value = 0;
669 unsigned int args_idx = 0;
671 memset((void *) &aw_info, 0, sizeof(struct dbg_address_watch_info));
673 dev = kfd_device_by_id(args->gpu_id);
677 if (dev->device_info->asic_family == CHIP_CARRIZO) {
678 pr_debug("kfd_ioctl_dbg_wave_control not supported on CZ\n");
682 cmd_from_user = (void __user *) args->content_ptr;
684 /* Validate arguments */
686 if ((args->buf_size_in_bytes > MAX_ALLOWED_AW_BUFF_SIZE) ||
687 (args->buf_size_in_bytes <= sizeof(*args) + sizeof(int) * 2) ||
688 (cmd_from_user == NULL))
691 /* this is the actual buffer to work with */
692 args_buff = memdup_user(cmd_from_user,
693 args->buf_size_in_bytes - sizeof(*args));
694 if (IS_ERR(args_buff))
695 return PTR_ERR(args_buff);
699 aw_info.num_watch_points = *((uint32_t *)(&args_buff[args_idx]));
700 args_idx += sizeof(aw_info.num_watch_points);
702 aw_info.watch_mode = (enum HSA_DBG_WATCH_MODE *) &args_buff[args_idx];
703 args_idx += sizeof(enum HSA_DBG_WATCH_MODE) * aw_info.num_watch_points;
706 * set watch address base pointer to point on the array base
709 aw_info.watch_address = (uint64_t *) &args_buff[args_idx];
711 /* skip over the addresses buffer */
712 args_idx += sizeof(aw_info.watch_address) * aw_info.num_watch_points;
714 if (args_idx >= args->buf_size_in_bytes - sizeof(*args)) {
719 watch_mask_value = (uint64_t) args_buff[args_idx];
721 if (watch_mask_value > 0) {
723 * There is an array of masks.
724 * set watch mask base pointer to point on the array base
727 aw_info.watch_mask = (uint64_t *) &args_buff[args_idx];
729 /* skip over the masks buffer */
730 args_idx += sizeof(aw_info.watch_mask) *
731 aw_info.num_watch_points;
733 /* just the NULL mask, set to NULL and skip over it */
734 aw_info.watch_mask = NULL;
735 args_idx += sizeof(aw_info.watch_mask);
738 if (args_idx >= args->buf_size_in_bytes - sizeof(args)) {
743 /* Currently HSA Event is not supported for DBG */
744 aw_info.watch_event = NULL;
746 mutex_lock(kfd_get_dbgmgr_mutex());
748 status = kfd_dbgmgr_address_watch(dev->dbgmgr, &aw_info);
750 mutex_unlock(kfd_get_dbgmgr_mutex());
758 /* Parse and generate fixed size data structure for wave control */
759 static int kfd_ioctl_dbg_wave_control(struct file *filep,
760 struct kfd_process *p, void *data)
762 struct kfd_ioctl_dbg_wave_control_args *args = data;
764 struct dbg_wave_control_info wac_info;
765 unsigned char *args_buff;
766 uint32_t computed_buff_size;
768 void __user *cmd_from_user;
769 unsigned int args_idx = 0;
771 memset((void *) &wac_info, 0, sizeof(struct dbg_wave_control_info));
773 /* we use compact form, independent of the packing attribute value */
774 computed_buff_size = sizeof(*args) +
775 sizeof(wac_info.mode) +
776 sizeof(wac_info.operand) +
777 sizeof(wac_info.dbgWave_msg.DbgWaveMsg) +
778 sizeof(wac_info.dbgWave_msg.MemoryVA) +
779 sizeof(wac_info.trapId);
781 dev = kfd_device_by_id(args->gpu_id);
785 if (dev->device_info->asic_family == CHIP_CARRIZO) {
786 pr_debug("kfd_ioctl_dbg_wave_control not supported on CZ\n");
790 /* input size must match the computed "compact" size */
791 if (args->buf_size_in_bytes != computed_buff_size) {
792 pr_debug("size mismatch, computed : actual %u : %u\n",
793 args->buf_size_in_bytes, computed_buff_size);
797 cmd_from_user = (void __user *) args->content_ptr;
799 if (cmd_from_user == NULL)
802 /* copy the entire buffer from user */
804 args_buff = memdup_user(cmd_from_user,
805 args->buf_size_in_bytes - sizeof(*args));
806 if (IS_ERR(args_buff))
807 return PTR_ERR(args_buff);
809 /* move ptr to the start of the "pay-load" area */
810 wac_info.process = p;
812 wac_info.operand = *((enum HSA_DBG_WAVEOP *)(&args_buff[args_idx]));
813 args_idx += sizeof(wac_info.operand);
815 wac_info.mode = *((enum HSA_DBG_WAVEMODE *)(&args_buff[args_idx]));
816 args_idx += sizeof(wac_info.mode);
818 wac_info.trapId = *((uint32_t *)(&args_buff[args_idx]));
819 args_idx += sizeof(wac_info.trapId);
821 wac_info.dbgWave_msg.DbgWaveMsg.WaveMsgInfoGen2.Value =
822 *((uint32_t *)(&args_buff[args_idx]));
823 wac_info.dbgWave_msg.MemoryVA = NULL;
825 mutex_lock(kfd_get_dbgmgr_mutex());
827 pr_debug("Calling dbg manager process %p, operand %u, mode %u, trapId %u, message %u\n",
828 wac_info.process, wac_info.operand,
829 wac_info.mode, wac_info.trapId,
830 wac_info.dbgWave_msg.DbgWaveMsg.WaveMsgInfoGen2.Value);
832 status = kfd_dbgmgr_wave_control(dev->dbgmgr, &wac_info);
834 pr_debug("Returned status of dbg manager is %ld\n", status);
836 mutex_unlock(kfd_get_dbgmgr_mutex());
843 static int kfd_ioctl_get_clock_counters(struct file *filep,
844 struct kfd_process *p, void *data)
846 struct kfd_ioctl_get_clock_counters_args *args = data;
849 dev = kfd_device_by_id(args->gpu_id);
851 /* Reading GPU clock counter from KGD */
852 args->gpu_clock_counter = amdgpu_amdkfd_get_gpu_clock_counter(dev->kgd);
854 /* Node without GPU resource */
855 args->gpu_clock_counter = 0;
857 /* No access to rdtsc. Using raw monotonic time */
858 args->cpu_clock_counter = ktime_get_raw_ns();
859 args->system_clock_counter = ktime_get_boottime_ns();
861 /* Since the counter is in nano-seconds we use 1GHz frequency */
862 args->system_clock_freq = 1000000000;
868 static int kfd_ioctl_get_process_apertures(struct file *filp,
869 struct kfd_process *p, void *data)
871 struct kfd_ioctl_get_process_apertures_args *args = data;
872 struct kfd_process_device_apertures *pAperture;
875 dev_dbg(kfd_device, "get apertures for PASID 0x%x", p->pasid);
877 args->num_of_nodes = 0;
879 mutex_lock(&p->mutex);
880 /* Run over all pdd of the process */
881 for (i = 0; i < p->n_pdds; i++) {
882 struct kfd_process_device *pdd = p->pdds[i];
885 &args->process_apertures[args->num_of_nodes];
886 pAperture->gpu_id = pdd->dev->id;
887 pAperture->lds_base = pdd->lds_base;
888 pAperture->lds_limit = pdd->lds_limit;
889 pAperture->gpuvm_base = pdd->gpuvm_base;
890 pAperture->gpuvm_limit = pdd->gpuvm_limit;
891 pAperture->scratch_base = pdd->scratch_base;
892 pAperture->scratch_limit = pdd->scratch_limit;
895 "node id %u\n", args->num_of_nodes);
897 "gpu id %u\n", pdd->dev->id);
899 "lds_base %llX\n", pdd->lds_base);
901 "lds_limit %llX\n", pdd->lds_limit);
903 "gpuvm_base %llX\n", pdd->gpuvm_base);
905 "gpuvm_limit %llX\n", pdd->gpuvm_limit);
907 "scratch_base %llX\n", pdd->scratch_base);
909 "scratch_limit %llX\n", pdd->scratch_limit);
911 if (++args->num_of_nodes >= NUM_OF_SUPPORTED_GPUS)
914 mutex_unlock(&p->mutex);
919 static int kfd_ioctl_get_process_apertures_new(struct file *filp,
920 struct kfd_process *p, void *data)
922 struct kfd_ioctl_get_process_apertures_new_args *args = data;
923 struct kfd_process_device_apertures *pa;
927 dev_dbg(kfd_device, "get apertures for PASID 0x%x", p->pasid);
929 if (args->num_of_nodes == 0) {
930 /* Return number of nodes, so that user space can alloacate
933 mutex_lock(&p->mutex);
934 args->num_of_nodes = p->n_pdds;
938 /* Fill in process-aperture information for all available
939 * nodes, but not more than args->num_of_nodes as that is
940 * the amount of memory allocated by user
942 pa = kzalloc((sizeof(struct kfd_process_device_apertures) *
943 args->num_of_nodes), GFP_KERNEL);
947 mutex_lock(&p->mutex);
950 args->num_of_nodes = 0;
955 /* Run over all pdd of the process */
956 for (i = 0; i < min(p->n_pdds, args->num_of_nodes); i++) {
957 struct kfd_process_device *pdd = p->pdds[i];
959 pa[i].gpu_id = pdd->dev->id;
960 pa[i].lds_base = pdd->lds_base;
961 pa[i].lds_limit = pdd->lds_limit;
962 pa[i].gpuvm_base = pdd->gpuvm_base;
963 pa[i].gpuvm_limit = pdd->gpuvm_limit;
964 pa[i].scratch_base = pdd->scratch_base;
965 pa[i].scratch_limit = pdd->scratch_limit;
968 "gpu id %u\n", pdd->dev->id);
970 "lds_base %llX\n", pdd->lds_base);
972 "lds_limit %llX\n", pdd->lds_limit);
974 "gpuvm_base %llX\n", pdd->gpuvm_base);
976 "gpuvm_limit %llX\n", pdd->gpuvm_limit);
978 "scratch_base %llX\n", pdd->scratch_base);
980 "scratch_limit %llX\n", pdd->scratch_limit);
982 mutex_unlock(&p->mutex);
984 args->num_of_nodes = i;
986 (void __user *)args->kfd_process_device_apertures_ptr,
988 (i * sizeof(struct kfd_process_device_apertures)));
990 return ret ? -EFAULT : 0;
993 mutex_unlock(&p->mutex);
997 static int kfd_ioctl_create_event(struct file *filp, struct kfd_process *p,
1000 struct kfd_ioctl_create_event_args *args = data;
1003 /* For dGPUs the event page is allocated in user mode. The
1004 * handle is passed to KFD with the first call to this IOCTL
1005 * through the event_page_offset field.
1007 if (args->event_page_offset) {
1008 struct kfd_dev *kfd;
1009 struct kfd_process_device *pdd;
1010 void *mem, *kern_addr;
1013 if (p->signal_page) {
1014 pr_err("Event page is already set\n");
1018 kfd = kfd_device_by_id(GET_GPU_ID(args->event_page_offset));
1020 pr_err("Getting device by id failed in %s\n", __func__);
1024 mutex_lock(&p->mutex);
1025 pdd = kfd_bind_process_to_device(kfd, p);
1031 mem = kfd_process_device_translate_handle(pdd,
1032 GET_IDR_HANDLE(args->event_page_offset));
1034 pr_err("Can't find BO, offset is 0x%llx\n",
1035 args->event_page_offset);
1039 mutex_unlock(&p->mutex);
1041 err = amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(kfd->kgd,
1042 mem, &kern_addr, &size);
1044 pr_err("Failed to map event page to kernel\n");
1048 err = kfd_event_page_set(p, kern_addr, size);
1050 pr_err("Failed to set event page\n");
1055 err = kfd_event_create(filp, p, args->event_type,
1056 args->auto_reset != 0, args->node_id,
1057 &args->event_id, &args->event_trigger_data,
1058 &args->event_page_offset,
1059 &args->event_slot_index);
1064 mutex_unlock(&p->mutex);
1068 static int kfd_ioctl_destroy_event(struct file *filp, struct kfd_process *p,
1071 struct kfd_ioctl_destroy_event_args *args = data;
1073 return kfd_event_destroy(p, args->event_id);
1076 static int kfd_ioctl_set_event(struct file *filp, struct kfd_process *p,
1079 struct kfd_ioctl_set_event_args *args = data;
1081 return kfd_set_event(p, args->event_id);
1084 static int kfd_ioctl_reset_event(struct file *filp, struct kfd_process *p,
1087 struct kfd_ioctl_reset_event_args *args = data;
1089 return kfd_reset_event(p, args->event_id);
1092 static int kfd_ioctl_wait_events(struct file *filp, struct kfd_process *p,
1095 struct kfd_ioctl_wait_events_args *args = data;
1098 err = kfd_wait_on_events(p, args->num_events,
1099 (void __user *)args->events_ptr,
1100 (args->wait_for_all != 0),
1101 args->timeout, &args->wait_result);
1105 static int kfd_ioctl_set_scratch_backing_va(struct file *filep,
1106 struct kfd_process *p, void *data)
1108 struct kfd_ioctl_set_scratch_backing_va_args *args = data;
1109 struct kfd_process_device *pdd;
1110 struct kfd_dev *dev;
1113 dev = kfd_device_by_id(args->gpu_id);
1117 mutex_lock(&p->mutex);
1119 pdd = kfd_bind_process_to_device(dev, p);
1122 goto bind_process_to_device_fail;
1125 pdd->qpd.sh_hidden_private_base = args->va_addr;
1127 mutex_unlock(&p->mutex);
1129 if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS &&
1130 pdd->qpd.vmid != 0 && dev->kfd2kgd->set_scratch_backing_va)
1131 dev->kfd2kgd->set_scratch_backing_va(
1132 dev->kgd, args->va_addr, pdd->qpd.vmid);
1136 bind_process_to_device_fail:
1137 mutex_unlock(&p->mutex);
1141 static int kfd_ioctl_get_tile_config(struct file *filep,
1142 struct kfd_process *p, void *data)
1144 struct kfd_ioctl_get_tile_config_args *args = data;
1145 struct kfd_dev *dev;
1146 struct tile_config config;
1149 dev = kfd_device_by_id(args->gpu_id);
1153 amdgpu_amdkfd_get_tile_config(dev->kgd, &config);
1155 args->gb_addr_config = config.gb_addr_config;
1156 args->num_banks = config.num_banks;
1157 args->num_ranks = config.num_ranks;
1159 if (args->num_tile_configs > config.num_tile_configs)
1160 args->num_tile_configs = config.num_tile_configs;
1161 err = copy_to_user((void __user *)args->tile_config_ptr,
1162 config.tile_config_ptr,
1163 args->num_tile_configs * sizeof(uint32_t));
1165 args->num_tile_configs = 0;
1169 if (args->num_macro_tile_configs > config.num_macro_tile_configs)
1170 args->num_macro_tile_configs =
1171 config.num_macro_tile_configs;
1172 err = copy_to_user((void __user *)args->macro_tile_config_ptr,
1173 config.macro_tile_config_ptr,
1174 args->num_macro_tile_configs * sizeof(uint32_t));
1176 args->num_macro_tile_configs = 0;
1183 static int kfd_ioctl_acquire_vm(struct file *filep, struct kfd_process *p,
1186 struct kfd_ioctl_acquire_vm_args *args = data;
1187 struct kfd_process_device *pdd;
1188 struct kfd_dev *dev;
1189 struct file *drm_file;
1192 dev = kfd_device_by_id(args->gpu_id);
1196 drm_file = fget(args->drm_fd);
1200 mutex_lock(&p->mutex);
1202 pdd = kfd_get_process_device_data(dev, p);
1208 if (pdd->drm_file) {
1209 ret = pdd->drm_file == drm_file ? 0 : -EBUSY;
1213 ret = kfd_process_device_init_vm(pdd, drm_file);
1216 /* On success, the PDD keeps the drm_file reference */
1217 mutex_unlock(&p->mutex);
1222 mutex_unlock(&p->mutex);
1227 bool kfd_dev_is_large_bar(struct kfd_dev *dev)
1229 struct kfd_local_mem_info mem_info;
1231 if (debug_largebar) {
1232 pr_debug("Simulate large-bar allocation on non large-bar machine\n");
1236 if (dev->use_iommu_v2)
1239 amdgpu_amdkfd_get_local_mem_info(dev->kgd, &mem_info);
1240 if (mem_info.local_mem_size_private == 0 &&
1241 mem_info.local_mem_size_public > 0)
1246 static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep,
1247 struct kfd_process *p, void *data)
1249 struct kfd_ioctl_alloc_memory_of_gpu_args *args = data;
1250 struct kfd_process_device *pdd;
1252 struct kfd_dev *dev;
1255 uint64_t offset = args->mmap_offset;
1256 uint32_t flags = args->flags;
1258 if (args->size == 0)
1261 dev = kfd_device_by_id(args->gpu_id);
1265 if ((flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) &&
1266 (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) &&
1267 !kfd_dev_is_large_bar(dev)) {
1268 pr_err("Alloc host visible vram on small bar is not allowed\n");
1272 mutex_lock(&p->mutex);
1274 pdd = kfd_bind_process_to_device(dev, p);
1280 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) {
1281 if (args->size != kfd_doorbell_process_slice(dev)) {
1285 offset = kfd_get_process_doorbells(pdd);
1286 } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) {
1287 if (args->size != PAGE_SIZE) {
1291 offset = amdgpu_amdkfd_get_mmio_remap_phys_addr(dev->kgd);
1298 err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
1299 dev->kgd, args->va_addr, args->size,
1300 pdd->vm, (struct kgd_mem **) &mem, &offset,
1306 idr_handle = kfd_process_device_create_obj_handle(pdd, mem);
1307 if (idr_handle < 0) {
1312 /* Update the VRAM usage count */
1313 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM)
1314 WRITE_ONCE(pdd->vram_usage, pdd->vram_usage + args->size);
1316 mutex_unlock(&p->mutex);
1318 args->handle = MAKE_HANDLE(args->gpu_id, idr_handle);
1319 args->mmap_offset = offset;
1321 /* MMIO is mapped through kfd device
1322 * Generate a kfd mmap offset
1324 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)
1325 args->mmap_offset = KFD_MMAP_TYPE_MMIO
1326 | KFD_MMAP_GPU_ID(args->gpu_id);
1331 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, (struct kgd_mem *)mem, NULL);
1333 mutex_unlock(&p->mutex);
1337 static int kfd_ioctl_free_memory_of_gpu(struct file *filep,
1338 struct kfd_process *p, void *data)
1340 struct kfd_ioctl_free_memory_of_gpu_args *args = data;
1341 struct kfd_process_device *pdd;
1343 struct kfd_dev *dev;
1347 dev = kfd_device_by_id(GET_GPU_ID(args->handle));
1351 mutex_lock(&p->mutex);
1353 pdd = kfd_get_process_device_data(dev, p);
1355 pr_err("Process device data doesn't exist\n");
1360 mem = kfd_process_device_translate_handle(
1361 pdd, GET_IDR_HANDLE(args->handle));
1367 ret = amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd,
1368 (struct kgd_mem *)mem, &size);
1370 /* If freeing the buffer failed, leave the handle in place for
1371 * clean-up during process tear-down.
1374 kfd_process_device_remove_obj_handle(
1375 pdd, GET_IDR_HANDLE(args->handle));
1377 WRITE_ONCE(pdd->vram_usage, pdd->vram_usage - size);
1380 mutex_unlock(&p->mutex);
1384 static int kfd_ioctl_map_memory_to_gpu(struct file *filep,
1385 struct kfd_process *p, void *data)
1387 struct kfd_ioctl_map_memory_to_gpu_args *args = data;
1388 struct kfd_process_device *pdd, *peer_pdd;
1390 struct kfd_dev *dev, *peer;
1393 uint32_t *devices_arr = NULL;
1395 dev = kfd_device_by_id(GET_GPU_ID(args->handle));
1399 if (!args->n_devices) {
1400 pr_debug("Device IDs array empty\n");
1403 if (args->n_success > args->n_devices) {
1404 pr_debug("n_success exceeds n_devices\n");
1408 devices_arr = kmalloc_array(args->n_devices, sizeof(*devices_arr),
1413 err = copy_from_user(devices_arr,
1414 (void __user *)args->device_ids_array_ptr,
1415 args->n_devices * sizeof(*devices_arr));
1418 goto copy_from_user_failed;
1421 mutex_lock(&p->mutex);
1423 pdd = kfd_bind_process_to_device(dev, p);
1426 goto bind_process_to_device_failed;
1429 mem = kfd_process_device_translate_handle(pdd,
1430 GET_IDR_HANDLE(args->handle));
1433 goto get_mem_obj_from_handle_failed;
1436 for (i = args->n_success; i < args->n_devices; i++) {
1437 peer = kfd_device_by_id(devices_arr[i]);
1439 pr_debug("Getting device by id failed for 0x%x\n",
1442 goto get_mem_obj_from_handle_failed;
1445 peer_pdd = kfd_bind_process_to_device(peer, p);
1446 if (IS_ERR(peer_pdd)) {
1447 err = PTR_ERR(peer_pdd);
1448 goto get_mem_obj_from_handle_failed;
1450 err = amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
1451 peer->kgd, (struct kgd_mem *)mem, peer_pdd->vm);
1453 pr_err("Failed to map to gpu %d/%d\n",
1454 i, args->n_devices);
1455 goto map_memory_to_gpu_failed;
1457 args->n_success = i+1;
1460 mutex_unlock(&p->mutex);
1462 err = amdgpu_amdkfd_gpuvm_sync_memory(dev->kgd, (struct kgd_mem *) mem, true);
1464 pr_debug("Sync memory failed, wait interrupted by user signal\n");
1465 goto sync_memory_failed;
1468 /* Flush TLBs after waiting for the page table updates to complete */
1469 for (i = 0; i < args->n_devices; i++) {
1470 peer = kfd_device_by_id(devices_arr[i]);
1471 if (WARN_ON_ONCE(!peer))
1473 peer_pdd = kfd_get_process_device_data(peer, p);
1474 if (WARN_ON_ONCE(!peer_pdd))
1476 kfd_flush_tlb(peer_pdd);
1483 bind_process_to_device_failed:
1484 get_mem_obj_from_handle_failed:
1485 map_memory_to_gpu_failed:
1486 mutex_unlock(&p->mutex);
1487 copy_from_user_failed:
1494 static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep,
1495 struct kfd_process *p, void *data)
1497 struct kfd_ioctl_unmap_memory_from_gpu_args *args = data;
1498 struct kfd_process_device *pdd, *peer_pdd;
1500 struct kfd_dev *dev, *peer;
1502 uint32_t *devices_arr = NULL, i;
1504 dev = kfd_device_by_id(GET_GPU_ID(args->handle));
1508 if (!args->n_devices) {
1509 pr_debug("Device IDs array empty\n");
1512 if (args->n_success > args->n_devices) {
1513 pr_debug("n_success exceeds n_devices\n");
1517 devices_arr = kmalloc_array(args->n_devices, sizeof(*devices_arr),
1522 err = copy_from_user(devices_arr,
1523 (void __user *)args->device_ids_array_ptr,
1524 args->n_devices * sizeof(*devices_arr));
1527 goto copy_from_user_failed;
1530 mutex_lock(&p->mutex);
1532 pdd = kfd_get_process_device_data(dev, p);
1535 goto bind_process_to_device_failed;
1538 mem = kfd_process_device_translate_handle(pdd,
1539 GET_IDR_HANDLE(args->handle));
1542 goto get_mem_obj_from_handle_failed;
1545 for (i = args->n_success; i < args->n_devices; i++) {
1546 peer = kfd_device_by_id(devices_arr[i]);
1549 goto get_mem_obj_from_handle_failed;
1552 peer_pdd = kfd_get_process_device_data(peer, p);
1555 goto get_mem_obj_from_handle_failed;
1557 err = amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
1558 peer->kgd, (struct kgd_mem *)mem, peer_pdd->vm);
1560 pr_err("Failed to unmap from gpu %d/%d\n",
1561 i, args->n_devices);
1562 goto unmap_memory_from_gpu_failed;
1564 args->n_success = i+1;
1568 mutex_unlock(&p->mutex);
1572 bind_process_to_device_failed:
1573 get_mem_obj_from_handle_failed:
1574 unmap_memory_from_gpu_failed:
1575 mutex_unlock(&p->mutex);
1576 copy_from_user_failed:
1581 static int kfd_ioctl_alloc_queue_gws(struct file *filep,
1582 struct kfd_process *p, void *data)
1585 struct kfd_ioctl_alloc_queue_gws_args *args = data;
1587 struct kfd_dev *dev;
1589 mutex_lock(&p->mutex);
1590 q = pqm_get_user_queue(&p->pqm, args->queue_id);
1604 if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) {
1609 retval = pqm_set_gws(&p->pqm, args->queue_id, args->num_gws ? dev->gws : NULL);
1610 mutex_unlock(&p->mutex);
1612 args->first_gws = 0;
1616 mutex_unlock(&p->mutex);
1620 static int kfd_ioctl_get_dmabuf_info(struct file *filep,
1621 struct kfd_process *p, void *data)
1623 struct kfd_ioctl_get_dmabuf_info_args *args = data;
1624 struct kfd_dev *dev = NULL;
1625 struct kgd_dev *dma_buf_kgd;
1626 void *metadata_buffer = NULL;
1631 /* Find a KFD GPU device that supports the get_dmabuf_info query */
1632 for (i = 0; kfd_topology_enum_kfd_devices(i, &dev) == 0; i++)
1638 if (args->metadata_ptr) {
1639 metadata_buffer = kzalloc(args->metadata_size, GFP_KERNEL);
1640 if (!metadata_buffer)
1644 /* Get dmabuf info from KGD */
1645 r = amdgpu_amdkfd_get_dmabuf_info(dev->kgd, args->dmabuf_fd,
1646 &dma_buf_kgd, &args->size,
1647 metadata_buffer, args->metadata_size,
1648 &args->metadata_size, &flags);
1652 /* Reverse-lookup gpu_id from kgd pointer */
1653 dev = kfd_device_by_kgd(dma_buf_kgd);
1658 args->gpu_id = dev->id;
1659 args->flags = flags;
1661 /* Copy metadata buffer to user mode */
1662 if (metadata_buffer) {
1663 r = copy_to_user((void __user *)args->metadata_ptr,
1664 metadata_buffer, args->metadata_size);
1670 kfree(metadata_buffer);
1675 static int kfd_ioctl_import_dmabuf(struct file *filep,
1676 struct kfd_process *p, void *data)
1678 struct kfd_ioctl_import_dmabuf_args *args = data;
1679 struct kfd_process_device *pdd;
1680 struct dma_buf *dmabuf;
1681 struct kfd_dev *dev;
1687 dev = kfd_device_by_id(args->gpu_id);
1691 dmabuf = dma_buf_get(args->dmabuf_fd);
1693 return PTR_ERR(dmabuf);
1695 mutex_lock(&p->mutex);
1697 pdd = kfd_bind_process_to_device(dev, p);
1703 r = amdgpu_amdkfd_gpuvm_import_dmabuf(dev->kgd, dmabuf,
1704 args->va_addr, pdd->vm,
1705 (struct kgd_mem **)&mem, &size,
1710 idr_handle = kfd_process_device_create_obj_handle(pdd, mem);
1711 if (idr_handle < 0) {
1716 mutex_unlock(&p->mutex);
1717 dma_buf_put(dmabuf);
1719 args->handle = MAKE_HANDLE(args->gpu_id, idr_handle);
1724 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, (struct kgd_mem *)mem, NULL);
1726 mutex_unlock(&p->mutex);
1727 dma_buf_put(dmabuf);
1731 /* Handle requests for watching SMI events */
1732 static int kfd_ioctl_smi_events(struct file *filep,
1733 struct kfd_process *p, void *data)
1735 struct kfd_ioctl_smi_events_args *args = data;
1736 struct kfd_dev *dev;
1738 dev = kfd_device_by_id(args->gpuid);
1742 return kfd_smi_event_open(dev, &args->anon_fd);
1745 #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \
1746 [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \
1747 .cmd_drv = 0, .name = #ioctl}
1750 static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = {
1751 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_VERSION,
1752 kfd_ioctl_get_version, 0),
1754 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_QUEUE,
1755 kfd_ioctl_create_queue, 0),
1757 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_QUEUE,
1758 kfd_ioctl_destroy_queue, 0),
1760 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_MEMORY_POLICY,
1761 kfd_ioctl_set_memory_policy, 0),
1763 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_CLOCK_COUNTERS,
1764 kfd_ioctl_get_clock_counters, 0),
1766 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES,
1767 kfd_ioctl_get_process_apertures, 0),
1769 AMDKFD_IOCTL_DEF(AMDKFD_IOC_UPDATE_QUEUE,
1770 kfd_ioctl_update_queue, 0),
1772 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_EVENT,
1773 kfd_ioctl_create_event, 0),
1775 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_EVENT,
1776 kfd_ioctl_destroy_event, 0),
1778 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_EVENT,
1779 kfd_ioctl_set_event, 0),
1781 AMDKFD_IOCTL_DEF(AMDKFD_IOC_RESET_EVENT,
1782 kfd_ioctl_reset_event, 0),
1784 AMDKFD_IOCTL_DEF(AMDKFD_IOC_WAIT_EVENTS,
1785 kfd_ioctl_wait_events, 0),
1787 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_REGISTER,
1788 kfd_ioctl_dbg_register, 0),
1790 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_UNREGISTER,
1791 kfd_ioctl_dbg_unregister, 0),
1793 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_ADDRESS_WATCH,
1794 kfd_ioctl_dbg_address_watch, 0),
1796 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_WAVE_CONTROL,
1797 kfd_ioctl_dbg_wave_control, 0),
1799 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_SCRATCH_BACKING_VA,
1800 kfd_ioctl_set_scratch_backing_va, 0),
1802 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_TILE_CONFIG,
1803 kfd_ioctl_get_tile_config, 0),
1805 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_TRAP_HANDLER,
1806 kfd_ioctl_set_trap_handler, 0),
1808 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES_NEW,
1809 kfd_ioctl_get_process_apertures_new, 0),
1811 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ACQUIRE_VM,
1812 kfd_ioctl_acquire_vm, 0),
1814 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ALLOC_MEMORY_OF_GPU,
1815 kfd_ioctl_alloc_memory_of_gpu, 0),
1817 AMDKFD_IOCTL_DEF(AMDKFD_IOC_FREE_MEMORY_OF_GPU,
1818 kfd_ioctl_free_memory_of_gpu, 0),
1820 AMDKFD_IOCTL_DEF(AMDKFD_IOC_MAP_MEMORY_TO_GPU,
1821 kfd_ioctl_map_memory_to_gpu, 0),
1823 AMDKFD_IOCTL_DEF(AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU,
1824 kfd_ioctl_unmap_memory_from_gpu, 0),
1826 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_CU_MASK,
1827 kfd_ioctl_set_cu_mask, 0),
1829 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_QUEUE_WAVE_STATE,
1830 kfd_ioctl_get_queue_wave_state, 0),
1832 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_DMABUF_INFO,
1833 kfd_ioctl_get_dmabuf_info, 0),
1835 AMDKFD_IOCTL_DEF(AMDKFD_IOC_IMPORT_DMABUF,
1836 kfd_ioctl_import_dmabuf, 0),
1838 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ALLOC_QUEUE_GWS,
1839 kfd_ioctl_alloc_queue_gws, 0),
1841 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SMI_EVENTS,
1842 kfd_ioctl_smi_events, 0),
1845 #define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls)
1847 static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
1849 struct kfd_process *process;
1850 amdkfd_ioctl_t *func;
1851 const struct amdkfd_ioctl_desc *ioctl = NULL;
1852 unsigned int nr = _IOC_NR(cmd);
1853 char stack_kdata[128];
1855 unsigned int usize, asize;
1856 int retcode = -EINVAL;
1858 if (nr >= AMDKFD_CORE_IOCTL_COUNT)
1861 if ((nr >= AMDKFD_COMMAND_START) && (nr < AMDKFD_COMMAND_END)) {
1864 ioctl = &amdkfd_ioctls[nr];
1866 amdkfd_size = _IOC_SIZE(ioctl->cmd);
1867 usize = asize = _IOC_SIZE(cmd);
1868 if (amdkfd_size > asize)
1869 asize = amdkfd_size;
1875 dev_dbg(kfd_device, "ioctl cmd 0x%x (#0x%x), arg 0x%lx\n", cmd, nr, arg);
1877 /* Get the process struct from the filep. Only the process
1878 * that opened /dev/kfd can use the file descriptor. Child
1879 * processes need to create their own KFD device context.
1881 process = filep->private_data;
1882 if (process->lead_thread != current->group_leader) {
1883 dev_dbg(kfd_device, "Using KFD FD in wrong process\n");
1888 /* Do not trust userspace, use our own definition */
1891 if (unlikely(!func)) {
1892 dev_dbg(kfd_device, "no function\n");
1897 if (cmd & (IOC_IN | IOC_OUT)) {
1898 if (asize <= sizeof(stack_kdata)) {
1899 kdata = stack_kdata;
1901 kdata = kmalloc(asize, GFP_KERNEL);
1908 memset(kdata + usize, 0, asize - usize);
1912 if (copy_from_user(kdata, (void __user *)arg, usize) != 0) {
1916 } else if (cmd & IOC_OUT) {
1917 memset(kdata, 0, usize);
1920 retcode = func(filep, process, kdata);
1923 if (copy_to_user((void __user *)arg, kdata, usize) != 0)
1928 dev_dbg(kfd_device, "invalid ioctl: pid=%d, cmd=0x%02x, nr=0x%02x\n",
1929 task_pid_nr(current), cmd, nr);
1931 if (kdata != stack_kdata)
1935 dev_dbg(kfd_device, "ioctl cmd (#0x%x), arg 0x%lx, ret = %d\n",
1941 static int kfd_mmio_mmap(struct kfd_dev *dev, struct kfd_process *process,
1942 struct vm_area_struct *vma)
1944 phys_addr_t address;
1947 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1950 address = amdgpu_amdkfd_get_mmio_remap_phys_addr(dev->kgd);
1952 vma->vm_flags |= VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_NORESERVE |
1953 VM_DONTDUMP | VM_PFNMAP;
1955 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1957 pr_debug("pasid 0x%x mapping mmio page\n"
1958 " target user address == 0x%08llX\n"
1959 " physical address == 0x%08llX\n"
1960 " vm_flags == 0x%04lX\n"
1961 " size == 0x%04lX\n",
1962 process->pasid, (unsigned long long) vma->vm_start,
1963 address, vma->vm_flags, PAGE_SIZE);
1965 ret = io_remap_pfn_range(vma,
1967 address >> PAGE_SHIFT,
1974 static int kfd_mmap(struct file *filp, struct vm_area_struct *vma)
1976 struct kfd_process *process;
1977 struct kfd_dev *dev = NULL;
1978 unsigned long mmap_offset;
1979 unsigned int gpu_id;
1981 process = kfd_get_process(current);
1982 if (IS_ERR(process))
1983 return PTR_ERR(process);
1985 mmap_offset = vma->vm_pgoff << PAGE_SHIFT;
1986 gpu_id = KFD_MMAP_GET_GPU_ID(mmap_offset);
1988 dev = kfd_device_by_id(gpu_id);
1990 switch (mmap_offset & KFD_MMAP_TYPE_MASK) {
1991 case KFD_MMAP_TYPE_DOORBELL:
1994 return kfd_doorbell_mmap(dev, process, vma);
1996 case KFD_MMAP_TYPE_EVENTS:
1997 return kfd_event_mmap(process, vma);
1999 case KFD_MMAP_TYPE_RESERVED_MEM:
2002 return kfd_reserved_mem_mmap(dev, process, vma);
2003 case KFD_MMAP_TYPE_MMIO:
2006 return kfd_mmio_mmap(dev, process, vma);