drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_vcn.h"
  28 #include "soc15.h"
  29 #include "soc15d.h"
  30 #include "amdgpu_pm.h"
  31 #include "amdgpu_psp.h"
  32 #include "mmsch_v2_0.h"
  33
  34 #include "vcn/vcn_2_0_0_offset.h"
  35 #include "vcn/vcn_2_0_0_sh_mask.h"
  36 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
  37
  38 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET                        0x1fd
  39 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET                    0x503
  40 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET                  0x504
  41 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET                  0x505
  42 #define mmUVD_NO_OP_INTERNAL_OFFSET                             0x53f
  43 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET                       0x54a
  44 #define mmUVD_SCRATCH9_INTERNAL_OFFSET                          0xc01d
  45
  46 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET                   0x1e1
  47 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET         0x5a6
  48 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET          0x5a7
  49 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET                       0x1e2
  50
  51 static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
  52 static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev);
  53 static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev);
  54 static int vcn_v2_0_set_powergating_state(void *handle,
  55                                 enum amd_powergating_state state);
  56 static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
  57                                 int inst_idx, struct dpg_pause_state *new_state);
  58 static int vcn_v2_0_start_sriov(struct amdgpu_device *adev);
  59 /**
  60  * vcn_v2_0_early_init - set function pointers
  61  *
  62  * @handle: amdgpu_device pointer
  63  *
  64  * Set ring and irq function pointers
  65  */
  66 static int vcn_v2_0_early_init(void *handle)
  67 {
  68         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  69
  70         adev->vcn.num_vcn_inst = 1;
  71         if (amdgpu_sriov_vf(adev))
  72                 adev->vcn.num_enc_rings = 1;
  73         else
  74                 adev->vcn.num_enc_rings = 2;
  75
  76         vcn_v2_0_set_dec_ring_funcs(adev);
  77         vcn_v2_0_set_enc_ring_funcs(adev);
  78         vcn_v2_0_set_irq_funcs(adev);
  79
  80         return 0;
  81 }
  82
  83 /**
  84  * vcn_v2_0_sw_init - sw init for VCN block
  85  *
  86  * @handle: amdgpu_device pointer
  87  *
  88  * Load firmware and sw initialization
  89  */
  90 static int vcn_v2_0_sw_init(void *handle)
  91 {
  92         struct amdgpu_ring *ring;
  93         int i, r;
  94         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  95
  96         /* VCN DEC TRAP */
  97         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
  98                               VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT,
  99                               &adev->vcn.inst->irq);
 100         if (r)
 101                 return r;
 102
 103         /* VCN ENC TRAP */
 104         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 105                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
 106                                       i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
 107                                       &adev->vcn.inst->irq);
 108                 if (r)
 109                         return r;
 110         }
 111
 112         r = amdgpu_vcn_sw_init(adev);
 113         if (r)
 114                 return r;
 115
 116         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 117                 const struct common_firmware_header *hdr;
 118                 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
 119                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
 120                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
 121                 adev->firmware.fw_size +=
 122                         ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
 123                 DRM_INFO("PSP loading VCN firmware\n");
 124         }
 125
 126         r = amdgpu_vcn_resume(adev);
 127         if (r)
 128                 return r;
 129
 130         ring = &adev->vcn.inst->ring_dec;
 131
 132         ring->use_doorbell = true;
 133         ring->doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 << 1;
 134
 135         sprintf(ring->name, "vcn_dec");
 136         r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0);
 137         if (r)
 138                 return r;
 139
 140         adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
 141         adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
 142         adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
 143         adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
 144         adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
 145         adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
 146
 147         adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
 148         adev->vcn.inst->external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
 149         adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
 150         adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
 151         adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
 152         adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
 153         adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
 154         adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
 155         adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
 156         adev->vcn.inst->external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
 157
 158         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 159                 ring = &adev->vcn.inst->ring_enc[i];
 160                 ring->use_doorbell = true;
 161                 if (!amdgpu_sriov_vf(adev))
 162                         ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i;
 163                 else
 164                         ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + i;
 165                 sprintf(ring->name, "vcn_enc%d", i);
 166                 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0);
 167                 if (r)
 168                         return r;
 169         }
 170
 171         adev->vcn.pause_dpg_mode = vcn_v2_0_pause_dpg_mode;
 172
 173         r = amdgpu_virt_alloc_mm_table(adev);
 174         if (r)
 175                 return r;
 176
 177         return 0;
 178 }
 179
 180 /**
 181  * vcn_v2_0_sw_fini - sw fini for VCN block
 182  *
 183  * @handle: amdgpu_device pointer
 184  *
 185  * VCN suspend and free up sw allocation
 186  */
 187 static int vcn_v2_0_sw_fini(void *handle)
 188 {
 189         int r;
 190         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 191
 192         amdgpu_virt_free_mm_table(adev);
 193
 194         r = amdgpu_vcn_suspend(adev);
 195         if (r)
 196                 return r;
 197
 198         r = amdgpu_vcn_sw_fini(adev);
 199
 200         return r;
 201 }
 202
 203 /**
 204  * vcn_v2_0_hw_init - start and test VCN block
 205  *
 206  * @handle: amdgpu_device pointer
 207  *
 208  * Initialize the hardware, boot up the VCPU and do some testing
 209  */
 210 static int vcn_v2_0_hw_init(void *handle)
 211 {
 212         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 213         struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
 214         int i, r;
 215
 216         adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
 217                                              ring->doorbell_index, 0);
 218
 219         if (amdgpu_sriov_vf(adev))
 220                 vcn_v2_0_start_sriov(adev);
 221
 222         r = amdgpu_ring_test_helper(ring);
 223         if (r)
 224                 goto done;
 225
 226         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 227                 ring = &adev->vcn.inst->ring_enc[i];
 228                 r = amdgpu_ring_test_helper(ring);
 229                 if (r)
 230                         goto done;
 231         }
 232
 233 done:
 234         if (!r)
 235                 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
 236                         (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
 237
 238         return r;
 239 }
 240
 241 /**
 242  * vcn_v2_0_hw_fini - stop the hardware block
 243  *
 244  * @handle: amdgpu_device pointer
 245  *
 246  * Stop the VCN block, mark ring as not ready any more
 247  */
 248 static int vcn_v2_0_hw_fini(void *handle)
 249 {
 250         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 251         struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
 252         int i;
 253
 254         if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
 255             (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
 256               RREG32_SOC15(VCN, 0, mmUVD_STATUS)))
 257                 vcn_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
 258
 259         ring->sched.ready = false;
 260
 261         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 262                 ring = &adev->vcn.inst->ring_enc[i];
 263                 ring->sched.ready = false;
 264         }
 265
 266         return 0;
 267 }
 268
 269 /**
 270  * vcn_v2_0_suspend - suspend VCN block
 271  *
 272  * @handle: amdgpu_device pointer
 273  *
 274  * HW fini and suspend VCN block
 275  */
 276 static int vcn_v2_0_suspend(void *handle)
 277 {
 278         int r;
 279         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 280
 281         r = vcn_v2_0_hw_fini(adev);
 282         if (r)
 283                 return r;
 284
 285         r = amdgpu_vcn_suspend(adev);
 286
 287         return r;
 288 }
 289
 290 /**
 291  * vcn_v2_0_resume - resume VCN block
 292  *
 293  * @handle: amdgpu_device pointer
 294  *
 295  * Resume firmware and hw init VCN block
 296  */
 297 static int vcn_v2_0_resume(void *handle)
 298 {
 299         int r;
 300         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 301
 302         r = amdgpu_vcn_resume(adev);
 303         if (r)
 304                 return r;
 305
 306         r = vcn_v2_0_hw_init(adev);
 307
 308         return r;
 309 }
 310
 311 /**
 312  * vcn_v2_0_mc_resume - memory controller programming
 313  *
 314  * @adev: amdgpu_device pointer
 315  *
 316  * Let the VCN memory controller know it's offsets
 317  */
 318 static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
 319 {
 320         uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
 321         uint32_t offset;
 322
 323         /* cache window 0: fw */
 324         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 325                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 326                         (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
 327                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 328                         (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
 329                 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
 330                 offset = 0;
 331         } else {
 332                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 333                         lower_32_bits(adev->vcn.inst->gpu_addr));
 334                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 335                         upper_32_bits(adev->vcn.inst->gpu_addr));
 336                 offset = size;
 337                 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
 338                         AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 339         }
 340
 341         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
 342
 343         /* cache window 1: stack */
 344         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 345                 lower_32_bits(adev->vcn.inst->gpu_addr + offset));
 346         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 347                 upper_32_bits(adev->vcn.inst->gpu_addr + offset));
 348         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
 349         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
 350
 351         /* cache window 2: context */
 352         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 353                 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 354         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 355                 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 356         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
 357         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
 358
 359         WREG32_SOC15(UVD, 0, mmUVD_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 360 }
 361
 362 static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirect)
 363 {
 364         uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
 365         uint32_t offset;
 366
 367         /* cache window 0: fw */
 368         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 369                 if (!indirect) {
 370                         WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 371                                 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 372                                 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect);
 373                         WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 374                                 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 375                                 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect);
 376                         WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 377                                 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
 378                 } else {
 379                         WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 380                                 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
 381                         WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 382                                 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
 383                         WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 384                                 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
 385                 }
 386                 offset = 0;
 387         } else {
 388                 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 389                         UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 390                         lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
 391                 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 392                         UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 393                         upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
 394                 offset = size;
 395                 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 396                         UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
 397                         AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
 398         }
 399
 400         if (!indirect)
 401                 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 402                         UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
 403         else
 404                 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 405                         UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
 406
 407         /* cache window 1: stack */
 408         if (!indirect) {
 409                 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 410                         UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
 411                         lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
 412                 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 413                         UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
 414                         upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
 415                 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 416                         UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
 417         } else {
 418                 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 419                         UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
 420                 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 421                         UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
 422                 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 423                         UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
 424         }
 425         WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 426                 UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
 427
 428         /* cache window 2: context */
 429         WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 430                 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
 431                 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
 432         WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 433                 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
 434                 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
 435         WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 436                 UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
 437         WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 438                 UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
 439
 440         /* non-cache window */
 441         WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 442                 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
 443         WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 444                 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
 445         WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 446                 UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
 447         WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 448                 UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
 449
 450         /* VCN global tiling registers */
 451         WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 452                 UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
 453 }
 454
 455 /**
 456  * vcn_v2_0_disable_clock_gating - disable VCN clock gating
 457  *
 458  * @adev: amdgpu_device pointer
 459  * @sw: enable SW clock gating
 460  *
 461  * Disable clock gating for VCN block
 462  */
 463 static void vcn_v2_0_disable_clock_gating(struct amdgpu_device *adev)
 464 {
 465         uint32_t data;
 466
 467         /* UVD disable CGC */
 468         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 469         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 470                 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 471         else
 472                 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 473         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 474         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 475         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 476
 477         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);
 478         data &= ~(UVD_CGC_GATE__SYS_MASK
 479                 | UVD_CGC_GATE__UDEC_MASK
 480                 | UVD_CGC_GATE__MPEG2_MASK
 481                 | UVD_CGC_GATE__REGS_MASK
 482                 | UVD_CGC_GATE__RBC_MASK
 483                 | UVD_CGC_GATE__LMI_MC_MASK
 484                 | UVD_CGC_GATE__LMI_UMC_MASK
 485                 | UVD_CGC_GATE__IDCT_MASK
 486                 | UVD_CGC_GATE__MPRD_MASK
 487                 | UVD_CGC_GATE__MPC_MASK
 488                 | UVD_CGC_GATE__LBSI_MASK
 489                 | UVD_CGC_GATE__LRBBM_MASK
 490                 | UVD_CGC_GATE__UDEC_RE_MASK
 491                 | UVD_CGC_GATE__UDEC_CM_MASK
 492                 | UVD_CGC_GATE__UDEC_IT_MASK
 493                 | UVD_CGC_GATE__UDEC_DB_MASK
 494                 | UVD_CGC_GATE__UDEC_MP_MASK
 495                 | UVD_CGC_GATE__WCB_MASK
 496                 | UVD_CGC_GATE__VCPU_MASK
 497                 | UVD_CGC_GATE__SCPU_MASK);
 498         WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);
 499
 500         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 501         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 502                 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 503                 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 504                 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 505                 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 506                 | UVD_CGC_CTRL__SYS_MODE_MASK
 507                 | UVD_CGC_CTRL__UDEC_MODE_MASK
 508                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 509                 | UVD_CGC_CTRL__REGS_MODE_MASK
 510                 | UVD_CGC_CTRL__RBC_MODE_MASK
 511                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 512                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 513                 | UVD_CGC_CTRL__IDCT_MODE_MASK
 514                 | UVD_CGC_CTRL__MPRD_MODE_MASK
 515                 | UVD_CGC_CTRL__MPC_MODE_MASK
 516                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 517                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 518                 | UVD_CGC_CTRL__WCB_MODE_MASK
 519                 | UVD_CGC_CTRL__VCPU_MODE_MASK
 520                 | UVD_CGC_CTRL__SCPU_MODE_MASK);
 521         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 522
 523         /* turn on */
 524         data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);
 525         data |= (UVD_SUVD_CGC_GATE__SRE_MASK
 526                 | UVD_SUVD_CGC_GATE__SIT_MASK
 527                 | UVD_SUVD_CGC_GATE__SMP_MASK
 528                 | UVD_SUVD_CGC_GATE__SCM_MASK
 529                 | UVD_SUVD_CGC_GATE__SDB_MASK
 530                 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
 531                 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
 532                 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
 533                 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
 534                 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
 535                 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
 536                 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
 537                 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
 538                 | UVD_SUVD_CGC_GATE__SCLR_MASK
 539                 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
 540                 | UVD_SUVD_CGC_GATE__ENT_MASK
 541                 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
 542                 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
 543                 | UVD_SUVD_CGC_GATE__SITE_MASK
 544                 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
 545                 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
 546                 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
 547                 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
 548                 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
 549         WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data);
 550
 551         data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
 552         data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 553                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 554                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 555                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 556                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 557                 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 558                 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 559                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 560                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 561                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 562         WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
 563 }
 564
 565 static void vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_device *adev,
 566                 uint8_t sram_sel, uint8_t indirect)
 567 {
 568         uint32_t reg_data = 0;
 569
 570         /* enable sw clock gating control */
 571         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 572                 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 573         else
 574                 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 575         reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 576         reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 577         reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
 578                  UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
 579                  UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
 580                  UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
 581                  UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
 582                  UVD_CGC_CTRL__SYS_MODE_MASK |
 583                  UVD_CGC_CTRL__UDEC_MODE_MASK |
 584                  UVD_CGC_CTRL__MPEG2_MODE_MASK |
 585                  UVD_CGC_CTRL__REGS_MODE_MASK |
 586                  UVD_CGC_CTRL__RBC_MODE_MASK |
 587                  UVD_CGC_CTRL__LMI_MC_MODE_MASK |
 588                  UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
 589                  UVD_CGC_CTRL__IDCT_MODE_MASK |
 590                  UVD_CGC_CTRL__MPRD_MODE_MASK |
 591                  UVD_CGC_CTRL__MPC_MODE_MASK |
 592                  UVD_CGC_CTRL__LBSI_MODE_MASK |
 593                  UVD_CGC_CTRL__LRBBM_MODE_MASK |
 594                  UVD_CGC_CTRL__WCB_MODE_MASK |
 595                  UVD_CGC_CTRL__VCPU_MODE_MASK |
 596                  UVD_CGC_CTRL__SCPU_MODE_MASK);
 597         WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 598                 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
 599
 600         /* turn off clock gating */
 601         WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 602                 UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);
 603
 604         /* turn on SUVD clock gating */
 605         WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 606                 UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
 607
 608         /* turn on sw mode in UVD_SUVD_CGC_CTRL */
 609         WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 610                 UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
 611 }
 612
 613 /**
 614  * vcn_v2_0_enable_clock_gating - enable VCN clock gating
 615  *
 616  * @adev: amdgpu_device pointer
 617  * @sw: enable SW clock gating
 618  *
 619  * Enable clock gating for VCN block
 620  */
 621 static void vcn_v2_0_enable_clock_gating(struct amdgpu_device *adev)
 622 {
 623         uint32_t data = 0;
 624
 625         /* enable UVD CGC */
 626         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 627         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 628                 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 629         else
 630                 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 631         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 632         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 633         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 634
 635         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 636         data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 637                 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 638                 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 639                 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 640                 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 641                 | UVD_CGC_CTRL__SYS_MODE_MASK
 642                 | UVD_CGC_CTRL__UDEC_MODE_MASK
 643                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 644                 | UVD_CGC_CTRL__REGS_MODE_MASK
 645                 | UVD_CGC_CTRL__RBC_MODE_MASK
 646                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 647                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 648                 | UVD_CGC_CTRL__IDCT_MODE_MASK
 649                 | UVD_CGC_CTRL__MPRD_MODE_MASK
 650                 | UVD_CGC_CTRL__MPC_MODE_MASK
 651                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 652                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 653                 | UVD_CGC_CTRL__WCB_MODE_MASK
 654                 | UVD_CGC_CTRL__VCPU_MODE_MASK
 655                 | UVD_CGC_CTRL__SCPU_MODE_MASK);
 656         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 657
 658         data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
 659         data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 660                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 661                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 662                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 663                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 664                 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 665                 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 666                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 667                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 668                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 669         WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
 670 }
 671
 672 static void vcn_v2_0_disable_static_power_gating(struct amdgpu_device *adev)
 673 {
 674         uint32_t data = 0;
 675         int ret;
 676
 677         if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
 678                 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 679                         | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 680                         | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 681                         | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 682                         | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 683                         | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
 684                         | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
 685                         | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 686                         | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 687                         | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
 688
 689                 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
 690                 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS,
 691                         UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0, 0xFFFFF, ret);
 692         } else {
 693                 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 694                         | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 695                         | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 696                         | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 697                         | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 698                         | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
 699                         | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
 700                         | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 701                         | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 702                         | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
 703                 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
 704                 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0,  0xFFFFF, ret);
 705         }
 706
 707         /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS,
 708          * UVDU_PWR_STATUS are 0 (power on) */
 709
 710         data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
 711         data &= ~0x103;
 712         if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
 713                 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON |
 714                         UVD_POWER_STATUS__UVD_PG_EN_MASK;
 715
 716         WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
 717 }
 718
 719 static void vcn_v2_0_enable_static_power_gating(struct amdgpu_device *adev)
 720 {
 721         uint32_t data = 0;
 722         int ret;
 723
 724         if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
 725                 /* Before power off, this indicator has to be turned on */
 726                 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
 727                 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
 728                 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
 729                 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
 730
 731
 732                 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 733                         | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 734                         | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 735                         | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 736                         | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 737                         | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
 738                         | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
 739                         | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 740                         | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 741                         | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
 742
 743                 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
 744
 745                 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
 746                         | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
 747                         | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
 748                         | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
 749                         | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
 750                         | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT
 751                         | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT
 752                         | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
 753                         | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
 754                         | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT);
 755                 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFF, ret);
 756         }
 757 }
 758
 759 static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)
 760 {
 761         struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
 762         uint32_t rb_bufsz, tmp;
 763
 764         vcn_v2_0_enable_static_power_gating(adev);
 765
 766         /* enable dynamic power gating mode */
 767         tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
 768         tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
 769         tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
 770         WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);
 771
 772         if (indirect)
 773                 adev->vcn.inst->dpg_sram_curr_addr = (uint32_t*)adev->vcn.inst->dpg_sram_cpu_addr;
 774
 775         /* enable clock gating */
 776         vcn_v2_0_clock_gating_dpg_mode(adev, 0, indirect);
 777
 778         /* enable VCPU clock */
 779         tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
 780         tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
 781         tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
 782         WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 783                 UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
 784
 785         /* disable master interupt */
 786         WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 787                 UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect);
 788
 789         /* setup mmUVD_LMI_CTRL */
 790         tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 791                 UVD_LMI_CTRL__REQ_MODE_MASK |
 792                 UVD_LMI_CTRL__CRC_RESET_MASK |
 793                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
 794                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 795                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 796                 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 797                 0x00100000L);
 798         WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 799                 UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);
 800
 801         WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 802                 UVD, 0, mmUVD_MPC_CNTL),
 803                 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
 804
 805         WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 806                 UVD, 0, mmUVD_MPC_SET_MUXA0),
 807                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
 808                  (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
 809                  (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
 810                  (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
 811
 812         WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 813                 UVD, 0, mmUVD_MPC_SET_MUXB0),
 814                 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
 815                  (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
 816                  (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
 817                  (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
 818
 819         WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 820                 UVD, 0, mmUVD_MPC_SET_MUX),
 821                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
 822                  (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
 823                  (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
 824
 825         vcn_v2_0_mc_resume_dpg_mode(adev, indirect);
 826
 827         WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 828                 UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
 829         WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 830                 UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
 831
 832         /* release VCPU reset to boot */
 833         WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 834                 UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect);
 835
 836         /* enable LMI MC and UMC channels */
 837         WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 838                 UVD, 0, mmUVD_LMI_CTRL2),
 839                 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 0, indirect);
 840
 841         /* enable master interrupt */
 842         WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
 843                 UVD, 0, mmUVD_MASTINT_EN),
 844                 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
 845
 846         if (indirect)
 847                 psp_update_vcn_sram(adev, 0, adev->vcn.inst->dpg_sram_gpu_addr,
 848                                     (uint32_t)((uintptr_t)adev->vcn.inst->dpg_sram_curr_addr -
 849                                                (uintptr_t)adev->vcn.inst->dpg_sram_cpu_addr));
 850
 851         /* force RBC into idle state */
 852         rb_bufsz = order_base_2(ring->ring_size);
 853         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
 854         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
 855         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 856         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
 857         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
 858         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
 859
 860         /* set the write pointer delay */
 861         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
 862
 863         /* set the wb address */
 864         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
 865                 (upper_32_bits(ring->gpu_addr) >> 2));
 866
 867         /* programm the RB_BASE for ring buffer */
 868         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
 869                 lower_32_bits(ring->gpu_addr));
 870         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
 871                 upper_32_bits(ring->gpu_addr));
 872
 873         /* Initialize the ring buffer's read and write pointers */
 874         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
 875
 876         WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
 877
 878         ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
 879         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
 880                 lower_32_bits(ring->wptr));
 881
 882         return 0;
 883 }
 884
 885 static int vcn_v2_0_start(struct amdgpu_device *adev)
 886 {
 887         struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
 888         uint32_t rb_bufsz, tmp;
 889         uint32_t lmi_swap_cntl;
 890         int i, j, r;
 891
 892         if (adev->pm.dpm_enabled)
 893                 amdgpu_dpm_enable_uvd(adev, true);
 894
 895         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
 896                 return vcn_v2_0_start_dpg_mode(adev, adev->vcn.indirect_sram);
 897
 898         vcn_v2_0_disable_static_power_gating(adev);
 899
 900         /* set uvd status busy */
 901         tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
 902         WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
 903
 904         /*SW clock gating */
 905         vcn_v2_0_disable_clock_gating(adev);
 906
 907         /* enable VCPU clock */
 908         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
 909                 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
 910
 911         /* disable master interrupt */
 912         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
 913                 ~UVD_MASTINT_EN__VCPU_EN_MASK);
 914
 915         /* setup mmUVD_LMI_CTRL */
 916         tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
 917         WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp |
 918                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 919                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
 920                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 921                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
 922
 923         /* setup mmUVD_MPC_CNTL */
 924         tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
 925         tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
 926         tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
 927         WREG32_SOC15(VCN, 0, mmUVD_MPC_CNTL, tmp);
 928
 929         /* setup UVD_MPC_SET_MUXA0 */
 930         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,
 931                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
 932                 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
 933                 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
 934                 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
 935
 936         /* setup UVD_MPC_SET_MUXB0 */
 937         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0,
 938                 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
 939                 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
 940                 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
 941                 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
 942
 943         /* setup mmUVD_MPC_SET_MUX */
 944         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX,
 945                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
 946                 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
 947                 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
 948
 949         vcn_v2_0_mc_resume(adev);
 950
 951         /* release VCPU reset to boot */
 952         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
 953                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 954
 955         /* enable LMI MC and UMC channels */
 956         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
 957                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 958
 959         tmp = RREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET);
 960         tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
 961         tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
 962         WREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET, tmp);
 963
 964         /* disable byte swapping */
 965         lmi_swap_cntl = 0;
 966 #ifdef __BIG_ENDIAN
 967         /* swap (8 in 32) RB and IB */
 968         lmi_swap_cntl = 0xa;
 969 #endif
 970         WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 971
 972         for (i = 0; i < 10; ++i) {
 973                 uint32_t status;
 974
 975                 for (j = 0; j < 100; ++j) {
 976                         status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
 977                         if (status & 2)
 978                                 break;
 979                         mdelay(10);
 980                 }
 981                 r = 0;
 982                 if (status & 2)
 983                         break;
 984
 985                 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
 986                 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
 987                         UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
 988                         ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 989                 mdelay(10);
 990                 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
 991                         ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 992                 mdelay(10);
 993                 r = -1;
 994         }
 995
 996         if (r) {
 997                 DRM_ERROR("VCN decode not responding, giving up!!!\n");
 998                 return r;
 999         }
1000
1001         /* enable master interrupt */
1002         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
1003                 UVD_MASTINT_EN__VCPU_EN_MASK,
1004                 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1005
1006         /* clear the busy bit of VCN_STATUS */
1007         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
1008                 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1009
1010         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_VMID, 0);
1011
1012         /* force RBC into idle state */
1013         rb_bufsz = order_base_2(ring->ring_size);
1014         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1015         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1016         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1017         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1018         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1019         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
1020
1021         /* programm the RB_BASE for ring buffer */
1022         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1023                 lower_32_bits(ring->gpu_addr));
1024         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1025                 upper_32_bits(ring->gpu_addr));
1026
1027         /* Initialize the ring buffer's read and write pointers */
1028         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
1029
1030         ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1031         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1032                         lower_32_bits(ring->wptr));
1033
1034         ring = &adev->vcn.inst->ring_enc[0];
1035         WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1036         WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1037         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1038         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1039         WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
1040
1041         ring = &adev->vcn.inst->ring_enc[1];
1042         WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1043         WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1044         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1045         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1046         WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
1047
1048         return 0;
1049 }
1050
1051 static int vcn_v2_0_stop_dpg_mode(struct amdgpu_device *adev)
1052 {
1053         int ret_code = 0;
1054         uint32_t tmp;
1055
1056         /* Wait for power status to be 1 */
1057         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,
1058                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1059
1060         /* wait for read ptr to be equal to write ptr */
1061         tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1062         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
1063
1064         tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1065         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF, ret_code);
1066
1067         tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1068         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
1069
1070         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,
1071                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1072
1073         /* disable dynamic power gating mode */
1074         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
1075                         ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1076
1077         return 0;
1078 }
1079
1080 static int vcn_v2_0_stop(struct amdgpu_device *adev)
1081 {
1082         uint32_t tmp;
1083         int r;
1084
1085         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1086                 r = vcn_v2_0_stop_dpg_mode(adev);
1087                 if (r)
1088                         return r;
1089                 goto power_off;
1090         }
1091
1092         /* wait for uvd idle */
1093         SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r);
1094         if (r)
1095                 return r;
1096
1097         tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1098                 UVD_LMI_STATUS__READ_CLEAN_MASK |
1099                 UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1100                 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1101         SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp, r);
1102         if (r)
1103                 return r;
1104
1105         /* stall UMC channel */
1106         tmp = RREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2);
1107         tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
1108         WREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2, tmp);
1109
1110         tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
1111                 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1112         SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp, r);
1113         if (r)
1114                 return r;
1115
1116         /* disable VCPU clock */
1117         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
1118                 ~(UVD_VCPU_CNTL__CLK_EN_MASK));
1119
1120         /* reset LMI UMC */
1121         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1122                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,
1123                 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
1124
1125         /* reset LMI */
1126         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1127                 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,
1128                 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
1129
1130         /* reset VCPU */
1131         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1132                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1133                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1134
1135         /* clear status */
1136         WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0);
1137
1138         vcn_v2_0_enable_clock_gating(adev);
1139         vcn_v2_0_enable_static_power_gating(adev);
1140
1141 power_off:
1142         if (adev->pm.dpm_enabled)
1143                 amdgpu_dpm_enable_uvd(adev, false);
1144
1145         return 0;
1146 }
1147
1148 static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
1149                                 int inst_idx, struct dpg_pause_state *new_state)
1150 {
1151         struct amdgpu_ring *ring;
1152         uint32_t reg_data = 0;
1153         int ret_code;
1154
1155         /* pause/unpause if state is changed */
1156         if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1157                 DRM_DEBUG("dpg pause state changed %d -> %d",
1158                         adev->vcn.inst[inst_idx].pause_state.fw_based,  new_state->fw_based);
1159                 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
1160                         (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1161
1162                 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1163                         ret_code = 0;
1164                         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 0x1,
1165                                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1166
1167                         if (!ret_code) {
1168                                 /* pause DPG */
1169                                 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1170                                 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1171
1172                                 /* wait for ACK */
1173                                 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
1174                                            UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1175                                            UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code);
1176
1177                                 /* Restore */
1178                                 ring = &adev->vcn.inst->ring_enc[0];
1179                                 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1180                                 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1181                                 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
1182                                 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1183                                 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1184
1185                                 ring = &adev->vcn.inst->ring_enc[1];
1186                                 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1187                                 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1188                                 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
1189                                 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1190                                 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1191
1192                                 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1193                                            RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
1194
1195                                 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1196                                            UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
1197                                            UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1198                         }
1199                 } else {
1200                         /* unpause dpg, no need to wait */
1201                         reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1202                         WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1203                 }
1204                 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1205         }
1206
1207         return 0;
1208 }
1209
1210 static bool vcn_v2_0_is_idle(void *handle)
1211 {
1212         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1213
1214         return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
1215 }
1216
1217 static int vcn_v2_0_wait_for_idle(void *handle)
1218 {
1219         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1220         int ret = 0;
1221
1222         SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
1223                 UVD_STATUS__IDLE, ret);
1224
1225         return ret;
1226 }
1227
1228 static int vcn_v2_0_set_clockgating_state(void *handle,
1229                                           enum amd_clockgating_state state)
1230 {
1231         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1232         bool enable = (state == AMD_CG_STATE_GATE);
1233
1234         if (enable) {
1235                 /* wait for STATUS to clear */
1236                 if (vcn_v2_0_is_idle(handle))
1237                         return -EBUSY;
1238                 vcn_v2_0_enable_clock_gating(adev);
1239         } else {
1240                 /* disable HW gating and enable Sw gating */
1241                 vcn_v2_0_disable_clock_gating(adev);
1242         }
1243         return 0;
1244 }
1245
1246 /**
1247  * vcn_v2_0_dec_ring_get_rptr - get read pointer
1248  *
1249  * @ring: amdgpu_ring pointer
1250  *
1251  * Returns the current hardware read pointer
1252  */
1253 static uint64_t vcn_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
1254 {
1255         struct amdgpu_device *adev = ring->adev;
1256
1257         return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1258 }
1259
1260 /**
1261  * vcn_v2_0_dec_ring_get_wptr - get write pointer
1262  *
1263  * @ring: amdgpu_ring pointer
1264  *
1265  * Returns the current hardware write pointer
1266  */
1267 static uint64_t vcn_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
1268 {
1269         struct amdgpu_device *adev = ring->adev;
1270
1271         if (ring->use_doorbell)
1272                 return adev->wb.wb[ring->wptr_offs];
1273         else
1274                 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
1275 }
1276
1277 /**
1278  * vcn_v2_0_dec_ring_set_wptr - set write pointer
1279  *
1280  * @ring: amdgpu_ring pointer
1281  *
1282  * Commits the write pointer to the hardware
1283  */
1284 static void vcn_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
1285 {
1286         struct amdgpu_device *adev = ring->adev;
1287
1288         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1289                 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2,
1290                         lower_32_bits(ring->wptr) | 0x80000000);
1291
1292         if (ring->use_doorbell) {
1293                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1294                 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1295         } else {
1296                 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1297         }
1298 }
1299
1300 /**
1301  * vcn_v2_0_dec_ring_insert_start - insert a start command
1302  *
1303  * @ring: amdgpu_ring pointer
1304  *
1305  * Write a start command to the ring.
1306  */
1307 void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)
1308 {
1309         struct amdgpu_device *adev = ring->adev;
1310
1311         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1312         amdgpu_ring_write(ring, 0);
1313         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1314         amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));
1315 }
1316
1317 /**
1318  * vcn_v2_0_dec_ring_insert_end - insert a end command
1319  *
1320  * @ring: amdgpu_ring pointer
1321  *
1322  * Write a end command to the ring.
1323  */
1324 void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)
1325 {
1326         struct amdgpu_device *adev = ring->adev;
1327
1328         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1329         amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1));
1330 }
1331
1332 /**
1333  * vcn_v2_0_dec_ring_insert_nop - insert a nop command
1334  *
1335  * @ring: amdgpu_ring pointer
1336  *
1337  * Write a nop command to the ring.
1338  */
1339 void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1340 {
1341         struct amdgpu_device *adev = ring->adev;
1342         int i;
1343
1344         WARN_ON(ring->wptr % 2 || count % 2);
1345
1346         for (i = 0; i < count / 2; i++) {
1347                 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.nop, 0));
1348                 amdgpu_ring_write(ring, 0);
1349         }
1350 }
1351
1352 /**
1353  * vcn_v2_0_dec_ring_emit_fence - emit an fence & trap command
1354  *
1355  * @ring: amdgpu_ring pointer
1356  * @fence: fence to emit
1357  *
1358  * Write a fence and a trap command to the ring.
1359  */
1360 void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1361                                 unsigned flags)
1362 {
1363         struct amdgpu_device *adev = ring->adev;
1364
1365         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1366         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.context_id, 0));
1367         amdgpu_ring_write(ring, seq);
1368
1369         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1370         amdgpu_ring_write(ring, addr & 0xffffffff);
1371
1372         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1373         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1374
1375         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1376         amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_FENCE << 1));
1377
1378         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1379         amdgpu_ring_write(ring, 0);
1380
1381         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1382         amdgpu_ring_write(ring, 0);
1383
1384         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1385
1386         amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_TRAP << 1));
1387 }
1388
1389 /**
1390  * vcn_v2_0_dec_ring_emit_ib - execute indirect buffer
1391  *
1392  * @ring: amdgpu_ring pointer
1393  * @ib: indirect buffer to execute
1394  *
1395  * Write ring commands to execute the indirect buffer
1396  */
1397 void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
1398                                struct amdgpu_job *job,
1399                                struct amdgpu_ib *ib,
1400                                uint32_t flags)
1401 {
1402         struct amdgpu_device *adev = ring->adev;
1403         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1404
1405         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_vmid, 0));
1406         amdgpu_ring_write(ring, vmid);
1407
1408         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_low, 0));
1409         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1410         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_high, 0));
1411         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1412         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_size, 0));
1413         amdgpu_ring_write(ring, ib->length_dw);
1414 }
1415
1416 void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1417                                 uint32_t val, uint32_t mask)
1418 {
1419         struct amdgpu_device *adev = ring->adev;
1420
1421         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1422         amdgpu_ring_write(ring, reg << 2);
1423
1424         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1425         amdgpu_ring_write(ring, val);
1426
1427         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.gp_scratch8, 0));
1428         amdgpu_ring_write(ring, mask);
1429
1430         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1431
1432         amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_REG_READ_COND_WAIT << 1));
1433 }
1434
1435 void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
1436                                 unsigned vmid, uint64_t pd_addr)
1437 {
1438         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1439         uint32_t data0, data1, mask;
1440
1441         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1442
1443         /* wait for register write */
1444         data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
1445         data1 = lower_32_bits(pd_addr);
1446         mask = 0xffffffff;
1447         vcn_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
1448 }
1449
1450 void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
1451                                 uint32_t reg, uint32_t val)
1452 {
1453         struct amdgpu_device *adev = ring->adev;
1454
1455         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1456         amdgpu_ring_write(ring, reg << 2);
1457
1458         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1459         amdgpu_ring_write(ring, val);
1460
1461         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1462
1463         amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_WRITE_REG << 1));
1464 }
1465
1466 /**
1467  * vcn_v2_0_enc_ring_get_rptr - get enc read pointer
1468  *
1469  * @ring: amdgpu_ring pointer
1470  *
1471  * Returns the current hardware enc read pointer
1472  */
1473 static uint64_t vcn_v2_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
1474 {
1475         struct amdgpu_device *adev = ring->adev;
1476
1477         if (ring == &adev->vcn.inst->ring_enc[0])
1478                 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
1479         else
1480                 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
1481 }
1482
1483  /**
1484  * vcn_v2_0_enc_ring_get_wptr - get enc write pointer
1485  *
1486  * @ring: amdgpu_ring pointer
1487  *
1488  * Returns the current hardware enc write pointer
1489  */
1490 static uint64_t vcn_v2_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
1491 {
1492         struct amdgpu_device *adev = ring->adev;
1493
1494         if (ring == &adev->vcn.inst->ring_enc[0]) {
1495                 if (ring->use_doorbell)
1496                         return adev->wb.wb[ring->wptr_offs];
1497                 else
1498                         return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1499         } else {
1500                 if (ring->use_doorbell)
1501                         return adev->wb.wb[ring->wptr_offs];
1502                 else
1503                         return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1504         }
1505 }
1506
1507  /**
1508  * vcn_v2_0_enc_ring_set_wptr - set enc write pointer
1509  *
1510  * @ring: amdgpu_ring pointer
1511  *
1512  * Commits the enc write pointer to the hardware
1513  */
1514 static void vcn_v2_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
1515 {
1516         struct amdgpu_device *adev = ring->adev;
1517
1518         if (ring == &adev->vcn.inst->ring_enc[0]) {
1519                 if (ring->use_doorbell) {
1520                         adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1521                         WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1522                 } else {
1523                         WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1524                 }
1525         } else {
1526                 if (ring->use_doorbell) {
1527                         adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1528                         WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1529                 } else {
1530                         WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1531                 }
1532         }
1533 }
1534
1535 /**
1536  * vcn_v2_0_enc_ring_emit_fence - emit an enc fence & trap command
1537  *
1538  * @ring: amdgpu_ring pointer
1539  * @fence: fence to emit
1540  *
1541  * Write enc a fence and a trap command to the ring.
1542  */
1543 void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1544                                 u64 seq, unsigned flags)
1545 {
1546         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1547
1548         amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE);
1549         amdgpu_ring_write(ring, addr);
1550         amdgpu_ring_write(ring, upper_32_bits(addr));
1551         amdgpu_ring_write(ring, seq);
1552         amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP);
1553 }
1554
1555 void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1556 {
1557         amdgpu_ring_write(ring, VCN_ENC_CMD_END);
1558 }
1559
1560 /**
1561  * vcn_v2_0_enc_ring_emit_ib - enc execute indirect buffer
1562  *
1563  * @ring: amdgpu_ring pointer
1564  * @ib: indirect buffer to execute
1565  *
1566  * Write enc ring commands to execute the indirect buffer
1567  */
1568 void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1569                                struct amdgpu_job *job,
1570                                struct amdgpu_ib *ib,
1571                                uint32_t flags)
1572 {
1573         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1574
1575         amdgpu_ring_write(ring, VCN_ENC_CMD_IB);
1576         amdgpu_ring_write(ring, vmid);
1577         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1578         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1579         amdgpu_ring_write(ring, ib->length_dw);
1580 }
1581
1582 void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1583                                 uint32_t val, uint32_t mask)
1584 {
1585         amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
1586         amdgpu_ring_write(ring, reg << 2);
1587         amdgpu_ring_write(ring, mask);
1588         amdgpu_ring_write(ring, val);
1589 }
1590
1591 void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1592                                 unsigned int vmid, uint64_t pd_addr)
1593 {
1594         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1595
1596         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1597
1598         /* wait for reg writes */
1599         vcn_v2_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2,
1600                                         lower_32_bits(pd_addr), 0xffffffff);
1601 }
1602
1603 void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
1604 {
1605         amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1606         amdgpu_ring_write(ring, reg << 2);
1607         amdgpu_ring_write(ring, val);
1608 }
1609
1610 static int vcn_v2_0_set_interrupt_state(struct amdgpu_device *adev,
1611                                         struct amdgpu_irq_src *source,
1612                                         unsigned type,
1613                                         enum amdgpu_interrupt_state state)
1614 {
1615         return 0;
1616 }
1617
1618 static int vcn_v2_0_process_interrupt(struct amdgpu_device *adev,
1619                                       struct amdgpu_irq_src *source,
1620                                       struct amdgpu_iv_entry *entry)
1621 {
1622         DRM_DEBUG("IH: VCN TRAP\n");
1623
1624         switch (entry->src_id) {
1625         case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT:
1626                 amdgpu_fence_process(&adev->vcn.inst->ring_dec);
1627                 break;
1628         case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
1629                 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]);
1630                 break;
1631         case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
1632                 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);
1633                 break;
1634         default:
1635                 DRM_ERROR("Unhandled interrupt: %d %d\n",
1636                           entry->src_id, entry->src_data[0]);
1637                 break;
1638         }
1639
1640         return 0;
1641 }
1642
1643 int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring)
1644 {
1645         struct amdgpu_device *adev = ring->adev;
1646         uint32_t tmp = 0;
1647         unsigned i;
1648         int r;
1649
1650         if (amdgpu_sriov_vf(adev))
1651                 return 0;
1652
1653         WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
1654         r = amdgpu_ring_alloc(ring, 4);
1655         if (r)
1656                 return r;
1657         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1658         amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));
1659         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));
1660         amdgpu_ring_write(ring, 0xDEADBEEF);
1661         amdgpu_ring_commit(ring);
1662         for (i = 0; i < adev->usec_timeout; i++) {
1663                 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
1664                 if (tmp == 0xDEADBEEF)
1665                         break;
1666                 udelay(1);
1667         }
1668
1669         if (i >= adev->usec_timeout)
1670                 r = -ETIMEDOUT;
1671
1672         return r;
1673 }
1674
1675
1676 static int vcn_v2_0_set_powergating_state(void *handle,
1677                                           enum amd_powergating_state state)
1678 {
1679         /* This doesn't actually powergate the VCN block.
1680          * That's done in the dpm code via the SMC.  This
1681          * just re-inits the block as necessary.  The actual
1682          * gating still happens in the dpm code.  We should
1683          * revisit this when there is a cleaner line between
1684          * the smc and the hw blocks
1685          */
1686         int ret;
1687         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1688
1689         if (state == adev->vcn.cur_state)
1690                 return 0;
1691
1692         if (state == AMD_PG_STATE_GATE)
1693                 ret = vcn_v2_0_stop(adev);
1694         else
1695                 ret = vcn_v2_0_start(adev);
1696
1697         if (!ret)
1698                 adev->vcn.cur_state = state;
1699         return ret;
1700 }
1701
1702 static int vcn_v2_0_start_mmsch(struct amdgpu_device *adev,
1703                                 struct amdgpu_mm_table *table)
1704 {
1705         uint32_t data = 0, loop;
1706         uint64_t addr = table->gpu_addr;
1707         struct mmsch_v2_0_init_header *header;
1708         uint32_t size;
1709         int i;
1710
1711         header = (struct mmsch_v2_0_init_header *)table->cpu_addr;
1712         size = header->header_size + header->vcn_table_size;
1713
1714         /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr
1715          * of memory descriptor location
1716          */
1717         WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));
1718         WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));
1719
1720         /* 2, update vmid of descriptor */
1721         data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID);
1722         data &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
1723         /* use domain0 for MM scheduler */
1724         data |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
1725         WREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID, data);
1726
1727         /* 3, notify mmsch about the size of this descriptor */
1728         WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_SIZE, size);
1729
1730         /* 4, set resp to zero */
1731         WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP, 0);
1732
1733         adev->vcn.inst->ring_dec.wptr = 0;
1734         adev->vcn.inst->ring_dec.wptr_old = 0;
1735         vcn_v2_0_dec_ring_set_wptr(&adev->vcn.inst->ring_dec);
1736
1737         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
1738                 adev->vcn.inst->ring_enc[i].wptr = 0;
1739                 adev->vcn.inst->ring_enc[i].wptr_old = 0;
1740                 vcn_v2_0_enc_ring_set_wptr(&adev->vcn.inst->ring_enc[i]);
1741         }
1742
1743         /* 5, kick off the initialization and wait until
1744          * VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero
1745          */
1746         WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001);
1747
1748         data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP);
1749         loop = 1000;
1750         while ((data & 0x10000002) != 0x10000002) {
1751                 udelay(10);
1752                 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP);
1753                 loop--;
1754                 if (!loop)
1755                         break;
1756         }
1757
1758         if (!loop) {
1759                 DRM_ERROR("failed to init MMSCH, " \
1760                         "mmMMSCH_VF_MAILBOX_RESP = 0x%08x\n", data);
1761                 return -EBUSY;
1762         }
1763
1764         return 0;
1765 }
1766
1767 static int vcn_v2_0_start_sriov(struct amdgpu_device *adev)
1768 {
1769         int r;
1770         uint32_t tmp;
1771         struct amdgpu_ring *ring;
1772         uint32_t offset, size;
1773         uint32_t table_size = 0;
1774         struct mmsch_v2_0_cmd_direct_write direct_wt = { {0} };
1775         struct mmsch_v2_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} };
1776         struct mmsch_v2_0_cmd_direct_polling direct_poll = { {0} };
1777         struct mmsch_v2_0_cmd_end end = { {0} };
1778         struct mmsch_v2_0_init_header *header;
1779         uint32_t *init_table = adev->virt.mm_table.cpu_addr;
1780         uint8_t i = 0;
1781
1782         header = (struct mmsch_v2_0_init_header *)init_table;
1783         direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;
1784         direct_rd_mod_wt.cmd_header.command_type =
1785                 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
1786         direct_poll.cmd_header.command_type =
1787                 MMSCH_COMMAND__DIRECT_REG_POLLING;
1788         end.cmd_header.command_type = MMSCH_COMMAND__END;
1789
1790         if (header->vcn_table_offset == 0 && header->vcn_table_size == 0) {
1791                 header->version = MMSCH_VERSION;
1792                 header->header_size = sizeof(struct mmsch_v2_0_init_header) >> 2;
1793
1794                 header->vcn_table_offset = header->header_size;
1795
1796                 init_table += header->vcn_table_offset;
1797
1798                 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
1799
1800                 MMSCH_V2_0_INSERT_DIRECT_RD_MOD_WT(
1801                         SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
1802                         0xFFFFFFFF, 0x00000004);
1803
1804                 /* mc resume*/
1805                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1806                         tmp = AMDGPU_UCODE_ID_VCN;
1807                         MMSCH_V2_0_INSERT_DIRECT_WT(
1808                                 SOC15_REG_OFFSET(UVD, i,
1809                                         mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1810                                 adev->firmware.ucode[tmp].tmr_mc_addr_lo);
1811                         MMSCH_V2_0_INSERT_DIRECT_WT(
1812                                 SOC15_REG_OFFSET(UVD, i,
1813                                         mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1814                                 adev->firmware.ucode[tmp].tmr_mc_addr_hi);
1815                         offset = 0;
1816                 } else {
1817                         MMSCH_V2_0_INSERT_DIRECT_WT(
1818                                 SOC15_REG_OFFSET(UVD, i,
1819                                         mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1820                                 lower_32_bits(adev->vcn.inst->gpu_addr));
1821                         MMSCH_V2_0_INSERT_DIRECT_WT(
1822                                 SOC15_REG_OFFSET(UVD, i,
1823                                         mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1824                                 upper_32_bits(adev->vcn.inst->gpu_addr));
1825                         offset = size;
1826                 }
1827
1828                 MMSCH_V2_0_INSERT_DIRECT_WT(
1829                         SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0),
1830                         0);
1831                 MMSCH_V2_0_INSERT_DIRECT_WT(
1832                         SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0),
1833                         size);
1834
1835                 MMSCH_V2_0_INSERT_DIRECT_WT(
1836                         SOC15_REG_OFFSET(UVD, i,
1837                                 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
1838                         lower_32_bits(adev->vcn.inst->gpu_addr + offset));
1839                 MMSCH_V2_0_INSERT_DIRECT_WT(
1840                         SOC15_REG_OFFSET(UVD, i,
1841                                 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
1842                         upper_32_bits(adev->vcn.inst->gpu_addr + offset));
1843                 MMSCH_V2_0_INSERT_DIRECT_WT(
1844                         SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1),
1845                         0);
1846                 MMSCH_V2_0_INSERT_DIRECT_WT(
1847                         SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1),
1848                         AMDGPU_VCN_STACK_SIZE);
1849
1850                 MMSCH_V2_0_INSERT_DIRECT_WT(
1851                         SOC15_REG_OFFSET(UVD, i,
1852                                 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
1853                         lower_32_bits(adev->vcn.inst->gpu_addr + offset +
1854                                 AMDGPU_VCN_STACK_SIZE));
1855                 MMSCH_V2_0_INSERT_DIRECT_WT(
1856                         SOC15_REG_OFFSET(UVD, i,
1857                                 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
1858                         upper_32_bits(adev->vcn.inst->gpu_addr + offset +
1859                                 AMDGPU_VCN_STACK_SIZE));
1860                 MMSCH_V2_0_INSERT_DIRECT_WT(
1861                         SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2),
1862                         0);
1863                 MMSCH_V2_0_INSERT_DIRECT_WT(
1864                         SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2),
1865                         AMDGPU_VCN_CONTEXT_SIZE);
1866
1867                 for (r = 0; r < adev->vcn.num_enc_rings; ++r) {
1868                         ring = &adev->vcn.inst->ring_enc[r];
1869                         ring->wptr = 0;
1870                         MMSCH_V2_0_INSERT_DIRECT_WT(
1871                                 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO),
1872                                 lower_32_bits(ring->gpu_addr));
1873                         MMSCH_V2_0_INSERT_DIRECT_WT(
1874                                 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI),
1875                                 upper_32_bits(ring->gpu_addr));
1876                         MMSCH_V2_0_INSERT_DIRECT_WT(
1877                                 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE),
1878                                 ring->ring_size / 4);
1879                 }
1880
1881                 ring = &adev->vcn.inst->ring_dec;
1882                 ring->wptr = 0;
1883                 MMSCH_V2_0_INSERT_DIRECT_WT(
1884                         SOC15_REG_OFFSET(UVD, i,
1885                                 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),
1886                         lower_32_bits(ring->gpu_addr));
1887                 MMSCH_V2_0_INSERT_DIRECT_WT(
1888                         SOC15_REG_OFFSET(UVD, i,
1889                                 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),
1890                         upper_32_bits(ring->gpu_addr));
1891                 /* force RBC into idle state */
1892                 tmp = order_base_2(ring->ring_size);
1893                 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp);
1894                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1895                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1896                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1897                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1898                 MMSCH_V2_0_INSERT_DIRECT_WT(
1899                         SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp);
1900
1901                 /* add end packet */
1902                 tmp = sizeof(struct mmsch_v2_0_cmd_end);
1903                 memcpy((void *)init_table, &end, tmp);
1904                 table_size += (tmp / 4);
1905                 header->vcn_table_size = table_size;
1906
1907         }
1908         return vcn_v2_0_start_mmsch(adev, &adev->virt.mm_table);
1909 }
1910
1911 static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {
1912         .name = "vcn_v2_0",
1913         .early_init = vcn_v2_0_early_init,
1914         .late_init = NULL,
1915         .sw_init = vcn_v2_0_sw_init,
1916         .sw_fini = vcn_v2_0_sw_fini,
1917         .hw_init = vcn_v2_0_hw_init,
1918         .hw_fini = vcn_v2_0_hw_fini,
1919         .suspend = vcn_v2_0_suspend,
1920         .resume = vcn_v2_0_resume,
1921         .is_idle = vcn_v2_0_is_idle,
1922         .wait_for_idle = vcn_v2_0_wait_for_idle,
1923         .check_soft_reset = NULL,
1924         .pre_soft_reset = NULL,
1925         .soft_reset = NULL,
1926         .post_soft_reset = NULL,
1927         .set_clockgating_state = vcn_v2_0_set_clockgating_state,
1928         .set_powergating_state = vcn_v2_0_set_powergating_state,
1929 };
1930
1931 static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = {
1932         .type = AMDGPU_RING_TYPE_VCN_DEC,
1933         .align_mask = 0xf,
1934         .vmhub = AMDGPU_MMHUB_0,
1935         .get_rptr = vcn_v2_0_dec_ring_get_rptr,
1936         .get_wptr = vcn_v2_0_dec_ring_get_wptr,
1937         .set_wptr = vcn_v2_0_dec_ring_set_wptr,
1938         .emit_frame_size =
1939                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1940                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1941                 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */
1942                 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */
1943                 6,
1944         .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */
1945         .emit_ib = vcn_v2_0_dec_ring_emit_ib,
1946         .emit_fence = vcn_v2_0_dec_ring_emit_fence,
1947         .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
1948         .test_ring = vcn_v2_0_dec_ring_test_ring,
1949         .test_ib = amdgpu_vcn_dec_ring_test_ib,
1950         .insert_nop = vcn_v2_0_dec_ring_insert_nop,
1951         .insert_start = vcn_v2_0_dec_ring_insert_start,
1952         .insert_end = vcn_v2_0_dec_ring_insert_end,
1953         .pad_ib = amdgpu_ring_generic_pad_ib,
1954         .begin_use = amdgpu_vcn_ring_begin_use,
1955         .end_use = amdgpu_vcn_ring_end_use,
1956         .emit_wreg = vcn_v2_0_dec_ring_emit_wreg,
1957         .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,
1958         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1959 };
1960
1961 static const struct amdgpu_ring_funcs vcn_v2_0_enc_ring_vm_funcs = {
1962         .type = AMDGPU_RING_TYPE_VCN_ENC,
1963         .align_mask = 0x3f,
1964         .nop = VCN_ENC_CMD_NO_OP,
1965         .vmhub = AMDGPU_MMHUB_0,
1966         .get_rptr = vcn_v2_0_enc_ring_get_rptr,
1967         .get_wptr = vcn_v2_0_enc_ring_get_wptr,
1968         .set_wptr = vcn_v2_0_enc_ring_set_wptr,
1969         .emit_frame_size =
1970                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1971                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1972                 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
1973                 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
1974                 1, /* vcn_v2_0_enc_ring_insert_end */
1975         .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
1976         .emit_ib = vcn_v2_0_enc_ring_emit_ib,
1977         .emit_fence = vcn_v2_0_enc_ring_emit_fence,
1978         .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
1979         .test_ring = amdgpu_vcn_enc_ring_test_ring,
1980         .test_ib = amdgpu_vcn_enc_ring_test_ib,
1981         .insert_nop = amdgpu_ring_insert_nop,
1982         .insert_end = vcn_v2_0_enc_ring_insert_end,
1983         .pad_ib = amdgpu_ring_generic_pad_ib,
1984         .begin_use = amdgpu_vcn_ring_begin_use,
1985         .end_use = amdgpu_vcn_ring_end_use,
1986         .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
1987         .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
1988         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1989 };
1990
1991 static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev)
1992 {
1993         adev->vcn.inst->ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs;
1994         DRM_INFO("VCN decode is enabled in VM mode\n");
1995 }
1996
1997 static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev)
1998 {
1999         int i;
2000
2001         for (i = 0; i < adev->vcn.num_enc_rings; ++i)
2002                 adev->vcn.inst->ring_enc[i].funcs = &vcn_v2_0_enc_ring_vm_funcs;
2003
2004         DRM_INFO("VCN encode is enabled in VM mode\n");
2005 }
2006
2007 static const struct amdgpu_irq_src_funcs vcn_v2_0_irq_funcs = {
2008         .set = vcn_v2_0_set_interrupt_state,
2009         .process = vcn_v2_0_process_interrupt,
2010 };
2011
2012 static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev)
2013 {
2014         adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 1;
2015         adev->vcn.inst->irq.funcs = &vcn_v2_0_irq_funcs;
2016 }
2017
2018 const struct amdgpu_ip_block_version vcn_v2_0_ip_block =
2019 {
2020                 .type = AMD_IP_BLOCK_TYPE_VCN,
2021                 .major = 2,
2022                 .minor = 0,
2023                 .rev = 0,
2024                 .funcs = &vcn_v2_0_ip_funcs,
2025 };