drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_vcn.h"
  28 #include "soc15.h"
  29 #include "soc15d.h"
  30 #include "amdgpu_pm.h"
  31 #include "amdgpu_psp.h"
  32
  33 #include "vcn/vcn_2_0_0_offset.h"
  34 #include "vcn/vcn_2_0_0_sh_mask.h"
  35 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
  36
  37 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET                        0x1fd
  38 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET                    0x503
  39 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET                  0x504
  40 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET                  0x505
  41 #define mmUVD_NO_OP_INTERNAL_OFFSET                             0x53f
  42 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET                       0x54a
  43 #define mmUVD_SCRATCH9_INTERNAL_OFFSET                          0xc01d
  44
  45 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET                   0x1e1
  46 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET         0x5a6
  47 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET          0x5a7
  48 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET                       0x1e2
  49
  50 #define mmUVD_RBC_XX_IB_REG_CHECK                                       0x026b
  51 #define mmUVD_RBC_XX_IB_REG_CHECK_BASE_IDX                              1
  52 #define mmUVD_REG_XX_MASK                                               0x026c
  53 #define mmUVD_REG_XX_MASK_BASE_IDX                                      1
  54
  55 static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
  56 static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev);
  57 static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev);
  58 static int vcn_v2_0_set_powergating_state(void *handle,
  59                                 enum amd_powergating_state state);
  60 static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
  61                                 struct dpg_pause_state *new_state);
  62
  63 /**
  64  * vcn_v2_0_early_init - set function pointers
  65  *
  66  * @handle: amdgpu_device pointer
  67  *
  68  * Set ring and irq function pointers
  69  */
  70 static int vcn_v2_0_early_init(void *handle)
  71 {
  72         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  73
  74         adev->vcn.num_vcn_inst = 1;
  75         adev->vcn.num_enc_rings = 2;
  76
  77         vcn_v2_0_set_dec_ring_funcs(adev);
  78         vcn_v2_0_set_enc_ring_funcs(adev);
  79         vcn_v2_0_set_irq_funcs(adev);
  80
  81         return 0;
  82 }
  83
  84 /**
  85  * vcn_v2_0_sw_init - sw init for VCN block
  86  *
  87  * @handle: amdgpu_device pointer
  88  *
  89  * Load firmware and sw initialization
  90  */
  91 static int vcn_v2_0_sw_init(void *handle)
  92 {
  93         struct amdgpu_ring *ring;
  94         int i, r;
  95         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  96
  97         /* VCN DEC TRAP */
  98         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
  99                               VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT,
 100                               &adev->vcn.inst->irq);
 101         if (r)
 102                 return r;
 103
 104         /* VCN ENC TRAP */
 105         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 106                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
 107                                       i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
 108                                       &adev->vcn.inst->irq);
 109                 if (r)
 110                         return r;
 111         }
 112
 113         r = amdgpu_vcn_sw_init(adev);
 114         if (r)
 115                 return r;
 116
 117         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 118                 const struct common_firmware_header *hdr;
 119                 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
 120                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
 121                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
 122                 adev->firmware.fw_size +=
 123                         ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
 124                 DRM_INFO("PSP loading VCN firmware\n");
 125         }
 126
 127         r = amdgpu_vcn_resume(adev);
 128         if (r)
 129                 return r;
 130
 131         ring = &adev->vcn.inst->ring_dec;
 132
 133         ring->use_doorbell = true;
 134         ring->doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 << 1;
 135
 136         sprintf(ring->name, "vcn_dec");
 137         r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0);
 138         if (r)
 139                 return r;
 140
 141         adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
 142         adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
 143         adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
 144         adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
 145         adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
 146         adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
 147
 148         adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
 149         adev->vcn.inst->external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
 150         adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
 151         adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
 152         adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
 153         adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
 154         adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
 155         adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
 156         adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
 157         adev->vcn.inst->external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
 158
 159         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 160                 ring = &adev->vcn.inst->ring_enc[i];
 161                 ring->use_doorbell = true;
 162                 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i;
 163                 sprintf(ring->name, "vcn_enc%d", i);
 164                 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0);
 165                 if (r)
 166                         return r;
 167         }
 168
 169         adev->vcn.pause_dpg_mode = vcn_v2_0_pause_dpg_mode;
 170
 171         return 0;
 172 }
 173
 174 /**
 175  * vcn_v2_0_sw_fini - sw fini for VCN block
 176  *
 177  * @handle: amdgpu_device pointer
 178  *
 179  * VCN suspend and free up sw allocation
 180  */
 181 static int vcn_v2_0_sw_fini(void *handle)
 182 {
 183         int r;
 184         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 185
 186         r = amdgpu_vcn_suspend(adev);
 187         if (r)
 188                 return r;
 189
 190         r = amdgpu_vcn_sw_fini(adev);
 191
 192         return r;
 193 }
 194
 195 /**
 196  * vcn_v2_0_hw_init - start and test VCN block
 197  *
 198  * @handle: amdgpu_device pointer
 199  *
 200  * Initialize the hardware, boot up the VCPU and do some testing
 201  */
 202 static int vcn_v2_0_hw_init(void *handle)
 203 {
 204         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 205         struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
 206         int i, r;
 207
 208         adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
 209                                              ring->doorbell_index, 0);
 210
 211         r = amdgpu_ring_test_helper(ring);
 212         if (r)
 213                 goto done;
 214
 215         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 216                 ring = &adev->vcn.inst->ring_enc[i];
 217                 r = amdgpu_ring_test_helper(ring);
 218                 if (r)
 219                         goto done;
 220         }
 221
 222 done:
 223         if (!r)
 224                 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
 225                         (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
 226
 227         return r;
 228 }
 229
 230 /**
 231  * vcn_v2_0_hw_fini - stop the hardware block
 232  *
 233  * @handle: amdgpu_device pointer
 234  *
 235  * Stop the VCN block, mark ring as not ready any more
 236  */
 237 static int vcn_v2_0_hw_fini(void *handle)
 238 {
 239         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 240         struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
 241         int i;
 242
 243         if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
 244             (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
 245               RREG32_SOC15(VCN, 0, mmUVD_STATUS)))
 246                 vcn_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
 247
 248         ring->sched.ready = false;
 249
 250         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 251                 ring = &adev->vcn.inst->ring_enc[i];
 252                 ring->sched.ready = false;
 253         }
 254
 255         return 0;
 256 }
 257
 258 /**
 259  * vcn_v2_0_suspend - suspend VCN block
 260  *
 261  * @handle: amdgpu_device pointer
 262  *
 263  * HW fini and suspend VCN block
 264  */
 265 static int vcn_v2_0_suspend(void *handle)
 266 {
 267         int r;
 268         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 269
 270         r = vcn_v2_0_hw_fini(adev);
 271         if (r)
 272                 return r;
 273
 274         r = amdgpu_vcn_suspend(adev);
 275
 276         return r;
 277 }
 278
 279 /**
 280  * vcn_v2_0_resume - resume VCN block
 281  *
 282  * @handle: amdgpu_device pointer
 283  *
 284  * Resume firmware and hw init VCN block
 285  */
 286 static int vcn_v2_0_resume(void *handle)
 287 {
 288         int r;
 289         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 290
 291         r = amdgpu_vcn_resume(adev);
 292         if (r)
 293                 return r;
 294
 295         r = vcn_v2_0_hw_init(adev);
 296
 297         return r;
 298 }
 299
 300 /**
 301  * vcn_v2_0_mc_resume - memory controller programming
 302  *
 303  * @adev: amdgpu_device pointer
 304  *
 305  * Let the VCN memory controller know it's offsets
 306  */
 307 static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
 308 {
 309         uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
 310         uint32_t offset;
 311
 312         /* cache window 0: fw */
 313         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 314                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 315                         (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
 316                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 317                         (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
 318                 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
 319                 offset = 0;
 320         } else {
 321                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 322                         lower_32_bits(adev->vcn.inst->gpu_addr));
 323                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 324                         upper_32_bits(adev->vcn.inst->gpu_addr));
 325                 offset = size;
 326                 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
 327                         AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 328         }
 329
 330         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
 331
 332         /* cache window 1: stack */
 333         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 334                 lower_32_bits(adev->vcn.inst->gpu_addr + offset));
 335         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 336                 upper_32_bits(adev->vcn.inst->gpu_addr + offset));
 337         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
 338         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
 339
 340         /* cache window 2: context */
 341         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 342                 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 343         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 344                 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 345         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
 346         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
 347
 348         WREG32_SOC15(UVD, 0, mmUVD_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 349 }
 350
 351 static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirect)
 352 {
 353         uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
 354         uint32_t offset;
 355
 356         /* cache window 0: fw */
 357         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 358                 if (!indirect) {
 359                         WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 360                                 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 361                                 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect);
 362                         WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 363                                 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 364                                 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect);
 365                         WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 366                                 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
 367                 } else {
 368                         WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 369                                 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
 370                         WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 371                                 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
 372                         WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 373                                 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
 374                 }
 375                 offset = 0;
 376         } else {
 377                 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 378                         UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 379                         lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
 380                 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 381                         UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 382                         upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
 383                 offset = size;
 384                 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 385                         UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
 386                         AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
 387         }
 388
 389         if (!indirect)
 390                 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 391                         UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
 392         else
 393                 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 394                         UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
 395
 396         /* cache window 1: stack */
 397         if (!indirect) {
 398                 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 399                         UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
 400                         lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
 401                 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 402                         UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
 403                         upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
 404                 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 405                         UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
 406         } else {
 407                 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 408                         UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
 409                 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 410                         UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
 411                 WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 412                         UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
 413         }
 414         WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 415                 UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
 416
 417         /* cache window 2: context */
 418         WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 419                 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
 420                 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
 421         WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 422                 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
 423                 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
 424         WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 425                 UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
 426         WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 427                 UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
 428
 429         /* non-cache window */
 430         WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 431                 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
 432         WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 433                 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
 434         WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 435                 UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
 436         WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 437                 UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
 438
 439         /* VCN global tiling registers */
 440         WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 441                 UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
 442 }
 443
 444 /**
 445  * vcn_v2_0_disable_clock_gating - disable VCN clock gating
 446  *
 447  * @adev: amdgpu_device pointer
 448  * @sw: enable SW clock gating
 449  *
 450  * Disable clock gating for VCN block
 451  */
 452 static void vcn_v2_0_disable_clock_gating(struct amdgpu_device *adev)
 453 {
 454         uint32_t data;
 455
 456         /* UVD disable CGC */
 457         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 458         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 459                 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 460         else
 461                 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 462         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 463         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 464         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 465
 466         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);
 467         data &= ~(UVD_CGC_GATE__SYS_MASK
 468                 | UVD_CGC_GATE__UDEC_MASK
 469                 | UVD_CGC_GATE__MPEG2_MASK
 470                 | UVD_CGC_GATE__REGS_MASK
 471                 | UVD_CGC_GATE__RBC_MASK
 472                 | UVD_CGC_GATE__LMI_MC_MASK
 473                 | UVD_CGC_GATE__LMI_UMC_MASK
 474                 | UVD_CGC_GATE__IDCT_MASK
 475                 | UVD_CGC_GATE__MPRD_MASK
 476                 | UVD_CGC_GATE__MPC_MASK
 477                 | UVD_CGC_GATE__LBSI_MASK
 478                 | UVD_CGC_GATE__LRBBM_MASK
 479                 | UVD_CGC_GATE__UDEC_RE_MASK
 480                 | UVD_CGC_GATE__UDEC_CM_MASK
 481                 | UVD_CGC_GATE__UDEC_IT_MASK
 482                 | UVD_CGC_GATE__UDEC_DB_MASK
 483                 | UVD_CGC_GATE__UDEC_MP_MASK
 484                 | UVD_CGC_GATE__WCB_MASK
 485                 | UVD_CGC_GATE__VCPU_MASK
 486                 | UVD_CGC_GATE__SCPU_MASK);
 487         WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);
 488
 489         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 490         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 491                 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 492                 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 493                 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 494                 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 495                 | UVD_CGC_CTRL__SYS_MODE_MASK
 496                 | UVD_CGC_CTRL__UDEC_MODE_MASK
 497                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 498                 | UVD_CGC_CTRL__REGS_MODE_MASK
 499                 | UVD_CGC_CTRL__RBC_MODE_MASK
 500                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 501                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 502                 | UVD_CGC_CTRL__IDCT_MODE_MASK
 503                 | UVD_CGC_CTRL__MPRD_MODE_MASK
 504                 | UVD_CGC_CTRL__MPC_MODE_MASK
 505                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 506                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 507                 | UVD_CGC_CTRL__WCB_MODE_MASK
 508                 | UVD_CGC_CTRL__VCPU_MODE_MASK
 509                 | UVD_CGC_CTRL__SCPU_MODE_MASK);
 510         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 511
 512         /* turn on */
 513         data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);
 514         data |= (UVD_SUVD_CGC_GATE__SRE_MASK
 515                 | UVD_SUVD_CGC_GATE__SIT_MASK
 516                 | UVD_SUVD_CGC_GATE__SMP_MASK
 517                 | UVD_SUVD_CGC_GATE__SCM_MASK
 518                 | UVD_SUVD_CGC_GATE__SDB_MASK
 519                 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
 520                 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
 521                 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
 522                 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
 523                 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
 524                 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
 525                 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
 526                 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
 527                 | UVD_SUVD_CGC_GATE__SCLR_MASK
 528                 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
 529                 | UVD_SUVD_CGC_GATE__ENT_MASK
 530                 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
 531                 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
 532                 | UVD_SUVD_CGC_GATE__SITE_MASK
 533                 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
 534                 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
 535                 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
 536                 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
 537                 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
 538         WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data);
 539
 540         data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
 541         data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 542                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 543                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 544                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 545                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 546                 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 547                 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 548                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 549                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 550                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 551         WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
 552 }
 553
 554 static void vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_device *adev,
 555                 uint8_t sram_sel, uint8_t indirect)
 556 {
 557         uint32_t reg_data = 0;
 558
 559         /* enable sw clock gating control */
 560         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 561                 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 562         else
 563                 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 564         reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 565         reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 566         reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
 567                  UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
 568                  UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
 569                  UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
 570                  UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
 571                  UVD_CGC_CTRL__SYS_MODE_MASK |
 572                  UVD_CGC_CTRL__UDEC_MODE_MASK |
 573                  UVD_CGC_CTRL__MPEG2_MODE_MASK |
 574                  UVD_CGC_CTRL__REGS_MODE_MASK |
 575                  UVD_CGC_CTRL__RBC_MODE_MASK |
 576                  UVD_CGC_CTRL__LMI_MC_MODE_MASK |
 577                  UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
 578                  UVD_CGC_CTRL__IDCT_MODE_MASK |
 579                  UVD_CGC_CTRL__MPRD_MODE_MASK |
 580                  UVD_CGC_CTRL__MPC_MODE_MASK |
 581                  UVD_CGC_CTRL__LBSI_MODE_MASK |
 582                  UVD_CGC_CTRL__LRBBM_MODE_MASK |
 583                  UVD_CGC_CTRL__WCB_MODE_MASK |
 584                  UVD_CGC_CTRL__VCPU_MODE_MASK |
 585                  UVD_CGC_CTRL__SCPU_MODE_MASK);
 586         WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 587                 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
 588
 589         /* turn off clock gating */
 590         WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 591                 UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);
 592
 593         /* turn on SUVD clock gating */
 594         WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 595                 UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
 596
 597         /* turn on sw mode in UVD_SUVD_CGC_CTRL */
 598         WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 599                 UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
 600 }
 601
 602 /**
 603  * vcn_v2_0_enable_clock_gating - enable VCN clock gating
 604  *
 605  * @adev: amdgpu_device pointer
 606  * @sw: enable SW clock gating
 607  *
 608  * Enable clock gating for VCN block
 609  */
 610 static void vcn_v2_0_enable_clock_gating(struct amdgpu_device *adev)
 611 {
 612         uint32_t data = 0;
 613
 614         /* enable UVD CGC */
 615         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 616         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 617                 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 618         else
 619                 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 620         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 621         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 622         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 623
 624         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 625         data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 626                 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 627                 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 628                 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 629                 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 630                 | UVD_CGC_CTRL__SYS_MODE_MASK
 631                 | UVD_CGC_CTRL__UDEC_MODE_MASK
 632                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 633                 | UVD_CGC_CTRL__REGS_MODE_MASK
 634                 | UVD_CGC_CTRL__RBC_MODE_MASK
 635                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 636                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 637                 | UVD_CGC_CTRL__IDCT_MODE_MASK
 638                 | UVD_CGC_CTRL__MPRD_MODE_MASK
 639                 | UVD_CGC_CTRL__MPC_MODE_MASK
 640                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 641                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 642                 | UVD_CGC_CTRL__WCB_MODE_MASK
 643                 | UVD_CGC_CTRL__VCPU_MODE_MASK
 644                 | UVD_CGC_CTRL__SCPU_MODE_MASK);
 645         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 646
 647         data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
 648         data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 649                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 650                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 651                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 652                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 653                 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 654                 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 655                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 656                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 657                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 658         WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
 659 }
 660
 661 static void vcn_v2_0_disable_static_power_gating(struct amdgpu_device *adev)
 662 {
 663         uint32_t data = 0;
 664         int ret;
 665
 666         if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
 667                 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 668                         | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 669                         | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 670                         | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 671                         | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 672                         | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
 673                         | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
 674                         | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 675                         | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 676                         | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
 677
 678                 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
 679                 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS,
 680                         UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0, 0xFFFFF, ret);
 681         } else {
 682                 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 683                         | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 684                         | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 685                         | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 686                         | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 687                         | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
 688                         | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
 689                         | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 690                         | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 691                         | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
 692                 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
 693                 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0,  0xFFFFF, ret);
 694         }
 695
 696         /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS,
 697          * UVDU_PWR_STATUS are 0 (power on) */
 698
 699         data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
 700         data &= ~0x103;
 701         if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
 702                 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON |
 703                         UVD_POWER_STATUS__UVD_PG_EN_MASK;
 704
 705         WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
 706 }
 707
 708 static void vcn_v2_0_enable_static_power_gating(struct amdgpu_device *adev)
 709 {
 710         uint32_t data = 0;
 711         int ret;
 712
 713         if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
 714                 /* Before power off, this indicator has to be turned on */
 715                 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
 716                 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
 717                 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
 718                 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
 719
 720
 721                 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 722                         | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 723                         | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 724                         | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 725                         | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 726                         | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
 727                         | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
 728                         | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 729                         | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 730                         | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
 731
 732                 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
 733
 734                 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
 735                         | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
 736                         | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
 737                         | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
 738                         | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
 739                         | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT
 740                         | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT
 741                         | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
 742                         | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
 743                         | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT);
 744                 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFF, ret);
 745         }
 746 }
 747
 748 static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)
 749 {
 750         struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
 751         uint32_t rb_bufsz, tmp;
 752
 753         vcn_v2_0_enable_static_power_gating(adev);
 754
 755         /* enable dynamic power gating mode */
 756         tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
 757         tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
 758         tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
 759         WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);
 760
 761         if (indirect)
 762                 adev->vcn.dpg_sram_curr_addr = (uint32_t*)adev->vcn.dpg_sram_cpu_addr;
 763
 764         /* enable clock gating */
 765         vcn_v2_0_clock_gating_dpg_mode(adev, 0, indirect);
 766
 767         /* enable VCPU clock */
 768         tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
 769         tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
 770         tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
 771         WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 772                 UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
 773
 774         /* disable master interupt */
 775         WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 776                 UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect);
 777
 778         /* setup mmUVD_LMI_CTRL */
 779         tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 780                 UVD_LMI_CTRL__REQ_MODE_MASK |
 781                 UVD_LMI_CTRL__CRC_RESET_MASK |
 782                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
 783                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 784                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 785                 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 786                 0x00100000L);
 787         WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 788                 UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);
 789
 790         WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 791                 UVD, 0, mmUVD_MPC_CNTL),
 792                 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
 793
 794         WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 795                 UVD, 0, mmUVD_MPC_SET_MUXA0),
 796                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
 797                  (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
 798                  (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
 799                  (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
 800
 801         WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 802                 UVD, 0, mmUVD_MPC_SET_MUXB0),
 803                 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
 804                  (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
 805                  (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
 806                  (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
 807
 808         WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 809                 UVD, 0, mmUVD_MPC_SET_MUX),
 810                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
 811                  (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
 812                  (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
 813
 814         vcn_v2_0_mc_resume_dpg_mode(adev, indirect);
 815
 816         WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 817                 UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
 818         WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 819                 UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
 820
 821         /* release VCPU reset to boot */
 822         WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 823                 UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect);
 824
 825         /* enable LMI MC and UMC channels */
 826         WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 827                 UVD, 0, mmUVD_LMI_CTRL2),
 828                 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 0, indirect);
 829
 830         /* enable master interrupt */
 831         WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
 832                 UVD, 0, mmUVD_MASTINT_EN),
 833                 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
 834
 835         if (indirect)
 836                 psp_update_vcn_sram(adev, 0, adev->vcn.dpg_sram_gpu_addr,
 837                                     (uint32_t)((uintptr_t)adev->vcn.dpg_sram_curr_addr -
 838                                                (uintptr_t)adev->vcn.dpg_sram_cpu_addr));
 839
 840         /* force RBC into idle state */
 841         rb_bufsz = order_base_2(ring->ring_size);
 842         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
 843         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
 844         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 845         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
 846         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
 847         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
 848
 849         /* set the write pointer delay */
 850         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
 851
 852         /* set the wb address */
 853         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
 854                 (upper_32_bits(ring->gpu_addr) >> 2));
 855
 856         /* programm the RB_BASE for ring buffer */
 857         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
 858                 lower_32_bits(ring->gpu_addr));
 859         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
 860                 upper_32_bits(ring->gpu_addr));
 861
 862         /* Initialize the ring buffer's read and write pointers */
 863         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
 864
 865         WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
 866
 867         ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
 868         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
 869                 lower_32_bits(ring->wptr));
 870
 871         return 0;
 872 }
 873
 874 static int vcn_v2_0_start(struct amdgpu_device *adev)
 875 {
 876         struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
 877         uint32_t rb_bufsz, tmp;
 878         uint32_t lmi_swap_cntl;
 879         int i, j, r;
 880
 881         if (adev->pm.dpm_enabled)
 882                 amdgpu_dpm_enable_uvd(adev, true);
 883
 884         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
 885                 return vcn_v2_0_start_dpg_mode(adev, adev->vcn.indirect_sram);
 886
 887         vcn_v2_0_disable_static_power_gating(adev);
 888
 889         /* set uvd status busy */
 890         tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
 891         WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
 892
 893         /*SW clock gating */
 894         vcn_v2_0_disable_clock_gating(adev);
 895
 896         /* enable VCPU clock */
 897         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
 898                 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
 899
 900         /* disable master interrupt */
 901         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
 902                 ~UVD_MASTINT_EN__VCPU_EN_MASK);
 903
 904         /* setup mmUVD_LMI_CTRL */
 905         tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
 906         WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp |
 907                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 908                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
 909                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 910                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
 911
 912         /* setup mmUVD_MPC_CNTL */
 913         tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
 914         tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
 915         tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
 916         WREG32_SOC15(VCN, 0, mmUVD_MPC_CNTL, tmp);
 917
 918         /* setup UVD_MPC_SET_MUXA0 */
 919         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,
 920                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
 921                 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
 922                 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
 923                 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
 924
 925         /* setup UVD_MPC_SET_MUXB0 */
 926         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0,
 927                 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
 928                 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
 929                 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
 930                 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
 931
 932         /* setup mmUVD_MPC_SET_MUX */
 933         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX,
 934                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
 935                 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
 936                 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
 937
 938         vcn_v2_0_mc_resume(adev);
 939
 940         /* release VCPU reset to boot */
 941         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
 942                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 943
 944         /* enable LMI MC and UMC channels */
 945         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
 946                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 947
 948         tmp = RREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET);
 949         tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
 950         tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
 951         WREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET, tmp);
 952
 953         /* disable byte swapping */
 954         lmi_swap_cntl = 0;
 955 #ifdef __BIG_ENDIAN
 956         /* swap (8 in 32) RB and IB */
 957         lmi_swap_cntl = 0xa;
 958 #endif
 959         WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 960
 961         for (i = 0; i < 10; ++i) {
 962                 uint32_t status;
 963
 964                 for (j = 0; j < 100; ++j) {
 965                         status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
 966                         if (status & 2)
 967                                 break;
 968                         mdelay(10);
 969                 }
 970                 r = 0;
 971                 if (status & 2)
 972                         break;
 973
 974                 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
 975                 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
 976                         UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
 977                         ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 978                 mdelay(10);
 979                 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
 980                         ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 981                 mdelay(10);
 982                 r = -1;
 983         }
 984
 985         if (r) {
 986                 DRM_ERROR("VCN decode not responding, giving up!!!\n");
 987                 return r;
 988         }
 989
 990         /* enable master interrupt */
 991         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
 992                 UVD_MASTINT_EN__VCPU_EN_MASK,
 993                 ~UVD_MASTINT_EN__VCPU_EN_MASK);
 994
 995         /* clear the busy bit of VCN_STATUS */
 996         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
 997                 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
 998
 999         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_VMID, 0);
1000
1001         /* force RBC into idle state */
1002         rb_bufsz = order_base_2(ring->ring_size);
1003         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1004         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1005         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1006         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1007         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1008         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
1009
1010         /* programm the RB_BASE for ring buffer */
1011         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1012                 lower_32_bits(ring->gpu_addr));
1013         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1014                 upper_32_bits(ring->gpu_addr));
1015
1016         /* Initialize the ring buffer's read and write pointers */
1017         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
1018
1019         ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1020         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1021                         lower_32_bits(ring->wptr));
1022
1023         ring = &adev->vcn.inst->ring_enc[0];
1024         WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1025         WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1026         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1027         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1028         WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
1029
1030         ring = &adev->vcn.inst->ring_enc[1];
1031         WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1032         WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1033         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1034         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1035         WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
1036
1037         return 0;
1038 }
1039
1040 static int vcn_v2_0_stop_dpg_mode(struct amdgpu_device *adev)
1041 {
1042         int ret_code = 0;
1043         uint32_t tmp;
1044
1045         /* Wait for power status to be 1 */
1046         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,
1047                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1048
1049         /* wait for read ptr to be equal to write ptr */
1050         tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1051         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
1052
1053         tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1054         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF, ret_code);
1055
1056         tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1057         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
1058
1059         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,
1060                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1061
1062         /* disable dynamic power gating mode */
1063         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
1064                         ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1065
1066         return 0;
1067 }
1068
1069 static int vcn_v2_0_stop(struct amdgpu_device *adev)
1070 {
1071         uint32_t tmp;
1072         int r;
1073
1074         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1075                 r = vcn_v2_0_stop_dpg_mode(adev);
1076                 if (r)
1077                         return r;
1078                 goto power_off;
1079         }
1080
1081         /* wait for uvd idle */
1082         SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r);
1083         if (r)
1084                 return r;
1085
1086         tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1087                 UVD_LMI_STATUS__READ_CLEAN_MASK |
1088                 UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1089                 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1090         SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp, r);
1091         if (r)
1092                 return r;
1093
1094         /* stall UMC channel */
1095         tmp = RREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2);
1096         tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
1097         WREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2, tmp);
1098
1099         tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
1100                 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1101         SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp, r);
1102         if (r)
1103                 return r;
1104
1105         /* disable VCPU clock */
1106         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
1107                 ~(UVD_VCPU_CNTL__CLK_EN_MASK));
1108
1109         /* reset LMI UMC */
1110         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1111                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,
1112                 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
1113
1114         /* reset LMI */
1115         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1116                 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,
1117                 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
1118
1119         /* reset VCPU */
1120         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1121                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1122                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1123
1124         /* clear status */
1125         WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0);
1126
1127         vcn_v2_0_enable_clock_gating(adev);
1128         vcn_v2_0_enable_static_power_gating(adev);
1129
1130 power_off:
1131         if (adev->pm.dpm_enabled)
1132                 amdgpu_dpm_enable_uvd(adev, false);
1133
1134         return 0;
1135 }
1136
1137 static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
1138                                 struct dpg_pause_state *new_state)
1139 {
1140         struct amdgpu_ring *ring;
1141         uint32_t reg_data = 0;
1142         int ret_code;
1143
1144         /* pause/unpause if state is changed */
1145         if (adev->vcn.pause_state.fw_based != new_state->fw_based) {
1146                 DRM_DEBUG("dpg pause state changed %d -> %d",
1147                         adev->vcn.pause_state.fw_based, new_state->fw_based);
1148                 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
1149                         (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1150
1151                 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1152                         ret_code = 0;
1153                         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 0x1,
1154                                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1155
1156                         if (!ret_code) {
1157                                 /* pause DPG */
1158                                 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1159                                 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1160
1161                                 /* wait for ACK */
1162                                 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
1163                                            UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1164                                            UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code);
1165
1166                                 /* Restore */
1167                                 ring = &adev->vcn.inst->ring_enc[0];
1168                                 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1169                                 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1170                                 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
1171                                 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1172                                 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1173
1174                                 ring = &adev->vcn.inst->ring_enc[1];
1175                                 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1176                                 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1177                                 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
1178                                 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1179                                 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1180
1181                                 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1182                                            RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
1183
1184                                 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1185                                            UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
1186                                            UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1187                         }
1188                 } else {
1189                         /* unpause dpg, no need to wait */
1190                         reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1191                         WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1192                 }
1193                 adev->vcn.pause_state.fw_based = new_state->fw_based;
1194         }
1195
1196         return 0;
1197 }
1198
1199 static bool vcn_v2_0_is_idle(void *handle)
1200 {
1201         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1202
1203         return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
1204 }
1205
1206 static int vcn_v2_0_wait_for_idle(void *handle)
1207 {
1208         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1209         int ret = 0;
1210
1211         SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
1212                 UVD_STATUS__IDLE, ret);
1213
1214         return ret;
1215 }
1216
1217 static int vcn_v2_0_set_clockgating_state(void *handle,
1218                                           enum amd_clockgating_state state)
1219 {
1220         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1221         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1222
1223         if (enable) {
1224                 /* wait for STATUS to clear */
1225                 if (vcn_v2_0_is_idle(handle))
1226                         return -EBUSY;
1227                 vcn_v2_0_enable_clock_gating(adev);
1228         } else {
1229                 /* disable HW gating and enable Sw gating */
1230                 vcn_v2_0_disable_clock_gating(adev);
1231         }
1232         return 0;
1233 }
1234
1235 /**
1236  * vcn_v2_0_dec_ring_get_rptr - get read pointer
1237  *
1238  * @ring: amdgpu_ring pointer
1239  *
1240  * Returns the current hardware read pointer
1241  */
1242 static uint64_t vcn_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
1243 {
1244         struct amdgpu_device *adev = ring->adev;
1245
1246         return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1247 }
1248
1249 /**
1250  * vcn_v2_0_dec_ring_get_wptr - get write pointer
1251  *
1252  * @ring: amdgpu_ring pointer
1253  *
1254  * Returns the current hardware write pointer
1255  */
1256 static uint64_t vcn_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
1257 {
1258         struct amdgpu_device *adev = ring->adev;
1259
1260         if (ring->use_doorbell)
1261                 return adev->wb.wb[ring->wptr_offs];
1262         else
1263                 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
1264 }
1265
1266 /**
1267  * vcn_v2_0_dec_ring_set_wptr - set write pointer
1268  *
1269  * @ring: amdgpu_ring pointer
1270  *
1271  * Commits the write pointer to the hardware
1272  */
1273 static void vcn_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
1274 {
1275         struct amdgpu_device *adev = ring->adev;
1276
1277         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1278                 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2,
1279                         lower_32_bits(ring->wptr) | 0x80000000);
1280
1281         if (ring->use_doorbell) {
1282                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1283                 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1284         } else {
1285                 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1286         }
1287 }
1288
1289 /**
1290  * vcn_v2_0_dec_ring_insert_start - insert a start command
1291  *
1292  * @ring: amdgpu_ring pointer
1293  *
1294  * Write a start command to the ring.
1295  */
1296 void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)
1297 {
1298         struct amdgpu_device *adev = ring->adev;
1299
1300         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1301         amdgpu_ring_write(ring, 0);
1302         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1303         amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));
1304 }
1305
1306 /**
1307  * vcn_v2_0_dec_ring_insert_end - insert a end command
1308  *
1309  * @ring: amdgpu_ring pointer
1310  *
1311  * Write a end command to the ring.
1312  */
1313 void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)
1314 {
1315         struct amdgpu_device *adev = ring->adev;
1316
1317         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1318         amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1));
1319 }
1320
1321 /**
1322  * vcn_v2_0_dec_ring_insert_nop - insert a nop command
1323  *
1324  * @ring: amdgpu_ring pointer
1325  *
1326  * Write a nop command to the ring.
1327  */
1328 void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1329 {
1330         struct amdgpu_device *adev = ring->adev;
1331         int i;
1332
1333         WARN_ON(ring->wptr % 2 || count % 2);
1334
1335         for (i = 0; i < count / 2; i++) {
1336                 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.nop, 0));
1337                 amdgpu_ring_write(ring, 0);
1338         }
1339 }
1340
1341 /**
1342  * vcn_v2_0_dec_ring_emit_fence - emit an fence & trap command
1343  *
1344  * @ring: amdgpu_ring pointer
1345  * @fence: fence to emit
1346  *
1347  * Write a fence and a trap command to the ring.
1348  */
1349 void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1350                                 unsigned flags)
1351 {
1352         struct amdgpu_device *adev = ring->adev;
1353
1354         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1355         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.context_id, 0));
1356         amdgpu_ring_write(ring, seq);
1357
1358         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1359         amdgpu_ring_write(ring, addr & 0xffffffff);
1360
1361         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1362         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1363
1364         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1365         amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_FENCE << 1));
1366
1367         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1368         amdgpu_ring_write(ring, 0);
1369
1370         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1371         amdgpu_ring_write(ring, 0);
1372
1373         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1374
1375         amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_TRAP << 1));
1376 }
1377
1378 /**
1379  * vcn_v2_0_dec_ring_emit_ib - execute indirect buffer
1380  *
1381  * @ring: amdgpu_ring pointer
1382  * @ib: indirect buffer to execute
1383  *
1384  * Write ring commands to execute the indirect buffer
1385  */
1386 void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
1387                                struct amdgpu_job *job,
1388                                struct amdgpu_ib *ib,
1389                                uint32_t flags)
1390 {
1391         struct amdgpu_device *adev = ring->adev;
1392         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1393
1394         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_vmid, 0));
1395         amdgpu_ring_write(ring, vmid);
1396
1397         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_low, 0));
1398         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1399         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_high, 0));
1400         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1401         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_size, 0));
1402         amdgpu_ring_write(ring, ib->length_dw);
1403 }
1404
1405 void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1406                                 uint32_t val, uint32_t mask)
1407 {
1408         struct amdgpu_device *adev = ring->adev;
1409
1410         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1411         amdgpu_ring_write(ring, reg << 2);
1412
1413         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1414         amdgpu_ring_write(ring, val);
1415
1416         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.gp_scratch8, 0));
1417         amdgpu_ring_write(ring, mask);
1418
1419         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1420
1421         amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_REG_READ_COND_WAIT << 1));
1422 }
1423
1424 void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
1425                                 unsigned vmid, uint64_t pd_addr)
1426 {
1427         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1428         uint32_t data0, data1, mask;
1429
1430         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1431
1432         /* wait for register write */
1433         data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
1434         data1 = lower_32_bits(pd_addr);
1435         mask = 0xffffffff;
1436         vcn_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
1437 }
1438
1439 void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
1440                                 uint32_t reg, uint32_t val)
1441 {
1442         struct amdgpu_device *adev = ring->adev;
1443
1444         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1445         amdgpu_ring_write(ring, reg << 2);
1446
1447         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1448         amdgpu_ring_write(ring, val);
1449
1450         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1451
1452         amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_WRITE_REG << 1));
1453 }
1454
1455 /**
1456  * vcn_v2_0_enc_ring_get_rptr - get enc read pointer
1457  *
1458  * @ring: amdgpu_ring pointer
1459  *
1460  * Returns the current hardware enc read pointer
1461  */
1462 static uint64_t vcn_v2_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
1463 {
1464         struct amdgpu_device *adev = ring->adev;
1465
1466         if (ring == &adev->vcn.inst->ring_enc[0])
1467                 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
1468         else
1469                 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
1470 }
1471
1472  /**
1473  * vcn_v2_0_enc_ring_get_wptr - get enc write pointer
1474  *
1475  * @ring: amdgpu_ring pointer
1476  *
1477  * Returns the current hardware enc write pointer
1478  */
1479 static uint64_t vcn_v2_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
1480 {
1481         struct amdgpu_device *adev = ring->adev;
1482
1483         if (ring == &adev->vcn.inst->ring_enc[0]) {
1484                 if (ring->use_doorbell)
1485                         return adev->wb.wb[ring->wptr_offs];
1486                 else
1487                         return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1488         } else {
1489                 if (ring->use_doorbell)
1490                         return adev->wb.wb[ring->wptr_offs];
1491                 else
1492                         return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1493         }
1494 }
1495
1496  /**
1497  * vcn_v2_0_enc_ring_set_wptr - set enc write pointer
1498  *
1499  * @ring: amdgpu_ring pointer
1500  *
1501  * Commits the enc write pointer to the hardware
1502  */
1503 static void vcn_v2_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
1504 {
1505         struct amdgpu_device *adev = ring->adev;
1506
1507         if (ring == &adev->vcn.inst->ring_enc[0]) {
1508                 if (ring->use_doorbell) {
1509                         adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1510                         WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1511                 } else {
1512                         WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1513                 }
1514         } else {
1515                 if (ring->use_doorbell) {
1516                         adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1517                         WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1518                 } else {
1519                         WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1520                 }
1521         }
1522 }
1523
1524 /**
1525  * vcn_v2_0_enc_ring_emit_fence - emit an enc fence & trap command
1526  *
1527  * @ring: amdgpu_ring pointer
1528  * @fence: fence to emit
1529  *
1530  * Write enc a fence and a trap command to the ring.
1531  */
1532 void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1533                                 u64 seq, unsigned flags)
1534 {
1535         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1536
1537         amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE);
1538         amdgpu_ring_write(ring, addr);
1539         amdgpu_ring_write(ring, upper_32_bits(addr));
1540         amdgpu_ring_write(ring, seq);
1541         amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP);
1542 }
1543
1544 void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1545 {
1546         amdgpu_ring_write(ring, VCN_ENC_CMD_END);
1547 }
1548
1549 /**
1550  * vcn_v2_0_enc_ring_emit_ib - enc execute indirect buffer
1551  *
1552  * @ring: amdgpu_ring pointer
1553  * @ib: indirect buffer to execute
1554  *
1555  * Write enc ring commands to execute the indirect buffer
1556  */
1557 void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1558                                struct amdgpu_job *job,
1559                                struct amdgpu_ib *ib,
1560                                uint32_t flags)
1561 {
1562         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1563
1564         amdgpu_ring_write(ring, VCN_ENC_CMD_IB);
1565         amdgpu_ring_write(ring, vmid);
1566         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1567         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1568         amdgpu_ring_write(ring, ib->length_dw);
1569 }
1570
1571 void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1572                                 uint32_t val, uint32_t mask)
1573 {
1574         amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
1575         amdgpu_ring_write(ring, reg << 2);
1576         amdgpu_ring_write(ring, mask);
1577         amdgpu_ring_write(ring, val);
1578 }
1579
1580 void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1581                                 unsigned int vmid, uint64_t pd_addr)
1582 {
1583         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1584
1585         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1586
1587         /* wait for reg writes */
1588         vcn_v2_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2,
1589                                         lower_32_bits(pd_addr), 0xffffffff);
1590 }
1591
1592 void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
1593 {
1594         amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1595         amdgpu_ring_write(ring, reg << 2);
1596         amdgpu_ring_write(ring, val);
1597 }
1598
1599 static int vcn_v2_0_set_interrupt_state(struct amdgpu_device *adev,
1600                                         struct amdgpu_irq_src *source,
1601                                         unsigned type,
1602                                         enum amdgpu_interrupt_state state)
1603 {
1604         return 0;
1605 }
1606
1607 static int vcn_v2_0_process_interrupt(struct amdgpu_device *adev,
1608                                       struct amdgpu_irq_src *source,
1609                                       struct amdgpu_iv_entry *entry)
1610 {
1611         DRM_DEBUG("IH: VCN TRAP\n");
1612
1613         switch (entry->src_id) {
1614         case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT:
1615                 amdgpu_fence_process(&adev->vcn.inst->ring_dec);
1616                 break;
1617         case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
1618                 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]);
1619                 break;
1620         case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
1621                 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);
1622                 break;
1623         default:
1624                 DRM_ERROR("Unhandled interrupt: %d %d\n",
1625                           entry->src_id, entry->src_data[0]);
1626                 break;
1627         }
1628
1629         return 0;
1630 }
1631
1632 static int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring)
1633 {
1634         struct amdgpu_device *adev = ring->adev;
1635         uint32_t tmp = 0;
1636         unsigned i;
1637         int r;
1638
1639         WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
1640         r = amdgpu_ring_alloc(ring, 4);
1641         if (r)
1642                 return r;
1643         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1644         amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));
1645         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));
1646         amdgpu_ring_write(ring, 0xDEADBEEF);
1647         amdgpu_ring_commit(ring);
1648         for (i = 0; i < adev->usec_timeout; i++) {
1649                 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
1650                 if (tmp == 0xDEADBEEF)
1651                         break;
1652                 udelay(1);
1653         }
1654
1655         if (i >= adev->usec_timeout)
1656                 r = -ETIMEDOUT;
1657
1658         return r;
1659 }
1660
1661
1662 static int vcn_v2_0_set_powergating_state(void *handle,
1663                                           enum amd_powergating_state state)
1664 {
1665         /* This doesn't actually powergate the VCN block.
1666          * That's done in the dpm code via the SMC.  This
1667          * just re-inits the block as necessary.  The actual
1668          * gating still happens in the dpm code.  We should
1669          * revisit this when there is a cleaner line between
1670          * the smc and the hw blocks
1671          */
1672         int ret;
1673         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1674
1675         if (state == adev->vcn.cur_state)
1676                 return 0;
1677
1678         if (state == AMD_PG_STATE_GATE)
1679                 ret = vcn_v2_0_stop(adev);
1680         else
1681                 ret = vcn_v2_0_start(adev);
1682
1683         if (!ret)
1684                 adev->vcn.cur_state = state;
1685         return ret;
1686 }
1687
1688 static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {
1689         .name = "vcn_v2_0",
1690         .early_init = vcn_v2_0_early_init,
1691         .late_init = NULL,
1692         .sw_init = vcn_v2_0_sw_init,
1693         .sw_fini = vcn_v2_0_sw_fini,
1694         .hw_init = vcn_v2_0_hw_init,
1695         .hw_fini = vcn_v2_0_hw_fini,
1696         .suspend = vcn_v2_0_suspend,
1697         .resume = vcn_v2_0_resume,
1698         .is_idle = vcn_v2_0_is_idle,
1699         .wait_for_idle = vcn_v2_0_wait_for_idle,
1700         .check_soft_reset = NULL,
1701         .pre_soft_reset = NULL,
1702         .soft_reset = NULL,
1703         .post_soft_reset = NULL,
1704         .set_clockgating_state = vcn_v2_0_set_clockgating_state,
1705         .set_powergating_state = vcn_v2_0_set_powergating_state,
1706 };
1707
1708 static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = {
1709         .type = AMDGPU_RING_TYPE_VCN_DEC,
1710         .align_mask = 0xf,
1711         .vmhub = AMDGPU_MMHUB_0,
1712         .get_rptr = vcn_v2_0_dec_ring_get_rptr,
1713         .get_wptr = vcn_v2_0_dec_ring_get_wptr,
1714         .set_wptr = vcn_v2_0_dec_ring_set_wptr,
1715         .emit_frame_size =
1716                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1717                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1718                 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */
1719                 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */
1720                 6,
1721         .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */
1722         .emit_ib = vcn_v2_0_dec_ring_emit_ib,
1723         .emit_fence = vcn_v2_0_dec_ring_emit_fence,
1724         .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
1725         .test_ring = vcn_v2_0_dec_ring_test_ring,
1726         .test_ib = amdgpu_vcn_dec_ring_test_ib,
1727         .insert_nop = vcn_v2_0_dec_ring_insert_nop,
1728         .insert_start = vcn_v2_0_dec_ring_insert_start,
1729         .insert_end = vcn_v2_0_dec_ring_insert_end,
1730         .pad_ib = amdgpu_ring_generic_pad_ib,
1731         .begin_use = amdgpu_vcn_ring_begin_use,
1732         .end_use = amdgpu_vcn_ring_end_use,
1733         .emit_wreg = vcn_v2_0_dec_ring_emit_wreg,
1734         .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,
1735         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1736 };
1737
1738 static const struct amdgpu_ring_funcs vcn_v2_0_enc_ring_vm_funcs = {
1739         .type = AMDGPU_RING_TYPE_VCN_ENC,
1740         .align_mask = 0x3f,
1741         .nop = VCN_ENC_CMD_NO_OP,
1742         .vmhub = AMDGPU_MMHUB_0,
1743         .get_rptr = vcn_v2_0_enc_ring_get_rptr,
1744         .get_wptr = vcn_v2_0_enc_ring_get_wptr,
1745         .set_wptr = vcn_v2_0_enc_ring_set_wptr,
1746         .emit_frame_size =
1747                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1748                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1749                 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
1750                 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
1751                 1, /* vcn_v2_0_enc_ring_insert_end */
1752         .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
1753         .emit_ib = vcn_v2_0_enc_ring_emit_ib,
1754         .emit_fence = vcn_v2_0_enc_ring_emit_fence,
1755         .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
1756         .test_ring = amdgpu_vcn_enc_ring_test_ring,
1757         .test_ib = amdgpu_vcn_enc_ring_test_ib,
1758         .insert_nop = amdgpu_ring_insert_nop,
1759         .insert_end = vcn_v2_0_enc_ring_insert_end,
1760         .pad_ib = amdgpu_ring_generic_pad_ib,
1761         .begin_use = amdgpu_vcn_ring_begin_use,
1762         .end_use = amdgpu_vcn_ring_end_use,
1763         .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
1764         .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
1765         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1766 };
1767
1768 static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev)
1769 {
1770         adev->vcn.inst->ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs;
1771         DRM_INFO("VCN decode is enabled in VM mode\n");
1772 }
1773
1774 static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev)
1775 {
1776         int i;
1777
1778         for (i = 0; i < adev->vcn.num_enc_rings; ++i)
1779                 adev->vcn.inst->ring_enc[i].funcs = &vcn_v2_0_enc_ring_vm_funcs;
1780
1781         DRM_INFO("VCN encode is enabled in VM mode\n");
1782 }
1783
1784 static const struct amdgpu_irq_src_funcs vcn_v2_0_irq_funcs = {
1785         .set = vcn_v2_0_set_interrupt_state,
1786         .process = vcn_v2_0_process_interrupt,
1787 };
1788
1789 static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev)
1790 {
1791         adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 1;
1792         adev->vcn.inst->irq.funcs = &vcn_v2_0_irq_funcs;
1793 }
1794
1795 const struct amdgpu_ip_block_version vcn_v2_0_ip_block =
1796 {
1797                 .type = AMD_IP_BLOCK_TYPE_VCN,
1798                 .major = 2,
1799                 .minor = 0,
1800                 .rev = 0,
1801                 .funcs = &vcn_v2_0_ip_funcs,
1802 };