drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Christian König <christian.koenig@amd.com>
  23  */
  24
  25 #include <linux/firmware.h>
  26 #include <drm/drmP.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_uvd.h"
  29 #include "vid.h"
  30 #include "uvd/uvd_6_0_d.h"
  31 #include "uvd/uvd_6_0_sh_mask.h"
  32 #include "oss/oss_2_0_d.h"
  33 #include "oss/oss_2_0_sh_mask.h"
  34 #include "smu/smu_7_1_3_d.h"
  35 #include "smu/smu_7_1_3_sh_mask.h"
  36 #include "bif/bif_5_1_d.h"
  37 #include "gmc/gmc_8_1_d.h"
  38 #include "vi.h"
  39 #include "ivsrcid/ivsrcid_vislands30.h"
  40
  41 /* Polaris10/11/12 firmware version */
  42 #define FW_1_130_16 ((1 << 24) | (130 << 16) | (16 << 8))
  43
  44 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev);
  45 static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev);
  46
  47 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev);
  48 static int uvd_v6_0_start(struct amdgpu_device *adev);
  49 static void uvd_v6_0_stop(struct amdgpu_device *adev);
  50 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev);
  51 static int uvd_v6_0_set_clockgating_state(void *handle,
  52                                           enum amd_clockgating_state state);
  53 static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
  54                                  bool enable);
  55
  56 /**
  57 * uvd_v6_0_enc_support - get encode support status
  58 *
  59 * @adev: amdgpu_device pointer
  60 *
  61 * Returns the current hardware encode support status
  62 */
  63 static inline bool uvd_v6_0_enc_support(struct amdgpu_device *adev)
  64 {
  65         return ((adev->asic_type >= CHIP_POLARIS10) &&
  66                         (adev->asic_type <= CHIP_VEGAM) &&
  67                         (!adev->uvd.fw_version || adev->uvd.fw_version >= FW_1_130_16));
  68 }
  69
  70 /**
  71  * uvd_v6_0_ring_get_rptr - get read pointer
  72  *
  73  * @ring: amdgpu_ring pointer
  74  *
  75  * Returns the current hardware read pointer
  76  */
  77 static uint64_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
  78 {
  79         struct amdgpu_device *adev = ring->adev;
  80
  81         return RREG32(mmUVD_RBC_RB_RPTR);
  82 }
  83
  84 /**
  85  * uvd_v6_0_enc_ring_get_rptr - get enc read pointer
  86  *
  87  * @ring: amdgpu_ring pointer
  88  *
  89  * Returns the current hardware enc read pointer
  90  */
  91 static uint64_t uvd_v6_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
  92 {
  93         struct amdgpu_device *adev = ring->adev;
  94
  95         if (ring == &adev->uvd.inst->ring_enc[0])
  96                 return RREG32(mmUVD_RB_RPTR);
  97         else
  98                 return RREG32(mmUVD_RB_RPTR2);
  99 }
 100 /**
 101  * uvd_v6_0_ring_get_wptr - get write pointer
 102  *
 103  * @ring: amdgpu_ring pointer
 104  *
 105  * Returns the current hardware write pointer
 106  */
 107 static uint64_t uvd_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
 108 {
 109         struct amdgpu_device *adev = ring->adev;
 110
 111         return RREG32(mmUVD_RBC_RB_WPTR);
 112 }
 113
 114 /**
 115  * uvd_v6_0_enc_ring_get_wptr - get enc write pointer
 116  *
 117  * @ring: amdgpu_ring pointer
 118  *
 119  * Returns the current hardware enc write pointer
 120  */
 121 static uint64_t uvd_v6_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
 122 {
 123         struct amdgpu_device *adev = ring->adev;
 124
 125         if (ring == &adev->uvd.inst->ring_enc[0])
 126                 return RREG32(mmUVD_RB_WPTR);
 127         else
 128                 return RREG32(mmUVD_RB_WPTR2);
 129 }
 130
 131 /**
 132  * uvd_v6_0_ring_set_wptr - set write pointer
 133  *
 134  * @ring: amdgpu_ring pointer
 135  *
 136  * Commits the write pointer to the hardware
 137  */
 138 static void uvd_v6_0_ring_set_wptr(struct amdgpu_ring *ring)
 139 {
 140         struct amdgpu_device *adev = ring->adev;
 141
 142         WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
 143 }
 144
 145 /**
 146  * uvd_v6_0_enc_ring_set_wptr - set enc write pointer
 147  *
 148  * @ring: amdgpu_ring pointer
 149  *
 150  * Commits the enc write pointer to the hardware
 151  */
 152 static void uvd_v6_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
 153 {
 154         struct amdgpu_device *adev = ring->adev;
 155
 156         if (ring == &adev->uvd.inst->ring_enc[0])
 157                 WREG32(mmUVD_RB_WPTR,
 158                         lower_32_bits(ring->wptr));
 159         else
 160                 WREG32(mmUVD_RB_WPTR2,
 161                         lower_32_bits(ring->wptr));
 162 }
 163
 164 /**
 165  * uvd_v6_0_enc_ring_test_ring - test if UVD ENC ring is working
 166  *
 167  * @ring: the engine to test on
 168  *
 169  */
 170 static int uvd_v6_0_enc_ring_test_ring(struct amdgpu_ring *ring)
 171 {
 172         struct amdgpu_device *adev = ring->adev;
 173         uint32_t rptr = amdgpu_ring_get_rptr(ring);
 174         unsigned i;
 175         int r;
 176
 177         r = amdgpu_ring_alloc(ring, 16);
 178         if (r) {
 179                 DRM_ERROR("amdgpu: uvd enc failed to lock ring %d (%d).\n",
 180                           ring->idx, r);
 181                 return r;
 182         }
 183         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
 184         amdgpu_ring_commit(ring);
 185
 186         for (i = 0; i < adev->usec_timeout; i++) {
 187                 if (amdgpu_ring_get_rptr(ring) != rptr)
 188                         break;
 189                 DRM_UDELAY(1);
 190         }
 191
 192         if (i < adev->usec_timeout) {
 193                 DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
 194                          ring->idx, i);
 195         } else {
 196                 DRM_ERROR("amdgpu: ring %d test failed\n",
 197                           ring->idx);
 198                 r = -ETIMEDOUT;
 199         }
 200
 201         return r;
 202 }
 203
 204 /**
 205  * uvd_v6_0_enc_get_create_msg - generate a UVD ENC create msg
 206  *
 207  * @adev: amdgpu_device pointer
 208  * @ring: ring we should submit the msg to
 209  * @handle: session handle to use
 210  * @fence: optional fence to return
 211  *
 212  * Open up a stream for HW test
 213  */
 214 static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 215                                        struct dma_fence **fence)
 216 {
 217         const unsigned ib_size_dw = 16;
 218         struct amdgpu_job *job;
 219         struct amdgpu_ib *ib;
 220         struct dma_fence *f = NULL;
 221         uint64_t dummy;
 222         int i, r;
 223
 224         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 225         if (r)
 226                 return r;
 227
 228         ib = &job->ibs[0];
 229         dummy = ib->gpu_addr + 1024;
 230
 231         ib->length_dw = 0;
 232         ib->ptr[ib->length_dw++] = 0x00000018;
 233         ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
 234         ib->ptr[ib->length_dw++] = handle;
 235         ib->ptr[ib->length_dw++] = 0x00010000;
 236         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 237         ib->ptr[ib->length_dw++] = dummy;
 238
 239         ib->ptr[ib->length_dw++] = 0x00000014;
 240         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 241         ib->ptr[ib->length_dw++] = 0x0000001c;
 242         ib->ptr[ib->length_dw++] = 0x00000001;
 243         ib->ptr[ib->length_dw++] = 0x00000000;
 244
 245         ib->ptr[ib->length_dw++] = 0x00000008;
 246         ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
 247
 248         for (i = ib->length_dw; i < ib_size_dw; ++i)
 249                 ib->ptr[i] = 0x0;
 250
 251         r = amdgpu_job_submit_direct(job, ring, &f);
 252         if (r)
 253                 goto err;
 254
 255         if (fence)
 256                 *fence = dma_fence_get(f);
 257         dma_fence_put(f);
 258         return 0;
 259
 260 err:
 261         amdgpu_job_free(job);
 262         return r;
 263 }
 264
 265 /**
 266  * uvd_v6_0_enc_get_destroy_msg - generate a UVD ENC destroy msg
 267  *
 268  * @adev: amdgpu_device pointer
 269  * @ring: ring we should submit the msg to
 270  * @handle: session handle to use
 271  * @fence: optional fence to return
 272  *
 273  * Close up a stream for HW test or if userspace failed to do so
 274  */
 275 static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring,
 276                                         uint32_t handle,
 277                                         struct dma_fence **fence)
 278 {
 279         const unsigned ib_size_dw = 16;
 280         struct amdgpu_job *job;
 281         struct amdgpu_ib *ib;
 282         struct dma_fence *f = NULL;
 283         uint64_t dummy;
 284         int i, r;
 285
 286         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 287         if (r)
 288                 return r;
 289
 290         ib = &job->ibs[0];
 291         dummy = ib->gpu_addr + 1024;
 292
 293         ib->length_dw = 0;
 294         ib->ptr[ib->length_dw++] = 0x00000018;
 295         ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
 296         ib->ptr[ib->length_dw++] = handle;
 297         ib->ptr[ib->length_dw++] = 0x00010000;
 298         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 299         ib->ptr[ib->length_dw++] = dummy;
 300
 301         ib->ptr[ib->length_dw++] = 0x00000014;
 302         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 303         ib->ptr[ib->length_dw++] = 0x0000001c;
 304         ib->ptr[ib->length_dw++] = 0x00000001;
 305         ib->ptr[ib->length_dw++] = 0x00000000;
 306
 307         ib->ptr[ib->length_dw++] = 0x00000008;
 308         ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
 309
 310         for (i = ib->length_dw; i < ib_size_dw; ++i)
 311                 ib->ptr[i] = 0x0;
 312
 313         r = amdgpu_job_submit_direct(job, ring, &f);
 314         if (r)
 315                 goto err;
 316
 317         if (fence)
 318                 *fence = dma_fence_get(f);
 319         dma_fence_put(f);
 320         return 0;
 321
 322 err:
 323         amdgpu_job_free(job);
 324         return r;
 325 }
 326
 327 /**
 328  * uvd_v6_0_enc_ring_test_ib - test if UVD ENC IBs are working
 329  *
 330  * @ring: the engine to test on
 331  *
 332  */
 333 static int uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 334 {
 335         struct dma_fence *fence = NULL;
 336         long r;
 337
 338         r = uvd_v6_0_enc_get_create_msg(ring, 1, NULL);
 339         if (r) {
 340                 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
 341                 goto error;
 342         }
 343
 344         r = uvd_v6_0_enc_get_destroy_msg(ring, 1, &fence);
 345         if (r) {
 346                 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
 347                 goto error;
 348         }
 349
 350         r = dma_fence_wait_timeout(fence, false, timeout);
 351         if (r == 0) {
 352                 DRM_ERROR("amdgpu: IB test timed out.\n");
 353                 r = -ETIMEDOUT;
 354         } else if (r < 0) {
 355                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 356         } else {
 357                 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
 358                 r = 0;
 359         }
 360 error:
 361         dma_fence_put(fence);
 362         return r;
 363 }
 364 static int uvd_v6_0_early_init(void *handle)
 365 {
 366         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 367         adev->uvd.num_uvd_inst = 1;
 368
 369         if (!(adev->flags & AMD_IS_APU) &&
 370             (RREG32_SMC(ixCC_HARVEST_FUSES) & CC_HARVEST_FUSES__UVD_DISABLE_MASK))
 371                 return -ENOENT;
 372
 373         uvd_v6_0_set_ring_funcs(adev);
 374
 375         if (uvd_v6_0_enc_support(adev)) {
 376                 adev->uvd.num_enc_rings = 2;
 377                 uvd_v6_0_set_enc_ring_funcs(adev);
 378         }
 379
 380         uvd_v6_0_set_irq_funcs(adev);
 381
 382         return 0;
 383 }
 384
 385 static int uvd_v6_0_sw_init(void *handle)
 386 {
 387         struct amdgpu_ring *ring;
 388         int i, r;
 389         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 390
 391         /* UVD TRAP */
 392         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq);
 393         if (r)
 394                 return r;
 395
 396         /* UVD ENC TRAP */
 397         if (uvd_v6_0_enc_support(adev)) {
 398                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 399                         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP, &adev->uvd.inst->irq);
 400                         if (r)
 401                                 return r;
 402                 }
 403         }
 404
 405         r = amdgpu_uvd_sw_init(adev);
 406         if (r)
 407                 return r;
 408
 409         if (!uvd_v6_0_enc_support(adev)) {
 410                 for (i = 0; i < adev->uvd.num_enc_rings; ++i)
 411                         adev->uvd.inst->ring_enc[i].funcs = NULL;
 412
 413                 adev->uvd.inst->irq.num_types = 1;
 414                 adev->uvd.num_enc_rings = 0;
 415
 416                 DRM_INFO("UVD ENC is disabled\n");
 417         }
 418
 419         r = amdgpu_uvd_resume(adev);
 420         if (r)
 421                 return r;
 422
 423         ring = &adev->uvd.inst->ring;
 424         sprintf(ring->name, "uvd");
 425         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0);
 426         if (r)
 427                 return r;
 428
 429         if (uvd_v6_0_enc_support(adev)) {
 430                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 431                         ring = &adev->uvd.inst->ring_enc[i];
 432                         sprintf(ring->name, "uvd_enc%d", i);
 433                         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0);
 434                         if (r)
 435                                 return r;
 436                 }
 437         }
 438
 439         r = amdgpu_uvd_entity_init(adev);
 440
 441         return r;
 442 }
 443
 444 static int uvd_v6_0_sw_fini(void *handle)
 445 {
 446         int i, r;
 447         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 448
 449         r = amdgpu_uvd_suspend(adev);
 450         if (r)
 451                 return r;
 452
 453         if (uvd_v6_0_enc_support(adev)) {
 454                 for (i = 0; i < adev->uvd.num_enc_rings; ++i)
 455                         amdgpu_ring_fini(&adev->uvd.inst->ring_enc[i]);
 456         }
 457
 458         return amdgpu_uvd_sw_fini(adev);
 459 }
 460
 461 /**
 462  * uvd_v6_0_hw_init - start and test UVD block
 463  *
 464  * @adev: amdgpu_device pointer
 465  *
 466  * Initialize the hardware, boot up the VCPU and do some testing
 467  */
 468 static int uvd_v6_0_hw_init(void *handle)
 469 {
 470         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 471         struct amdgpu_ring *ring = &adev->uvd.inst->ring;
 472         uint32_t tmp;
 473         int i, r;
 474
 475         amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
 476         uvd_v6_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
 477         uvd_v6_0_enable_mgcg(adev, true);
 478
 479         ring->ready = true;
 480         r = amdgpu_ring_test_ring(ring);
 481         if (r) {
 482                 ring->ready = false;
 483                 goto done;
 484         }
 485
 486         r = amdgpu_ring_alloc(ring, 10);
 487         if (r) {
 488                 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
 489                 goto done;
 490         }
 491
 492         tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
 493         amdgpu_ring_write(ring, tmp);
 494         amdgpu_ring_write(ring, 0xFFFFF);
 495
 496         tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
 497         amdgpu_ring_write(ring, tmp);
 498         amdgpu_ring_write(ring, 0xFFFFF);
 499
 500         tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
 501         amdgpu_ring_write(ring, tmp);
 502         amdgpu_ring_write(ring, 0xFFFFF);
 503
 504         /* Clear timeout status bits */
 505         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
 506         amdgpu_ring_write(ring, 0x8);
 507
 508         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
 509         amdgpu_ring_write(ring, 3);
 510
 511         amdgpu_ring_commit(ring);
 512
 513         if (uvd_v6_0_enc_support(adev)) {
 514                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 515                         ring = &adev->uvd.inst->ring_enc[i];
 516                         ring->ready = true;
 517                         r = amdgpu_ring_test_ring(ring);
 518                         if (r) {
 519                                 ring->ready = false;
 520                                 goto done;
 521                         }
 522                 }
 523         }
 524
 525 done:
 526         if (!r) {
 527                 if (uvd_v6_0_enc_support(adev))
 528                         DRM_INFO("UVD and UVD ENC initialized successfully.\n");
 529                 else
 530                         DRM_INFO("UVD initialized successfully.\n");
 531         }
 532
 533         return r;
 534 }
 535
 536 /**
 537  * uvd_v6_0_hw_fini - stop the hardware block
 538  *
 539  * @adev: amdgpu_device pointer
 540  *
 541  * Stop the UVD block, mark ring as not ready any more
 542  */
 543 static int uvd_v6_0_hw_fini(void *handle)
 544 {
 545         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 546         struct amdgpu_ring *ring = &adev->uvd.inst->ring;
 547
 548         if (RREG32(mmUVD_STATUS) != 0)
 549                 uvd_v6_0_stop(adev);
 550
 551         ring->ready = false;
 552
 553         return 0;
 554 }
 555
 556 static int uvd_v6_0_suspend(void *handle)
 557 {
 558         int r;
 559         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 560
 561         r = uvd_v6_0_hw_fini(adev);
 562         if (r)
 563                 return r;
 564
 565         return amdgpu_uvd_suspend(adev);
 566 }
 567
 568 static int uvd_v6_0_resume(void *handle)
 569 {
 570         int r;
 571         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 572
 573         r = amdgpu_uvd_resume(adev);
 574         if (r)
 575                 return r;
 576
 577         return uvd_v6_0_hw_init(adev);
 578 }
 579
 580 /**
 581  * uvd_v6_0_mc_resume - memory controller programming
 582  *
 583  * @adev: amdgpu_device pointer
 584  *
 585  * Let the UVD memory controller know it's offsets
 586  */
 587 static void uvd_v6_0_mc_resume(struct amdgpu_device *adev)
 588 {
 589         uint64_t offset;
 590         uint32_t size;
 591
 592         /* programm memory controller bits 0-27 */
 593         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 594                         lower_32_bits(adev->uvd.inst->gpu_addr));
 595         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 596                         upper_32_bits(adev->uvd.inst->gpu_addr));
 597
 598         offset = AMDGPU_UVD_FIRMWARE_OFFSET;
 599         size = AMDGPU_UVD_FIRMWARE_SIZE(adev);
 600         WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
 601         WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
 602
 603         offset += size;
 604         size = AMDGPU_UVD_HEAP_SIZE;
 605         WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
 606         WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
 607
 608         offset += size;
 609         size = AMDGPU_UVD_STACK_SIZE +
 610                (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles);
 611         WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
 612         WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
 613
 614         WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 615         WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 616         WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 617
 618         WREG32(mmUVD_GP_SCRATCH4, adev->uvd.max_handles);
 619 }
 620
 621 #if 0
 622 static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev,
 623                 bool enable)
 624 {
 625         u32 data, data1;
 626
 627         data = RREG32(mmUVD_CGC_GATE);
 628         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
 629         if (enable) {
 630                 data |= UVD_CGC_GATE__SYS_MASK |
 631                                 UVD_CGC_GATE__UDEC_MASK |
 632                                 UVD_CGC_GATE__MPEG2_MASK |
 633                                 UVD_CGC_GATE__RBC_MASK |
 634                                 UVD_CGC_GATE__LMI_MC_MASK |
 635                                 UVD_CGC_GATE__IDCT_MASK |
 636                                 UVD_CGC_GATE__MPRD_MASK |
 637                                 UVD_CGC_GATE__MPC_MASK |
 638                                 UVD_CGC_GATE__LBSI_MASK |
 639                                 UVD_CGC_GATE__LRBBM_MASK |
 640                                 UVD_CGC_GATE__UDEC_RE_MASK |
 641                                 UVD_CGC_GATE__UDEC_CM_MASK |
 642                                 UVD_CGC_GATE__UDEC_IT_MASK |
 643                                 UVD_CGC_GATE__UDEC_DB_MASK |
 644                                 UVD_CGC_GATE__UDEC_MP_MASK |
 645                                 UVD_CGC_GATE__WCB_MASK |
 646                                 UVD_CGC_GATE__VCPU_MASK |
 647                                 UVD_CGC_GATE__SCPU_MASK;
 648                 data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
 649                                 UVD_SUVD_CGC_GATE__SIT_MASK |
 650                                 UVD_SUVD_CGC_GATE__SMP_MASK |
 651                                 UVD_SUVD_CGC_GATE__SCM_MASK |
 652                                 UVD_SUVD_CGC_GATE__SDB_MASK |
 653                                 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
 654                                 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
 655                                 UVD_SUVD_CGC_GATE__SIT_H264_MASK |
 656                                 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
 657                                 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
 658                                 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
 659                                 UVD_SUVD_CGC_GATE__SDB_H264_MASK |
 660                                 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK;
 661         } else {
 662                 data &= ~(UVD_CGC_GATE__SYS_MASK |
 663                                 UVD_CGC_GATE__UDEC_MASK |
 664                                 UVD_CGC_GATE__MPEG2_MASK |
 665                                 UVD_CGC_GATE__RBC_MASK |
 666                                 UVD_CGC_GATE__LMI_MC_MASK |
 667                                 UVD_CGC_GATE__LMI_UMC_MASK |
 668                                 UVD_CGC_GATE__IDCT_MASK |
 669                                 UVD_CGC_GATE__MPRD_MASK |
 670                                 UVD_CGC_GATE__MPC_MASK |
 671                                 UVD_CGC_GATE__LBSI_MASK |
 672                                 UVD_CGC_GATE__LRBBM_MASK |
 673                                 UVD_CGC_GATE__UDEC_RE_MASK |
 674                                 UVD_CGC_GATE__UDEC_CM_MASK |
 675                                 UVD_CGC_GATE__UDEC_IT_MASK |
 676                                 UVD_CGC_GATE__UDEC_DB_MASK |
 677                                 UVD_CGC_GATE__UDEC_MP_MASK |
 678                                 UVD_CGC_GATE__WCB_MASK |
 679                                 UVD_CGC_GATE__VCPU_MASK |
 680                                 UVD_CGC_GATE__SCPU_MASK);
 681                 data1 &= ~(UVD_SUVD_CGC_GATE__SRE_MASK |
 682                                 UVD_SUVD_CGC_GATE__SIT_MASK |
 683                                 UVD_SUVD_CGC_GATE__SMP_MASK |
 684                                 UVD_SUVD_CGC_GATE__SCM_MASK |
 685                                 UVD_SUVD_CGC_GATE__SDB_MASK |
 686                                 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
 687                                 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
 688                                 UVD_SUVD_CGC_GATE__SIT_H264_MASK |
 689                                 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
 690                                 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
 691                                 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
 692                                 UVD_SUVD_CGC_GATE__SDB_H264_MASK |
 693                                 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK);
 694         }
 695         WREG32(mmUVD_CGC_GATE, data);
 696         WREG32(mmUVD_SUVD_CGC_GATE, data1);
 697 }
 698 #endif
 699
 700 /**
 701  * uvd_v6_0_start - start UVD block
 702  *
 703  * @adev: amdgpu_device pointer
 704  *
 705  * Setup and start the UVD block
 706  */
 707 static int uvd_v6_0_start(struct amdgpu_device *adev)
 708 {
 709         struct amdgpu_ring *ring = &adev->uvd.inst->ring;
 710         uint32_t rb_bufsz, tmp;
 711         uint32_t lmi_swap_cntl;
 712         uint32_t mp_swap_cntl;
 713         int i, j, r;
 714
 715         /* disable DPG */
 716         WREG32_P(mmUVD_POWER_STATUS, 0, ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
 717
 718         /* disable byte swapping */
 719         lmi_swap_cntl = 0;
 720         mp_swap_cntl = 0;
 721
 722         uvd_v6_0_mc_resume(adev);
 723
 724         /* disable interupt */
 725         WREG32_FIELD(UVD_MASTINT_EN, VCPU_EN, 0);
 726
 727         /* stall UMC and register bus before resetting VCPU */
 728         WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 1);
 729         mdelay(1);
 730
 731         /* put LMI, VCPU, RBC etc... into reset */
 732         WREG32(mmUVD_SOFT_RESET,
 733                 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 734                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 735                 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 736                 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
 737                 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 738                 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
 739                 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 740                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
 741         mdelay(5);
 742
 743         /* take UVD block out of reset */
 744         WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_UVD, 0);
 745         mdelay(5);
 746
 747         /* initialize UVD memory controller */
 748         WREG32(mmUVD_LMI_CTRL,
 749                 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 750                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 751                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 752                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 753                 UVD_LMI_CTRL__REQ_MODE_MASK |
 754                 UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK);
 755
 756 #ifdef __BIG_ENDIAN
 757         /* swap (8 in 32) RB and IB */
 758         lmi_swap_cntl = 0xa;
 759         mp_swap_cntl = 0;
 760 #endif
 761         WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 762         WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
 763
 764         WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
 765         WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
 766         WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
 767         WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
 768         WREG32(mmUVD_MPC_SET_ALU, 0);
 769         WREG32(mmUVD_MPC_SET_MUX, 0x88);
 770
 771         /* take all subblocks out of reset, except VCPU */
 772         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 773         mdelay(5);
 774
 775         /* enable VCPU clock */
 776         WREG32(mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
 777
 778         /* enable UMC */
 779         WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 0);
 780
 781         /* boot up the VCPU */
 782         WREG32(mmUVD_SOFT_RESET, 0);
 783         mdelay(10);
 784
 785         for (i = 0; i < 10; ++i) {
 786                 uint32_t status;
 787
 788                 for (j = 0; j < 100; ++j) {
 789                         status = RREG32(mmUVD_STATUS);
 790                         if (status & 2)
 791                                 break;
 792                         mdelay(10);
 793                 }
 794                 r = 0;
 795                 if (status & 2)
 796                         break;
 797
 798                 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
 799                 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 1);
 800                 mdelay(10);
 801                 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 0);
 802                 mdelay(10);
 803                 r = -1;
 804         }
 805
 806         if (r) {
 807                 DRM_ERROR("UVD not responding, giving up!!!\n");
 808                 return r;
 809         }
 810         /* enable master interrupt */
 811         WREG32_P(mmUVD_MASTINT_EN,
 812                 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
 813                 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
 814
 815         /* clear the bit 4 of UVD_STATUS */
 816         WREG32_P(mmUVD_STATUS, 0, ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
 817
 818         /* force RBC into idle state */
 819         rb_bufsz = order_base_2(ring->ring_size);
 820         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
 821         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
 822         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 823         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
 824         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
 825         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
 826         WREG32(mmUVD_RBC_RB_CNTL, tmp);
 827
 828         /* set the write pointer delay */
 829         WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
 830
 831         /* set the wb address */
 832         WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
 833
 834         /* programm the RB_BASE for ring buffer */
 835         WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
 836                         lower_32_bits(ring->gpu_addr));
 837         WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
 838                         upper_32_bits(ring->gpu_addr));
 839
 840         /* Initialize the ring buffer's read and write pointers */
 841         WREG32(mmUVD_RBC_RB_RPTR, 0);
 842
 843         ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
 844         WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
 845
 846         WREG32_FIELD(UVD_RBC_RB_CNTL, RB_NO_FETCH, 0);
 847
 848         if (uvd_v6_0_enc_support(adev)) {
 849                 ring = &adev->uvd.inst->ring_enc[0];
 850                 WREG32(mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
 851                 WREG32(mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
 852                 WREG32(mmUVD_RB_BASE_LO, ring->gpu_addr);
 853                 WREG32(mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
 854                 WREG32(mmUVD_RB_SIZE, ring->ring_size / 4);
 855
 856                 ring = &adev->uvd.inst->ring_enc[1];
 857                 WREG32(mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
 858                 WREG32(mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
 859                 WREG32(mmUVD_RB_BASE_LO2, ring->gpu_addr);
 860                 WREG32(mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
 861                 WREG32(mmUVD_RB_SIZE2, ring->ring_size / 4);
 862         }
 863
 864         return 0;
 865 }
 866
 867 /**
 868  * uvd_v6_0_stop - stop UVD block
 869  *
 870  * @adev: amdgpu_device pointer
 871  *
 872  * stop the UVD block
 873  */
 874 static void uvd_v6_0_stop(struct amdgpu_device *adev)
 875 {
 876         /* force RBC into idle state */
 877         WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
 878
 879         /* Stall UMC and register bus before resetting VCPU */
 880         WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
 881         mdelay(1);
 882
 883         /* put VCPU into reset */
 884         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 885         mdelay(5);
 886
 887         /* disable VCPU clock */
 888         WREG32(mmUVD_VCPU_CNTL, 0x0);
 889
 890         /* Unstall UMC and register bus */
 891         WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
 892
 893         WREG32(mmUVD_STATUS, 0);
 894 }
 895
 896 /**
 897  * uvd_v6_0_ring_emit_fence - emit an fence & trap command
 898  *
 899  * @ring: amdgpu_ring pointer
 900  * @fence: fence to emit
 901  *
 902  * Write a fence and a trap command to the ring.
 903  */
 904 static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 905                                      unsigned flags)
 906 {
 907         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 908
 909         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
 910         amdgpu_ring_write(ring, seq);
 911         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 912         amdgpu_ring_write(ring, addr & 0xffffffff);
 913         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 914         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
 915         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 916         amdgpu_ring_write(ring, 0);
 917
 918         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 919         amdgpu_ring_write(ring, 0);
 920         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 921         amdgpu_ring_write(ring, 0);
 922         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 923         amdgpu_ring_write(ring, 2);
 924 }
 925
 926 /**
 927  * uvd_v6_0_enc_ring_emit_fence - emit an enc fence & trap command
 928  *
 929  * @ring: amdgpu_ring pointer
 930  * @fence: fence to emit
 931  *
 932  * Write enc a fence and a trap command to the ring.
 933  */
 934 static void uvd_v6_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
 935                         u64 seq, unsigned flags)
 936 {
 937         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 938
 939         amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE);
 940         amdgpu_ring_write(ring, addr);
 941         amdgpu_ring_write(ring, upper_32_bits(addr));
 942         amdgpu_ring_write(ring, seq);
 943         amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
 944 }
 945
 946 /**
 947  * uvd_v6_0_ring_emit_hdp_flush - skip HDP flushing
 948  *
 949  * @ring: amdgpu_ring pointer
 950  */
 951 static void uvd_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 952 {
 953         /* The firmware doesn't seem to like touching registers at this point. */
 954 }
 955
 956 /**
 957  * uvd_v6_0_ring_test_ring - register write test
 958  *
 959  * @ring: amdgpu_ring pointer
 960  *
 961  * Test if we can successfully write to the context register
 962  */
 963 static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring)
 964 {
 965         struct amdgpu_device *adev = ring->adev;
 966         uint32_t tmp = 0;
 967         unsigned i;
 968         int r;
 969
 970         WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
 971         r = amdgpu_ring_alloc(ring, 3);
 972         if (r) {
 973                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 974                           ring->idx, r);
 975                 return r;
 976         }
 977         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
 978         amdgpu_ring_write(ring, 0xDEADBEEF);
 979         amdgpu_ring_commit(ring);
 980         for (i = 0; i < adev->usec_timeout; i++) {
 981                 tmp = RREG32(mmUVD_CONTEXT_ID);
 982                 if (tmp == 0xDEADBEEF)
 983                         break;
 984                 DRM_UDELAY(1);
 985         }
 986
 987         if (i < adev->usec_timeout) {
 988                 DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
 989                          ring->idx, i);
 990         } else {
 991                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 992                           ring->idx, tmp);
 993                 r = -EINVAL;
 994         }
 995         return r;
 996 }
 997
 998 /**
 999  * uvd_v6_0_ring_emit_ib - execute indirect buffer
1000  *
1001  * @ring: amdgpu_ring pointer
1002  * @ib: indirect buffer to execute
1003  *
1004  * Write ring commands to execute the indirect buffer
1005  */
1006 static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
1007                                   struct amdgpu_ib *ib,
1008                                   unsigned vmid, bool ctx_switch)
1009 {
1010         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_VMID, 0));
1011         amdgpu_ring_write(ring, vmid);
1012
1013         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
1014         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1015         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0));
1016         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1017         amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
1018         amdgpu_ring_write(ring, ib->length_dw);
1019 }
1020
1021 /**
1022  * uvd_v6_0_enc_ring_emit_ib - enc execute indirect buffer
1023  *
1024  * @ring: amdgpu_ring pointer
1025  * @ib: indirect buffer to execute
1026  *
1027  * Write enc ring commands to execute the indirect buffer
1028  */
1029 static void uvd_v6_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1030                 struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch)
1031 {
1032         amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM);
1033         amdgpu_ring_write(ring, vmid);
1034         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1035         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1036         amdgpu_ring_write(ring, ib->length_dw);
1037 }
1038
1039 static void uvd_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
1040                                     uint32_t reg, uint32_t val)
1041 {
1042         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
1043         amdgpu_ring_write(ring, reg << 2);
1044         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
1045         amdgpu_ring_write(ring, val);
1046         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
1047         amdgpu_ring_write(ring, 0x8);
1048 }
1049
1050 static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1051                                         unsigned vmid, uint64_t pd_addr)
1052 {
1053         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1054
1055         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
1056         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1057         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
1058         amdgpu_ring_write(ring, 0);
1059         amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));
1060         amdgpu_ring_write(ring, 1 << vmid); /* mask */
1061         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
1062         amdgpu_ring_write(ring, 0xC);
1063 }
1064
1065 static void uvd_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1066 {
1067         uint32_t seq = ring->fence_drv.sync_seq;
1068         uint64_t addr = ring->fence_drv.gpu_addr;
1069
1070         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
1071         amdgpu_ring_write(ring, lower_32_bits(addr));
1072         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
1073         amdgpu_ring_write(ring, upper_32_bits(addr));
1074         amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));
1075         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1076         amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH9, 0));
1077         amdgpu_ring_write(ring, seq);
1078         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
1079         amdgpu_ring_write(ring, 0xE);
1080 }
1081
1082 static void uvd_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1083 {
1084         int i;
1085
1086         WARN_ON(ring->wptr % 2 || count % 2);
1087
1088         for (i = 0; i < count / 2; i++) {
1089                 amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0));
1090                 amdgpu_ring_write(ring, 0);
1091         }
1092 }
1093
1094 static void uvd_v6_0_enc_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1095 {
1096         uint32_t seq = ring->fence_drv.sync_seq;
1097         uint64_t addr = ring->fence_drv.gpu_addr;
1098
1099         amdgpu_ring_write(ring, HEVC_ENC_CMD_WAIT_GE);
1100         amdgpu_ring_write(ring, lower_32_bits(addr));
1101         amdgpu_ring_write(ring, upper_32_bits(addr));
1102         amdgpu_ring_write(ring, seq);
1103 }
1104
1105 static void uvd_v6_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1106 {
1107         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
1108 }
1109
1110 static void uvd_v6_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1111                                             unsigned int vmid, uint64_t pd_addr)
1112 {
1113         amdgpu_ring_write(ring, HEVC_ENC_CMD_UPDATE_PTB);
1114         amdgpu_ring_write(ring, vmid);
1115         amdgpu_ring_write(ring, pd_addr >> 12);
1116
1117         amdgpu_ring_write(ring, HEVC_ENC_CMD_FLUSH_TLB);
1118         amdgpu_ring_write(ring, vmid);
1119 }
1120
1121 static bool uvd_v6_0_is_idle(void *handle)
1122 {
1123         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1124
1125         return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
1126 }
1127
1128 static int uvd_v6_0_wait_for_idle(void *handle)
1129 {
1130         unsigned i;
1131         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1132
1133         for (i = 0; i < adev->usec_timeout; i++) {
1134                 if (uvd_v6_0_is_idle(handle))
1135                         return 0;
1136         }
1137         return -ETIMEDOUT;
1138 }
1139
1140 #define AMDGPU_UVD_STATUS_BUSY_MASK    0xfd
1141 static bool uvd_v6_0_check_soft_reset(void *handle)
1142 {
1143         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1144         u32 srbm_soft_reset = 0;
1145         u32 tmp = RREG32(mmSRBM_STATUS);
1146
1147         if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||
1148             REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||
1149             (RREG32(mmUVD_STATUS) & AMDGPU_UVD_STATUS_BUSY_MASK))
1150                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
1151
1152         if (srbm_soft_reset) {
1153                 adev->uvd.inst->srbm_soft_reset = srbm_soft_reset;
1154                 return true;
1155         } else {
1156                 adev->uvd.inst->srbm_soft_reset = 0;
1157                 return false;
1158         }
1159 }
1160
1161 static int uvd_v6_0_pre_soft_reset(void *handle)
1162 {
1163         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1164
1165         if (!adev->uvd.inst->srbm_soft_reset)
1166                 return 0;
1167
1168         uvd_v6_0_stop(adev);
1169         return 0;
1170 }
1171
1172 static int uvd_v6_0_soft_reset(void *handle)
1173 {
1174         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1175         u32 srbm_soft_reset;
1176
1177         if (!adev->uvd.inst->srbm_soft_reset)
1178                 return 0;
1179         srbm_soft_reset = adev->uvd.inst->srbm_soft_reset;
1180
1181         if (srbm_soft_reset) {
1182                 u32 tmp;
1183
1184                 tmp = RREG32(mmSRBM_SOFT_RESET);
1185                 tmp |= srbm_soft_reset;
1186                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1187                 WREG32(mmSRBM_SOFT_RESET, tmp);
1188                 tmp = RREG32(mmSRBM_SOFT_RESET);
1189
1190                 udelay(50);
1191
1192                 tmp &= ~srbm_soft_reset;
1193                 WREG32(mmSRBM_SOFT_RESET, tmp);
1194                 tmp = RREG32(mmSRBM_SOFT_RESET);
1195
1196                 /* Wait a little for things to settle down */
1197                 udelay(50);
1198         }
1199
1200         return 0;
1201 }
1202
1203 static int uvd_v6_0_post_soft_reset(void *handle)
1204 {
1205         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1206
1207         if (!adev->uvd.inst->srbm_soft_reset)
1208                 return 0;
1209
1210         mdelay(5);
1211
1212         return uvd_v6_0_start(adev);
1213 }
1214
1215 static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev,
1216                                         struct amdgpu_irq_src *source,
1217                                         unsigned type,
1218                                         enum amdgpu_interrupt_state state)
1219 {
1220         // TODO
1221         return 0;
1222 }
1223
1224 static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev,
1225                                       struct amdgpu_irq_src *source,
1226                                       struct amdgpu_iv_entry *entry)
1227 {
1228         bool int_handled = true;
1229         DRM_DEBUG("IH: UVD TRAP\n");
1230
1231         switch (entry->src_id) {
1232         case 124:
1233                 amdgpu_fence_process(&adev->uvd.inst->ring);
1234                 break;
1235         case 119:
1236                 if (likely(uvd_v6_0_enc_support(adev)))
1237                         amdgpu_fence_process(&adev->uvd.inst->ring_enc[0]);
1238                 else
1239                         int_handled = false;
1240                 break;
1241         case 120:
1242                 if (likely(uvd_v6_0_enc_support(adev)))
1243                         amdgpu_fence_process(&adev->uvd.inst->ring_enc[1]);
1244                 else
1245                         int_handled = false;
1246                 break;
1247         }
1248
1249         if (false == int_handled)
1250                         DRM_ERROR("Unhandled interrupt: %d %d\n",
1251                           entry->src_id, entry->src_data[0]);
1252
1253         return 0;
1254 }
1255
1256 static void uvd_v6_0_enable_clock_gating(struct amdgpu_device *adev, bool enable)
1257 {
1258         uint32_t data1, data3;
1259
1260         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
1261         data3 = RREG32(mmUVD_CGC_GATE);
1262
1263         data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
1264                      UVD_SUVD_CGC_GATE__SIT_MASK |
1265                      UVD_SUVD_CGC_GATE__SMP_MASK |
1266                      UVD_SUVD_CGC_GATE__SCM_MASK |
1267                      UVD_SUVD_CGC_GATE__SDB_MASK |
1268                      UVD_SUVD_CGC_GATE__SRE_H264_MASK |
1269                      UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
1270                      UVD_SUVD_CGC_GATE__SIT_H264_MASK |
1271                      UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
1272                      UVD_SUVD_CGC_GATE__SCM_H264_MASK |
1273                      UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
1274                      UVD_SUVD_CGC_GATE__SDB_H264_MASK |
1275                      UVD_SUVD_CGC_GATE__SDB_HEVC_MASK;
1276
1277         if (enable) {
1278                 data3 |= (UVD_CGC_GATE__SYS_MASK       |
1279                         UVD_CGC_GATE__UDEC_MASK      |
1280                         UVD_CGC_GATE__MPEG2_MASK     |
1281                         UVD_CGC_GATE__RBC_MASK       |
1282                         UVD_CGC_GATE__LMI_MC_MASK    |
1283                         UVD_CGC_GATE__LMI_UMC_MASK   |
1284                         UVD_CGC_GATE__IDCT_MASK      |
1285                         UVD_CGC_GATE__MPRD_MASK      |
1286                         UVD_CGC_GATE__MPC_MASK       |
1287                         UVD_CGC_GATE__LBSI_MASK      |
1288                         UVD_CGC_GATE__LRBBM_MASK     |
1289                         UVD_CGC_GATE__UDEC_RE_MASK   |
1290                         UVD_CGC_GATE__UDEC_CM_MASK   |
1291                         UVD_CGC_GATE__UDEC_IT_MASK   |
1292                         UVD_CGC_GATE__UDEC_DB_MASK   |
1293                         UVD_CGC_GATE__UDEC_MP_MASK   |
1294                         UVD_CGC_GATE__WCB_MASK       |
1295                         UVD_CGC_GATE__JPEG_MASK      |
1296                         UVD_CGC_GATE__SCPU_MASK      |
1297                         UVD_CGC_GATE__JPEG2_MASK);
1298                 /* only in pg enabled, we can gate clock to vcpu*/
1299                 if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
1300                         data3 |= UVD_CGC_GATE__VCPU_MASK;
1301
1302                 data3 &= ~UVD_CGC_GATE__REGS_MASK;
1303         } else {
1304                 data3 = 0;
1305         }
1306
1307         WREG32(mmUVD_SUVD_CGC_GATE, data1);
1308         WREG32(mmUVD_CGC_GATE, data3);
1309 }
1310
1311 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev)
1312 {
1313         uint32_t data, data2;
1314
1315         data = RREG32(mmUVD_CGC_CTRL);
1316         data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
1317
1318
1319         data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
1320                   UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
1321
1322
1323         data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
1324                 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
1325                 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
1326
1327         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
1328                         UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
1329                         UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
1330                         UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
1331                         UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
1332                         UVD_CGC_CTRL__SYS_MODE_MASK |
1333                         UVD_CGC_CTRL__UDEC_MODE_MASK |
1334                         UVD_CGC_CTRL__MPEG2_MODE_MASK |
1335                         UVD_CGC_CTRL__REGS_MODE_MASK |
1336                         UVD_CGC_CTRL__RBC_MODE_MASK |
1337                         UVD_CGC_CTRL__LMI_MC_MODE_MASK |
1338                         UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
1339                         UVD_CGC_CTRL__IDCT_MODE_MASK |
1340                         UVD_CGC_CTRL__MPRD_MODE_MASK |
1341                         UVD_CGC_CTRL__MPC_MODE_MASK |
1342                         UVD_CGC_CTRL__LBSI_MODE_MASK |
1343                         UVD_CGC_CTRL__LRBBM_MODE_MASK |
1344                         UVD_CGC_CTRL__WCB_MODE_MASK |
1345                         UVD_CGC_CTRL__VCPU_MODE_MASK |
1346                         UVD_CGC_CTRL__JPEG_MODE_MASK |
1347                         UVD_CGC_CTRL__SCPU_MODE_MASK |
1348                         UVD_CGC_CTRL__JPEG2_MODE_MASK);
1349         data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
1350                         UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
1351                         UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
1352                         UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
1353                         UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
1354
1355         WREG32(mmUVD_CGC_CTRL, data);
1356         WREG32(mmUVD_SUVD_CGC_CTRL, data2);
1357 }
1358
1359 #if 0
1360 static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev)
1361 {
1362         uint32_t data, data1, cgc_flags, suvd_flags;
1363
1364         data = RREG32(mmUVD_CGC_GATE);
1365         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
1366
1367         cgc_flags = UVD_CGC_GATE__SYS_MASK |
1368                 UVD_CGC_GATE__UDEC_MASK |
1369                 UVD_CGC_GATE__MPEG2_MASK |
1370                 UVD_CGC_GATE__RBC_MASK |
1371                 UVD_CGC_GATE__LMI_MC_MASK |
1372                 UVD_CGC_GATE__IDCT_MASK |
1373                 UVD_CGC_GATE__MPRD_MASK |
1374                 UVD_CGC_GATE__MPC_MASK |
1375                 UVD_CGC_GATE__LBSI_MASK |
1376                 UVD_CGC_GATE__LRBBM_MASK |
1377                 UVD_CGC_GATE__UDEC_RE_MASK |
1378                 UVD_CGC_GATE__UDEC_CM_MASK |
1379                 UVD_CGC_GATE__UDEC_IT_MASK |
1380                 UVD_CGC_GATE__UDEC_DB_MASK |
1381                 UVD_CGC_GATE__UDEC_MP_MASK |
1382                 UVD_CGC_GATE__WCB_MASK |
1383                 UVD_CGC_GATE__VCPU_MASK |
1384                 UVD_CGC_GATE__SCPU_MASK |
1385                 UVD_CGC_GATE__JPEG_MASK |
1386                 UVD_CGC_GATE__JPEG2_MASK;
1387
1388         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1389                                 UVD_SUVD_CGC_GATE__SIT_MASK |
1390                                 UVD_SUVD_CGC_GATE__SMP_MASK |
1391                                 UVD_SUVD_CGC_GATE__SCM_MASK |
1392                                 UVD_SUVD_CGC_GATE__SDB_MASK;
1393
1394         data |= cgc_flags;
1395         data1 |= suvd_flags;
1396
1397         WREG32(mmUVD_CGC_GATE, data);
1398         WREG32(mmUVD_SUVD_CGC_GATE, data1);
1399 }
1400 #endif
1401
1402 static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
1403                                  bool enable)
1404 {
1405         u32 orig, data;
1406
1407         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
1408                 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
1409                 data |= 0xfff;
1410                 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
1411
1412                 orig = data = RREG32(mmUVD_CGC_CTRL);
1413                 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
1414                 if (orig != data)
1415                         WREG32(mmUVD_CGC_CTRL, data);
1416         } else {
1417                 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
1418                 data &= ~0xfff;
1419                 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
1420
1421                 orig = data = RREG32(mmUVD_CGC_CTRL);
1422                 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
1423                 if (orig != data)
1424                         WREG32(mmUVD_CGC_CTRL, data);
1425         }
1426 }
1427
1428 static int uvd_v6_0_set_clockgating_state(void *handle,
1429                                           enum amd_clockgating_state state)
1430 {
1431         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1432         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1433
1434         if (enable) {
1435                 /* wait for STATUS to clear */
1436                 if (uvd_v6_0_wait_for_idle(handle))
1437                         return -EBUSY;
1438                 uvd_v6_0_enable_clock_gating(adev, true);
1439                 /* enable HW gates because UVD is idle */
1440 /*              uvd_v6_0_set_hw_clock_gating(adev); */
1441         } else {
1442                 /* disable HW gating and enable Sw gating */
1443                 uvd_v6_0_enable_clock_gating(adev, false);
1444         }
1445         uvd_v6_0_set_sw_clock_gating(adev);
1446         return 0;
1447 }
1448
1449 static int uvd_v6_0_set_powergating_state(void *handle,
1450                                           enum amd_powergating_state state)
1451 {
1452         /* This doesn't actually powergate the UVD block.
1453          * That's done in the dpm code via the SMC.  This
1454          * just re-inits the block as necessary.  The actual
1455          * gating still happens in the dpm code.  We should
1456          * revisit this when there is a cleaner line between
1457          * the smc and the hw blocks
1458          */
1459         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1460         int ret = 0;
1461
1462         WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
1463
1464         if (state == AMD_PG_STATE_GATE) {
1465                 uvd_v6_0_stop(adev);
1466         } else {
1467                 ret = uvd_v6_0_start(adev);
1468                 if (ret)
1469                         goto out;
1470         }
1471
1472 out:
1473         return ret;
1474 }
1475
1476 static void uvd_v6_0_get_clockgating_state(void *handle, u32 *flags)
1477 {
1478         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1479         int data;
1480
1481         mutex_lock(&adev->pm.mutex);
1482
1483         if (adev->flags & AMD_IS_APU)
1484                 data = RREG32_SMC(ixCURRENT_PG_STATUS_APU);
1485         else
1486                 data = RREG32_SMC(ixCURRENT_PG_STATUS);
1487
1488         if (data & CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) {
1489                 DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
1490                 goto out;
1491         }
1492
1493         /* AMD_CG_SUPPORT_UVD_MGCG */
1494         data = RREG32(mmUVD_CGC_CTRL);
1495         if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
1496                 *flags |= AMD_CG_SUPPORT_UVD_MGCG;
1497
1498 out:
1499         mutex_unlock(&adev->pm.mutex);
1500 }
1501
1502 static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
1503         .name = "uvd_v6_0",
1504         .early_init = uvd_v6_0_early_init,
1505         .late_init = NULL,
1506         .sw_init = uvd_v6_0_sw_init,
1507         .sw_fini = uvd_v6_0_sw_fini,
1508         .hw_init = uvd_v6_0_hw_init,
1509         .hw_fini = uvd_v6_0_hw_fini,
1510         .suspend = uvd_v6_0_suspend,
1511         .resume = uvd_v6_0_resume,
1512         .is_idle = uvd_v6_0_is_idle,
1513         .wait_for_idle = uvd_v6_0_wait_for_idle,
1514         .check_soft_reset = uvd_v6_0_check_soft_reset,
1515         .pre_soft_reset = uvd_v6_0_pre_soft_reset,
1516         .soft_reset = uvd_v6_0_soft_reset,
1517         .post_soft_reset = uvd_v6_0_post_soft_reset,
1518         .set_clockgating_state = uvd_v6_0_set_clockgating_state,
1519         .set_powergating_state = uvd_v6_0_set_powergating_state,
1520         .get_clockgating_state = uvd_v6_0_get_clockgating_state,
1521 };
1522
1523 static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
1524         .type = AMDGPU_RING_TYPE_UVD,
1525         .align_mask = 0xf,
1526         .support_64bit_ptrs = false,
1527         .get_rptr = uvd_v6_0_ring_get_rptr,
1528         .get_wptr = uvd_v6_0_ring_get_wptr,
1529         .set_wptr = uvd_v6_0_ring_set_wptr,
1530         .parse_cs = amdgpu_uvd_ring_parse_cs,
1531         .emit_frame_size =
1532                 6 + /* hdp invalidate */
1533                 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
1534                 14, /* uvd_v6_0_ring_emit_fence x1 no user fence */
1535         .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
1536         .emit_ib = uvd_v6_0_ring_emit_ib,
1537         .emit_fence = uvd_v6_0_ring_emit_fence,
1538         .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
1539         .test_ring = uvd_v6_0_ring_test_ring,
1540         .test_ib = amdgpu_uvd_ring_test_ib,
1541         .insert_nop = uvd_v6_0_ring_insert_nop,
1542         .pad_ib = amdgpu_ring_generic_pad_ib,
1543         .begin_use = amdgpu_uvd_ring_begin_use,
1544         .end_use = amdgpu_uvd_ring_end_use,
1545         .emit_wreg = uvd_v6_0_ring_emit_wreg,
1546 };
1547
1548 static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
1549         .type = AMDGPU_RING_TYPE_UVD,
1550         .align_mask = 0xf,
1551         .support_64bit_ptrs = false,
1552         .get_rptr = uvd_v6_0_ring_get_rptr,
1553         .get_wptr = uvd_v6_0_ring_get_wptr,
1554         .set_wptr = uvd_v6_0_ring_set_wptr,
1555         .emit_frame_size =
1556                 6 + /* hdp invalidate */
1557                 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
1558                 VI_FLUSH_GPU_TLB_NUM_WREG * 6 + 8 + /* uvd_v6_0_ring_emit_vm_flush */
1559                 14 + 14, /* uvd_v6_0_ring_emit_fence x2 vm fence */
1560         .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
1561         .emit_ib = uvd_v6_0_ring_emit_ib,
1562         .emit_fence = uvd_v6_0_ring_emit_fence,
1563         .emit_vm_flush = uvd_v6_0_ring_emit_vm_flush,
1564         .emit_pipeline_sync = uvd_v6_0_ring_emit_pipeline_sync,
1565         .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
1566         .test_ring = uvd_v6_0_ring_test_ring,
1567         .test_ib = amdgpu_uvd_ring_test_ib,
1568         .insert_nop = uvd_v6_0_ring_insert_nop,
1569         .pad_ib = amdgpu_ring_generic_pad_ib,
1570         .begin_use = amdgpu_uvd_ring_begin_use,
1571         .end_use = amdgpu_uvd_ring_end_use,
1572         .emit_wreg = uvd_v6_0_ring_emit_wreg,
1573 };
1574
1575 static const struct amdgpu_ring_funcs uvd_v6_0_enc_ring_vm_funcs = {
1576         .type = AMDGPU_RING_TYPE_UVD_ENC,
1577         .align_mask = 0x3f,
1578         .nop = HEVC_ENC_CMD_NO_OP,
1579         .support_64bit_ptrs = false,
1580         .get_rptr = uvd_v6_0_enc_ring_get_rptr,
1581         .get_wptr = uvd_v6_0_enc_ring_get_wptr,
1582         .set_wptr = uvd_v6_0_enc_ring_set_wptr,
1583         .emit_frame_size =
1584                 4 + /* uvd_v6_0_enc_ring_emit_pipeline_sync */
1585                 5 + /* uvd_v6_0_enc_ring_emit_vm_flush */
1586                 5 + 5 + /* uvd_v6_0_enc_ring_emit_fence x2 vm fence */
1587                 1, /* uvd_v6_0_enc_ring_insert_end */
1588         .emit_ib_size = 5, /* uvd_v6_0_enc_ring_emit_ib */
1589         .emit_ib = uvd_v6_0_enc_ring_emit_ib,
1590         .emit_fence = uvd_v6_0_enc_ring_emit_fence,
1591         .emit_vm_flush = uvd_v6_0_enc_ring_emit_vm_flush,
1592         .emit_pipeline_sync = uvd_v6_0_enc_ring_emit_pipeline_sync,
1593         .test_ring = uvd_v6_0_enc_ring_test_ring,
1594         .test_ib = uvd_v6_0_enc_ring_test_ib,
1595         .insert_nop = amdgpu_ring_insert_nop,
1596         .insert_end = uvd_v6_0_enc_ring_insert_end,
1597         .pad_ib = amdgpu_ring_generic_pad_ib,
1598         .begin_use = amdgpu_uvd_ring_begin_use,
1599         .end_use = amdgpu_uvd_ring_end_use,
1600 };
1601
1602 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev)
1603 {
1604         if (adev->asic_type >= CHIP_POLARIS10) {
1605                 adev->uvd.inst->ring.funcs = &uvd_v6_0_ring_vm_funcs;
1606                 DRM_INFO("UVD is enabled in VM mode\n");
1607         } else {
1608                 adev->uvd.inst->ring.funcs = &uvd_v6_0_ring_phys_funcs;
1609                 DRM_INFO("UVD is enabled in physical mode\n");
1610         }
1611 }
1612
1613 static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev)
1614 {
1615         int i;
1616
1617         for (i = 0; i < adev->uvd.num_enc_rings; ++i)
1618                 adev->uvd.inst->ring_enc[i].funcs = &uvd_v6_0_enc_ring_vm_funcs;
1619
1620         DRM_INFO("UVD ENC is enabled in VM mode\n");
1621 }
1622
1623 static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs = {
1624         .set = uvd_v6_0_set_interrupt_state,
1625         .process = uvd_v6_0_process_interrupt,
1626 };
1627
1628 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1629 {
1630         if (uvd_v6_0_enc_support(adev))
1631                 adev->uvd.inst->irq.num_types = adev->uvd.num_enc_rings + 1;
1632         else
1633                 adev->uvd.inst->irq.num_types = 1;
1634
1635         adev->uvd.inst->irq.funcs = &uvd_v6_0_irq_funcs;
1636 }
1637
1638 const struct amdgpu_ip_block_version uvd_v6_0_ip_block =
1639 {
1640                 .type = AMD_IP_BLOCK_TYPE_UVD,
1641                 .major = 6,
1642                 .minor = 0,
1643                 .rev = 0,
1644                 .funcs = &uvd_v6_0_ip_funcs,
1645 };
1646
1647 const struct amdgpu_ip_block_version uvd_v6_2_ip_block =
1648 {
1649                 .type = AMD_IP_BLOCK_TYPE_UVD,
1650                 .major = 6,
1651                 .minor = 2,
1652                 .rev = 0,
1653                 .funcs = &uvd_v6_0_ip_funcs,
1654 };
1655
1656 const struct amdgpu_ip_block_version uvd_v6_3_ip_block =
1657 {
1658                 .type = AMD_IP_BLOCK_TYPE_UVD,
1659                 .major = 6,
1660                 .minor = 3,
1661                 .rev = 0,
1662                 .funcs = &uvd_v6_0_ip_funcs,
1663 };