drivers/gpu/drm/amd/amdgpu/tonga_ih.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/pci.h>
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_ih.h"
  28 #include "vid.h"
  29
  30 #include "oss/oss_3_0_d.h"
  31 #include "oss/oss_3_0_sh_mask.h"
  32
  33 #include "bif/bif_5_1_d.h"
  34 #include "bif/bif_5_1_sh_mask.h"
  35
  36 /*
  37  * Interrupts
  38  * Starting with r6xx, interrupts are handled via a ring buffer.
  39  * Ring buffers are areas of GPU accessible memory that the GPU
  40  * writes interrupt vectors into and the host reads vectors out of.
  41  * There is a rptr (read pointer) that determines where the
  42  * host is currently reading, and a wptr (write pointer)
  43  * which determines where the GPU has written.  When the
  44  * pointers are equal, the ring is idle.  When the GPU
  45  * writes vectors to the ring buffer, it increments the
  46  * wptr.  When there is an interrupt, the host then starts
  47  * fetching commands and processing them until the pointers are
  48  * equal again at which point it updates the rptr.
  49  */
  50
  51 static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev);
  52
  53 /**
  54  * tonga_ih_enable_interrupts - Enable the interrupt ring buffer
  55  *
  56  * @adev: amdgpu_device pointer
  57  *
  58  * Enable the interrupt ring buffer (VI).
  59  */
  60 static void tonga_ih_enable_interrupts(struct amdgpu_device *adev)
  61 {
  62         u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
  63
  64         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
  65         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
  66         WREG32(mmIH_RB_CNTL, ih_rb_cntl);
  67         adev->irq.ih.enabled = true;
  68 }
  69
  70 /**
  71  * tonga_ih_disable_interrupts - Disable the interrupt ring buffer
  72  *
  73  * @adev: amdgpu_device pointer
  74  *
  75  * Disable the interrupt ring buffer (VI).
  76  */
  77 static void tonga_ih_disable_interrupts(struct amdgpu_device *adev)
  78 {
  79         u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
  80
  81         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
  82         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
  83         WREG32(mmIH_RB_CNTL, ih_rb_cntl);
  84         /* set rptr, wptr to 0 */
  85         WREG32(mmIH_RB_RPTR, 0);
  86         WREG32(mmIH_RB_WPTR, 0);
  87         adev->irq.ih.enabled = false;
  88         adev->irq.ih.rptr = 0;
  89 }
  90
  91 /**
  92  * tonga_ih_irq_init - init and enable the interrupt ring
  93  *
  94  * @adev: amdgpu_device pointer
  95  *
  96  * Allocate a ring buffer for the interrupt controller,
  97  * enable the RLC, disable interrupts, enable the IH
  98  * ring buffer and enable it (VI).
  99  * Called at device load and reume.
 100  * Returns 0 for success, errors for failure.
 101  */
 102 static int tonga_ih_irq_init(struct amdgpu_device *adev)
 103 {
 104         u32 interrupt_cntl, ih_rb_cntl, ih_doorbell_rtpr;
 105         struct amdgpu_ih_ring *ih = &adev->irq.ih;
 106         int rb_bufsz;
 107
 108         /* disable irqs */
 109         tonga_ih_disable_interrupts(adev);
 110
 111         /* setup interrupt control */
 112         WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
 113         interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
 114         /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
 115          * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
 116          */
 117         interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
 118         /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
 119         interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
 120         WREG32(mmINTERRUPT_CNTL, interrupt_cntl);
 121
 122         /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
 123         WREG32(mmIH_RB_BASE, ih->gpu_addr >> 8);
 124
 125         rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
 126         ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
 127         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
 128         /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */
 129         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);
 130         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
 131
 132         if (adev->irq.msi_enabled)
 133                 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1);
 134
 135         WREG32(mmIH_RB_CNTL, ih_rb_cntl);
 136
 137         /* set the writeback address whether it's enabled or not */
 138         WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
 139         WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);
 140
 141         /* set rptr, wptr to 0 */
 142         WREG32(mmIH_RB_RPTR, 0);
 143         WREG32(mmIH_RB_WPTR, 0);
 144
 145         ih_doorbell_rtpr = RREG32(mmIH_DOORBELL_RPTR);
 146         if (adev->irq.ih.use_doorbell) {
 147                 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
 148                                                  OFFSET, adev->irq.ih.doorbell_index);
 149                 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
 150                                                  ENABLE, 1);
 151         } else {
 152                 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
 153                                                  ENABLE, 0);
 154         }
 155         WREG32(mmIH_DOORBELL_RPTR, ih_doorbell_rtpr);
 156
 157         pci_set_master(adev->pdev);
 158
 159         /* enable interrupts */
 160         tonga_ih_enable_interrupts(adev);
 161
 162         return 0;
 163 }
 164
 165 /**
 166  * tonga_ih_irq_disable - disable interrupts
 167  *
 168  * @adev: amdgpu_device pointer
 169  *
 170  * Disable interrupts on the hw (VI).
 171  */
 172 static void tonga_ih_irq_disable(struct amdgpu_device *adev)
 173 {
 174         tonga_ih_disable_interrupts(adev);
 175
 176         /* Wait and acknowledge irq */
 177         mdelay(1);
 178 }
 179
 180 /**
 181  * tonga_ih_get_wptr - get the IH ring buffer wptr
 182  *
 183  * @adev: amdgpu_device pointer
 184  * @ih: IH ring buffer to fetch wptr
 185  *
 186  * Get the IH ring buffer wptr from either the register
 187  * or the writeback memory buffer (VI).  Also check for
 188  * ring buffer overflow and deal with it.
 189  * Used by cz_irq_process(VI).
 190  * Returns the value of the wptr.
 191  */
 192 static u32 tonga_ih_get_wptr(struct amdgpu_device *adev,
 193                              struct amdgpu_ih_ring *ih)
 194 {
 195         u32 wptr, tmp;
 196
 197         wptr = le32_to_cpu(*ih->wptr_cpu);
 198
 199         if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
 200                 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
 201                 /* When a ring buffer overflow happen start parsing interrupt
 202                  * from the last not overwritten vector (wptr + 16). Hopefully
 203                  * this should allow us to catchup.
 204                  */
 205                 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
 206                          wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
 207                 ih->rptr = (wptr + 16) & ih->ptr_mask;
 208                 tmp = RREG32(mmIH_RB_CNTL);
 209                 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
 210                 WREG32(mmIH_RB_CNTL, tmp);
 211         }
 212         return (wptr & ih->ptr_mask);
 213 }
 214
 215 /**
 216  * tonga_ih_decode_iv - decode an interrupt vector
 217  *
 218  * @adev: amdgpu_device pointer
 219  * @ih: IH ring buffer to decode
 220  * @entry: IV entry to place decoded information into
 221  *
 222  * Decodes the interrupt vector at the current rptr
 223  * position and also advance the position.
 224  */
 225 static void tonga_ih_decode_iv(struct amdgpu_device *adev,
 226                                struct amdgpu_ih_ring *ih,
 227                                struct amdgpu_iv_entry *entry)
 228 {
 229         /* wptr/rptr are in bytes! */
 230         u32 ring_index = ih->rptr >> 2;
 231         uint32_t dw[4];
 232
 233         dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);
 234         dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);
 235         dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);
 236         dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);
 237
 238         entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
 239         entry->src_id = dw[0] & 0xff;
 240         entry->src_data[0] = dw[1] & 0xfffffff;
 241         entry->ring_id = dw[2] & 0xff;
 242         entry->vmid = (dw[2] >> 8) & 0xff;
 243         entry->pasid = (dw[2] >> 16) & 0xffff;
 244
 245         /* wptr/rptr are in bytes! */
 246         ih->rptr += 16;
 247 }
 248
 249 /**
 250  * tonga_ih_set_rptr - set the IH ring buffer rptr
 251  *
 252  * @adev: amdgpu_device pointer
 253  * @ih: IH ring buffer to set rptr
 254  *
 255  * Set the IH ring buffer rptr.
 256  */
 257 static void tonga_ih_set_rptr(struct amdgpu_device *adev,
 258                               struct amdgpu_ih_ring *ih)
 259 {
 260         if (ih->use_doorbell) {
 261                 /* XXX check if swapping is necessary on BE */
 262                 *ih->rptr_cpu = ih->rptr;
 263                 WDOORBELL32(ih->doorbell_index, ih->rptr);
 264         } else {
 265                 WREG32(mmIH_RB_RPTR, ih->rptr);
 266         }
 267 }
 268
 269 static int tonga_ih_early_init(void *handle)
 270 {
 271         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 272         int ret;
 273
 274         ret = amdgpu_irq_add_domain(adev);
 275         if (ret)
 276                 return ret;
 277
 278         tonga_ih_set_interrupt_funcs(adev);
 279
 280         return 0;
 281 }
 282
 283 static int tonga_ih_sw_init(void *handle)
 284 {
 285         int r;
 286         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 287
 288         r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, true);
 289         if (r)
 290                 return r;
 291
 292         adev->irq.ih.use_doorbell = true;
 293         adev->irq.ih.doorbell_index = adev->doorbell_index.ih;
 294
 295         r = amdgpu_irq_init(adev);
 296
 297         return r;
 298 }
 299
 300 static int tonga_ih_sw_fini(void *handle)
 301 {
 302         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 303
 304         amdgpu_irq_fini(adev);
 305         amdgpu_ih_ring_fini(adev, &adev->irq.ih);
 306         amdgpu_irq_remove_domain(adev);
 307
 308         return 0;
 309 }
 310
 311 static int tonga_ih_hw_init(void *handle)
 312 {
 313         int r;
 314         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 315
 316         r = tonga_ih_irq_init(adev);
 317         if (r)
 318                 return r;
 319
 320         return 0;
 321 }
 322
 323 static int tonga_ih_hw_fini(void *handle)
 324 {
 325         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 326
 327         tonga_ih_irq_disable(adev);
 328
 329         return 0;
 330 }
 331
 332 static int tonga_ih_suspend(void *handle)
 333 {
 334         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 335
 336         return tonga_ih_hw_fini(adev);
 337 }
 338
 339 static int tonga_ih_resume(void *handle)
 340 {
 341         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 342
 343         return tonga_ih_hw_init(adev);
 344 }
 345
 346 static bool tonga_ih_is_idle(void *handle)
 347 {
 348         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 349         u32 tmp = RREG32(mmSRBM_STATUS);
 350
 351         if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
 352                 return false;
 353
 354         return true;
 355 }
 356
 357 static int tonga_ih_wait_for_idle(void *handle)
 358 {
 359         unsigned i;
 360         u32 tmp;
 361         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 362
 363         for (i = 0; i < adev->usec_timeout; i++) {
 364                 /* read MC_STATUS */
 365                 tmp = RREG32(mmSRBM_STATUS);
 366                 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
 367                         return 0;
 368                 udelay(1);
 369         }
 370         return -ETIMEDOUT;
 371 }
 372
 373 static bool tonga_ih_check_soft_reset(void *handle)
 374 {
 375         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 376         u32 srbm_soft_reset = 0;
 377         u32 tmp = RREG32(mmSRBM_STATUS);
 378
 379         if (tmp & SRBM_STATUS__IH_BUSY_MASK)
 380                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
 381                                                 SOFT_RESET_IH, 1);
 382
 383         if (srbm_soft_reset) {
 384                 adev->irq.srbm_soft_reset = srbm_soft_reset;
 385                 return true;
 386         } else {
 387                 adev->irq.srbm_soft_reset = 0;
 388                 return false;
 389         }
 390 }
 391
 392 static int tonga_ih_pre_soft_reset(void *handle)
 393 {
 394         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 395
 396         if (!adev->irq.srbm_soft_reset)
 397                 return 0;
 398
 399         return tonga_ih_hw_fini(adev);
 400 }
 401
 402 static int tonga_ih_post_soft_reset(void *handle)
 403 {
 404         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 405
 406         if (!adev->irq.srbm_soft_reset)
 407                 return 0;
 408
 409         return tonga_ih_hw_init(adev);
 410 }
 411
 412 static int tonga_ih_soft_reset(void *handle)
 413 {
 414         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 415         u32 srbm_soft_reset;
 416
 417         if (!adev->irq.srbm_soft_reset)
 418                 return 0;
 419         srbm_soft_reset = adev->irq.srbm_soft_reset;
 420
 421         if (srbm_soft_reset) {
 422                 u32 tmp;
 423
 424                 tmp = RREG32(mmSRBM_SOFT_RESET);
 425                 tmp |= srbm_soft_reset;
 426                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
 427                 WREG32(mmSRBM_SOFT_RESET, tmp);
 428                 tmp = RREG32(mmSRBM_SOFT_RESET);
 429
 430                 udelay(50);
 431
 432                 tmp &= ~srbm_soft_reset;
 433                 WREG32(mmSRBM_SOFT_RESET, tmp);
 434                 tmp = RREG32(mmSRBM_SOFT_RESET);
 435
 436                 /* Wait a little for things to settle down */
 437                 udelay(50);
 438         }
 439
 440         return 0;
 441 }
 442
 443 static int tonga_ih_set_clockgating_state(void *handle,
 444                                           enum amd_clockgating_state state)
 445 {
 446         return 0;
 447 }
 448
 449 static int tonga_ih_set_powergating_state(void *handle,
 450                                           enum amd_powergating_state state)
 451 {
 452         return 0;
 453 }
 454
 455 static const struct amd_ip_funcs tonga_ih_ip_funcs = {
 456         .name = "tonga_ih",
 457         .early_init = tonga_ih_early_init,
 458         .late_init = NULL,
 459         .sw_init = tonga_ih_sw_init,
 460         .sw_fini = tonga_ih_sw_fini,
 461         .hw_init = tonga_ih_hw_init,
 462         .hw_fini = tonga_ih_hw_fini,
 463         .suspend = tonga_ih_suspend,
 464         .resume = tonga_ih_resume,
 465         .is_idle = tonga_ih_is_idle,
 466         .wait_for_idle = tonga_ih_wait_for_idle,
 467         .check_soft_reset = tonga_ih_check_soft_reset,
 468         .pre_soft_reset = tonga_ih_pre_soft_reset,
 469         .soft_reset = tonga_ih_soft_reset,
 470         .post_soft_reset = tonga_ih_post_soft_reset,
 471         .set_clockgating_state = tonga_ih_set_clockgating_state,
 472         .set_powergating_state = tonga_ih_set_powergating_state,
 473 };
 474
 475 static const struct amdgpu_ih_funcs tonga_ih_funcs = {
 476         .get_wptr = tonga_ih_get_wptr,
 477         .decode_iv = tonga_ih_decode_iv,
 478         .set_rptr = tonga_ih_set_rptr
 479 };
 480
 481 static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev)
 482 {
 483         adev->irq.ih_funcs = &tonga_ih_funcs;
 484 }
 485
 486 const struct amdgpu_ip_block_version tonga_ih_ip_block =
 487 {
 488         .type = AMD_IP_BLOCK_TYPE_IH,
 489         .major = 3,
 490         .minor = 0,
 491         .rev = 0,
 492         .funcs = &tonga_ih_ip_funcs,
 493 };