2 * Copyright 2021 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
29 #include "amdgpu_atombios.h"
30 #include "amdgpu_ih.h"
31 #include "amdgpu_uvd.h"
32 #include "amdgpu_vce.h"
33 #include "amdgpu_ucode.h"
34 #include "amdgpu_psp.h"
35 #include "amdgpu_smu.h"
39 #include "gc/gc_11_0_0_offset.h"
40 #include "gc/gc_11_0_0_sh_mask.h"
41 #include "mp/mp_13_0_0_offset.h"
44 #include "soc15_common.h"
47 static const struct amd_ip_funcs soc21_common_ip_funcs;
50 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array[] =
52 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
53 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
56 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode =
58 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array),
59 .codec_array = vcn_4_0_0_video_codecs_encode_array,
62 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array[] =
64 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
65 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
66 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
67 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
68 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
71 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode =
73 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array),
74 .codec_array = vcn_4_0_0_video_codecs_decode_array,
77 static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode,
78 const struct amdgpu_video_codecs **codecs)
80 switch (adev->ip_versions[UVD_HWIP][0]) {
82 case IP_VERSION(4, 0, 0):
83 case IP_VERSION(4, 0, 2):
85 *codecs = &vcn_4_0_0_video_codecs_encode;
87 *codecs = &vcn_4_0_0_video_codecs_decode;
94 * Indirect registers accessor
96 static u32 soc21_pcie_rreg(struct amdgpu_device *adev, u32 reg)
98 unsigned long address, data;
99 address = adev->nbio.funcs->get_pcie_index_offset(adev);
100 data = adev->nbio.funcs->get_pcie_data_offset(adev);
102 return amdgpu_device_indirect_rreg(adev, address, data, reg);
105 static void soc21_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
107 unsigned long address, data;
109 address = adev->nbio.funcs->get_pcie_index_offset(adev);
110 data = adev->nbio.funcs->get_pcie_data_offset(adev);
112 amdgpu_device_indirect_wreg(adev, address, data, reg, v);
115 static u64 soc21_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
117 unsigned long address, data;
118 address = adev->nbio.funcs->get_pcie_index_offset(adev);
119 data = adev->nbio.funcs->get_pcie_data_offset(adev);
121 return amdgpu_device_indirect_rreg64(adev, address, data, reg);
124 static void soc21_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
126 unsigned long address, data;
128 address = adev->nbio.funcs->get_pcie_index_offset(adev);
129 data = adev->nbio.funcs->get_pcie_data_offset(adev);
131 amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
134 static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg)
136 unsigned long flags, address, data;
139 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX);
140 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA);
142 spin_lock_irqsave(&adev->didt_idx_lock, flags);
143 WREG32(address, (reg));
145 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
149 static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
151 unsigned long flags, address, data;
153 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX);
154 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA);
156 spin_lock_irqsave(&adev->didt_idx_lock, flags);
157 WREG32(address, (reg));
159 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
162 static u32 soc21_get_config_memsize(struct amdgpu_device *adev)
164 return adev->nbio.funcs->get_memsize(adev);
167 static u32 soc21_get_xclk(struct amdgpu_device *adev)
169 return adev->clock.spll.reference_freq;
173 void soc21_grbm_select(struct amdgpu_device *adev,
174 u32 me, u32 pipe, u32 queue, u32 vmid)
176 u32 grbm_gfx_cntl = 0;
177 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
178 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
179 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
180 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
182 WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL), grbm_gfx_cntl);
185 static void soc21_vga_set_state(struct amdgpu_device *adev, bool state)
190 static bool soc21_read_disabled_bios(struct amdgpu_device *adev)
196 static struct soc15_allowed_register_entry soc21_allowed_read_registers[] = {
197 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)},
198 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)},
199 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)},
200 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)},
201 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)},
202 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)},
203 { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)},
204 { SOC15_REG_ENTRY(SDMA1, 0, regSDMA1_STATUS_REG)},
205 { SOC15_REG_ENTRY(GC, 0, regCP_STAT)},
206 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)},
207 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2)},
208 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3)},
209 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT)},
210 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1)},
211 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)},
212 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT)},
213 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1)},
214 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)},
215 { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)},
218 static uint32_t soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
219 u32 sh_num, u32 reg_offset)
223 mutex_lock(&adev->grbm_idx_mutex);
224 if (se_num != 0xffffffff || sh_num != 0xffffffff)
225 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
227 val = RREG32(reg_offset);
229 if (se_num != 0xffffffff || sh_num != 0xffffffff)
230 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
231 mutex_unlock(&adev->grbm_idx_mutex);
235 static uint32_t soc21_get_register_value(struct amdgpu_device *adev,
236 bool indexed, u32 se_num,
237 u32 sh_num, u32 reg_offset)
240 return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset);
242 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config)
243 return adev->gfx.config.gb_addr_config;
244 return RREG32(reg_offset);
248 static int soc21_read_register(struct amdgpu_device *adev, u32 se_num,
249 u32 sh_num, u32 reg_offset, u32 *value)
252 struct soc15_allowed_register_entry *en;
255 for (i = 0; i < ARRAY_SIZE(soc21_allowed_read_registers); i++) {
256 en = &soc21_allowed_read_registers[i];
257 if (adev->reg_offset[en->hwip][en->inst] &&
258 reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
262 *value = soc21_get_register_value(adev,
263 soc21_allowed_read_registers[i].grbm_indexed,
264 se_num, sh_num, reg_offset);
271 static int soc21_asic_mode1_reset(struct amdgpu_device *adev)
276 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
279 pci_clear_master(adev->pdev);
281 amdgpu_device_cache_pci_state(adev->pdev);
283 if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
284 dev_info(adev->dev, "GPU smu mode1 reset\n");
285 ret = amdgpu_dpm_mode1_reset(adev);
287 dev_info(adev->dev, "GPU psp mode1 reset\n");
288 ret = psp_gpu_reset(adev);
292 dev_err(adev->dev, "GPU mode1 reset failed\n");
293 amdgpu_device_load_pci_state(adev->pdev);
295 /* wait for asic to come out of reset */
296 for (i = 0; i < adev->usec_timeout; i++) {
297 u32 memsize = adev->nbio.funcs->get_memsize(adev);
299 if (memsize != 0xffffffff)
304 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
310 static enum amd_reset_method
311 soc21_asic_reset_method(struct amdgpu_device *adev)
313 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
314 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
315 amdgpu_reset_method == AMD_RESET_METHOD_BACO)
316 return amdgpu_reset_method;
318 if (amdgpu_reset_method != -1)
319 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
320 amdgpu_reset_method);
322 switch (adev->ip_versions[MP1_HWIP][0]) {
323 case IP_VERSION(13, 0, 0):
324 case IP_VERSION(13, 0, 7):
325 return AMD_RESET_METHOD_MODE1;
326 case IP_VERSION(13, 0, 4):
327 return AMD_RESET_METHOD_MODE2;
329 if (amdgpu_dpm_is_baco_supported(adev))
330 return AMD_RESET_METHOD_BACO;
332 return AMD_RESET_METHOD_MODE1;
336 static int soc21_asic_reset(struct amdgpu_device *adev)
340 switch (soc21_asic_reset_method(adev)) {
341 case AMD_RESET_METHOD_PCI:
342 dev_info(adev->dev, "PCI reset\n");
343 ret = amdgpu_device_pci_reset(adev);
345 case AMD_RESET_METHOD_BACO:
346 dev_info(adev->dev, "BACO reset\n");
347 ret = amdgpu_dpm_baco_reset(adev);
349 case AMD_RESET_METHOD_MODE2:
350 dev_info(adev->dev, "MODE2 reset\n");
351 ret = amdgpu_dpm_mode2_reset(adev);
354 dev_info(adev->dev, "MODE1 reset\n");
355 ret = amdgpu_device_mode1_reset(adev);
362 static int soc21_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
368 static int soc21_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
374 static void soc21_pcie_gen3_enable(struct amdgpu_device *adev)
376 if (pci_is_root_bus(adev->pdev->bus))
379 if (amdgpu_pcie_gen2 == 0)
382 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
383 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
389 static void soc21_program_aspm(struct amdgpu_device *adev)
391 if (!amdgpu_device_should_use_aspm(adev))
394 if (!(adev->flags & AMD_IS_APU) &&
395 (adev->nbio.funcs->program_aspm))
396 adev->nbio.funcs->program_aspm(adev);
399 static void soc21_enable_doorbell_aperture(struct amdgpu_device *adev,
402 adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
403 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
406 const struct amdgpu_ip_block_version soc21_common_ip_block =
408 .type = AMD_IP_BLOCK_TYPE_COMMON,
412 .funcs = &soc21_common_ip_funcs,
415 static uint32_t soc21_get_rev_id(struct amdgpu_device *adev)
417 return adev->nbio.funcs->get_rev_id(adev);
420 static bool soc21_need_full_reset(struct amdgpu_device *adev)
422 switch (adev->ip_versions[GC_HWIP][0]) {
423 case IP_VERSION(11, 0, 0):
424 case IP_VERSION(11, 0, 2):
431 static bool soc21_need_reset_on_init(struct amdgpu_device *adev)
435 if (adev->flags & AMD_IS_APU)
438 /* Check sOS sign of life register to confirm sys driver and sOS
439 * are already been loaded.
441 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
448 static uint64_t soc21_get_pcie_replay_count(struct amdgpu_device *adev)
452 * dummy implement for pcie_replay_count sysfs interface
458 static void soc21_init_doorbell_index(struct amdgpu_device *adev)
460 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
461 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
462 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
463 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
464 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
465 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
466 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
467 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
468 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
469 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
470 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
471 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
472 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
473 adev->doorbell_index.gfx_userqueue_start =
474 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START;
475 adev->doorbell_index.gfx_userqueue_end =
476 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END;
477 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0;
478 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1;
479 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
480 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
481 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
482 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
483 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
484 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
485 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
486 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
487 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
489 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
490 adev->doorbell_index.sdma_doorbell_range = 20;
493 static void soc21_pre_asic_init(struct amdgpu_device *adev)
497 static const struct amdgpu_asic_funcs soc21_asic_funcs =
499 .read_disabled_bios = &soc21_read_disabled_bios,
500 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
501 .read_register = &soc21_read_register,
502 .reset = &soc21_asic_reset,
503 .reset_method = &soc21_asic_reset_method,
504 .set_vga_state = &soc21_vga_set_state,
505 .get_xclk = &soc21_get_xclk,
506 .set_uvd_clocks = &soc21_set_uvd_clocks,
507 .set_vce_clocks = &soc21_set_vce_clocks,
508 .get_config_memsize = &soc21_get_config_memsize,
509 .init_doorbell_index = &soc21_init_doorbell_index,
510 .need_full_reset = &soc21_need_full_reset,
511 .need_reset_on_init = &soc21_need_reset_on_init,
512 .get_pcie_replay_count = &soc21_get_pcie_replay_count,
513 .supports_baco = &amdgpu_dpm_is_baco_supported,
514 .pre_asic_init = &soc21_pre_asic_init,
515 .query_video_codecs = &soc21_query_video_codecs,
518 static int soc21_common_early_init(void *handle)
520 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
521 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
523 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
524 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
525 adev->smc_rreg = NULL;
526 adev->smc_wreg = NULL;
527 adev->pcie_rreg = &soc21_pcie_rreg;
528 adev->pcie_wreg = &soc21_pcie_wreg;
529 adev->pcie_rreg64 = &soc21_pcie_rreg64;
530 adev->pcie_wreg64 = &soc21_pcie_wreg64;
531 adev->pciep_rreg = amdgpu_device_pcie_port_rreg;
532 adev->pciep_wreg = amdgpu_device_pcie_port_wreg;
534 /* TODO: will add them during VCN v2 implementation */
535 adev->uvd_ctx_rreg = NULL;
536 adev->uvd_ctx_wreg = NULL;
538 adev->didt_rreg = &soc21_didt_rreg;
539 adev->didt_wreg = &soc21_didt_wreg;
541 adev->asic_funcs = &soc21_asic_funcs;
543 adev->rev_id = soc21_get_rev_id(adev);
544 adev->external_rev_id = 0xff;
545 switch (adev->ip_versions[GC_HWIP][0]) {
546 case IP_VERSION(11, 0, 0):
547 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG |
548 AMD_CG_SUPPORT_GFX_CGLS |
549 AMD_CG_SUPPORT_GFX_3D_CGCG |
550 AMD_CG_SUPPORT_GFX_3D_CGLS |
551 AMD_CG_SUPPORT_GFX_MGCG |
552 AMD_CG_SUPPORT_REPEATER_FGCG |
553 AMD_CG_SUPPORT_GFX_FGCG |
554 AMD_CG_SUPPORT_GFX_PERF_CLK |
555 AMD_CG_SUPPORT_VCN_MGCG |
556 AMD_CG_SUPPORT_JPEG_MGCG |
557 AMD_CG_SUPPORT_ATHUB_MGCG |
558 AMD_CG_SUPPORT_ATHUB_LS |
559 AMD_CG_SUPPORT_MC_MGCG |
560 AMD_CG_SUPPORT_MC_LS |
561 AMD_CG_SUPPORT_IH_CG |
562 AMD_CG_SUPPORT_HDP_SD;
563 adev->pg_flags = AMD_PG_SUPPORT_VCN |
564 AMD_PG_SUPPORT_VCN_DPG |
565 AMD_PG_SUPPORT_JPEG |
566 AMD_PG_SUPPORT_ATHUB |
567 AMD_PG_SUPPORT_MMHUB;
568 adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update
570 case IP_VERSION(11, 0, 2):
572 AMD_CG_SUPPORT_GFX_CGCG |
573 AMD_CG_SUPPORT_GFX_CGLS |
574 AMD_CG_SUPPORT_REPEATER_FGCG |
575 AMD_CG_SUPPORT_VCN_MGCG |
576 AMD_CG_SUPPORT_JPEG_MGCG |
577 AMD_CG_SUPPORT_ATHUB_MGCG |
578 AMD_CG_SUPPORT_ATHUB_LS;
581 AMD_PG_SUPPORT_VCN_DPG |
582 AMD_PG_SUPPORT_JPEG |
583 AMD_PG_SUPPORT_ATHUB |
584 AMD_PG_SUPPORT_MMHUB;
585 adev->external_rev_id = adev->rev_id + 0x10;
587 case IP_VERSION(11, 0, 1):
589 AMD_CG_SUPPORT_VCN_MGCG |
590 AMD_CG_SUPPORT_JPEG_MGCG;
593 adev->external_rev_id = adev->rev_id + 0x1;
596 /* FIXME: not supported yet */
603 static int soc21_common_late_init(void *handle)
608 static int soc21_common_sw_init(void *handle)
613 static int soc21_common_sw_fini(void *handle)
618 static int soc21_common_hw_init(void *handle)
620 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
622 /* enable pcie gen2/3 link */
623 soc21_pcie_gen3_enable(adev);
625 soc21_program_aspm(adev);
626 /* setup nbio registers */
627 adev->nbio.funcs->init_registers(adev);
628 /* remap HDP registers to a hole in mmio space,
629 * for the purpose of expose those registers
632 if (adev->nbio.funcs->remap_hdp_registers)
633 adev->nbio.funcs->remap_hdp_registers(adev);
634 /* enable the doorbell aperture */
635 soc21_enable_doorbell_aperture(adev, true);
640 static int soc21_common_hw_fini(void *handle)
642 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
644 /* disable the doorbell aperture */
645 soc21_enable_doorbell_aperture(adev, false);
650 static int soc21_common_suspend(void *handle)
652 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
654 return soc21_common_hw_fini(adev);
657 static int soc21_common_resume(void *handle)
659 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
661 return soc21_common_hw_init(adev);
664 static bool soc21_common_is_idle(void *handle)
669 static int soc21_common_wait_for_idle(void *handle)
674 static int soc21_common_soft_reset(void *handle)
679 static int soc21_common_set_clockgating_state(void *handle,
680 enum amd_clockgating_state state)
682 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
684 switch (adev->ip_versions[NBIO_HWIP][0]) {
685 case IP_VERSION(4, 3, 0):
686 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
687 state == AMD_CG_STATE_GATE);
688 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
689 state == AMD_CG_STATE_GATE);
690 adev->hdp.funcs->update_clock_gating(adev,
691 state == AMD_CG_STATE_GATE);
699 static int soc21_common_set_powergating_state(void *handle,
700 enum amd_powergating_state state)
702 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
704 switch (adev->ip_versions[LSDMA_HWIP][0]) {
705 case IP_VERSION(6, 0, 0):
706 case IP_VERSION(6, 0, 2):
707 adev->lsdma.funcs->update_memory_power_gating(adev,
708 state == AMD_PG_STATE_GATE);
717 static void soc21_common_get_clockgating_state(void *handle, u64 *flags)
719 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
721 adev->nbio.funcs->get_clockgating_state(adev, flags);
723 adev->hdp.funcs->get_clock_gating_state(adev, flags);
728 static const struct amd_ip_funcs soc21_common_ip_funcs = {
729 .name = "soc21_common",
730 .early_init = soc21_common_early_init,
731 .late_init = soc21_common_late_init,
732 .sw_init = soc21_common_sw_init,
733 .sw_fini = soc21_common_sw_fini,
734 .hw_init = soc21_common_hw_init,
735 .hw_fini = soc21_common_hw_fini,
736 .suspend = soc21_common_suspend,
737 .resume = soc21_common_resume,
738 .is_idle = soc21_common_is_idle,
739 .wait_for_idle = soc21_common_wait_for_idle,
740 .soft_reset = soc21_common_soft_reset,
741 .set_clockgating_state = soc21_common_set_clockgating_state,
742 .set_powergating_state = soc21_common_set_powergating_state,
743 .get_clockgating_state = soc21_common_get_clockgating_state,