drivers/gpu/drm/amd/amdgpu/soc15_common.h

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef __SOC15_COMMON_H__
  25 #define __SOC15_COMMON_H__
  26
  27 /* Register Access Macros */
  28 #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
  29
  30 #define WREG32_FIELD15(ip, idx, reg, field, val)        \
  31         WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg,  \
  32         (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \
  33         & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
  34
  35 #define RREG32_SOC15(ip, inst, reg) \
  36         RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
  37
  38 #define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \
  39         RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset)
  40
  41 #define WREG32_SOC15(ip, inst, reg, value) \
  42         WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
  43
  44 #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \
  45         WREG32_NO_KIQ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
  46
  47 #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \
  48         WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value)
  49
  50 #define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask, ret) \
  51         do {                                                    \
  52                 uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
  53                 uint32_t loop = adev->usec_timeout;             \
  54                 while ((tmp_ & (mask)) != (expected_value)) {   \
  55                         udelay(2);                              \
  56                         tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
  57                         loop--;                                 \
  58                         if (!loop) {                            \
  59                                 DRM_ERROR("Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n", \
  60                                           inst, #reg, (unsigned)expected_value, (unsigned)(tmp_ & (mask))); \
  61                                 ret = -ETIMEDOUT;               \
  62                                 break;                          \
  63                         }                                       \
  64                 }                                               \
  65         } while (0)
  66
  67 #define RREG32_SOC15_DPG_MODE(ip, inst, reg, mask, sram_sel)    \
  68                 ({ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \
  69                         WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL,       \
  70                                 UVD_DPG_LMA_CTL__MASK_EN_MASK |                         \
  71                                 ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \
  72                                 << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \
  73                                 (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT));        \
  74                         RREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA); })
  75
  76 #define WREG32_SOC15_DPG_MODE(ip, inst, reg, value, mask, sram_sel)     \
  77         do {                                                    \
  78                 WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA, value);      \
  79                 WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask);               \
  80                 WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL,       \
  81                         UVD_DPG_LMA_CTL__READ_WRITE_MASK |      \
  82                         ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \
  83                         << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) |   \
  84                         (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
  85         } while (0)
  86
  87 #endif
  88
  89