2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #ifndef __SOC15_COMMON_H__
25 #define __SOC15_COMMON_H__
27 /* Register Access Macros */
28 #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
30 #define WREG32_FIELD15(ip, idx, reg, field, val) \
31 WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
32 (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \
33 & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
35 #define RREG32_SOC15(ip, inst, reg) \
36 RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
38 #define RREG32_SOC15_NO_KIQ(ip, inst, reg) \
39 RREG32_NO_KIQ(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
41 #define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \
42 RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset)
44 #define WREG32_SOC15(ip, inst, reg, value) \
45 WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
47 #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \
48 WREG32_NO_KIQ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
50 #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \
51 WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value)
53 #define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask) \
57 uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
58 uint32_t loop = adev->usec_timeout; \
60 while ((tmp_ & (mask)) != (expected_value)) { \
62 loop = adev->usec_timeout; \
66 tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
69 DRM_WARN("Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n", \
70 inst, #reg, (unsigned)expected_value, (unsigned)(tmp_ & (mask))); \
79 #define WREG32_RLC(reg, value) \
81 if (adev->gfx.rlc.funcs->rlcg_wreg) \
82 adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value, 0); \
87 #define WREG32_RLC_EX(prefix, reg, value) \
89 if (amdgpu_sriov_fullaccess(adev)) { \
91 uint32_t retries = 50000; \
92 uint32_t r0 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG0_BASE_IDX] + prefix##SCRATCH_REG0; \
93 uint32_t r1 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG1; \
94 uint32_t spare_int = adev->reg_offset[GC_HWIP][0][prefix##RLC_SPARE_INT_BASE_IDX] + prefix##RLC_SPARE_INT; \
96 WREG32(r1, (reg | 0x80000000)); \
97 WREG32(spare_int, 0x1); \
98 for (i = 0; i < retries; i++) { \
99 u32 tmp = RREG32(r1); \
100 if (!(tmp & 0x80000000)) \
105 pr_err("timeout: rlcg program reg:0x%05x failed !\n", reg); \
107 WREG32(reg, value); \
111 #define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \
112 WREG32_RLC((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
114 #define RREG32_RLC(reg) \
115 (adev->gfx.rlc.funcs->rlcg_rreg ? \
116 adev->gfx.rlc.funcs->rlcg_rreg(adev, reg, 0) : RREG32(reg))
118 #define WREG32_RLC_NO_KIQ(reg, value) \
120 if (adev->gfx.rlc.funcs->rlcg_wreg) \
121 adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value, AMDGPU_REGS_NO_KIQ); \
123 WREG32_NO_KIQ(reg, value); \
126 #define RREG32_RLC_NO_KIQ(reg) \
127 (adev->gfx.rlc.funcs->rlcg_rreg ? \
128 adev->gfx.rlc.funcs->rlcg_rreg(adev, reg, AMDGPU_REGS_NO_KIQ) : RREG32_NO_KIQ(reg))
130 #define WREG32_SOC15_RLC_SHADOW_EX(prefix, ip, inst, reg, value) \
132 uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\
133 if (amdgpu_sriov_fullaccess(adev)) { \
134 uint32_t r2 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG2; \
135 uint32_t r3 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG3; \
136 uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][0][prefix##GRBM_GFX_CNTL_BASE_IDX] + prefix##GRBM_GFX_CNTL; \
137 uint32_t grbm_idx = adev->reg_offset[GC_HWIP][0][prefix##GRBM_GFX_INDEX_BASE_IDX] + prefix##GRBM_GFX_INDEX; \
138 if (target_reg == grbm_cntl) \
140 else if (target_reg == grbm_idx) \
142 WREG32(target_reg, value); \
144 WREG32(target_reg, value); \
148 #define RREG32_SOC15_RLC(ip, inst, reg) \
149 RREG32_RLC(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
151 #define WREG32_SOC15_RLC(ip, inst, reg, value) \
153 uint32_t target_reg = adev->reg_offset[ip##_HWIP][0][reg##_BASE_IDX] + reg;\
154 WREG32_RLC(target_reg, value); \
157 #define WREG32_SOC15_RLC_EX(prefix, ip, inst, reg, value) \
159 uint32_t target_reg = adev->reg_offset[GC_HWIP][0][reg##_BASE_IDX] + reg;\
160 WREG32_RLC_EX(prefix, target_reg, value); \
163 #define WREG32_FIELD15_RLC(ip, idx, reg, field, val) \
164 WREG32_RLC((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \
165 (RREG32_RLC(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \
166 & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
168 #define WREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset, value) \
169 WREG32_RLC(((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset), value)
171 #define RREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset) \
172 RREG32_RLC(((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset))