drivers/gpu/drm/amd/amdgpu/soc15.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_atombios.h"
  30 #include "amdgpu_ih.h"
  31 #include "amdgpu_uvd.h"
  32 #include "amdgpu_vce.h"
  33 #include "amdgpu_ucode.h"
  34 #include "amdgpu_psp.h"
  35 #include "atom.h"
  36 #include "amd_pcie.h"
  37
  38 #include "uvd/uvd_7_0_offset.h"
  39 #include "gc/gc_9_0_offset.h"
  40 #include "gc/gc_9_0_sh_mask.h"
  41 #include "sdma0/sdma0_4_0_offset.h"
  42 #include "sdma1/sdma1_4_0_offset.h"
  43 #include "hdp/hdp_4_0_offset.h"
  44 #include "hdp/hdp_4_0_sh_mask.h"
  45 #include "smuio/smuio_9_0_offset.h"
  46 #include "smuio/smuio_9_0_sh_mask.h"
  47 #include "nbio/nbio_7_0_default.h"
  48 #include "nbio/nbio_7_0_offset.h"
  49 #include "nbio/nbio_7_0_sh_mask.h"
  50 #include "nbio/nbio_7_0_smn.h"
  51 #include "mp/mp_9_0_offset.h"
  52
  53 #include "soc15.h"
  54 #include "soc15_common.h"
  55 #include "gfx_v9_0.h"
  56 #include "gmc_v9_0.h"
  57 #include "gfxhub_v1_0.h"
  58 #include "mmhub_v1_0.h"
  59 #include "df_v1_7.h"
  60 #include "df_v3_6.h"
  61 #include "nbio_v6_1.h"
  62 #include "nbio_v7_0.h"
  63 #include "nbio_v7_4.h"
  64 #include "vega10_ih.h"
  65 #include "sdma_v4_0.h"
  66 #include "uvd_v7_0.h"
  67 #include "vce_v4_0.h"
  68 #include "vcn_v1_0.h"
  69 #include "vcn_v2_0.h"
  70 #include "jpeg_v2_0.h"
  71 #include "vcn_v2_5.h"
  72 #include "jpeg_v2_5.h"
  73 #include "dce_virtual.h"
  74 #include "mxgpu_ai.h"
  75 #include "amdgpu_smu.h"
  76 #include "amdgpu_ras.h"
  77 #include "amdgpu_xgmi.h"
  78 #include <uapi/linux/kfd_ioctl.h>
  79
  80 #define mmMP0_MISC_CGTT_CTRL0                                                                   0x01b9
  81 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX                                                          0
  82 #define mmMP0_MISC_LIGHT_SLEEP_CTRL                                                             0x01ba
  83 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX                                                    0
  84
  85 /* for Vega20 register name change */
  86 #define mmHDP_MEM_POWER_CTRL    0x00d4
  87 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK  0x00000001L
  88 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK    0x00000002L
  89 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK   0x00010000L
  90 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK             0x00020000L
  91 #define mmHDP_MEM_POWER_CTRL_BASE_IDX   0
  92 /*
  93  * Indirect registers accessor
  94  */
  95 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
  96 {
  97         unsigned long flags, address, data;
  98         u32 r;
  99         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 100         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 101
 102         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 103         WREG32(address, reg);
 104         (void)RREG32(address);
 105         r = RREG32(data);
 106         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 107         return r;
 108 }
 109
 110 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 111 {
 112         unsigned long flags, address, data;
 113
 114         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 115         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 116
 117         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 118         WREG32(address, reg);
 119         (void)RREG32(address);
 120         WREG32(data, v);
 121         (void)RREG32(data);
 122         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 123 }
 124
 125 static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
 126 {
 127         unsigned long flags, address, data;
 128         u64 r;
 129         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 130         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 131
 132         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 133         /* read low 32 bit */
 134         WREG32(address, reg);
 135         (void)RREG32(address);
 136         r = RREG32(data);
 137
 138         /* read high 32 bit*/
 139         WREG32(address, reg + 4);
 140         (void)RREG32(address);
 141         r |= ((u64)RREG32(data) << 32);
 142         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 143         return r;
 144 }
 145
 146 static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
 147 {
 148         unsigned long flags, address, data;
 149
 150         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 151         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 152
 153         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 154         /* write low 32 bit */
 155         WREG32(address, reg);
 156         (void)RREG32(address);
 157         WREG32(data, (u32)(v & 0xffffffffULL));
 158         (void)RREG32(data);
 159
 160         /* write high 32 bit */
 161         WREG32(address, reg + 4);
 162         (void)RREG32(address);
 163         WREG32(data, (u32)(v >> 32));
 164         (void)RREG32(data);
 165         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 166 }
 167
 168 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
 169 {
 170         unsigned long flags, address, data;
 171         u32 r;
 172
 173         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 174         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 175
 176         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 177         WREG32(address, ((reg) & 0x1ff));
 178         r = RREG32(data);
 179         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 180         return r;
 181 }
 182
 183 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 184 {
 185         unsigned long flags, address, data;
 186
 187         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 188         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 189
 190         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 191         WREG32(address, ((reg) & 0x1ff));
 192         WREG32(data, (v));
 193         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 194 }
 195
 196 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
 197 {
 198         unsigned long flags, address, data;
 199         u32 r;
 200
 201         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 202         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 203
 204         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 205         WREG32(address, (reg));
 206         r = RREG32(data);
 207         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 208         return r;
 209 }
 210
 211 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 212 {
 213         unsigned long flags, address, data;
 214
 215         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 216         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 217
 218         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 219         WREG32(address, (reg));
 220         WREG32(data, (v));
 221         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 222 }
 223
 224 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
 225 {
 226         unsigned long flags;
 227         u32 r;
 228
 229         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 230         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
 231         r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
 232         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 233         return r;
 234 }
 235
 236 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 237 {
 238         unsigned long flags;
 239
 240         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 241         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
 242         WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
 243         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 244 }
 245
 246 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
 247 {
 248         unsigned long flags;
 249         u32 r;
 250
 251         spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
 252         WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
 253         r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
 254         spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
 255         return r;
 256 }
 257
 258 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 259 {
 260         unsigned long flags;
 261
 262         spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
 263         WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
 264         WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
 265         spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
 266 }
 267
 268 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
 269 {
 270         return adev->nbio.funcs->get_memsize(adev);
 271 }
 272
 273 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 274 {
 275         u32 reference_clock = adev->clock.spll.reference_freq;
 276
 277         if (adev->asic_type == CHIP_RAVEN)
 278                 return reference_clock / 4;
 279
 280         return reference_clock;
 281 }
 282
 283
 284 void soc15_grbm_select(struct amdgpu_device *adev,
 285                      u32 me, u32 pipe, u32 queue, u32 vmid)
 286 {
 287         u32 grbm_gfx_cntl = 0;
 288         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 289         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 290         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 291         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 292
 293         WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
 294 }
 295
 296 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
 297 {
 298         /* todo */
 299 }
 300
 301 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
 302 {
 303         /* todo */
 304         return false;
 305 }
 306
 307 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
 308                                      u8 *bios, u32 length_bytes)
 309 {
 310         u32 *dw_ptr;
 311         u32 i, length_dw;
 312
 313         if (bios == NULL)
 314                 return false;
 315         if (length_bytes == 0)
 316                 return false;
 317         /* APU vbios image is part of sbios image */
 318         if (adev->flags & AMD_IS_APU)
 319                 return false;
 320
 321         dw_ptr = (u32 *)bios;
 322         length_dw = ALIGN(length_bytes, 4) / 4;
 323
 324         /* set rom index to 0 */
 325         WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
 326         /* read out the rom data */
 327         for (i = 0; i < length_dw; i++)
 328                 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
 329
 330         return true;
 331 }
 332
 333 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
 334         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 335         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
 336         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
 337         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
 338         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
 339         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
 340         { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
 341         { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
 342         { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
 343         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
 344         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
 345         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
 346         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
 347         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
 348         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
 349         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
 350         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 351         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 352         { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 353         { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
 354 };
 355
 356 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 357                                          u32 sh_num, u32 reg_offset)
 358 {
 359         uint32_t val;
 360
 361         mutex_lock(&adev->grbm_idx_mutex);
 362         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 363                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 364
 365         val = RREG32(reg_offset);
 366
 367         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 368                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 369         mutex_unlock(&adev->grbm_idx_mutex);
 370         return val;
 371 }
 372
 373 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
 374                                          bool indexed, u32 se_num,
 375                                          u32 sh_num, u32 reg_offset)
 376 {
 377         if (indexed) {
 378                 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
 379         } else {
 380                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 381                         return adev->gfx.config.gb_addr_config;
 382                 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
 383                         return adev->gfx.config.db_debug2;
 384                 return RREG32(reg_offset);
 385         }
 386 }
 387
 388 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
 389                             u32 sh_num, u32 reg_offset, u32 *value)
 390 {
 391         uint32_t i;
 392         struct soc15_allowed_register_entry  *en;
 393
 394         *value = 0;
 395         for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
 396                 en = &soc15_allowed_read_registers[i];
 397                 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
 398                                         + en->reg_offset))
 399                         continue;
 400
 401                 *value = soc15_get_register_value(adev,
 402                                                   soc15_allowed_read_registers[i].grbm_indexed,
 403                                                   se_num, sh_num, reg_offset);
 404                 return 0;
 405         }
 406         return -EINVAL;
 407 }
 408
 409
 410 /**
 411  * soc15_program_register_sequence - program an array of registers.
 412  *
 413  * @adev: amdgpu_device pointer
 414  * @regs: pointer to the register array
 415  * @array_size: size of the register array
 416  *
 417  * Programs an array or registers with and and or masks.
 418  * This is a helper for setting golden registers.
 419  */
 420
 421 void soc15_program_register_sequence(struct amdgpu_device *adev,
 422                                              const struct soc15_reg_golden *regs,
 423                                              const u32 array_size)
 424 {
 425         const struct soc15_reg_golden *entry;
 426         u32 tmp, reg;
 427         int i;
 428
 429         for (i = 0; i < array_size; ++i) {
 430                 entry = &regs[i];
 431                 reg =  adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
 432
 433                 if (entry->and_mask == 0xffffffff) {
 434                         tmp = entry->or_mask;
 435                 } else {
 436                         tmp = RREG32(reg);
 437                         tmp &= ~(entry->and_mask);
 438                         tmp |= (entry->or_mask & entry->and_mask);
 439                 }
 440
 441                 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
 442                         reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
 443                         reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
 444                         reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
 445                         WREG32_RLC(reg, tmp);
 446                 else
 447                         WREG32(reg, tmp);
 448
 449         }
 450
 451 }
 452
 453 static int soc15_asic_mode1_reset(struct amdgpu_device *adev)
 454 {
 455         u32 i;
 456         int ret = 0;
 457
 458         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 459
 460         dev_info(adev->dev, "GPU mode1 reset\n");
 461
 462         /* disable BM */
 463         pci_clear_master(adev->pdev);
 464
 465         pci_save_state(adev->pdev);
 466
 467         ret = psp_gpu_reset(adev);
 468         if (ret)
 469                 dev_err(adev->dev, "GPU mode1 reset failed\n");
 470
 471         pci_restore_state(adev->pdev);
 472
 473         /* wait for asic to come out of reset */
 474         for (i = 0; i < adev->usec_timeout; i++) {
 475                 u32 memsize = adev->nbio.funcs->get_memsize(adev);
 476
 477                 if (memsize != 0xffffffff)
 478                         break;
 479                 udelay(1);
 480         }
 481
 482         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 483
 484         return ret;
 485 }
 486
 487 static int soc15_asic_baco_reset(struct amdgpu_device *adev)
 488 {
 489         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 490         int ret = 0;
 491
 492         /* avoid NBIF got stuck when do RAS recovery in BACO reset */
 493         if (ras && ras->supported)
 494                 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
 495
 496         ret = amdgpu_dpm_baco_reset(adev);
 497         if (ret)
 498                 return ret;
 499
 500         /* re-enable doorbell interrupt after BACO exit */
 501         if (ras && ras->supported)
 502                 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
 503
 504         return 0;
 505 }
 506
 507 static enum amd_reset_method
 508 soc15_asic_reset_method(struct amdgpu_device *adev)
 509 {
 510         bool baco_reset = false;
 511         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 512
 513         switch (adev->asic_type) {
 514         case CHIP_RAVEN:
 515         case CHIP_RENOIR:
 516                 return AMD_RESET_METHOD_MODE2;
 517         case CHIP_VEGA10:
 518         case CHIP_VEGA12:
 519         case CHIP_ARCTURUS:
 520                 baco_reset = amdgpu_dpm_is_baco_supported(adev);
 521                 break;
 522         case CHIP_VEGA20:
 523                 if (adev->psp.sos_fw_version >= 0x80067)
 524                         baco_reset = amdgpu_dpm_is_baco_supported(adev);
 525
 526                 /*
 527                  * 1. PMFW version > 0x284300: all cases use baco
 528                  * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco
 529                  */
 530                 if ((ras && ras->supported) && adev->pm.fw_version <= 0x283400)
 531                         baco_reset = false;
 532                 break;
 533         default:
 534                 break;
 535         }
 536
 537         if (baco_reset)
 538                 return AMD_RESET_METHOD_BACO;
 539         else
 540                 return AMD_RESET_METHOD_MODE1;
 541 }
 542
 543 static int soc15_asic_reset(struct amdgpu_device *adev)
 544 {
 545         /* original raven doesn't have full asic reset */
 546         if (adev->pdev->device == 0x15dd && adev->rev_id < 0x8)
 547                 return 0;
 548
 549         switch (soc15_asic_reset_method(adev)) {
 550                 case AMD_RESET_METHOD_BACO:
 551                         if (!adev->in_suspend)
 552                                 amdgpu_inc_vram_lost(adev);
 553                         return soc15_asic_baco_reset(adev);
 554                 case AMD_RESET_METHOD_MODE2:
 555                         return amdgpu_dpm_mode2_reset(adev);
 556                 default:
 557                         if (!adev->in_suspend)
 558                                 amdgpu_inc_vram_lost(adev);
 559                         return soc15_asic_mode1_reset(adev);
 560         }
 561 }
 562
 563 static bool soc15_supports_baco(struct amdgpu_device *adev)
 564 {
 565         switch (adev->asic_type) {
 566         case CHIP_VEGA10:
 567         case CHIP_VEGA12:
 568         case CHIP_ARCTURUS:
 569                 return amdgpu_dpm_is_baco_supported(adev);
 570         case CHIP_VEGA20:
 571                 if (adev->psp.sos_fw_version >= 0x80067)
 572                         return amdgpu_dpm_is_baco_supported(adev);
 573                 return false;
 574         default:
 575                 return false;
 576         }
 577 }
 578
 579 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
 580                         u32 cntl_reg, u32 status_reg)
 581 {
 582         return 0;
 583 }*/
 584
 585 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 586 {
 587         /*int r;
 588
 589         r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
 590         if (r)
 591                 return r;
 592
 593         r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
 594         */
 595         return 0;
 596 }
 597
 598 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 599 {
 600         /* todo */
 601
 602         return 0;
 603 }
 604
 605 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
 606 {
 607         if (pci_is_root_bus(adev->pdev->bus))
 608                 return;
 609
 610         if (amdgpu_pcie_gen2 == 0)
 611                 return;
 612
 613         if (adev->flags & AMD_IS_APU)
 614                 return;
 615
 616         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 617                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 618                 return;
 619
 620         /* todo */
 621 }
 622
 623 static void soc15_program_aspm(struct amdgpu_device *adev)
 624 {
 625
 626         if (amdgpu_aspm == 0)
 627                 return;
 628
 629         /* todo */
 630 }
 631
 632 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
 633                                            bool enable)
 634 {
 635         adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
 636         adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
 637 }
 638
 639 static const struct amdgpu_ip_block_version vega10_common_ip_block =
 640 {
 641         .type = AMD_IP_BLOCK_TYPE_COMMON,
 642         .major = 2,
 643         .minor = 0,
 644         .rev = 0,
 645         .funcs = &soc15_common_ip_funcs,
 646 };
 647
 648 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
 649 {
 650         return adev->nbio.funcs->get_rev_id(adev);
 651 }
 652
 653 int soc15_set_ip_blocks(struct amdgpu_device *adev)
 654 {
 655         /* Set IP register base before any HW register access */
 656         switch (adev->asic_type) {
 657         case CHIP_VEGA10:
 658         case CHIP_VEGA12:
 659         case CHIP_RAVEN:
 660         case CHIP_RENOIR:
 661                 vega10_reg_base_init(adev);
 662                 break;
 663         case CHIP_VEGA20:
 664                 vega20_reg_base_init(adev);
 665                 break;
 666         case CHIP_ARCTURUS:
 667                 arct_reg_base_init(adev);
 668                 break;
 669         default:
 670                 return -EINVAL;
 671         }
 672
 673         if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
 674                 adev->gmc.xgmi.supported = true;
 675
 676         if (adev->flags & AMD_IS_APU) {
 677                 adev->nbio.funcs = &nbio_v7_0_funcs;
 678                 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
 679         } else if (adev->asic_type == CHIP_VEGA20 ||
 680                    adev->asic_type == CHIP_ARCTURUS) {
 681                 adev->nbio.funcs = &nbio_v7_4_funcs;
 682                 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
 683         } else {
 684                 adev->nbio.funcs = &nbio_v6_1_funcs;
 685                 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
 686         }
 687
 688         if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
 689                 adev->df.funcs = &df_v3_6_funcs;
 690         else
 691                 adev->df.funcs = &df_v1_7_funcs;
 692
 693         adev->rev_id = soc15_get_rev_id(adev);
 694         adev->nbio.funcs->detect_hw_virt(adev);
 695
 696         if (amdgpu_sriov_vf(adev))
 697                 adev->virt.ops = &xgpu_ai_virt_ops;
 698
 699         switch (adev->asic_type) {
 700         case CHIP_VEGA10:
 701         case CHIP_VEGA12:
 702         case CHIP_VEGA20:
 703                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 704                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 705
 706                 /* For Vega10 SR-IOV, PSP need to be initialized before IH */
 707                 if (amdgpu_sriov_vf(adev)) {
 708                         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
 709                                 if (adev->asic_type == CHIP_VEGA20)
 710                                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 711                                 else
 712                                         amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
 713                         }
 714                         amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 715                 } else {
 716                         amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 717                         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
 718                                 if (adev->asic_type == CHIP_VEGA20)
 719                                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 720                                 else
 721                                         amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
 722                         }
 723                 }
 724                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 725                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 726                 if (is_support_sw_smu(adev)) {
 727                         if (!amdgpu_sriov_vf(adev))
 728                                 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 729                 } else {
 730                         amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
 731                 }
 732                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 733                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 734 #if defined(CONFIG_DRM_AMD_DC)
 735                 else if (amdgpu_device_has_dc_support(adev))
 736                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 737 #endif
 738                 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) {
 739                         amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
 740                         amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
 741                 }
 742                 break;
 743         case CHIP_RAVEN:
 744                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 745                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 746                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 747                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 748                         amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
 749                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 750                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 751                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
 752                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 753                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 754 #if defined(CONFIG_DRM_AMD_DC)
 755                 else if (amdgpu_device_has_dc_support(adev))
 756                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 757 #endif
 758                 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
 759                 break;
 760         case CHIP_ARCTURUS:
 761                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 762                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 763
 764                 if (amdgpu_sriov_vf(adev)) {
 765                         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 766                                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 767                         amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 768                 } else {
 769                         amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 770                         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 771                                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 772                 }
 773
 774                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 775                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 776                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 777                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 778                 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 779
 780                 if (amdgpu_sriov_vf(adev)) {
 781                         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 782                                 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
 783                 } else {
 784                         amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
 785                 }
 786                 if (!amdgpu_sriov_vf(adev))
 787                         amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
 788                 break;
 789         case CHIP_RENOIR:
 790                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 791                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 792                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 793                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 794                         amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
 795                 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
 796                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 797                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 798                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 799                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 800 #if defined(CONFIG_DRM_AMD_DC)
 801                 else if (amdgpu_device_has_dc_support(adev))
 802                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 803 #endif
 804                 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 805                 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
 806                 break;
 807         default:
 808                 return -EINVAL;
 809         }
 810
 811         return 0;
 812 }
 813
 814 static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
 815 {
 816         adev->nbio.funcs->hdp_flush(adev, ring);
 817 }
 818
 819 static void soc15_invalidate_hdp(struct amdgpu_device *adev,
 820                                  struct amdgpu_ring *ring)
 821 {
 822         if (!ring || !ring->funcs->emit_wreg)
 823                 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
 824         else
 825                 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
 826                         HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
 827 }
 828
 829 static bool soc15_need_full_reset(struct amdgpu_device *adev)
 830 {
 831         /* change this when we implement soft reset */
 832         return true;
 833 }
 834 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
 835                                  uint64_t *count1)
 836 {
 837         uint32_t perfctr = 0;
 838         uint64_t cnt0_of, cnt1_of;
 839         int tmp;
 840
 841         /* This reports 0 on APUs, so return to avoid writing/reading registers
 842          * that may or may not be different from their GPU counterparts
 843          */
 844         if (adev->flags & AMD_IS_APU)
 845                 return;
 846
 847         /* Set the 2 events that we wish to watch, defined above */
 848         /* Reg 40 is # received msgs */
 849         /* Reg 104 is # of posted requests sent */
 850         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
 851         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
 852
 853         /* Write to enable desired perf counters */
 854         WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
 855         /* Zero out and enable the perf counters
 856          * Write 0x5:
 857          * Bit 0 = Start all counters(1)
 858          * Bit 2 = Global counter reset enable(1)
 859          */
 860         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
 861
 862         msleep(1000);
 863
 864         /* Load the shadow and disable the perf counters
 865          * Write 0x2:
 866          * Bit 0 = Stop counters(0)
 867          * Bit 1 = Load the shadow counters(1)
 868          */
 869         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
 870
 871         /* Read register values to get any >32bit overflow */
 872         tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
 873         cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
 874         cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
 875
 876         /* Get the values and add the overflow */
 877         *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
 878         *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
 879 }
 880
 881 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
 882                                  uint64_t *count1)
 883 {
 884         uint32_t perfctr = 0;
 885         uint64_t cnt0_of, cnt1_of;
 886         int tmp;
 887
 888         /* This reports 0 on APUs, so return to avoid writing/reading registers
 889          * that may or may not be different from their GPU counterparts
 890          */
 891         if (adev->flags & AMD_IS_APU)
 892                 return;
 893
 894         /* Set the 2 events that we wish to watch, defined above */
 895         /* Reg 40 is # received msgs */
 896         /* Reg 108 is # of posted requests sent on VG20 */
 897         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
 898                                 EVENT0_SEL, 40);
 899         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
 900                                 EVENT1_SEL, 108);
 901
 902         /* Write to enable desired perf counters */
 903         WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr);
 904         /* Zero out and enable the perf counters
 905          * Write 0x5:
 906          * Bit 0 = Start all counters(1)
 907          * Bit 2 = Global counter reset enable(1)
 908          */
 909         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
 910
 911         msleep(1000);
 912
 913         /* Load the shadow and disable the perf counters
 914          * Write 0x2:
 915          * Bit 0 = Stop counters(0)
 916          * Bit 1 = Load the shadow counters(1)
 917          */
 918         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
 919
 920         /* Read register values to get any >32bit overflow */
 921         tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3);
 922         cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER);
 923         cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER);
 924
 925         /* Get the values and add the overflow */
 926         *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32);
 927         *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32);
 928 }
 929
 930 static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
 931 {
 932         u32 sol_reg;
 933
 934         /* Just return false for soc15 GPUs.  Reset does not seem to
 935          * be necessary.
 936          */
 937         if (!amdgpu_passthrough(adev))
 938                 return false;
 939
 940         if (adev->flags & AMD_IS_APU)
 941                 return false;
 942
 943         /* Check sOS sign of life register to confirm sys driver and sOS
 944          * are already been loaded.
 945          */
 946         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 947         if (sol_reg)
 948                 return true;
 949
 950         return false;
 951 }
 952
 953 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
 954 {
 955         uint64_t nak_r, nak_g;
 956
 957         /* Get the number of NAKs received and generated */
 958         nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
 959         nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
 960
 961         /* Add the total number of NAKs, i.e the number of replays */
 962         return (nak_r + nak_g);
 963 }
 964
 965 static const struct amdgpu_asic_funcs soc15_asic_funcs =
 966 {
 967         .read_disabled_bios = &soc15_read_disabled_bios,
 968         .read_bios_from_rom = &soc15_read_bios_from_rom,
 969         .read_register = &soc15_read_register,
 970         .reset = &soc15_asic_reset,
 971         .reset_method = &soc15_asic_reset_method,
 972         .set_vga_state = &soc15_vga_set_state,
 973         .get_xclk = &soc15_get_xclk,
 974         .set_uvd_clocks = &soc15_set_uvd_clocks,
 975         .set_vce_clocks = &soc15_set_vce_clocks,
 976         .get_config_memsize = &soc15_get_config_memsize,
 977         .flush_hdp = &soc15_flush_hdp,
 978         .invalidate_hdp = &soc15_invalidate_hdp,
 979         .need_full_reset = &soc15_need_full_reset,
 980         .init_doorbell_index = &vega10_doorbell_index_init,
 981         .get_pcie_usage = &soc15_get_pcie_usage,
 982         .need_reset_on_init = &soc15_need_reset_on_init,
 983         .get_pcie_replay_count = &soc15_get_pcie_replay_count,
 984         .supports_baco = &soc15_supports_baco,
 985 };
 986
 987 static const struct amdgpu_asic_funcs vega20_asic_funcs =
 988 {
 989         .read_disabled_bios = &soc15_read_disabled_bios,
 990         .read_bios_from_rom = &soc15_read_bios_from_rom,
 991         .read_register = &soc15_read_register,
 992         .reset = &soc15_asic_reset,
 993         .reset_method = &soc15_asic_reset_method,
 994         .set_vga_state = &soc15_vga_set_state,
 995         .get_xclk = &soc15_get_xclk,
 996         .set_uvd_clocks = &soc15_set_uvd_clocks,
 997         .set_vce_clocks = &soc15_set_vce_clocks,
 998         .get_config_memsize = &soc15_get_config_memsize,
 999         .flush_hdp = &soc15_flush_hdp,
1000         .invalidate_hdp = &soc15_invalidate_hdp,
1001         .need_full_reset = &soc15_need_full_reset,
1002         .init_doorbell_index = &vega20_doorbell_index_init,
1003         .get_pcie_usage = &vega20_get_pcie_usage,
1004         .need_reset_on_init = &soc15_need_reset_on_init,
1005         .get_pcie_replay_count = &soc15_get_pcie_replay_count,
1006         .supports_baco = &soc15_supports_baco,
1007 };
1008
1009 static int soc15_common_early_init(void *handle)
1010 {
1011 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
1012         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1013
1014         adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
1015         adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
1016         adev->smc_rreg = NULL;
1017         adev->smc_wreg = NULL;
1018         adev->pcie_rreg = &soc15_pcie_rreg;
1019         adev->pcie_wreg = &soc15_pcie_wreg;
1020         adev->pcie_rreg64 = &soc15_pcie_rreg64;
1021         adev->pcie_wreg64 = &soc15_pcie_wreg64;
1022         adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
1023         adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
1024         adev->didt_rreg = &soc15_didt_rreg;
1025         adev->didt_wreg = &soc15_didt_wreg;
1026         adev->gc_cac_rreg = &soc15_gc_cac_rreg;
1027         adev->gc_cac_wreg = &soc15_gc_cac_wreg;
1028         adev->se_cac_rreg = &soc15_se_cac_rreg;
1029         adev->se_cac_wreg = &soc15_se_cac_wreg;
1030
1031
1032         adev->external_rev_id = 0xFF;
1033         switch (adev->asic_type) {
1034         case CHIP_VEGA10:
1035                 adev->asic_funcs = &soc15_asic_funcs;
1036                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1037                         AMD_CG_SUPPORT_GFX_MGLS |
1038                         AMD_CG_SUPPORT_GFX_RLC_LS |
1039                         AMD_CG_SUPPORT_GFX_CP_LS |
1040                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1041                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1042                         AMD_CG_SUPPORT_GFX_CGCG |
1043                         AMD_CG_SUPPORT_GFX_CGLS |
1044                         AMD_CG_SUPPORT_BIF_MGCG |
1045                         AMD_CG_SUPPORT_BIF_LS |
1046                         AMD_CG_SUPPORT_HDP_LS |
1047                         AMD_CG_SUPPORT_DRM_MGCG |
1048                         AMD_CG_SUPPORT_DRM_LS |
1049                         AMD_CG_SUPPORT_ROM_MGCG |
1050                         AMD_CG_SUPPORT_DF_MGCG |
1051                         AMD_CG_SUPPORT_SDMA_MGCG |
1052                         AMD_CG_SUPPORT_SDMA_LS |
1053                         AMD_CG_SUPPORT_MC_MGCG |
1054                         AMD_CG_SUPPORT_MC_LS;
1055                 adev->pg_flags = 0;
1056                 adev->external_rev_id = 0x1;
1057                 break;
1058         case CHIP_VEGA12:
1059                 adev->asic_funcs = &soc15_asic_funcs;
1060                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1061                         AMD_CG_SUPPORT_GFX_MGLS |
1062                         AMD_CG_SUPPORT_GFX_CGCG |
1063                         AMD_CG_SUPPORT_GFX_CGLS |
1064                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1065                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1066                         AMD_CG_SUPPORT_GFX_CP_LS |
1067                         AMD_CG_SUPPORT_MC_LS |
1068                         AMD_CG_SUPPORT_MC_MGCG |
1069                         AMD_CG_SUPPORT_SDMA_MGCG |
1070                         AMD_CG_SUPPORT_SDMA_LS |
1071                         AMD_CG_SUPPORT_BIF_MGCG |
1072                         AMD_CG_SUPPORT_BIF_LS |
1073                         AMD_CG_SUPPORT_HDP_MGCG |
1074                         AMD_CG_SUPPORT_HDP_LS |
1075                         AMD_CG_SUPPORT_ROM_MGCG |
1076                         AMD_CG_SUPPORT_VCE_MGCG |
1077                         AMD_CG_SUPPORT_UVD_MGCG;
1078                 adev->pg_flags = 0;
1079                 adev->external_rev_id = adev->rev_id + 0x14;
1080                 break;
1081         case CHIP_VEGA20:
1082                 adev->asic_funcs = &vega20_asic_funcs;
1083                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1084                         AMD_CG_SUPPORT_GFX_MGLS |
1085                         AMD_CG_SUPPORT_GFX_CGCG |
1086                         AMD_CG_SUPPORT_GFX_CGLS |
1087                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1088                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1089                         AMD_CG_SUPPORT_GFX_CP_LS |
1090                         AMD_CG_SUPPORT_MC_LS |
1091                         AMD_CG_SUPPORT_MC_MGCG |
1092                         AMD_CG_SUPPORT_SDMA_MGCG |
1093                         AMD_CG_SUPPORT_SDMA_LS |
1094                         AMD_CG_SUPPORT_BIF_MGCG |
1095                         AMD_CG_SUPPORT_BIF_LS |
1096                         AMD_CG_SUPPORT_HDP_MGCG |
1097                         AMD_CG_SUPPORT_HDP_LS |
1098                         AMD_CG_SUPPORT_ROM_MGCG |
1099                         AMD_CG_SUPPORT_VCE_MGCG |
1100                         AMD_CG_SUPPORT_UVD_MGCG;
1101                 adev->pg_flags = 0;
1102                 adev->external_rev_id = adev->rev_id + 0x28;
1103                 break;
1104         case CHIP_RAVEN:
1105                 adev->asic_funcs = &soc15_asic_funcs;
1106                 if (adev->rev_id >= 0x8)
1107                         adev->external_rev_id = adev->rev_id + 0x79;
1108                 else if (adev->pdev->device == 0x15d8)
1109                         adev->external_rev_id = adev->rev_id + 0x41;
1110                 else if (adev->rev_id == 1)
1111                         adev->external_rev_id = adev->rev_id + 0x20;
1112                 else
1113                         adev->external_rev_id = adev->rev_id + 0x01;
1114
1115                 if (adev->rev_id >= 0x8) {
1116                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1117                                 AMD_CG_SUPPORT_GFX_MGLS |
1118                                 AMD_CG_SUPPORT_GFX_CP_LS |
1119                                 AMD_CG_SUPPORT_GFX_3D_CGCG |
1120                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
1121                                 AMD_CG_SUPPORT_GFX_CGCG |
1122                                 AMD_CG_SUPPORT_GFX_CGLS |
1123                                 AMD_CG_SUPPORT_BIF_LS |
1124                                 AMD_CG_SUPPORT_HDP_LS |
1125                                 AMD_CG_SUPPORT_ROM_MGCG |
1126                                 AMD_CG_SUPPORT_MC_MGCG |
1127                                 AMD_CG_SUPPORT_MC_LS |
1128                                 AMD_CG_SUPPORT_SDMA_MGCG |
1129                                 AMD_CG_SUPPORT_SDMA_LS |
1130                                 AMD_CG_SUPPORT_VCN_MGCG;
1131
1132                         adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1133                 } else if (adev->pdev->device == 0x15d8) {
1134                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1135                                 AMD_CG_SUPPORT_GFX_MGLS |
1136                                 AMD_CG_SUPPORT_GFX_CP_LS |
1137                                 AMD_CG_SUPPORT_GFX_3D_CGCG |
1138                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
1139                                 AMD_CG_SUPPORT_GFX_CGCG |
1140                                 AMD_CG_SUPPORT_GFX_CGLS |
1141                                 AMD_CG_SUPPORT_BIF_LS |
1142                                 AMD_CG_SUPPORT_HDP_LS |
1143                                 AMD_CG_SUPPORT_ROM_MGCG |
1144                                 AMD_CG_SUPPORT_MC_MGCG |
1145                                 AMD_CG_SUPPORT_MC_LS |
1146                                 AMD_CG_SUPPORT_SDMA_MGCG |
1147                                 AMD_CG_SUPPORT_SDMA_LS;
1148
1149                         adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1150                                 AMD_PG_SUPPORT_MMHUB |
1151                                 AMD_PG_SUPPORT_VCN |
1152                                 AMD_PG_SUPPORT_VCN_DPG;
1153                 } else {
1154                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1155                                 AMD_CG_SUPPORT_GFX_MGLS |
1156                                 AMD_CG_SUPPORT_GFX_RLC_LS |
1157                                 AMD_CG_SUPPORT_GFX_CP_LS |
1158                                 AMD_CG_SUPPORT_GFX_3D_CGCG |
1159                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
1160                                 AMD_CG_SUPPORT_GFX_CGCG |
1161                                 AMD_CG_SUPPORT_GFX_CGLS |
1162                                 AMD_CG_SUPPORT_BIF_MGCG |
1163                                 AMD_CG_SUPPORT_BIF_LS |
1164                                 AMD_CG_SUPPORT_HDP_MGCG |
1165                                 AMD_CG_SUPPORT_HDP_LS |
1166                                 AMD_CG_SUPPORT_DRM_MGCG |
1167                                 AMD_CG_SUPPORT_DRM_LS |
1168                                 AMD_CG_SUPPORT_ROM_MGCG |
1169                                 AMD_CG_SUPPORT_MC_MGCG |
1170                                 AMD_CG_SUPPORT_MC_LS |
1171                                 AMD_CG_SUPPORT_SDMA_MGCG |
1172                                 AMD_CG_SUPPORT_SDMA_LS |
1173                                 AMD_CG_SUPPORT_VCN_MGCG;
1174
1175                         adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1176                 }
1177                 break;
1178         case CHIP_ARCTURUS:
1179                 adev->asic_funcs = &vega20_asic_funcs;
1180                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1181                         AMD_CG_SUPPORT_GFX_MGLS |
1182                         AMD_CG_SUPPORT_GFX_CGCG |
1183                         AMD_CG_SUPPORT_GFX_CGLS |
1184                         AMD_CG_SUPPORT_GFX_CP_LS |
1185                         AMD_CG_SUPPORT_HDP_MGCG |
1186                         AMD_CG_SUPPORT_HDP_LS |
1187                         AMD_CG_SUPPORT_SDMA_MGCG |
1188                         AMD_CG_SUPPORT_SDMA_LS |
1189                         AMD_CG_SUPPORT_MC_MGCG |
1190                         AMD_CG_SUPPORT_MC_LS |
1191                         AMD_CG_SUPPORT_IH_CG |
1192                         AMD_CG_SUPPORT_VCN_MGCG |
1193                         AMD_CG_SUPPORT_JPEG_MGCG;
1194                 adev->pg_flags = 0;
1195                 adev->external_rev_id = adev->rev_id + 0x32;
1196                 break;
1197         case CHIP_RENOIR:
1198                 adev->asic_funcs = &soc15_asic_funcs;
1199                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1200                                  AMD_CG_SUPPORT_GFX_MGLS |
1201                                  AMD_CG_SUPPORT_GFX_3D_CGCG |
1202                                  AMD_CG_SUPPORT_GFX_3D_CGLS |
1203                                  AMD_CG_SUPPORT_GFX_CGCG |
1204                                  AMD_CG_SUPPORT_GFX_CGLS |
1205                                  AMD_CG_SUPPORT_GFX_CP_LS |
1206                                  AMD_CG_SUPPORT_MC_MGCG |
1207                                  AMD_CG_SUPPORT_MC_LS |
1208                                  AMD_CG_SUPPORT_SDMA_MGCG |
1209                                  AMD_CG_SUPPORT_SDMA_LS |
1210                                  AMD_CG_SUPPORT_BIF_LS |
1211                                  AMD_CG_SUPPORT_HDP_LS |
1212                                  AMD_CG_SUPPORT_ROM_MGCG |
1213                                  AMD_CG_SUPPORT_VCN_MGCG |
1214                                  AMD_CG_SUPPORT_JPEG_MGCG |
1215                                  AMD_CG_SUPPORT_IH_CG |
1216                                  AMD_CG_SUPPORT_ATHUB_LS |
1217                                  AMD_CG_SUPPORT_ATHUB_MGCG |
1218                                  AMD_CG_SUPPORT_DF_MGCG;
1219                 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1220                                  AMD_PG_SUPPORT_VCN |
1221                                  AMD_PG_SUPPORT_JPEG |
1222                                  AMD_PG_SUPPORT_VCN_DPG;
1223                 adev->external_rev_id = adev->rev_id + 0x91;
1224                 break;
1225         default:
1226                 /* FIXME: not supported yet */
1227                 return -EINVAL;
1228         }
1229
1230         if (amdgpu_sriov_vf(adev)) {
1231                 amdgpu_virt_init_setting(adev);
1232                 xgpu_ai_mailbox_set_irq_funcs(adev);
1233         }
1234
1235         return 0;
1236 }
1237
1238 static int soc15_common_late_init(void *handle)
1239 {
1240         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1241         int r = 0;
1242
1243         if (amdgpu_sriov_vf(adev))
1244                 xgpu_ai_mailbox_get_irq(adev);
1245
1246         if (adev->nbio.funcs->ras_late_init)
1247                 r = adev->nbio.funcs->ras_late_init(adev);
1248
1249         return r;
1250 }
1251
1252 static int soc15_common_sw_init(void *handle)
1253 {
1254         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1255
1256         if (amdgpu_sriov_vf(adev))
1257                 xgpu_ai_mailbox_add_irq_id(adev);
1258
1259         adev->df.funcs->sw_init(adev);
1260
1261         return 0;
1262 }
1263
1264 static int soc15_common_sw_fini(void *handle)
1265 {
1266         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1267
1268         amdgpu_nbio_ras_fini(adev);
1269         adev->df.funcs->sw_fini(adev);
1270         return 0;
1271 }
1272
1273 static void soc15_doorbell_range_init(struct amdgpu_device *adev)
1274 {
1275         int i;
1276         struct amdgpu_ring *ring;
1277
1278         /* sdma/ih doorbell range are programed by hypervisor */
1279         if (!amdgpu_sriov_vf(adev)) {
1280                 for (i = 0; i < adev->sdma.num_instances; i++) {
1281                         ring = &adev->sdma.instance[i].ring;
1282                         adev->nbio.funcs->sdma_doorbell_range(adev, i,
1283                                 ring->use_doorbell, ring->doorbell_index,
1284                                 adev->doorbell_index.sdma_doorbell_range);
1285                 }
1286
1287                 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
1288                                                 adev->irq.ih.doorbell_index);
1289         }
1290 }
1291
1292 static int soc15_common_hw_init(void *handle)
1293 {
1294         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1295
1296         /* enable pcie gen2/3 link */
1297         soc15_pcie_gen3_enable(adev);
1298         /* enable aspm */
1299         soc15_program_aspm(adev);
1300         /* setup nbio registers */
1301         adev->nbio.funcs->init_registers(adev);
1302         /* remap HDP registers to a hole in mmio space,
1303          * for the purpose of expose those registers
1304          * to process space
1305          */
1306         if (adev->nbio.funcs->remap_hdp_registers)
1307                 adev->nbio.funcs->remap_hdp_registers(adev);
1308
1309         /* enable the doorbell aperture */
1310         soc15_enable_doorbell_aperture(adev, true);
1311         /* HW doorbell routing policy: doorbell writing not
1312          * in SDMA/IH/MM/ACV range will be routed to CP. So
1313          * we need to init SDMA/IH/MM/ACV doorbell range prior
1314          * to CP ip block init and ring test.
1315          */
1316         soc15_doorbell_range_init(adev);
1317
1318         return 0;
1319 }
1320
1321 static int soc15_common_hw_fini(void *handle)
1322 {
1323         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1324
1325         /* disable the doorbell aperture */
1326         soc15_enable_doorbell_aperture(adev, false);
1327         if (amdgpu_sriov_vf(adev))
1328                 xgpu_ai_mailbox_put_irq(adev);
1329
1330         if (adev->nbio.ras_if &&
1331             amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
1332                 if (adev->nbio.funcs->init_ras_controller_interrupt)
1333                         amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);
1334                 if (adev->nbio.funcs->init_ras_err_event_athub_interrupt)
1335                         amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
1336         }
1337
1338         return 0;
1339 }
1340
1341 static int soc15_common_suspend(void *handle)
1342 {
1343         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1344
1345         return soc15_common_hw_fini(adev);
1346 }
1347
1348 static int soc15_common_resume(void *handle)
1349 {
1350         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1351
1352         return soc15_common_hw_init(adev);
1353 }
1354
1355 static bool soc15_common_is_idle(void *handle)
1356 {
1357         return true;
1358 }
1359
1360 static int soc15_common_wait_for_idle(void *handle)
1361 {
1362         return 0;
1363 }
1364
1365 static int soc15_common_soft_reset(void *handle)
1366 {
1367         return 0;
1368 }
1369
1370 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
1371 {
1372         uint32_t def, data;
1373
1374         if (adev->asic_type == CHIP_VEGA20 ||
1375                 adev->asic_type == CHIP_ARCTURUS) {
1376                 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
1377
1378                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1379                         data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1380                                 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1381                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1382                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
1383                 else
1384                         data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1385                                 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1386                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1387                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
1388
1389                 if (def != data)
1390                         WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
1391         } else {
1392                 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1393
1394                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1395                         data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1396                 else
1397                         data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1398
1399                 if (def != data)
1400                         WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
1401         }
1402 }
1403
1404 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1405 {
1406         uint32_t def, data;
1407
1408         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1409
1410         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1411                 data &= ~(0x01000000 |
1412                           0x02000000 |
1413                           0x04000000 |
1414                           0x08000000 |
1415                           0x10000000 |
1416                           0x20000000 |
1417                           0x40000000 |
1418                           0x80000000);
1419         else
1420                 data |= (0x01000000 |
1421                          0x02000000 |
1422                          0x04000000 |
1423                          0x08000000 |
1424                          0x10000000 |
1425                          0x20000000 |
1426                          0x40000000 |
1427                          0x80000000);
1428
1429         if (def != data)
1430                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1431 }
1432
1433 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1434 {
1435         uint32_t def, data;
1436
1437         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1438
1439         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1440                 data |= 1;
1441         else
1442                 data &= ~1;
1443
1444         if (def != data)
1445                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1446 }
1447
1448 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1449                                                        bool enable)
1450 {
1451         uint32_t def, data;
1452
1453         def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1454
1455         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1456                 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1457                         CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1458         else
1459                 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1460                         CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1461
1462         if (def != data)
1463                 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
1464 }
1465
1466 static int soc15_common_set_clockgating_state(void *handle,
1467                                             enum amd_clockgating_state state)
1468 {
1469         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1470
1471         if (amdgpu_sriov_vf(adev))
1472                 return 0;
1473
1474         switch (adev->asic_type) {
1475         case CHIP_VEGA10:
1476         case CHIP_VEGA12:
1477         case CHIP_VEGA20:
1478                 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1479                                 state == AMD_CG_STATE_GATE);
1480                 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1481                                 state == AMD_CG_STATE_GATE);
1482                 soc15_update_hdp_light_sleep(adev,
1483                                 state == AMD_CG_STATE_GATE);
1484                 soc15_update_drm_clock_gating(adev,
1485                                 state == AMD_CG_STATE_GATE);
1486                 soc15_update_drm_light_sleep(adev,
1487                                 state == AMD_CG_STATE_GATE);
1488                 soc15_update_rom_medium_grain_clock_gating(adev,
1489                                 state == AMD_CG_STATE_GATE);
1490                 adev->df.funcs->update_medium_grain_clock_gating(adev,
1491                                 state == AMD_CG_STATE_GATE);
1492                 break;
1493         case CHIP_RAVEN:
1494         case CHIP_RENOIR:
1495                 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1496                                 state == AMD_CG_STATE_GATE);
1497                 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1498                                 state == AMD_CG_STATE_GATE);
1499                 soc15_update_hdp_light_sleep(adev,
1500                                 state == AMD_CG_STATE_GATE);
1501                 soc15_update_drm_clock_gating(adev,
1502                                 state == AMD_CG_STATE_GATE);
1503                 soc15_update_drm_light_sleep(adev,
1504                                 state == AMD_CG_STATE_GATE);
1505                 soc15_update_rom_medium_grain_clock_gating(adev,
1506                                 state == AMD_CG_STATE_GATE);
1507                 break;
1508         case CHIP_ARCTURUS:
1509                 soc15_update_hdp_light_sleep(adev,
1510                                 state == AMD_CG_STATE_GATE);
1511                 break;
1512         default:
1513                 break;
1514         }
1515         return 0;
1516 }
1517
1518 static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
1519 {
1520         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1521         int data;
1522
1523         if (amdgpu_sriov_vf(adev))
1524                 *flags = 0;
1525
1526         adev->nbio.funcs->get_clockgating_state(adev, flags);
1527
1528         /* AMD_CG_SUPPORT_HDP_LS */
1529         data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1530         if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1531                 *flags |= AMD_CG_SUPPORT_HDP_LS;
1532
1533         /* AMD_CG_SUPPORT_DRM_MGCG */
1534         data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1535         if (!(data & 0x01000000))
1536                 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1537
1538         /* AMD_CG_SUPPORT_DRM_LS */
1539         data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1540         if (data & 0x1)
1541                 *flags |= AMD_CG_SUPPORT_DRM_LS;
1542
1543         /* AMD_CG_SUPPORT_ROM_MGCG */
1544         data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1545         if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
1546                 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
1547
1548         adev->df.funcs->get_clockgating_state(adev, flags);
1549 }
1550
1551 static int soc15_common_set_powergating_state(void *handle,
1552                                             enum amd_powergating_state state)
1553 {
1554         /* todo */
1555         return 0;
1556 }
1557
1558 const struct amd_ip_funcs soc15_common_ip_funcs = {
1559         .name = "soc15_common",
1560         .early_init = soc15_common_early_init,
1561         .late_init = soc15_common_late_init,
1562         .sw_init = soc15_common_sw_init,
1563         .sw_fini = soc15_common_sw_fini,
1564         .hw_init = soc15_common_hw_init,
1565         .hw_fini = soc15_common_hw_fini,
1566         .suspend = soc15_common_suspend,
1567         .resume = soc15_common_resume,
1568         .is_idle = soc15_common_is_idle,
1569         .wait_for_idle = soc15_common_wait_for_idle,
1570         .soft_reset = soc15_common_soft_reset,
1571         .set_clockgating_state = soc15_common_set_clockgating_state,
1572         .set_powergating_state = soc15_common_set_powergating_state,
1573         .get_clockgating_state= soc15_common_get_clockgating_state,
1574 };