drivers/gpu/drm/amd/amdgpu/soc15.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_atombios.h"
  30 #include "amdgpu_ih.h"
  31 #include "amdgpu_uvd.h"
  32 #include "amdgpu_vce.h"
  33 #include "amdgpu_ucode.h"
  34 #include "amdgpu_psp.h"
  35 #include "atom.h"
  36 #include "amd_pcie.h"
  37
  38 #include "uvd/uvd_7_0_offset.h"
  39 #include "gc/gc_9_0_offset.h"
  40 #include "gc/gc_9_0_sh_mask.h"
  41 #include "sdma0/sdma0_4_0_offset.h"
  42 #include "sdma1/sdma1_4_0_offset.h"
  43 #include "hdp/hdp_4_0_offset.h"
  44 #include "hdp/hdp_4_0_sh_mask.h"
  45 #include "nbio/nbio_7_0_default.h"
  46 #include "nbio/nbio_7_0_offset.h"
  47 #include "nbio/nbio_7_0_sh_mask.h"
  48 #include "nbio/nbio_7_0_smn.h"
  49 #include "mp/mp_9_0_offset.h"
  50
  51 #include "soc15.h"
  52 #include "soc15_common.h"
  53 #include "gfx_v9_0.h"
  54 #include "gmc_v9_0.h"
  55 #include "gfxhub_v1_0.h"
  56 #include "mmhub_v1_0.h"
  57 #include "df_v1_7.h"
  58 #include "df_v3_6.h"
  59 #include "nbio_v6_1.h"
  60 #include "nbio_v7_0.h"
  61 #include "nbio_v7_4.h"
  62 #include "vega10_ih.h"
  63 #include "navi10_ih.h"
  64 #include "sdma_v4_0.h"
  65 #include "uvd_v7_0.h"
  66 #include "vce_v4_0.h"
  67 #include "vcn_v1_0.h"
  68 #include "vcn_v2_0.h"
  69 #include "jpeg_v2_0.h"
  70 #include "vcn_v2_5.h"
  71 #include "jpeg_v2_5.h"
  72 #include "smuio_v9_0.h"
  73 #include "smuio_v11_0.h"
  74 #include "dce_virtual.h"
  75 #include "mxgpu_ai.h"
  76 #include "amdgpu_smu.h"
  77 #include "amdgpu_ras.h"
  78 #include "amdgpu_xgmi.h"
  79 #include <uapi/linux/kfd_ioctl.h>
  80
  81 #define mmMP0_MISC_CGTT_CTRL0                                                                   0x01b9
  82 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX                                                          0
  83 #define mmMP0_MISC_LIGHT_SLEEP_CTRL                                                             0x01ba
  84 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX                                                    0
  85
  86 /* for Vega20 register name change */
  87 #define mmHDP_MEM_POWER_CTRL    0x00d4
  88 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK  0x00000001L
  89 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK    0x00000002L
  90 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK   0x00010000L
  91 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK             0x00020000L
  92 #define mmHDP_MEM_POWER_CTRL_BASE_IDX   0
  93
  94 /*
  95  * Indirect registers accessor
  96  */
  97 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
  98 {
  99         unsigned long address, data;
 100         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 101         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 102
 103         return amdgpu_device_indirect_rreg(adev, address, data, reg);
 104 }
 105
 106 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 107 {
 108         unsigned long address, data;
 109
 110         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 111         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 112
 113         amdgpu_device_indirect_wreg(adev, address, data, reg, v);
 114 }
 115
 116 static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
 117 {
 118         unsigned long address, data;
 119         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 120         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 121
 122         return amdgpu_device_indirect_rreg64(adev, address, data, reg);
 123 }
 124
 125 static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
 126 {
 127         unsigned long address, data;
 128
 129         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 130         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 131
 132         amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
 133 }
 134
 135 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
 136 {
 137         unsigned long flags, address, data;
 138         u32 r;
 139
 140         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 141         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 142
 143         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 144         WREG32(address, ((reg) & 0x1ff));
 145         r = RREG32(data);
 146         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 147         return r;
 148 }
 149
 150 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 151 {
 152         unsigned long flags, address, data;
 153
 154         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 155         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 156
 157         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 158         WREG32(address, ((reg) & 0x1ff));
 159         WREG32(data, (v));
 160         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 161 }
 162
 163 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
 164 {
 165         unsigned long flags, address, data;
 166         u32 r;
 167
 168         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 169         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 170
 171         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 172         WREG32(address, (reg));
 173         r = RREG32(data);
 174         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 175         return r;
 176 }
 177
 178 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 179 {
 180         unsigned long flags, address, data;
 181
 182         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 183         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 184
 185         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 186         WREG32(address, (reg));
 187         WREG32(data, (v));
 188         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 189 }
 190
 191 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
 192 {
 193         unsigned long flags;
 194         u32 r;
 195
 196         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 197         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
 198         r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
 199         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 200         return r;
 201 }
 202
 203 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 204 {
 205         unsigned long flags;
 206
 207         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 208         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
 209         WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
 210         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 211 }
 212
 213 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
 214 {
 215         unsigned long flags;
 216         u32 r;
 217
 218         spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
 219         WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
 220         r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
 221         spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
 222         return r;
 223 }
 224
 225 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 226 {
 227         unsigned long flags;
 228
 229         spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
 230         WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
 231         WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
 232         spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
 233 }
 234
 235 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
 236 {
 237         return adev->nbio.funcs->get_memsize(adev);
 238 }
 239
 240 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 241 {
 242         u32 reference_clock = adev->clock.spll.reference_freq;
 243
 244         if (adev->asic_type == CHIP_RAVEN)
 245                 return reference_clock / 4;
 246
 247         return reference_clock;
 248 }
 249
 250
 251 void soc15_grbm_select(struct amdgpu_device *adev,
 252                      u32 me, u32 pipe, u32 queue, u32 vmid)
 253 {
 254         u32 grbm_gfx_cntl = 0;
 255         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 256         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 257         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 258         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 259
 260         WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
 261 }
 262
 263 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
 264 {
 265         /* todo */
 266 }
 267
 268 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
 269 {
 270         /* todo */
 271         return false;
 272 }
 273
 274 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
 275                                      u8 *bios, u32 length_bytes)
 276 {
 277         u32 *dw_ptr;
 278         u32 i, length_dw;
 279         uint32_t rom_index_offset;
 280         uint32_t rom_data_offset;
 281
 282         if (bios == NULL)
 283                 return false;
 284         if (length_bytes == 0)
 285                 return false;
 286         /* APU vbios image is part of sbios image */
 287         if (adev->flags & AMD_IS_APU)
 288                 return false;
 289
 290         dw_ptr = (u32 *)bios;
 291         length_dw = ALIGN(length_bytes, 4) / 4;
 292
 293         rom_index_offset =
 294                 adev->smuio.funcs->get_rom_index_offset(adev);
 295         rom_data_offset =
 296                 adev->smuio.funcs->get_rom_data_offset(adev);
 297
 298         /* set rom index to 0 */
 299         WREG32(rom_index_offset, 0);
 300         /* read out the rom data */
 301         for (i = 0; i < length_dw; i++)
 302                 dw_ptr[i] = RREG32(rom_data_offset);
 303
 304         return true;
 305 }
 306
 307 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
 308         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 309         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
 310         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
 311         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
 312         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
 313         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
 314         { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
 315         { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
 316         { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
 317         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
 318         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
 319         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
 320         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
 321         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
 322         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
 323         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
 324         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 325         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 326         { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 327         { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
 328 };
 329
 330 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 331                                          u32 sh_num, u32 reg_offset)
 332 {
 333         uint32_t val;
 334
 335         mutex_lock(&adev->grbm_idx_mutex);
 336         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 337                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 338
 339         val = RREG32(reg_offset);
 340
 341         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 342                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 343         mutex_unlock(&adev->grbm_idx_mutex);
 344         return val;
 345 }
 346
 347 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
 348                                          bool indexed, u32 se_num,
 349                                          u32 sh_num, u32 reg_offset)
 350 {
 351         if (indexed) {
 352                 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
 353         } else {
 354                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 355                         return adev->gfx.config.gb_addr_config;
 356                 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
 357                         return adev->gfx.config.db_debug2;
 358                 return RREG32(reg_offset);
 359         }
 360 }
 361
 362 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
 363                             u32 sh_num, u32 reg_offset, u32 *value)
 364 {
 365         uint32_t i;
 366         struct soc15_allowed_register_entry  *en;
 367
 368         *value = 0;
 369         for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
 370                 en = &soc15_allowed_read_registers[i];
 371                 if (adev->reg_offset[en->hwip][en->inst] &&
 372                         reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
 373                                         + en->reg_offset))
 374                         continue;
 375
 376                 *value = soc15_get_register_value(adev,
 377                                                   soc15_allowed_read_registers[i].grbm_indexed,
 378                                                   se_num, sh_num, reg_offset);
 379                 return 0;
 380         }
 381         return -EINVAL;
 382 }
 383
 384
 385 /**
 386  * soc15_program_register_sequence - program an array of registers.
 387  *
 388  * @adev: amdgpu_device pointer
 389  * @regs: pointer to the register array
 390  * @array_size: size of the register array
 391  *
 392  * Programs an array or registers with and and or masks.
 393  * This is a helper for setting golden registers.
 394  */
 395
 396 void soc15_program_register_sequence(struct amdgpu_device *adev,
 397                                              const struct soc15_reg_golden *regs,
 398                                              const u32 array_size)
 399 {
 400         const struct soc15_reg_golden *entry;
 401         u32 tmp, reg;
 402         int i;
 403
 404         for (i = 0; i < array_size; ++i) {
 405                 entry = &regs[i];
 406                 reg =  adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
 407
 408                 if (entry->and_mask == 0xffffffff) {
 409                         tmp = entry->or_mask;
 410                 } else {
 411                         tmp = RREG32(reg);
 412                         tmp &= ~(entry->and_mask);
 413                         tmp |= (entry->or_mask & entry->and_mask);
 414                 }
 415
 416                 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
 417                         reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
 418                         reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
 419                         reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
 420                         WREG32_RLC(reg, tmp);
 421                 else
 422                         WREG32(reg, tmp);
 423
 424         }
 425
 426 }
 427
 428 static int soc15_asic_mode1_reset(struct amdgpu_device *adev)
 429 {
 430         u32 i;
 431         int ret = 0;
 432
 433         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 434
 435         dev_info(adev->dev, "GPU mode1 reset\n");
 436
 437         /* disable BM */
 438         pci_clear_master(adev->pdev);
 439
 440         amdgpu_device_cache_pci_state(adev->pdev);
 441
 442         ret = psp_gpu_reset(adev);
 443         if (ret)
 444                 dev_err(adev->dev, "GPU mode1 reset failed\n");
 445
 446         amdgpu_device_load_pci_state(adev->pdev);
 447
 448         /* wait for asic to come out of reset */
 449         for (i = 0; i < adev->usec_timeout; i++) {
 450                 u32 memsize = adev->nbio.funcs->get_memsize(adev);
 451
 452                 if (memsize != 0xffffffff)
 453                         break;
 454                 udelay(1);
 455         }
 456
 457         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 458
 459         return ret;
 460 }
 461
 462 static int soc15_asic_baco_reset(struct amdgpu_device *adev)
 463 {
 464         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 465         int ret = 0;
 466
 467         /* avoid NBIF got stuck when do RAS recovery in BACO reset */
 468         if (ras && ras->supported)
 469                 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
 470
 471         ret = amdgpu_dpm_baco_reset(adev);
 472         if (ret)
 473                 return ret;
 474
 475         /* re-enable doorbell interrupt after BACO exit */
 476         if (ras && ras->supported)
 477                 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
 478
 479         return 0;
 480 }
 481
 482 static enum amd_reset_method
 483 soc15_asic_reset_method(struct amdgpu_device *adev)
 484 {
 485         bool baco_reset = false;
 486         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 487
 488         if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
 489             amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
 490                 amdgpu_reset_method == AMD_RESET_METHOD_BACO)
 491                 return amdgpu_reset_method;
 492
 493         if (amdgpu_reset_method != -1)
 494                 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
 495                                   amdgpu_reset_method);
 496
 497         switch (adev->asic_type) {
 498         case CHIP_RAVEN:
 499         case CHIP_RENOIR:
 500                 return AMD_RESET_METHOD_MODE2;
 501         case CHIP_VEGA10:
 502         case CHIP_VEGA12:
 503         case CHIP_ARCTURUS:
 504                 baco_reset = amdgpu_dpm_is_baco_supported(adev);
 505                 break;
 506         case CHIP_VEGA20:
 507                 if (adev->psp.sos_fw_version >= 0x80067)
 508                         baco_reset = amdgpu_dpm_is_baco_supported(adev);
 509
 510                 /*
 511                  * 1. PMFW version > 0x284300: all cases use baco
 512                  * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco
 513                  */
 514                 if ((ras && ras->supported) && adev->pm.fw_version <= 0x283400)
 515                         baco_reset = false;
 516                 break;
 517         default:
 518                 break;
 519         }
 520
 521         if (baco_reset)
 522                 return AMD_RESET_METHOD_BACO;
 523         else
 524                 return AMD_RESET_METHOD_MODE1;
 525 }
 526
 527 static int soc15_asic_reset(struct amdgpu_device *adev)
 528 {
 529         /* original raven doesn't have full asic reset */
 530         if ((adev->apu_flags & AMD_APU_IS_RAVEN) &&
 531             !(adev->apu_flags & AMD_APU_IS_RAVEN2))
 532                 return 0;
 533
 534         switch (soc15_asic_reset_method(adev)) {
 535                 case AMD_RESET_METHOD_BACO:
 536                         dev_info(adev->dev, "BACO reset\n");
 537                         return soc15_asic_baco_reset(adev);
 538                 case AMD_RESET_METHOD_MODE2:
 539                         dev_info(adev->dev, "MODE2 reset\n");
 540                         return amdgpu_dpm_mode2_reset(adev);
 541                 default:
 542                         dev_info(adev->dev, "MODE1 reset\n");
 543                         return soc15_asic_mode1_reset(adev);
 544         }
 545 }
 546
 547 static bool soc15_supports_baco(struct amdgpu_device *adev)
 548 {
 549         switch (adev->asic_type) {
 550         case CHIP_VEGA10:
 551         case CHIP_VEGA12:
 552         case CHIP_ARCTURUS:
 553                 return amdgpu_dpm_is_baco_supported(adev);
 554         case CHIP_VEGA20:
 555                 if (adev->psp.sos_fw_version >= 0x80067)
 556                         return amdgpu_dpm_is_baco_supported(adev);
 557                 return false;
 558         default:
 559                 return false;
 560         }
 561 }
 562
 563 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
 564                         u32 cntl_reg, u32 status_reg)
 565 {
 566         return 0;
 567 }*/
 568
 569 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 570 {
 571         /*int r;
 572
 573         r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
 574         if (r)
 575                 return r;
 576
 577         r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
 578         */
 579         return 0;
 580 }
 581
 582 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 583 {
 584         /* todo */
 585
 586         return 0;
 587 }
 588
 589 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
 590 {
 591         if (pci_is_root_bus(adev->pdev->bus))
 592                 return;
 593
 594         if (amdgpu_pcie_gen2 == 0)
 595                 return;
 596
 597         if (adev->flags & AMD_IS_APU)
 598                 return;
 599
 600         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 601                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 602                 return;
 603
 604         /* todo */
 605 }
 606
 607 static void soc15_program_aspm(struct amdgpu_device *adev)
 608 {
 609
 610         if (amdgpu_aspm == 0)
 611                 return;
 612
 613         /* todo */
 614 }
 615
 616 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
 617                                            bool enable)
 618 {
 619         adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
 620         adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
 621 }
 622
 623 static const struct amdgpu_ip_block_version vega10_common_ip_block =
 624 {
 625         .type = AMD_IP_BLOCK_TYPE_COMMON,
 626         .major = 2,
 627         .minor = 0,
 628         .rev = 0,
 629         .funcs = &soc15_common_ip_funcs,
 630 };
 631
 632 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
 633 {
 634         return adev->nbio.funcs->get_rev_id(adev);
 635 }
 636
 637 static void soc15_reg_base_init(struct amdgpu_device *adev)
 638 {
 639         int r;
 640
 641         /* Set IP register base before any HW register access */
 642         switch (adev->asic_type) {
 643         case CHIP_VEGA10:
 644         case CHIP_VEGA12:
 645         case CHIP_RAVEN:
 646                 vega10_reg_base_init(adev);
 647                 break;
 648         case CHIP_RENOIR:
 649                 /* It's safe to do ip discovery here for Renior,
 650                  * it doesn't support SRIOV. */
 651                 if (amdgpu_discovery) {
 652                         r = amdgpu_discovery_reg_base_init(adev);
 653                         if (r == 0)
 654                                 break;
 655                         DRM_WARN("failed to init reg base from ip discovery table, "
 656                                  "fallback to legacy init method\n");
 657                 }
 658                 vega10_reg_base_init(adev);
 659                 break;
 660         case CHIP_VEGA20:
 661                 vega20_reg_base_init(adev);
 662                 break;
 663         case CHIP_ARCTURUS:
 664                 arct_reg_base_init(adev);
 665                 break;
 666         default:
 667                 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type);
 668                 break;
 669         }
 670 }
 671
 672 void soc15_set_virt_ops(struct amdgpu_device *adev)
 673 {
 674         adev->virt.ops = &xgpu_ai_virt_ops;
 675
 676         /* init soc15 reg base early enough so we can
 677          * request request full access for sriov before
 678          * set_ip_blocks. */
 679         soc15_reg_base_init(adev);
 680 }
 681
 682 int soc15_set_ip_blocks(struct amdgpu_device *adev)
 683 {
 684         /* for bare metal case */
 685         if (!amdgpu_sriov_vf(adev))
 686                 soc15_reg_base_init(adev);
 687
 688         if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
 689                 adev->gmc.xgmi.supported = true;
 690
 691         if (adev->flags & AMD_IS_APU) {
 692                 adev->nbio.funcs = &nbio_v7_0_funcs;
 693                 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
 694         } else if (adev->asic_type == CHIP_VEGA20 ||
 695                    adev->asic_type == CHIP_ARCTURUS) {
 696                 adev->nbio.funcs = &nbio_v7_4_funcs;
 697                 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
 698         } else {
 699                 adev->nbio.funcs = &nbio_v6_1_funcs;
 700                 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
 701         }
 702
 703         if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
 704                 adev->df.funcs = &df_v3_6_funcs;
 705         else
 706                 adev->df.funcs = &df_v1_7_funcs;
 707
 708         if (adev->asic_type == CHIP_VEGA20 ||
 709             adev->asic_type == CHIP_ARCTURUS)
 710                 adev->smuio.funcs = &smuio_v11_0_funcs;
 711         else
 712                 adev->smuio.funcs = &smuio_v9_0_funcs;
 713
 714         adev->rev_id = soc15_get_rev_id(adev);
 715
 716         switch (adev->asic_type) {
 717         case CHIP_VEGA10:
 718         case CHIP_VEGA12:
 719         case CHIP_VEGA20:
 720                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 721                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 722
 723                 /* For Vega10 SR-IOV, PSP need to be initialized before IH */
 724                 if (amdgpu_sriov_vf(adev)) {
 725                         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
 726                                 if (adev->asic_type == CHIP_VEGA20)
 727                                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 728                                 else
 729                                         amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
 730                         }
 731                         if (adev->asic_type == CHIP_VEGA20)
 732                                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 733                         else
 734                                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 735                 } else {
 736                         if (adev->asic_type == CHIP_VEGA20)
 737                                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 738                         else
 739                                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 740                         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
 741                                 if (adev->asic_type == CHIP_VEGA20)
 742                                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 743                                 else
 744                                         amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
 745                         }
 746                 }
 747                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 748                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 749                 if (is_support_sw_smu(adev)) {
 750                         if (!amdgpu_sriov_vf(adev))
 751                                 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 752                 } else {
 753                         amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
 754                 }
 755                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 756                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 757 #if defined(CONFIG_DRM_AMD_DC)
 758                 else if (amdgpu_device_has_dc_support(adev))
 759                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 760 #endif
 761                 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) {
 762                         amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
 763                         amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
 764                 }
 765                 break;
 766         case CHIP_RAVEN:
 767                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 768                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 769                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 770                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 771                         amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
 772                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 773                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 774                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
 775                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 776                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 777 #if defined(CONFIG_DRM_AMD_DC)
 778                 else if (amdgpu_device_has_dc_support(adev))
 779                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 780 #endif
 781                 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
 782                 break;
 783         case CHIP_ARCTURUS:
 784                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 785                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 786
 787                 if (amdgpu_sriov_vf(adev)) {
 788                         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 789                                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 790                         amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 791                 } else {
 792                         amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 793                         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 794                                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 795                 }
 796
 797                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 798                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 799                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 800                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 801                 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 802
 803                 if (amdgpu_sriov_vf(adev)) {
 804                         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 805                                 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
 806                 } else {
 807                         amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
 808                 }
 809                 if (!amdgpu_sriov_vf(adev))
 810                         amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
 811                 break;
 812         case CHIP_RENOIR:
 813                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 814                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 815                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 816                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 817                         amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
 818                 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
 819                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 820                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 821                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 822                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 823 #if defined(CONFIG_DRM_AMD_DC)
 824                 else if (amdgpu_device_has_dc_support(adev))
 825                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 826 #endif
 827                 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 828                 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
 829                 break;
 830         default:
 831                 return -EINVAL;
 832         }
 833
 834         return 0;
 835 }
 836
 837 static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
 838 {
 839         adev->nbio.funcs->hdp_flush(adev, ring);
 840 }
 841
 842 static void soc15_invalidate_hdp(struct amdgpu_device *adev,
 843                                  struct amdgpu_ring *ring)
 844 {
 845         if (!ring || !ring->funcs->emit_wreg)
 846                 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
 847         else
 848                 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
 849                         HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
 850 }
 851
 852 static bool soc15_need_full_reset(struct amdgpu_device *adev)
 853 {
 854         /* change this when we implement soft reset */
 855         return true;
 856 }
 857
 858 static void vega20_reset_hdp_ras_error_count(struct amdgpu_device *adev)
 859 {
 860         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
 861                 return;
 862         /*read back hdp ras counter to reset it to 0 */
 863         RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);
 864 }
 865
 866 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
 867                                  uint64_t *count1)
 868 {
 869         uint32_t perfctr = 0;
 870         uint64_t cnt0_of, cnt1_of;
 871         int tmp;
 872
 873         /* This reports 0 on APUs, so return to avoid writing/reading registers
 874          * that may or may not be different from their GPU counterparts
 875          */
 876         if (adev->flags & AMD_IS_APU)
 877                 return;
 878
 879         /* Set the 2 events that we wish to watch, defined above */
 880         /* Reg 40 is # received msgs */
 881         /* Reg 104 is # of posted requests sent */
 882         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
 883         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
 884
 885         /* Write to enable desired perf counters */
 886         WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
 887         /* Zero out and enable the perf counters
 888          * Write 0x5:
 889          * Bit 0 = Start all counters(1)
 890          * Bit 2 = Global counter reset enable(1)
 891          */
 892         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
 893
 894         msleep(1000);
 895
 896         /* Load the shadow and disable the perf counters
 897          * Write 0x2:
 898          * Bit 0 = Stop counters(0)
 899          * Bit 1 = Load the shadow counters(1)
 900          */
 901         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
 902
 903         /* Read register values to get any >32bit overflow */
 904         tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
 905         cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
 906         cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
 907
 908         /* Get the values and add the overflow */
 909         *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
 910         *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
 911 }
 912
 913 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
 914                                  uint64_t *count1)
 915 {
 916         uint32_t perfctr = 0;
 917         uint64_t cnt0_of, cnt1_of;
 918         int tmp;
 919
 920         /* This reports 0 on APUs, so return to avoid writing/reading registers
 921          * that may or may not be different from their GPU counterparts
 922          */
 923         if (adev->flags & AMD_IS_APU)
 924                 return;
 925
 926         /* Set the 2 events that we wish to watch, defined above */
 927         /* Reg 40 is # received msgs */
 928         /* Reg 108 is # of posted requests sent on VG20 */
 929         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
 930                                 EVENT0_SEL, 40);
 931         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
 932                                 EVENT1_SEL, 108);
 933
 934         /* Write to enable desired perf counters */
 935         WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr);
 936         /* Zero out and enable the perf counters
 937          * Write 0x5:
 938          * Bit 0 = Start all counters(1)
 939          * Bit 2 = Global counter reset enable(1)
 940          */
 941         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
 942
 943         msleep(1000);
 944
 945         /* Load the shadow and disable the perf counters
 946          * Write 0x2:
 947          * Bit 0 = Stop counters(0)
 948          * Bit 1 = Load the shadow counters(1)
 949          */
 950         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
 951
 952         /* Read register values to get any >32bit overflow */
 953         tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3);
 954         cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER);
 955         cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER);
 956
 957         /* Get the values and add the overflow */
 958         *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32);
 959         *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32);
 960 }
 961
 962 static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
 963 {
 964         u32 sol_reg;
 965
 966         /* Just return false for soc15 GPUs.  Reset does not seem to
 967          * be necessary.
 968          */
 969         if (!amdgpu_passthrough(adev))
 970                 return false;
 971
 972         if (adev->flags & AMD_IS_APU)
 973                 return false;
 974
 975         /* Check sOS sign of life register to confirm sys driver and sOS
 976          * are already been loaded.
 977          */
 978         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 979         if (sol_reg)
 980                 return true;
 981
 982         return false;
 983 }
 984
 985 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
 986 {
 987         uint64_t nak_r, nak_g;
 988
 989         /* Get the number of NAKs received and generated */
 990         nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
 991         nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
 992
 993         /* Add the total number of NAKs, i.e the number of replays */
 994         return (nak_r + nak_g);
 995 }
 996
 997 static void soc15_pre_asic_init(struct amdgpu_device *adev)
 998 {
 999         gmc_v9_0_restore_registers(adev);
1000 }
1001
1002 static const struct amdgpu_asic_funcs soc15_asic_funcs =
1003 {
1004         .read_disabled_bios = &soc15_read_disabled_bios,
1005         .read_bios_from_rom = &soc15_read_bios_from_rom,
1006         .read_register = &soc15_read_register,
1007         .reset = &soc15_asic_reset,
1008         .reset_method = &soc15_asic_reset_method,
1009         .set_vga_state = &soc15_vga_set_state,
1010         .get_xclk = &soc15_get_xclk,
1011         .set_uvd_clocks = &soc15_set_uvd_clocks,
1012         .set_vce_clocks = &soc15_set_vce_clocks,
1013         .get_config_memsize = &soc15_get_config_memsize,
1014         .flush_hdp = &soc15_flush_hdp,
1015         .invalidate_hdp = &soc15_invalidate_hdp,
1016         .need_full_reset = &soc15_need_full_reset,
1017         .init_doorbell_index = &vega10_doorbell_index_init,
1018         .get_pcie_usage = &soc15_get_pcie_usage,
1019         .need_reset_on_init = &soc15_need_reset_on_init,
1020         .get_pcie_replay_count = &soc15_get_pcie_replay_count,
1021         .supports_baco = &soc15_supports_baco,
1022         .pre_asic_init = &soc15_pre_asic_init,
1023 };
1024
1025 static const struct amdgpu_asic_funcs vega20_asic_funcs =
1026 {
1027         .read_disabled_bios = &soc15_read_disabled_bios,
1028         .read_bios_from_rom = &soc15_read_bios_from_rom,
1029         .read_register = &soc15_read_register,
1030         .reset = &soc15_asic_reset,
1031         .reset_method = &soc15_asic_reset_method,
1032         .set_vga_state = &soc15_vga_set_state,
1033         .get_xclk = &soc15_get_xclk,
1034         .set_uvd_clocks = &soc15_set_uvd_clocks,
1035         .set_vce_clocks = &soc15_set_vce_clocks,
1036         .get_config_memsize = &soc15_get_config_memsize,
1037         .flush_hdp = &soc15_flush_hdp,
1038         .invalidate_hdp = &soc15_invalidate_hdp,
1039         .reset_hdp_ras_error_count = &vega20_reset_hdp_ras_error_count,
1040         .need_full_reset = &soc15_need_full_reset,
1041         .init_doorbell_index = &vega20_doorbell_index_init,
1042         .get_pcie_usage = &vega20_get_pcie_usage,
1043         .need_reset_on_init = &soc15_need_reset_on_init,
1044         .get_pcie_replay_count = &soc15_get_pcie_replay_count,
1045         .supports_baco = &soc15_supports_baco,
1046         .pre_asic_init = &soc15_pre_asic_init,
1047 };
1048
1049 static int soc15_common_early_init(void *handle)
1050 {
1051 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
1052         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1053
1054         adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
1055         adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
1056         adev->smc_rreg = NULL;
1057         adev->smc_wreg = NULL;
1058         adev->pcie_rreg = &soc15_pcie_rreg;
1059         adev->pcie_wreg = &soc15_pcie_wreg;
1060         adev->pcie_rreg64 = &soc15_pcie_rreg64;
1061         adev->pcie_wreg64 = &soc15_pcie_wreg64;
1062         adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
1063         adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
1064         adev->didt_rreg = &soc15_didt_rreg;
1065         adev->didt_wreg = &soc15_didt_wreg;
1066         adev->gc_cac_rreg = &soc15_gc_cac_rreg;
1067         adev->gc_cac_wreg = &soc15_gc_cac_wreg;
1068         adev->se_cac_rreg = &soc15_se_cac_rreg;
1069         adev->se_cac_wreg = &soc15_se_cac_wreg;
1070
1071
1072         adev->external_rev_id = 0xFF;
1073         switch (adev->asic_type) {
1074         case CHIP_VEGA10:
1075                 adev->asic_funcs = &soc15_asic_funcs;
1076                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1077                         AMD_CG_SUPPORT_GFX_MGLS |
1078                         AMD_CG_SUPPORT_GFX_RLC_LS |
1079                         AMD_CG_SUPPORT_GFX_CP_LS |
1080                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1081                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1082                         AMD_CG_SUPPORT_GFX_CGCG |
1083                         AMD_CG_SUPPORT_GFX_CGLS |
1084                         AMD_CG_SUPPORT_BIF_MGCG |
1085                         AMD_CG_SUPPORT_BIF_LS |
1086                         AMD_CG_SUPPORT_HDP_LS |
1087                         AMD_CG_SUPPORT_DRM_MGCG |
1088                         AMD_CG_SUPPORT_DRM_LS |
1089                         AMD_CG_SUPPORT_ROM_MGCG |
1090                         AMD_CG_SUPPORT_DF_MGCG |
1091                         AMD_CG_SUPPORT_SDMA_MGCG |
1092                         AMD_CG_SUPPORT_SDMA_LS |
1093                         AMD_CG_SUPPORT_MC_MGCG |
1094                         AMD_CG_SUPPORT_MC_LS;
1095                 adev->pg_flags = 0;
1096                 adev->external_rev_id = 0x1;
1097                 break;
1098         case CHIP_VEGA12:
1099                 adev->asic_funcs = &soc15_asic_funcs;
1100                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1101                         AMD_CG_SUPPORT_GFX_MGLS |
1102                         AMD_CG_SUPPORT_GFX_CGCG |
1103                         AMD_CG_SUPPORT_GFX_CGLS |
1104                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1105                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1106                         AMD_CG_SUPPORT_GFX_CP_LS |
1107                         AMD_CG_SUPPORT_MC_LS |
1108                         AMD_CG_SUPPORT_MC_MGCG |
1109                         AMD_CG_SUPPORT_SDMA_MGCG |
1110                         AMD_CG_SUPPORT_SDMA_LS |
1111                         AMD_CG_SUPPORT_BIF_MGCG |
1112                         AMD_CG_SUPPORT_BIF_LS |
1113                         AMD_CG_SUPPORT_HDP_MGCG |
1114                         AMD_CG_SUPPORT_HDP_LS |
1115                         AMD_CG_SUPPORT_ROM_MGCG |
1116                         AMD_CG_SUPPORT_VCE_MGCG |
1117                         AMD_CG_SUPPORT_UVD_MGCG;
1118                 adev->pg_flags = 0;
1119                 adev->external_rev_id = adev->rev_id + 0x14;
1120                 break;
1121         case CHIP_VEGA20:
1122                 adev->asic_funcs = &vega20_asic_funcs;
1123                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1124                         AMD_CG_SUPPORT_GFX_MGLS |
1125                         AMD_CG_SUPPORT_GFX_CGCG |
1126                         AMD_CG_SUPPORT_GFX_CGLS |
1127                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1128                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1129                         AMD_CG_SUPPORT_GFX_CP_LS |
1130                         AMD_CG_SUPPORT_MC_LS |
1131                         AMD_CG_SUPPORT_MC_MGCG |
1132                         AMD_CG_SUPPORT_SDMA_MGCG |
1133                         AMD_CG_SUPPORT_SDMA_LS |
1134                         AMD_CG_SUPPORT_BIF_MGCG |
1135                         AMD_CG_SUPPORT_BIF_LS |
1136                         AMD_CG_SUPPORT_HDP_MGCG |
1137                         AMD_CG_SUPPORT_HDP_LS |
1138                         AMD_CG_SUPPORT_ROM_MGCG |
1139                         AMD_CG_SUPPORT_VCE_MGCG |
1140                         AMD_CG_SUPPORT_UVD_MGCG;
1141                 adev->pg_flags = 0;
1142                 adev->external_rev_id = adev->rev_id + 0x28;
1143                 break;
1144         case CHIP_RAVEN:
1145                 adev->asic_funcs = &soc15_asic_funcs;
1146                 if (adev->pdev->device == 0x15dd)
1147                         adev->apu_flags |= AMD_APU_IS_RAVEN;
1148                 if (adev->pdev->device == 0x15d8)
1149                         adev->apu_flags |= AMD_APU_IS_PICASSO;
1150                 if (adev->rev_id >= 0x8)
1151                         adev->apu_flags |= AMD_APU_IS_RAVEN2;
1152
1153                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1154                         adev->external_rev_id = adev->rev_id + 0x79;
1155                 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1156                         adev->external_rev_id = adev->rev_id + 0x41;
1157                 else if (adev->rev_id == 1)
1158                         adev->external_rev_id = adev->rev_id + 0x20;
1159                 else
1160                         adev->external_rev_id = adev->rev_id + 0x01;
1161
1162                 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
1163                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1164                                 AMD_CG_SUPPORT_GFX_MGLS |
1165                                 AMD_CG_SUPPORT_GFX_CP_LS |
1166                                 AMD_CG_SUPPORT_GFX_3D_CGCG |
1167                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
1168                                 AMD_CG_SUPPORT_GFX_CGCG |
1169                                 AMD_CG_SUPPORT_GFX_CGLS |
1170                                 AMD_CG_SUPPORT_BIF_LS |
1171                                 AMD_CG_SUPPORT_HDP_LS |
1172                                 AMD_CG_SUPPORT_MC_MGCG |
1173                                 AMD_CG_SUPPORT_MC_LS |
1174                                 AMD_CG_SUPPORT_SDMA_MGCG |
1175                                 AMD_CG_SUPPORT_SDMA_LS |
1176                                 AMD_CG_SUPPORT_VCN_MGCG;
1177
1178                         adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1179                 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) {
1180                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1181                                 AMD_CG_SUPPORT_GFX_MGLS |
1182                                 AMD_CG_SUPPORT_GFX_CP_LS |
1183                                 AMD_CG_SUPPORT_GFX_3D_CGCG |
1184                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
1185                                 AMD_CG_SUPPORT_GFX_CGCG |
1186                                 AMD_CG_SUPPORT_GFX_CGLS |
1187                                 AMD_CG_SUPPORT_BIF_LS |
1188                                 AMD_CG_SUPPORT_HDP_LS |
1189                                 AMD_CG_SUPPORT_MC_MGCG |
1190                                 AMD_CG_SUPPORT_MC_LS |
1191                                 AMD_CG_SUPPORT_SDMA_MGCG |
1192                                 AMD_CG_SUPPORT_SDMA_LS;
1193
1194                         adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1195                                 AMD_PG_SUPPORT_MMHUB |
1196                                 AMD_PG_SUPPORT_VCN;
1197                 } else {
1198                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1199                                 AMD_CG_SUPPORT_GFX_MGLS |
1200                                 AMD_CG_SUPPORT_GFX_RLC_LS |
1201                                 AMD_CG_SUPPORT_GFX_CP_LS |
1202                                 AMD_CG_SUPPORT_GFX_3D_CGCG |
1203                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
1204                                 AMD_CG_SUPPORT_GFX_CGCG |
1205                                 AMD_CG_SUPPORT_GFX_CGLS |
1206                                 AMD_CG_SUPPORT_BIF_MGCG |
1207                                 AMD_CG_SUPPORT_BIF_LS |
1208                                 AMD_CG_SUPPORT_HDP_MGCG |
1209                                 AMD_CG_SUPPORT_HDP_LS |
1210                                 AMD_CG_SUPPORT_DRM_MGCG |
1211                                 AMD_CG_SUPPORT_DRM_LS |
1212                                 AMD_CG_SUPPORT_MC_MGCG |
1213                                 AMD_CG_SUPPORT_MC_LS |
1214                                 AMD_CG_SUPPORT_SDMA_MGCG |
1215                                 AMD_CG_SUPPORT_SDMA_LS |
1216                                 AMD_CG_SUPPORT_VCN_MGCG;
1217
1218                         adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1219                 }
1220                 break;
1221         case CHIP_ARCTURUS:
1222                 adev->asic_funcs = &vega20_asic_funcs;
1223                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1224                         AMD_CG_SUPPORT_GFX_MGLS |
1225                         AMD_CG_SUPPORT_GFX_CGCG |
1226                         AMD_CG_SUPPORT_GFX_CGLS |
1227                         AMD_CG_SUPPORT_GFX_CP_LS |
1228                         AMD_CG_SUPPORT_HDP_MGCG |
1229                         AMD_CG_SUPPORT_HDP_LS |
1230                         AMD_CG_SUPPORT_SDMA_MGCG |
1231                         AMD_CG_SUPPORT_SDMA_LS |
1232                         AMD_CG_SUPPORT_MC_MGCG |
1233                         AMD_CG_SUPPORT_MC_LS |
1234                         AMD_CG_SUPPORT_IH_CG |
1235                         AMD_CG_SUPPORT_VCN_MGCG |
1236                         AMD_CG_SUPPORT_JPEG_MGCG;
1237                 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG;
1238                 adev->external_rev_id = adev->rev_id + 0x32;
1239                 break;
1240         case CHIP_RENOIR:
1241                 adev->asic_funcs = &soc15_asic_funcs;
1242                 if (adev->pdev->device == 0x1636)
1243                         adev->apu_flags |= AMD_APU_IS_RENOIR;
1244                 else
1245                         adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE;
1246
1247                 if (adev->apu_flags & AMD_APU_IS_RENOIR)
1248                         adev->external_rev_id = adev->rev_id + 0x91;
1249                 else
1250                         adev->external_rev_id = adev->rev_id + 0xa1;
1251                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1252                                  AMD_CG_SUPPORT_GFX_MGLS |
1253                                  AMD_CG_SUPPORT_GFX_3D_CGCG |
1254                                  AMD_CG_SUPPORT_GFX_3D_CGLS |
1255                                  AMD_CG_SUPPORT_GFX_CGCG |
1256                                  AMD_CG_SUPPORT_GFX_CGLS |
1257                                  AMD_CG_SUPPORT_GFX_CP_LS |
1258                                  AMD_CG_SUPPORT_MC_MGCG |
1259                                  AMD_CG_SUPPORT_MC_LS |
1260                                  AMD_CG_SUPPORT_SDMA_MGCG |
1261                                  AMD_CG_SUPPORT_SDMA_LS |
1262                                  AMD_CG_SUPPORT_BIF_LS |
1263                                  AMD_CG_SUPPORT_HDP_LS |
1264                                  AMD_CG_SUPPORT_VCN_MGCG |
1265                                  AMD_CG_SUPPORT_JPEG_MGCG |
1266                                  AMD_CG_SUPPORT_IH_CG |
1267                                  AMD_CG_SUPPORT_ATHUB_LS |
1268                                  AMD_CG_SUPPORT_ATHUB_MGCG |
1269                                  AMD_CG_SUPPORT_DF_MGCG;
1270                 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1271                                  AMD_PG_SUPPORT_VCN |
1272                                  AMD_PG_SUPPORT_JPEG |
1273                                  AMD_PG_SUPPORT_VCN_DPG;
1274                 break;
1275         default:
1276                 /* FIXME: not supported yet */
1277                 return -EINVAL;
1278         }
1279
1280         if (amdgpu_sriov_vf(adev)) {
1281                 amdgpu_virt_init_setting(adev);
1282                 xgpu_ai_mailbox_set_irq_funcs(adev);
1283         }
1284
1285         return 0;
1286 }
1287
1288 static int soc15_common_late_init(void *handle)
1289 {
1290         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1291         int r = 0;
1292
1293         if (amdgpu_sriov_vf(adev))
1294                 xgpu_ai_mailbox_get_irq(adev);
1295
1296         if (adev->asic_funcs &&
1297             adev->asic_funcs->reset_hdp_ras_error_count)
1298                 adev->asic_funcs->reset_hdp_ras_error_count(adev);
1299
1300         if (adev->nbio.funcs->ras_late_init)
1301                 r = adev->nbio.funcs->ras_late_init(adev);
1302
1303         return r;
1304 }
1305
1306 static int soc15_common_sw_init(void *handle)
1307 {
1308         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1309
1310         if (amdgpu_sriov_vf(adev))
1311                 xgpu_ai_mailbox_add_irq_id(adev);
1312
1313         adev->df.funcs->sw_init(adev);
1314
1315         return 0;
1316 }
1317
1318 static int soc15_common_sw_fini(void *handle)
1319 {
1320         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1321
1322         amdgpu_nbio_ras_fini(adev);
1323         adev->df.funcs->sw_fini(adev);
1324         return 0;
1325 }
1326
1327 static void soc15_doorbell_range_init(struct amdgpu_device *adev)
1328 {
1329         int i;
1330         struct amdgpu_ring *ring;
1331
1332         /* sdma/ih doorbell range are programed by hypervisor */
1333         if (!amdgpu_sriov_vf(adev)) {
1334                 for (i = 0; i < adev->sdma.num_instances; i++) {
1335                         ring = &adev->sdma.instance[i].ring;
1336                         adev->nbio.funcs->sdma_doorbell_range(adev, i,
1337                                 ring->use_doorbell, ring->doorbell_index,
1338                                 adev->doorbell_index.sdma_doorbell_range);
1339                 }
1340
1341                 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
1342                                                 adev->irq.ih.doorbell_index);
1343         }
1344 }
1345
1346 static int soc15_common_hw_init(void *handle)
1347 {
1348         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1349
1350         /* enable pcie gen2/3 link */
1351         soc15_pcie_gen3_enable(adev);
1352         /* enable aspm */
1353         soc15_program_aspm(adev);
1354         /* setup nbio registers */
1355         adev->nbio.funcs->init_registers(adev);
1356         /* remap HDP registers to a hole in mmio space,
1357          * for the purpose of expose those registers
1358          * to process space
1359          */
1360         if (adev->nbio.funcs->remap_hdp_registers)
1361                 adev->nbio.funcs->remap_hdp_registers(adev);
1362
1363         /* enable the doorbell aperture */
1364         soc15_enable_doorbell_aperture(adev, true);
1365         /* HW doorbell routing policy: doorbell writing not
1366          * in SDMA/IH/MM/ACV range will be routed to CP. So
1367          * we need to init SDMA/IH/MM/ACV doorbell range prior
1368          * to CP ip block init and ring test.
1369          */
1370         soc15_doorbell_range_init(adev);
1371
1372         return 0;
1373 }
1374
1375 static int soc15_common_hw_fini(void *handle)
1376 {
1377         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1378
1379         /* disable the doorbell aperture */
1380         soc15_enable_doorbell_aperture(adev, false);
1381         if (amdgpu_sriov_vf(adev))
1382                 xgpu_ai_mailbox_put_irq(adev);
1383
1384         if (adev->nbio.ras_if &&
1385             amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
1386                 if (adev->nbio.funcs->init_ras_controller_interrupt)
1387                         amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);
1388                 if (adev->nbio.funcs->init_ras_err_event_athub_interrupt)
1389                         amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
1390         }
1391
1392         return 0;
1393 }
1394
1395 static int soc15_common_suspend(void *handle)
1396 {
1397         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1398
1399         return soc15_common_hw_fini(adev);
1400 }
1401
1402 static int soc15_common_resume(void *handle)
1403 {
1404         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1405
1406         return soc15_common_hw_init(adev);
1407 }
1408
1409 static bool soc15_common_is_idle(void *handle)
1410 {
1411         return true;
1412 }
1413
1414 static int soc15_common_wait_for_idle(void *handle)
1415 {
1416         return 0;
1417 }
1418
1419 static int soc15_common_soft_reset(void *handle)
1420 {
1421         return 0;
1422 }
1423
1424 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
1425 {
1426         uint32_t def, data;
1427
1428         if (adev->asic_type == CHIP_VEGA20 ||
1429                 adev->asic_type == CHIP_ARCTURUS ||
1430                 adev->asic_type == CHIP_RENOIR) {
1431                 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
1432
1433                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1434                         data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1435                                 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1436                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1437                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
1438                 else
1439                         data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1440                                 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1441                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1442                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
1443
1444                 if (def != data)
1445                         WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
1446         } else {
1447                 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1448
1449                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1450                         data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1451                 else
1452                         data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1453
1454                 if (def != data)
1455                         WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
1456         }
1457 }
1458
1459 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1460 {
1461         uint32_t def, data;
1462
1463         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1464
1465         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1466                 data &= ~(0x01000000 |
1467                           0x02000000 |
1468                           0x04000000 |
1469                           0x08000000 |
1470                           0x10000000 |
1471                           0x20000000 |
1472                           0x40000000 |
1473                           0x80000000);
1474         else
1475                 data |= (0x01000000 |
1476                          0x02000000 |
1477                          0x04000000 |
1478                          0x08000000 |
1479                          0x10000000 |
1480                          0x20000000 |
1481                          0x40000000 |
1482                          0x80000000);
1483
1484         if (def != data)
1485                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1486 }
1487
1488 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1489 {
1490         uint32_t def, data;
1491
1492         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1493
1494         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1495                 data |= 1;
1496         else
1497                 data &= ~1;
1498
1499         if (def != data)
1500                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1501 }
1502
1503 static int soc15_common_set_clockgating_state(void *handle,
1504                                             enum amd_clockgating_state state)
1505 {
1506         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1507
1508         if (amdgpu_sriov_vf(adev))
1509                 return 0;
1510
1511         switch (adev->asic_type) {
1512         case CHIP_VEGA10:
1513         case CHIP_VEGA12:
1514         case CHIP_VEGA20:
1515                 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1516                                 state == AMD_CG_STATE_GATE);
1517                 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1518                                 state == AMD_CG_STATE_GATE);
1519                 soc15_update_hdp_light_sleep(adev,
1520                                 state == AMD_CG_STATE_GATE);
1521                 soc15_update_drm_clock_gating(adev,
1522                                 state == AMD_CG_STATE_GATE);
1523                 soc15_update_drm_light_sleep(adev,
1524                                 state == AMD_CG_STATE_GATE);
1525                 adev->smuio.funcs->update_rom_clock_gating(adev,
1526                                 state == AMD_CG_STATE_GATE);
1527                 adev->df.funcs->update_medium_grain_clock_gating(adev,
1528                                 state == AMD_CG_STATE_GATE);
1529                 break;
1530         case CHIP_RAVEN:
1531         case CHIP_RENOIR:
1532                 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1533                                 state == AMD_CG_STATE_GATE);
1534                 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1535                                 state == AMD_CG_STATE_GATE);
1536                 soc15_update_hdp_light_sleep(adev,
1537                                 state == AMD_CG_STATE_GATE);
1538                 soc15_update_drm_clock_gating(adev,
1539                                 state == AMD_CG_STATE_GATE);
1540                 soc15_update_drm_light_sleep(adev,
1541                                 state == AMD_CG_STATE_GATE);
1542                 break;
1543         case CHIP_ARCTURUS:
1544                 soc15_update_hdp_light_sleep(adev,
1545                                 state == AMD_CG_STATE_GATE);
1546                 break;
1547         default:
1548                 break;
1549         }
1550         return 0;
1551 }
1552
1553 static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
1554 {
1555         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1556         int data;
1557
1558         if (amdgpu_sriov_vf(adev))
1559                 *flags = 0;
1560
1561         adev->nbio.funcs->get_clockgating_state(adev, flags);
1562
1563         /* AMD_CG_SUPPORT_HDP_LS */
1564         data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1565         if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1566                 *flags |= AMD_CG_SUPPORT_HDP_LS;
1567
1568         /* AMD_CG_SUPPORT_DRM_MGCG */
1569         data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1570         if (!(data & 0x01000000))
1571                 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1572
1573         /* AMD_CG_SUPPORT_DRM_LS */
1574         data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1575         if (data & 0x1)
1576                 *flags |= AMD_CG_SUPPORT_DRM_LS;
1577
1578         /* AMD_CG_SUPPORT_ROM_MGCG */
1579         adev->smuio.funcs->get_clock_gating_state(adev, flags);
1580
1581         adev->df.funcs->get_clockgating_state(adev, flags);
1582 }
1583
1584 static int soc15_common_set_powergating_state(void *handle,
1585                                             enum amd_powergating_state state)
1586 {
1587         /* todo */
1588         return 0;
1589 }
1590
1591 const struct amd_ip_funcs soc15_common_ip_funcs = {
1592         .name = "soc15_common",
1593         .early_init = soc15_common_early_init,
1594         .late_init = soc15_common_late_init,
1595         .sw_init = soc15_common_sw_init,
1596         .sw_fini = soc15_common_sw_fini,
1597         .hw_init = soc15_common_hw_init,
1598         .hw_fini = soc15_common_hw_fini,
1599         .suspend = soc15_common_suspend,
1600         .resume = soc15_common_resume,
1601         .is_idle = soc15_common_is_idle,
1602         .wait_for_idle = soc15_common_wait_for_idle,
1603         .soft_reset = soc15_common_soft_reset,
1604         .set_clockgating_state = soc15_common_set_clockgating_state,
1605         .set_powergating_state = soc15_common_set_powergating_state,
1606         .get_clockgating_state= soc15_common_get_clockgating_state,
1607 };