drivers/gpu/drm/amd/amdgpu/soc15.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <drm/drmP.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_atombios.h"
  29 #include "amdgpu_ih.h"
  30 #include "amdgpu_uvd.h"
  31 #include "amdgpu_vce.h"
  32 #include "amdgpu_ucode.h"
  33 #include "amdgpu_psp.h"
  34 #include "atom.h"
  35 #include "amd_pcie.h"
  36
  37 #include "uvd/uvd_7_0_offset.h"
  38 #include "gc/gc_9_0_offset.h"
  39 #include "gc/gc_9_0_sh_mask.h"
  40 #include "sdma0/sdma0_4_0_offset.h"
  41 #include "sdma1/sdma1_4_0_offset.h"
  42 #include "hdp/hdp_4_0_offset.h"
  43 #include "hdp/hdp_4_0_sh_mask.h"
  44 #include "mp/mp_9_0_offset.h"
  45 #include "mp/mp_9_0_sh_mask.h"
  46 #include "smuio/smuio_9_0_offset.h"
  47 #include "smuio/smuio_9_0_sh_mask.h"
  48
  49 #include "soc15.h"
  50 #include "soc15_common.h"
  51 #include "gfx_v9_0.h"
  52 #include "gmc_v9_0.h"
  53 #include "gfxhub_v1_0.h"
  54 #include "mmhub_v1_0.h"
  55 #include "vega10_ih.h"
  56 #include "sdma_v4_0.h"
  57 #include "uvd_v7_0.h"
  58 #include "vce_v4_0.h"
  59 #include "vcn_v1_0.h"
  60 #include "dce_virtual.h"
  61 #include "mxgpu_ai.h"
  62
  63 #define mmFabricConfigAccessControl                                                                    0x0410
  64 #define mmFabricConfigAccessControl_BASE_IDX                                                           0
  65 #define mmFabricConfigAccessControl_DEFAULT                                      0x00000000
  66 //FabricConfigAccessControl
  67 #define FabricConfigAccessControl__CfgRegInstAccEn__SHIFT                                                     0x0
  68 #define FabricConfigAccessControl__CfgRegInstAccRegLock__SHIFT                                                0x1
  69 #define FabricConfigAccessControl__CfgRegInstID__SHIFT                                                        0x10
  70 #define FabricConfigAccessControl__CfgRegInstAccEn_MASK                                                       0x00000001L
  71 #define FabricConfigAccessControl__CfgRegInstAccRegLock_MASK                                                  0x00000002L
  72 #define FabricConfigAccessControl__CfgRegInstID_MASK                                                          0x00FF0000L
  73
  74
  75 #define mmDF_PIE_AON0_DfGlobalClkGater                                                                 0x00fc
  76 #define mmDF_PIE_AON0_DfGlobalClkGater_BASE_IDX                                                        0
  77 //DF_PIE_AON0_DfGlobalClkGater
  78 #define DF_PIE_AON0_DfGlobalClkGater__MGCGMode__SHIFT                                                         0x0
  79 #define DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK                                                           0x0000000FL
  80
  81 enum {
  82         DF_MGCG_DISABLE = 0,
  83         DF_MGCG_ENABLE_00_CYCLE_DELAY =1,
  84         DF_MGCG_ENABLE_01_CYCLE_DELAY =2,
  85         DF_MGCG_ENABLE_15_CYCLE_DELAY =13,
  86         DF_MGCG_ENABLE_31_CYCLE_DELAY =14,
  87         DF_MGCG_ENABLE_63_CYCLE_DELAY =15
  88 };
  89
  90 #define mmMP0_MISC_CGTT_CTRL0                                                                   0x01b9
  91 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX                                                          0
  92 #define mmMP0_MISC_LIGHT_SLEEP_CTRL                                                             0x01ba
  93 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX                                                    0
  94
  95 /*
  96  * Indirect registers accessor
  97  */
  98 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
  99 {
 100         unsigned long flags, address, data;
 101         u32 r;
 102         address = adev->nbio_funcs->get_pcie_index_offset(adev);
 103         data = adev->nbio_funcs->get_pcie_data_offset(adev);
 104
 105         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 106         WREG32(address, reg);
 107         (void)RREG32(address);
 108         r = RREG32(data);
 109         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 110         return r;
 111 }
 112
 113 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 114 {
 115         unsigned long flags, address, data;
 116
 117         address = adev->nbio_funcs->get_pcie_index_offset(adev);
 118         data = adev->nbio_funcs->get_pcie_data_offset(adev);
 119
 120         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 121         WREG32(address, reg);
 122         (void)RREG32(address);
 123         WREG32(data, v);
 124         (void)RREG32(data);
 125         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 126 }
 127
 128 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
 129 {
 130         unsigned long flags, address, data;
 131         u32 r;
 132
 133         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 134         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 135
 136         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 137         WREG32(address, ((reg) & 0x1ff));
 138         r = RREG32(data);
 139         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 140         return r;
 141 }
 142
 143 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 144 {
 145         unsigned long flags, address, data;
 146
 147         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 148         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 149
 150         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 151         WREG32(address, ((reg) & 0x1ff));
 152         WREG32(data, (v));
 153         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 154 }
 155
 156 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
 157 {
 158         unsigned long flags, address, data;
 159         u32 r;
 160
 161         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 162         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 163
 164         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 165         WREG32(address, (reg));
 166         r = RREG32(data);
 167         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 168         return r;
 169 }
 170
 171 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 172 {
 173         unsigned long flags, address, data;
 174
 175         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 176         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 177
 178         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 179         WREG32(address, (reg));
 180         WREG32(data, (v));
 181         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 182 }
 183
 184 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
 185 {
 186         unsigned long flags;
 187         u32 r;
 188
 189         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 190         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
 191         r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
 192         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 193         return r;
 194 }
 195
 196 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 197 {
 198         unsigned long flags;
 199
 200         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 201         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
 202         WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
 203         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 204 }
 205
 206 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
 207 {
 208         unsigned long flags;
 209         u32 r;
 210
 211         spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
 212         WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
 213         r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
 214         spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
 215         return r;
 216 }
 217
 218 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 219 {
 220         unsigned long flags;
 221
 222         spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
 223         WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
 224         WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
 225         spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
 226 }
 227
 228 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
 229 {
 230         return adev->nbio_funcs->get_memsize(adev);
 231 }
 232
 233 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 234 {
 235         return adev->clock.spll.reference_freq;
 236 }
 237
 238
 239 void soc15_grbm_select(struct amdgpu_device *adev,
 240                      u32 me, u32 pipe, u32 queue, u32 vmid)
 241 {
 242         u32 grbm_gfx_cntl = 0;
 243         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 244         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 245         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 246         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 247
 248         WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
 249 }
 250
 251 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
 252 {
 253         /* todo */
 254 }
 255
 256 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
 257 {
 258         /* todo */
 259         return false;
 260 }
 261
 262 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
 263                                      u8 *bios, u32 length_bytes)
 264 {
 265         u32 *dw_ptr;
 266         u32 i, length_dw;
 267
 268         if (bios == NULL)
 269                 return false;
 270         if (length_bytes == 0)
 271                 return false;
 272         /* APU vbios image is part of sbios image */
 273         if (adev->flags & AMD_IS_APU)
 274                 return false;
 275
 276         dw_ptr = (u32 *)bios;
 277         length_dw = ALIGN(length_bytes, 4) / 4;
 278
 279         /* set rom index to 0 */
 280         WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
 281         /* read out the rom data */
 282         for (i = 0; i < length_dw; i++)
 283                 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
 284
 285         return true;
 286 }
 287
 288 struct soc15_allowed_register_entry {
 289         uint32_t hwip;
 290         uint32_t inst;
 291         uint32_t seg;
 292         uint32_t reg_offset;
 293         bool grbm_indexed;
 294 };
 295
 296
 297 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
 298         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 299         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
 300         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
 301         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
 302         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
 303         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
 304         { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
 305         { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
 306         { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
 307         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
 308         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
 309         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
 310         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
 311         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
 312         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
 313         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 314         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 315         { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 316 };
 317
 318 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 319                                          u32 sh_num, u32 reg_offset)
 320 {
 321         uint32_t val;
 322
 323         mutex_lock(&adev->grbm_idx_mutex);
 324         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 325                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 326
 327         val = RREG32(reg_offset);
 328
 329         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 330                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 331         mutex_unlock(&adev->grbm_idx_mutex);
 332         return val;
 333 }
 334
 335 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
 336                                          bool indexed, u32 se_num,
 337                                          u32 sh_num, u32 reg_offset)
 338 {
 339         if (indexed) {
 340                 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
 341         } else {
 342                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 343                         return adev->gfx.config.gb_addr_config;
 344                 return RREG32(reg_offset);
 345         }
 346 }
 347
 348 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
 349                             u32 sh_num, u32 reg_offset, u32 *value)
 350 {
 351         uint32_t i;
 352         struct soc15_allowed_register_entry  *en;
 353
 354         *value = 0;
 355         for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
 356                 en = &soc15_allowed_read_registers[i];
 357                 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
 358                                         + en->reg_offset))
 359                         continue;
 360
 361                 *value = soc15_get_register_value(adev,
 362                                                   soc15_allowed_read_registers[i].grbm_indexed,
 363                                                   se_num, sh_num, reg_offset);
 364                 return 0;
 365         }
 366         return -EINVAL;
 367 }
 368
 369
 370 /**
 371  * soc15_program_register_sequence - program an array of registers.
 372  *
 373  * @adev: amdgpu_device pointer
 374  * @regs: pointer to the register array
 375  * @array_size: size of the register array
 376  *
 377  * Programs an array or registers with and and or masks.
 378  * This is a helper for setting golden registers.
 379  */
 380
 381 void soc15_program_register_sequence(struct amdgpu_device *adev,
 382                                              const struct soc15_reg_golden *regs,
 383                                              const u32 array_size)
 384 {
 385         const struct soc15_reg_golden *entry;
 386         u32 tmp, reg;
 387         int i;
 388
 389         for (i = 0; i < array_size; ++i) {
 390                 entry = &regs[i];
 391                 reg =  adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
 392
 393                 if (entry->and_mask == 0xffffffff) {
 394                         tmp = entry->or_mask;
 395                 } else {
 396                         tmp = RREG32(reg);
 397                         tmp &= ~(entry->and_mask);
 398                         tmp |= entry->or_mask;
 399                 }
 400                 WREG32(reg, tmp);
 401         }
 402
 403 }
 404
 405
 406 static int soc15_asic_reset(struct amdgpu_device *adev)
 407 {
 408         u32 i;
 409
 410         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 411
 412         dev_info(adev->dev, "GPU reset\n");
 413
 414         /* disable BM */
 415         pci_clear_master(adev->pdev);
 416
 417         pci_save_state(adev->pdev);
 418
 419         psp_gpu_reset(adev);
 420
 421         pci_restore_state(adev->pdev);
 422
 423         /* wait for asic to come out of reset */
 424         for (i = 0; i < adev->usec_timeout; i++) {
 425                 u32 memsize = adev->nbio_funcs->get_memsize(adev);
 426
 427                 if (memsize != 0xffffffff)
 428                         break;
 429                 udelay(1);
 430         }
 431
 432         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 433
 434         return 0;
 435 }
 436
 437 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
 438                         u32 cntl_reg, u32 status_reg)
 439 {
 440         return 0;
 441 }*/
 442
 443 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 444 {
 445         /*int r;
 446
 447         r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
 448         if (r)
 449                 return r;
 450
 451         r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
 452         */
 453         return 0;
 454 }
 455
 456 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 457 {
 458         /* todo */
 459
 460         return 0;
 461 }
 462
 463 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
 464 {
 465         if (pci_is_root_bus(adev->pdev->bus))
 466                 return;
 467
 468         if (amdgpu_pcie_gen2 == 0)
 469                 return;
 470
 471         if (adev->flags & AMD_IS_APU)
 472                 return;
 473
 474         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 475                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 476                 return;
 477
 478         /* todo */
 479 }
 480
 481 static void soc15_program_aspm(struct amdgpu_device *adev)
 482 {
 483
 484         if (amdgpu_aspm == 0)
 485                 return;
 486
 487         /* todo */
 488 }
 489
 490 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
 491                                            bool enable)
 492 {
 493         adev->nbio_funcs->enable_doorbell_aperture(adev, enable);
 494         adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable);
 495 }
 496
 497 static const struct amdgpu_ip_block_version vega10_common_ip_block =
 498 {
 499         .type = AMD_IP_BLOCK_TYPE_COMMON,
 500         .major = 2,
 501         .minor = 0,
 502         .rev = 0,
 503         .funcs = &soc15_common_ip_funcs,
 504 };
 505
 506 int soc15_set_ip_blocks(struct amdgpu_device *adev)
 507 {
 508         /* Set IP register base before any HW register access */
 509         switch (adev->asic_type) {
 510         case CHIP_VEGA10:
 511         case CHIP_VEGA12:
 512         case CHIP_RAVEN:
 513                 vega10_reg_base_init(adev);
 514                 break;
 515         default:
 516                 return -EINVAL;
 517         }
 518
 519         if (adev->flags & AMD_IS_APU)
 520                 adev->nbio_funcs = &nbio_v7_0_funcs;
 521         else
 522                 adev->nbio_funcs = &nbio_v6_1_funcs;
 523
 524         adev->nbio_funcs->detect_hw_virt(adev);
 525
 526         if (amdgpu_sriov_vf(adev))
 527                 adev->virt.ops = &xgpu_ai_virt_ops;
 528
 529         switch (adev->asic_type) {
 530         case CHIP_VEGA10:
 531         case CHIP_VEGA12:
 532                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 533                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 534                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 535                 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
 536                 if (!amdgpu_sriov_vf(adev))
 537                         amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
 538                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 539                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 540 #if defined(CONFIG_DRM_AMD_DC)
 541                 else if (amdgpu_device_has_dc_support(adev))
 542                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 543 #else
 544 #       warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
 545 #endif
 546                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 547                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 548                 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
 549                 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
 550                 break;
 551         case CHIP_RAVEN:
 552                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 553                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 554                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 555                 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
 556                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
 557                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 558                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 559 #if defined(CONFIG_DRM_AMD_DC)
 560                 else if (amdgpu_device_has_dc_support(adev))
 561                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 562 #else
 563 #       warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
 564 #endif
 565                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 566                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 567                 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
 568                 break;
 569         default:
 570                 return -EINVAL;
 571         }
 572
 573         return 0;
 574 }
 575
 576 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
 577 {
 578         return adev->nbio_funcs->get_rev_id(adev);
 579 }
 580
 581 static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
 582 {
 583         adev->nbio_funcs->hdp_flush(adev, ring);
 584 }
 585
 586 static void soc15_invalidate_hdp(struct amdgpu_device *adev,
 587                                  struct amdgpu_ring *ring)
 588 {
 589         if (!ring || !ring->funcs->emit_wreg)
 590                 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
 591         else
 592                 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
 593                         HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
 594 }
 595
 596 static const struct amdgpu_asic_funcs soc15_asic_funcs =
 597 {
 598         .read_disabled_bios = &soc15_read_disabled_bios,
 599         .read_bios_from_rom = &soc15_read_bios_from_rom,
 600         .read_register = &soc15_read_register,
 601         .reset = &soc15_asic_reset,
 602         .set_vga_state = &soc15_vga_set_state,
 603         .get_xclk = &soc15_get_xclk,
 604         .set_uvd_clocks = &soc15_set_uvd_clocks,
 605         .set_vce_clocks = &soc15_set_vce_clocks,
 606         .get_config_memsize = &soc15_get_config_memsize,
 607         .flush_hdp = &soc15_flush_hdp,
 608         .invalidate_hdp = &soc15_invalidate_hdp,
 609 };
 610
 611 static int soc15_common_early_init(void *handle)
 612 {
 613         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 614
 615         adev->smc_rreg = NULL;
 616         adev->smc_wreg = NULL;
 617         adev->pcie_rreg = &soc15_pcie_rreg;
 618         adev->pcie_wreg = &soc15_pcie_wreg;
 619         adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
 620         adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
 621         adev->didt_rreg = &soc15_didt_rreg;
 622         adev->didt_wreg = &soc15_didt_wreg;
 623         adev->gc_cac_rreg = &soc15_gc_cac_rreg;
 624         adev->gc_cac_wreg = &soc15_gc_cac_wreg;
 625         adev->se_cac_rreg = &soc15_se_cac_rreg;
 626         adev->se_cac_wreg = &soc15_se_cac_wreg;
 627
 628         adev->asic_funcs = &soc15_asic_funcs;
 629
 630         adev->rev_id = soc15_get_rev_id(adev);
 631         adev->external_rev_id = 0xFF;
 632         switch (adev->asic_type) {
 633         case CHIP_VEGA10:
 634                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 635                         AMD_CG_SUPPORT_GFX_MGLS |
 636                         AMD_CG_SUPPORT_GFX_RLC_LS |
 637                         AMD_CG_SUPPORT_GFX_CP_LS |
 638                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 639                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 640                         AMD_CG_SUPPORT_GFX_CGCG |
 641                         AMD_CG_SUPPORT_GFX_CGLS |
 642                         AMD_CG_SUPPORT_BIF_MGCG |
 643                         AMD_CG_SUPPORT_BIF_LS |
 644                         AMD_CG_SUPPORT_HDP_LS |
 645                         AMD_CG_SUPPORT_DRM_MGCG |
 646                         AMD_CG_SUPPORT_DRM_LS |
 647                         AMD_CG_SUPPORT_ROM_MGCG |
 648                         AMD_CG_SUPPORT_DF_MGCG |
 649                         AMD_CG_SUPPORT_SDMA_MGCG |
 650                         AMD_CG_SUPPORT_SDMA_LS |
 651                         AMD_CG_SUPPORT_MC_MGCG |
 652                         AMD_CG_SUPPORT_MC_LS;
 653                 adev->pg_flags = 0;
 654                 adev->external_rev_id = 0x1;
 655                 break;
 656         case CHIP_VEGA12:
 657                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 658                         AMD_CG_SUPPORT_GFX_MGLS |
 659                         AMD_CG_SUPPORT_GFX_CGCG |
 660                         AMD_CG_SUPPORT_GFX_CGLS |
 661                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 662                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 663                         AMD_CG_SUPPORT_GFX_CP_LS |
 664                         AMD_CG_SUPPORT_MC_LS |
 665                         AMD_CG_SUPPORT_MC_MGCG |
 666                         AMD_CG_SUPPORT_SDMA_MGCG |
 667                         AMD_CG_SUPPORT_SDMA_LS |
 668                         AMD_CG_SUPPORT_BIF_MGCG |
 669                         AMD_CG_SUPPORT_BIF_LS |
 670                         AMD_CG_SUPPORT_HDP_MGCG |
 671                         AMD_CG_SUPPORT_HDP_LS |
 672                         AMD_CG_SUPPORT_ROM_MGCG |
 673                         AMD_CG_SUPPORT_VCE_MGCG |
 674                         AMD_CG_SUPPORT_UVD_MGCG;
 675                 adev->pg_flags = 0;
 676                 adev->external_rev_id = adev->rev_id + 0x14;
 677                 break;
 678         case CHIP_RAVEN:
 679                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 680                         AMD_CG_SUPPORT_GFX_MGLS |
 681                         AMD_CG_SUPPORT_GFX_RLC_LS |
 682                         AMD_CG_SUPPORT_GFX_CP_LS |
 683                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 684                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 685                         AMD_CG_SUPPORT_GFX_CGCG |
 686                         AMD_CG_SUPPORT_GFX_CGLS |
 687                         AMD_CG_SUPPORT_BIF_MGCG |
 688                         AMD_CG_SUPPORT_BIF_LS |
 689                         AMD_CG_SUPPORT_HDP_MGCG |
 690                         AMD_CG_SUPPORT_HDP_LS |
 691                         AMD_CG_SUPPORT_DRM_MGCG |
 692                         AMD_CG_SUPPORT_DRM_LS |
 693                         AMD_CG_SUPPORT_ROM_MGCG |
 694                         AMD_CG_SUPPORT_MC_MGCG |
 695                         AMD_CG_SUPPORT_MC_LS |
 696                         AMD_CG_SUPPORT_SDMA_MGCG |
 697                         AMD_CG_SUPPORT_SDMA_LS;
 698                 adev->pg_flags = AMD_PG_SUPPORT_SDMA;
 699
 700                 adev->external_rev_id = 0x1;
 701                 break;
 702         default:
 703                 /* FIXME: not supported yet */
 704                 return -EINVAL;
 705         }
 706
 707         if (amdgpu_sriov_vf(adev)) {
 708                 amdgpu_virt_init_setting(adev);
 709                 xgpu_ai_mailbox_set_irq_funcs(adev);
 710         }
 711
 712         return 0;
 713 }
 714
 715 static int soc15_common_late_init(void *handle)
 716 {
 717         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 718
 719         if (amdgpu_sriov_vf(adev))
 720                 xgpu_ai_mailbox_get_irq(adev);
 721
 722         return 0;
 723 }
 724
 725 static int soc15_common_sw_init(void *handle)
 726 {
 727         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 728
 729         if (amdgpu_sriov_vf(adev))
 730                 xgpu_ai_mailbox_add_irq_id(adev);
 731
 732         return 0;
 733 }
 734
 735 static int soc15_common_sw_fini(void *handle)
 736 {
 737         return 0;
 738 }
 739
 740 static int soc15_common_hw_init(void *handle)
 741 {
 742         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 743
 744         /* enable pcie gen2/3 link */
 745         soc15_pcie_gen3_enable(adev);
 746         /* enable aspm */
 747         soc15_program_aspm(adev);
 748         /* setup nbio registers */
 749         adev->nbio_funcs->init_registers(adev);
 750         /* enable the doorbell aperture */
 751         soc15_enable_doorbell_aperture(adev, true);
 752
 753         return 0;
 754 }
 755
 756 static int soc15_common_hw_fini(void *handle)
 757 {
 758         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 759
 760         /* disable the doorbell aperture */
 761         soc15_enable_doorbell_aperture(adev, false);
 762         if (amdgpu_sriov_vf(adev))
 763                 xgpu_ai_mailbox_put_irq(adev);
 764
 765         return 0;
 766 }
 767
 768 static int soc15_common_suspend(void *handle)
 769 {
 770         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 771
 772         return soc15_common_hw_fini(adev);
 773 }
 774
 775 static int soc15_common_resume(void *handle)
 776 {
 777         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 778
 779         return soc15_common_hw_init(adev);
 780 }
 781
 782 static bool soc15_common_is_idle(void *handle)
 783 {
 784         return true;
 785 }
 786
 787 static int soc15_common_wait_for_idle(void *handle)
 788 {
 789         return 0;
 790 }
 791
 792 static int soc15_common_soft_reset(void *handle)
 793 {
 794         return 0;
 795 }
 796
 797 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
 798 {
 799         uint32_t def, data;
 800
 801         def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
 802
 803         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
 804                 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
 805         else
 806                 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
 807
 808         if (def != data)
 809                 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
 810 }
 811
 812 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
 813 {
 814         uint32_t def, data;
 815
 816         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
 817
 818         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
 819                 data &= ~(0x01000000 |
 820                           0x02000000 |
 821                           0x04000000 |
 822                           0x08000000 |
 823                           0x10000000 |
 824                           0x20000000 |
 825                           0x40000000 |
 826                           0x80000000);
 827         else
 828                 data |= (0x01000000 |
 829                          0x02000000 |
 830                          0x04000000 |
 831                          0x08000000 |
 832                          0x10000000 |
 833                          0x20000000 |
 834                          0x40000000 |
 835                          0x80000000);
 836
 837         if (def != data)
 838                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
 839 }
 840
 841 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
 842 {
 843         uint32_t def, data;
 844
 845         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
 846
 847         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
 848                 data |= 1;
 849         else
 850                 data &= ~1;
 851
 852         if (def != data)
 853                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
 854 }
 855
 856 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
 857                                                        bool enable)
 858 {
 859         uint32_t def, data;
 860
 861         def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
 862
 863         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
 864                 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
 865                         CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
 866         else
 867                 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
 868                         CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
 869
 870         if (def != data)
 871                 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
 872 }
 873
 874 static void soc15_update_df_medium_grain_clock_gating(struct amdgpu_device *adev,
 875                                                        bool enable)
 876 {
 877         uint32_t data;
 878
 879         /* Put DF on broadcast mode */
 880         data = RREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl));
 881         data &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
 882         WREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl), data);
 883
 884         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
 885                 data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
 886                 data &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
 887                 data |= DF_MGCG_ENABLE_15_CYCLE_DELAY;
 888                 WREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater), data);
 889         } else {
 890                 data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
 891                 data &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
 892                 data |= DF_MGCG_DISABLE;
 893                 WREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater), data);
 894         }
 895
 896         WREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl),
 897                mmFabricConfigAccessControl_DEFAULT);
 898 }
 899
 900 static int soc15_common_set_clockgating_state(void *handle,
 901                                             enum amd_clockgating_state state)
 902 {
 903         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 904
 905         if (amdgpu_sriov_vf(adev))
 906                 return 0;
 907
 908         switch (adev->asic_type) {
 909         case CHIP_VEGA10:
 910         case CHIP_VEGA12:
 911                 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
 912                                 state == AMD_CG_STATE_GATE ? true : false);
 913                 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
 914                                 state == AMD_CG_STATE_GATE ? true : false);
 915                 soc15_update_hdp_light_sleep(adev,
 916                                 state == AMD_CG_STATE_GATE ? true : false);
 917                 soc15_update_drm_clock_gating(adev,
 918                                 state == AMD_CG_STATE_GATE ? true : false);
 919                 soc15_update_drm_light_sleep(adev,
 920                                 state == AMD_CG_STATE_GATE ? true : false);
 921                 soc15_update_rom_medium_grain_clock_gating(adev,
 922                                 state == AMD_CG_STATE_GATE ? true : false);
 923                 soc15_update_df_medium_grain_clock_gating(adev,
 924                                 state == AMD_CG_STATE_GATE ? true : false);
 925                 break;
 926         case CHIP_RAVEN:
 927                 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
 928                                 state == AMD_CG_STATE_GATE ? true : false);
 929                 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
 930                                 state == AMD_CG_STATE_GATE ? true : false);
 931                 soc15_update_hdp_light_sleep(adev,
 932                                 state == AMD_CG_STATE_GATE ? true : false);
 933                 soc15_update_drm_clock_gating(adev,
 934                                 state == AMD_CG_STATE_GATE ? true : false);
 935                 soc15_update_drm_light_sleep(adev,
 936                                 state == AMD_CG_STATE_GATE ? true : false);
 937                 soc15_update_rom_medium_grain_clock_gating(adev,
 938                                 state == AMD_CG_STATE_GATE ? true : false);
 939                 break;
 940         default:
 941                 break;
 942         }
 943         return 0;
 944 }
 945
 946 static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
 947 {
 948         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 949         int data;
 950
 951         if (amdgpu_sriov_vf(adev))
 952                 *flags = 0;
 953
 954         adev->nbio_funcs->get_clockgating_state(adev, flags);
 955
 956         /* AMD_CG_SUPPORT_HDP_LS */
 957         data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
 958         if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
 959                 *flags |= AMD_CG_SUPPORT_HDP_LS;
 960
 961         /* AMD_CG_SUPPORT_DRM_MGCG */
 962         data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
 963         if (!(data & 0x01000000))
 964                 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
 965
 966         /* AMD_CG_SUPPORT_DRM_LS */
 967         data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
 968         if (data & 0x1)
 969                 *flags |= AMD_CG_SUPPORT_DRM_LS;
 970
 971         /* AMD_CG_SUPPORT_ROM_MGCG */
 972         data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
 973         if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
 974                 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
 975
 976         /* AMD_CG_SUPPORT_DF_MGCG */
 977         data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
 978         if (data & DF_MGCG_ENABLE_15_CYCLE_DELAY)
 979                 *flags |= AMD_CG_SUPPORT_DF_MGCG;
 980 }
 981
 982 static int soc15_common_set_powergating_state(void *handle,
 983                                             enum amd_powergating_state state)
 984 {
 985         /* todo */
 986         return 0;
 987 }
 988
 989 const struct amd_ip_funcs soc15_common_ip_funcs = {
 990         .name = "soc15_common",
 991         .early_init = soc15_common_early_init,
 992         .late_init = soc15_common_late_init,
 993         .sw_init = soc15_common_sw_init,
 994         .sw_fini = soc15_common_sw_fini,
 995         .hw_init = soc15_common_hw_init,
 996         .hw_fini = soc15_common_hw_fini,
 997         .suspend = soc15_common_suspend,
 998         .resume = soc15_common_resume,
 999         .is_idle = soc15_common_is_idle,
1000         .wait_for_idle = soc15_common_wait_for_idle,
1001         .soft_reset = soc15_common_soft_reset,
1002         .set_clockgating_state = soc15_common_set_clockgating_state,
1003         .set_powergating_state = soc15_common_set_powergating_state,
1004         .get_clockgating_state= soc15_common_get_clockgating_state,
1005 };