2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
28 #include <drm/amdgpu_drm.h>
31 #include "amdgpu_atombios.h"
32 #include "amdgpu_ih.h"
33 #include "amdgpu_uvd.h"
34 #include "amdgpu_vce.h"
35 #include "amdgpu_ucode.h"
36 #include "amdgpu_psp.h"
40 #include "uvd/uvd_7_0_offset.h"
41 #include "gc/gc_9_0_offset.h"
42 #include "gc/gc_9_0_sh_mask.h"
43 #include "sdma0/sdma0_4_0_offset.h"
44 #include "sdma1/sdma1_4_0_offset.h"
45 #include "nbio/nbio_7_0_default.h"
46 #include "nbio/nbio_7_0_offset.h"
47 #include "nbio/nbio_7_0_sh_mask.h"
48 #include "nbio/nbio_7_0_smn.h"
49 #include "mp/mp_9_0_offset.h"
52 #include "soc15_common.h"
55 #include "gfxhub_v1_0.h"
56 #include "mmhub_v1_0.h"
59 #include "nbio_v6_1.h"
60 #include "nbio_v7_0.h"
61 #include "nbio_v7_4.h"
63 #include "vega10_ih.h"
64 #include "vega20_ih.h"
65 #include "navi10_ih.h"
66 #include "sdma_v4_0.h"
71 #include "jpeg_v2_0.h"
73 #include "jpeg_v2_5.h"
74 #include "smuio_v9_0.h"
75 #include "smuio_v11_0.h"
76 #include "smuio_v13_0.h"
77 #include "dce_virtual.h"
79 #include "amdgpu_ras.h"
80 #include "amdgpu_xgmi.h"
81 #include <uapi/linux/kfd_ioctl.h>
83 #define mmMP0_MISC_CGTT_CTRL0 0x01b9
84 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
85 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
86 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
88 /* Vega, Raven, Arcturus */
89 static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] =
92 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
95 .max_pixels_per_frame = 4096 * 2304,
99 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
102 .max_pixels_per_frame = 4096 * 2304,
107 static const struct amdgpu_video_codecs vega_video_codecs_encode =
109 .codec_count = ARRAY_SIZE(vega_video_codecs_encode_array),
110 .codec_array = vega_video_codecs_encode_array,
114 static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] =
117 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
120 .max_pixels_per_frame = 4096 * 4096,
124 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
127 .max_pixels_per_frame = 4096 * 4096,
131 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
134 .max_pixels_per_frame = 4096 * 4096,
138 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
141 .max_pixels_per_frame = 4096 * 4096,
145 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
148 .max_pixels_per_frame = 4096 * 4096,
152 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
155 .max_pixels_per_frame = 4096 * 4096,
160 static const struct amdgpu_video_codecs vega_video_codecs_decode =
162 .codec_count = ARRAY_SIZE(vega_video_codecs_decode_array),
163 .codec_array = vega_video_codecs_decode_array,
167 static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] =
170 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
173 .max_pixels_per_frame = 4096 * 4096,
177 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
180 .max_pixels_per_frame = 4096 * 4096,
184 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
187 .max_pixels_per_frame = 4096 * 4096,
191 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
194 .max_pixels_per_frame = 4096 * 4096,
198 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
201 .max_pixels_per_frame = 4096 * 4096,
205 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
208 .max_pixels_per_frame = 4096 * 4096,
212 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9,
215 .max_pixels_per_frame = 4096 * 4096,
220 static const struct amdgpu_video_codecs rv_video_codecs_decode =
222 .codec_count = ARRAY_SIZE(rv_video_codecs_decode_array),
223 .codec_array = rv_video_codecs_decode_array,
226 /* Renoir, Arcturus */
227 static const struct amdgpu_video_codec_info rn_video_codecs_decode_array[] =
230 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
233 .max_pixels_per_frame = 4096 * 4096,
237 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
240 .max_pixels_per_frame = 4096 * 4096,
244 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
247 .max_pixels_per_frame = 4096 * 4096,
251 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
254 .max_pixels_per_frame = 4096 * 4096,
258 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
261 .max_pixels_per_frame = 4096 * 4096,
265 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
268 .max_pixels_per_frame = 4096 * 4096,
272 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9,
275 .max_pixels_per_frame = 4096 * 4096,
280 static const struct amdgpu_video_codecs rn_video_codecs_decode =
282 .codec_count = ARRAY_SIZE(rn_video_codecs_decode_array),
283 .codec_array = rn_video_codecs_decode_array,
286 static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,
287 const struct amdgpu_video_codecs **codecs)
289 switch (adev->asic_type) {
294 *codecs = &vega_video_codecs_encode;
296 *codecs = &vega_video_codecs_decode;
300 *codecs = &vega_video_codecs_encode;
302 *codecs = &rv_video_codecs_decode;
307 *codecs = &vega_video_codecs_encode;
309 *codecs = &rn_video_codecs_decode;
317 * Indirect registers accessor
319 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
321 unsigned long address, data;
322 address = adev->nbio.funcs->get_pcie_index_offset(adev);
323 data = adev->nbio.funcs->get_pcie_data_offset(adev);
325 return amdgpu_device_indirect_rreg(adev, address, data, reg);
328 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
330 unsigned long address, data;
332 address = adev->nbio.funcs->get_pcie_index_offset(adev);
333 data = adev->nbio.funcs->get_pcie_data_offset(adev);
335 amdgpu_device_indirect_wreg(adev, address, data, reg, v);
338 static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
340 unsigned long address, data;
341 address = adev->nbio.funcs->get_pcie_index_offset(adev);
342 data = adev->nbio.funcs->get_pcie_data_offset(adev);
344 return amdgpu_device_indirect_rreg64(adev, address, data, reg);
347 static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
349 unsigned long address, data;
351 address = adev->nbio.funcs->get_pcie_index_offset(adev);
352 data = adev->nbio.funcs->get_pcie_data_offset(adev);
354 amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
357 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
359 unsigned long flags, address, data;
362 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
363 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
365 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
366 WREG32(address, ((reg) & 0x1ff));
368 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
372 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
374 unsigned long flags, address, data;
376 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
377 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
379 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
380 WREG32(address, ((reg) & 0x1ff));
382 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
385 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
387 unsigned long flags, address, data;
390 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
391 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
393 spin_lock_irqsave(&adev->didt_idx_lock, flags);
394 WREG32(address, (reg));
396 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
400 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
402 unsigned long flags, address, data;
404 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
405 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
407 spin_lock_irqsave(&adev->didt_idx_lock, flags);
408 WREG32(address, (reg));
410 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
413 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
418 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
419 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
420 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
421 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
425 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
429 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
430 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
431 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
432 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
435 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
440 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
441 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
442 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
443 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
447 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
451 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
452 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
453 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
454 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
457 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
459 return adev->nbio.funcs->get_memsize(adev);
462 static u32 soc15_get_xclk(struct amdgpu_device *adev)
464 u32 reference_clock = adev->clock.spll.reference_freq;
466 if (adev->asic_type == CHIP_RENOIR)
468 if (adev->asic_type == CHIP_RAVEN)
469 return reference_clock / 4;
471 return reference_clock;
475 void soc15_grbm_select(struct amdgpu_device *adev,
476 u32 me, u32 pipe, u32 queue, u32 vmid)
478 u32 grbm_gfx_cntl = 0;
479 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
480 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
481 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
482 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
484 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
487 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
492 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
498 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
499 u8 *bios, u32 length_bytes)
503 uint32_t rom_index_offset;
504 uint32_t rom_data_offset;
508 if (length_bytes == 0)
510 /* APU vbios image is part of sbios image */
511 if (adev->flags & AMD_IS_APU)
514 dw_ptr = (u32 *)bios;
515 length_dw = ALIGN(length_bytes, 4) / 4;
518 adev->smuio.funcs->get_rom_index_offset(adev);
520 adev->smuio.funcs->get_rom_data_offset(adev);
522 /* set rom index to 0 */
523 WREG32(rom_index_offset, 0);
524 /* read out the rom data */
525 for (i = 0; i < length_dw; i++)
526 dw_ptr[i] = RREG32(rom_data_offset);
531 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
532 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
533 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
534 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
535 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
536 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
537 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
538 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
539 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
540 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
541 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
542 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
543 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
544 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
545 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
546 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
547 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
548 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
549 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
550 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
551 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
554 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
555 u32 sh_num, u32 reg_offset)
559 mutex_lock(&adev->grbm_idx_mutex);
560 if (se_num != 0xffffffff || sh_num != 0xffffffff)
561 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
563 val = RREG32(reg_offset);
565 if (se_num != 0xffffffff || sh_num != 0xffffffff)
566 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
567 mutex_unlock(&adev->grbm_idx_mutex);
571 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
572 bool indexed, u32 se_num,
573 u32 sh_num, u32 reg_offset)
576 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
578 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
579 return adev->gfx.config.gb_addr_config;
580 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
581 return adev->gfx.config.db_debug2;
582 return RREG32(reg_offset);
586 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
587 u32 sh_num, u32 reg_offset, u32 *value)
590 struct soc15_allowed_register_entry *en;
593 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
594 en = &soc15_allowed_read_registers[i];
595 if (adev->reg_offset[en->hwip][en->inst] &&
596 reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
600 *value = soc15_get_register_value(adev,
601 soc15_allowed_read_registers[i].grbm_indexed,
602 se_num, sh_num, reg_offset);
610 * soc15_program_register_sequence - program an array of registers.
612 * @adev: amdgpu_device pointer
613 * @regs: pointer to the register array
614 * @array_size: size of the register array
616 * Programs an array or registers with and and or masks.
617 * This is a helper for setting golden registers.
620 void soc15_program_register_sequence(struct amdgpu_device *adev,
621 const struct soc15_reg_golden *regs,
622 const u32 array_size)
624 const struct soc15_reg_golden *entry;
628 for (i = 0; i < array_size; ++i) {
630 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
632 if (entry->and_mask == 0xffffffff) {
633 tmp = entry->or_mask;
636 tmp &= ~(entry->and_mask);
637 tmp |= (entry->or_mask & entry->and_mask);
640 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
641 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
642 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
643 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
644 WREG32_RLC(reg, tmp);
652 static int soc15_asic_baco_reset(struct amdgpu_device *adev)
654 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
657 /* avoid NBIF got stuck when do RAS recovery in BACO reset */
658 if (ras && adev->ras_enabled)
659 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
661 ret = amdgpu_dpm_baco_reset(adev);
665 /* re-enable doorbell interrupt after BACO exit */
666 if (ras && adev->ras_enabled)
667 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
672 static enum amd_reset_method
673 soc15_asic_reset_method(struct amdgpu_device *adev)
675 bool baco_reset = false;
676 bool connected_to_cpu = false;
677 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
679 if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu)
680 connected_to_cpu = true;
682 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
683 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
684 amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
685 amdgpu_reset_method == AMD_RESET_METHOD_PCI) {
686 /* If connected to cpu, driver only support mode2 */
687 if (connected_to_cpu)
688 return AMD_RESET_METHOD_MODE2;
689 return amdgpu_reset_method;
692 if (amdgpu_reset_method != -1)
693 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
694 amdgpu_reset_method);
696 switch (adev->asic_type) {
699 return AMD_RESET_METHOD_MODE2;
703 baco_reset = amdgpu_dpm_is_baco_supported(adev);
706 if (adev->psp.sos_fw_version >= 0x80067)
707 baco_reset = amdgpu_dpm_is_baco_supported(adev);
710 * 1. PMFW version > 0x284300: all cases use baco
711 * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco
713 if (ras && adev->ras_enabled &&
714 adev->pm.fw_version <= 0x283400)
719 * 1.connected to cpu: driver issue mode2 reset
720 * 2.discret gpu: driver issue mode1 reset
722 if (connected_to_cpu)
723 return AMD_RESET_METHOD_MODE2;
730 return AMD_RESET_METHOD_BACO;
732 return AMD_RESET_METHOD_MODE1;
735 static int soc15_asic_reset(struct amdgpu_device *adev)
737 /* original raven doesn't have full asic reset */
738 if ((adev->apu_flags & AMD_APU_IS_RAVEN) &&
739 !(adev->apu_flags & AMD_APU_IS_RAVEN2))
742 switch (soc15_asic_reset_method(adev)) {
743 case AMD_RESET_METHOD_PCI:
744 dev_info(adev->dev, "PCI reset\n");
745 return amdgpu_device_pci_reset(adev);
746 case AMD_RESET_METHOD_BACO:
747 dev_info(adev->dev, "BACO reset\n");
748 return soc15_asic_baco_reset(adev);
749 case AMD_RESET_METHOD_MODE2:
750 dev_info(adev->dev, "MODE2 reset\n");
751 return amdgpu_dpm_mode2_reset(adev);
753 dev_info(adev->dev, "MODE1 reset\n");
754 return amdgpu_device_mode1_reset(adev);
758 static bool soc15_supports_baco(struct amdgpu_device *adev)
760 switch (adev->asic_type) {
764 return amdgpu_dpm_is_baco_supported(adev);
766 if (adev->psp.sos_fw_version >= 0x80067)
767 return amdgpu_dpm_is_baco_supported(adev);
774 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
775 u32 cntl_reg, u32 status_reg)
780 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
784 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
788 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
793 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
800 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
802 if (pci_is_root_bus(adev->pdev->bus))
805 if (amdgpu_pcie_gen2 == 0)
808 if (adev->flags & AMD_IS_APU)
811 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
812 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
818 static void soc15_program_aspm(struct amdgpu_device *adev)
820 if (amdgpu_aspm != 1)
823 if (!(adev->flags & AMD_IS_APU) &&
824 (adev->nbio.funcs->program_aspm))
825 adev->nbio.funcs->program_aspm(adev);
828 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
831 adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
832 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
835 static const struct amdgpu_ip_block_version vega10_common_ip_block =
837 .type = AMD_IP_BLOCK_TYPE_COMMON,
841 .funcs = &soc15_common_ip_funcs,
844 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
846 return adev->nbio.funcs->get_rev_id(adev);
849 static void soc15_reg_base_init(struct amdgpu_device *adev)
853 /* Set IP register base before any HW register access */
854 switch (adev->asic_type) {
858 vega10_reg_base_init(adev);
861 /* It's safe to do ip discovery here for Renior,
862 * it doesn't support SRIOV. */
863 if (amdgpu_discovery) {
864 r = amdgpu_discovery_reg_base_init(adev);
867 DRM_WARN("failed to init reg base from ip discovery table, "
868 "fallback to legacy init method\n");
870 vega10_reg_base_init(adev);
873 vega20_reg_base_init(adev);
876 arct_reg_base_init(adev);
879 aldebaran_reg_base_init(adev);
882 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type);
887 void soc15_set_virt_ops(struct amdgpu_device *adev)
889 adev->virt.ops = &xgpu_ai_virt_ops;
891 /* init soc15 reg base early enough so we can
892 * request request full access for sriov before
894 soc15_reg_base_init(adev);
897 int soc15_set_ip_blocks(struct amdgpu_device *adev)
899 /* for bare metal case */
900 if (!amdgpu_sriov_vf(adev))
901 soc15_reg_base_init(adev);
903 if (adev->flags & AMD_IS_APU) {
904 adev->nbio.funcs = &nbio_v7_0_funcs;
905 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
906 } else if (adev->asic_type == CHIP_VEGA20 ||
907 adev->asic_type == CHIP_ARCTURUS ||
908 adev->asic_type == CHIP_ALDEBARAN) {
909 adev->nbio.funcs = &nbio_v7_4_funcs;
910 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
912 adev->nbio.funcs = &nbio_v6_1_funcs;
913 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
915 adev->hdp.funcs = &hdp_v4_0_funcs;
917 if (adev->asic_type == CHIP_VEGA20 ||
918 adev->asic_type == CHIP_ARCTURUS ||
919 adev->asic_type == CHIP_ALDEBARAN)
920 adev->df.funcs = &df_v3_6_funcs;
922 adev->df.funcs = &df_v1_7_funcs;
924 if (adev->asic_type == CHIP_VEGA20 ||
925 adev->asic_type == CHIP_ARCTURUS)
926 adev->smuio.funcs = &smuio_v11_0_funcs;
927 else if (adev->asic_type == CHIP_ALDEBARAN)
928 adev->smuio.funcs = &smuio_v13_0_funcs;
930 adev->smuio.funcs = &smuio_v9_0_funcs;
932 adev->rev_id = soc15_get_rev_id(adev);
934 switch (adev->asic_type) {
938 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
939 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
941 /* For Vega10 SR-IOV, PSP need to be initialized before IH */
942 if (amdgpu_sriov_vf(adev)) {
943 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
944 if (adev->asic_type == CHIP_VEGA20)
945 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
947 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
949 if (adev->asic_type == CHIP_VEGA20)
950 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
952 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
954 if (adev->asic_type == CHIP_VEGA20)
955 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
957 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
958 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
959 if (adev->asic_type == CHIP_VEGA20)
960 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
962 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
965 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
966 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
967 if (is_support_sw_smu(adev)) {
968 if (!amdgpu_sriov_vf(adev))
969 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
971 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
973 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
974 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
975 #if defined(CONFIG_DRM_AMD_DC)
976 else if (amdgpu_device_has_dc_support(adev))
977 amdgpu_device_ip_block_add(adev, &dm_ip_block);
979 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) {
980 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
981 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
985 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
986 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
987 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
988 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
989 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
990 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
991 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
992 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
993 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
994 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
995 #if defined(CONFIG_DRM_AMD_DC)
996 else if (amdgpu_device_has_dc_support(adev))
997 amdgpu_device_ip_block_add(adev, &dm_ip_block);
999 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
1002 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
1003 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
1005 if (amdgpu_sriov_vf(adev)) {
1006 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
1007 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
1008 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
1010 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
1011 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
1012 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
1015 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
1016 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1017 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
1018 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
1019 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
1021 if (amdgpu_sriov_vf(adev)) {
1022 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
1023 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
1025 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
1027 if (!amdgpu_sriov_vf(adev))
1028 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
1031 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
1032 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
1033 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
1034 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
1035 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
1036 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
1037 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
1038 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
1039 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
1040 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1041 #if defined(CONFIG_DRM_AMD_DC)
1042 else if (amdgpu_device_has_dc_support(adev))
1043 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1045 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
1046 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
1048 case CHIP_ALDEBARAN:
1049 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
1050 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
1052 if (amdgpu_sriov_vf(adev)) {
1053 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
1054 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
1055 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
1057 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
1058 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
1059 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
1062 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
1063 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
1065 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
1066 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block);
1067 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block);
1076 static bool soc15_need_full_reset(struct amdgpu_device *adev)
1078 /* change this when we implement soft reset */
1082 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
1085 uint32_t perfctr = 0;
1086 uint64_t cnt0_of, cnt1_of;
1089 /* This reports 0 on APUs, so return to avoid writing/reading registers
1090 * that may or may not be different from their GPU counterparts
1092 if (adev->flags & AMD_IS_APU)
1095 /* Set the 2 events that we wish to watch, defined above */
1096 /* Reg 40 is # received msgs */
1097 /* Reg 104 is # of posted requests sent */
1098 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
1099 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
1101 /* Write to enable desired perf counters */
1102 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
1103 /* Zero out and enable the perf counters
1105 * Bit 0 = Start all counters(1)
1106 * Bit 2 = Global counter reset enable(1)
1108 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
1112 /* Load the shadow and disable the perf counters
1114 * Bit 0 = Stop counters(0)
1115 * Bit 1 = Load the shadow counters(1)
1117 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
1119 /* Read register values to get any >32bit overflow */
1120 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
1121 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
1122 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
1124 /* Get the values and add the overflow */
1125 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
1126 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
1129 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
1132 uint32_t perfctr = 0;
1133 uint64_t cnt0_of, cnt1_of;
1136 /* This reports 0 on APUs, so return to avoid writing/reading registers
1137 * that may or may not be different from their GPU counterparts
1139 if (adev->flags & AMD_IS_APU)
1142 /* Set the 2 events that we wish to watch, defined above */
1143 /* Reg 40 is # received msgs */
1144 /* Reg 108 is # of posted requests sent on VG20 */
1145 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
1147 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
1150 /* Write to enable desired perf counters */
1151 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr);
1152 /* Zero out and enable the perf counters
1154 * Bit 0 = Start all counters(1)
1155 * Bit 2 = Global counter reset enable(1)
1157 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
1161 /* Load the shadow and disable the perf counters
1163 * Bit 0 = Stop counters(0)
1164 * Bit 1 = Load the shadow counters(1)
1166 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
1168 /* Read register values to get any >32bit overflow */
1169 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3);
1170 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER);
1171 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER);
1173 /* Get the values and add the overflow */
1174 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32);
1175 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32);
1178 static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
1182 /* Just return false for soc15 GPUs. Reset does not seem to
1185 if (!amdgpu_passthrough(adev))
1188 if (adev->flags & AMD_IS_APU)
1191 /* Check sOS sign of life register to confirm sys driver and sOS
1192 * are already been loaded.
1194 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
1201 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
1203 uint64_t nak_r, nak_g;
1205 /* Get the number of NAKs received and generated */
1206 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
1207 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
1209 /* Add the total number of NAKs, i.e the number of replays */
1210 return (nak_r + nak_g);
1213 static void soc15_pre_asic_init(struct amdgpu_device *adev)
1215 gmc_v9_0_restore_registers(adev);
1218 static const struct amdgpu_asic_funcs soc15_asic_funcs =
1220 .read_disabled_bios = &soc15_read_disabled_bios,
1221 .read_bios_from_rom = &soc15_read_bios_from_rom,
1222 .read_register = &soc15_read_register,
1223 .reset = &soc15_asic_reset,
1224 .reset_method = &soc15_asic_reset_method,
1225 .set_vga_state = &soc15_vga_set_state,
1226 .get_xclk = &soc15_get_xclk,
1227 .set_uvd_clocks = &soc15_set_uvd_clocks,
1228 .set_vce_clocks = &soc15_set_vce_clocks,
1229 .get_config_memsize = &soc15_get_config_memsize,
1230 .need_full_reset = &soc15_need_full_reset,
1231 .init_doorbell_index = &vega10_doorbell_index_init,
1232 .get_pcie_usage = &soc15_get_pcie_usage,
1233 .need_reset_on_init = &soc15_need_reset_on_init,
1234 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
1235 .supports_baco = &soc15_supports_baco,
1236 .pre_asic_init = &soc15_pre_asic_init,
1237 .query_video_codecs = &soc15_query_video_codecs,
1240 static const struct amdgpu_asic_funcs vega20_asic_funcs =
1242 .read_disabled_bios = &soc15_read_disabled_bios,
1243 .read_bios_from_rom = &soc15_read_bios_from_rom,
1244 .read_register = &soc15_read_register,
1245 .reset = &soc15_asic_reset,
1246 .reset_method = &soc15_asic_reset_method,
1247 .set_vga_state = &soc15_vga_set_state,
1248 .get_xclk = &soc15_get_xclk,
1249 .set_uvd_clocks = &soc15_set_uvd_clocks,
1250 .set_vce_clocks = &soc15_set_vce_clocks,
1251 .get_config_memsize = &soc15_get_config_memsize,
1252 .need_full_reset = &soc15_need_full_reset,
1253 .init_doorbell_index = &vega20_doorbell_index_init,
1254 .get_pcie_usage = &vega20_get_pcie_usage,
1255 .need_reset_on_init = &soc15_need_reset_on_init,
1256 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
1257 .supports_baco = &soc15_supports_baco,
1258 .pre_asic_init = &soc15_pre_asic_init,
1259 .query_video_codecs = &soc15_query_video_codecs,
1262 static int soc15_common_early_init(void *handle)
1264 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
1265 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1267 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
1268 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
1269 adev->smc_rreg = NULL;
1270 adev->smc_wreg = NULL;
1271 adev->pcie_rreg = &soc15_pcie_rreg;
1272 adev->pcie_wreg = &soc15_pcie_wreg;
1273 adev->pcie_rreg64 = &soc15_pcie_rreg64;
1274 adev->pcie_wreg64 = &soc15_pcie_wreg64;
1275 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
1276 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
1277 adev->didt_rreg = &soc15_didt_rreg;
1278 adev->didt_wreg = &soc15_didt_wreg;
1279 adev->gc_cac_rreg = &soc15_gc_cac_rreg;
1280 adev->gc_cac_wreg = &soc15_gc_cac_wreg;
1281 adev->se_cac_rreg = &soc15_se_cac_rreg;
1282 adev->se_cac_wreg = &soc15_se_cac_wreg;
1285 adev->external_rev_id = 0xFF;
1286 switch (adev->asic_type) {
1288 adev->asic_funcs = &soc15_asic_funcs;
1289 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1290 AMD_CG_SUPPORT_GFX_MGLS |
1291 AMD_CG_SUPPORT_GFX_RLC_LS |
1292 AMD_CG_SUPPORT_GFX_CP_LS |
1293 AMD_CG_SUPPORT_GFX_3D_CGCG |
1294 AMD_CG_SUPPORT_GFX_3D_CGLS |
1295 AMD_CG_SUPPORT_GFX_CGCG |
1296 AMD_CG_SUPPORT_GFX_CGLS |
1297 AMD_CG_SUPPORT_BIF_MGCG |
1298 AMD_CG_SUPPORT_BIF_LS |
1299 AMD_CG_SUPPORT_HDP_LS |
1300 AMD_CG_SUPPORT_DRM_MGCG |
1301 AMD_CG_SUPPORT_DRM_LS |
1302 AMD_CG_SUPPORT_ROM_MGCG |
1303 AMD_CG_SUPPORT_DF_MGCG |
1304 AMD_CG_SUPPORT_SDMA_MGCG |
1305 AMD_CG_SUPPORT_SDMA_LS |
1306 AMD_CG_SUPPORT_MC_MGCG |
1307 AMD_CG_SUPPORT_MC_LS;
1309 adev->external_rev_id = 0x1;
1312 adev->asic_funcs = &soc15_asic_funcs;
1313 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1314 AMD_CG_SUPPORT_GFX_MGLS |
1315 AMD_CG_SUPPORT_GFX_CGCG |
1316 AMD_CG_SUPPORT_GFX_CGLS |
1317 AMD_CG_SUPPORT_GFX_3D_CGCG |
1318 AMD_CG_SUPPORT_GFX_3D_CGLS |
1319 AMD_CG_SUPPORT_GFX_CP_LS |
1320 AMD_CG_SUPPORT_MC_LS |
1321 AMD_CG_SUPPORT_MC_MGCG |
1322 AMD_CG_SUPPORT_SDMA_MGCG |
1323 AMD_CG_SUPPORT_SDMA_LS |
1324 AMD_CG_SUPPORT_BIF_MGCG |
1325 AMD_CG_SUPPORT_BIF_LS |
1326 AMD_CG_SUPPORT_HDP_MGCG |
1327 AMD_CG_SUPPORT_HDP_LS |
1328 AMD_CG_SUPPORT_ROM_MGCG |
1329 AMD_CG_SUPPORT_VCE_MGCG |
1330 AMD_CG_SUPPORT_UVD_MGCG;
1332 adev->external_rev_id = adev->rev_id + 0x14;
1335 adev->asic_funcs = &vega20_asic_funcs;
1336 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1337 AMD_CG_SUPPORT_GFX_MGLS |
1338 AMD_CG_SUPPORT_GFX_CGCG |
1339 AMD_CG_SUPPORT_GFX_CGLS |
1340 AMD_CG_SUPPORT_GFX_3D_CGCG |
1341 AMD_CG_SUPPORT_GFX_3D_CGLS |
1342 AMD_CG_SUPPORT_GFX_CP_LS |
1343 AMD_CG_SUPPORT_MC_LS |
1344 AMD_CG_SUPPORT_MC_MGCG |
1345 AMD_CG_SUPPORT_SDMA_MGCG |
1346 AMD_CG_SUPPORT_SDMA_LS |
1347 AMD_CG_SUPPORT_BIF_MGCG |
1348 AMD_CG_SUPPORT_BIF_LS |
1349 AMD_CG_SUPPORT_HDP_MGCG |
1350 AMD_CG_SUPPORT_HDP_LS |
1351 AMD_CG_SUPPORT_ROM_MGCG |
1352 AMD_CG_SUPPORT_VCE_MGCG |
1353 AMD_CG_SUPPORT_UVD_MGCG;
1355 adev->external_rev_id = adev->rev_id + 0x28;
1358 adev->asic_funcs = &soc15_asic_funcs;
1359 if (adev->pdev->device == 0x15dd)
1360 adev->apu_flags |= AMD_APU_IS_RAVEN;
1361 if (adev->pdev->device == 0x15d8)
1362 adev->apu_flags |= AMD_APU_IS_PICASSO;
1363 if (adev->rev_id >= 0x8)
1364 adev->apu_flags |= AMD_APU_IS_RAVEN2;
1366 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1367 adev->external_rev_id = adev->rev_id + 0x79;
1368 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1369 adev->external_rev_id = adev->rev_id + 0x41;
1370 else if (adev->rev_id == 1)
1371 adev->external_rev_id = adev->rev_id + 0x20;
1373 adev->external_rev_id = adev->rev_id + 0x01;
1375 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
1376 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1377 AMD_CG_SUPPORT_GFX_MGLS |
1378 AMD_CG_SUPPORT_GFX_CP_LS |
1379 AMD_CG_SUPPORT_GFX_3D_CGCG |
1380 AMD_CG_SUPPORT_GFX_3D_CGLS |
1381 AMD_CG_SUPPORT_GFX_CGCG |
1382 AMD_CG_SUPPORT_GFX_CGLS |
1383 AMD_CG_SUPPORT_BIF_LS |
1384 AMD_CG_SUPPORT_HDP_LS |
1385 AMD_CG_SUPPORT_MC_MGCG |
1386 AMD_CG_SUPPORT_MC_LS |
1387 AMD_CG_SUPPORT_SDMA_MGCG |
1388 AMD_CG_SUPPORT_SDMA_LS |
1389 AMD_CG_SUPPORT_VCN_MGCG;
1391 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1392 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) {
1393 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1394 AMD_CG_SUPPORT_GFX_MGLS |
1395 AMD_CG_SUPPORT_GFX_CP_LS |
1396 AMD_CG_SUPPORT_GFX_3D_CGCG |
1397 AMD_CG_SUPPORT_GFX_3D_CGLS |
1398 AMD_CG_SUPPORT_GFX_CGCG |
1399 AMD_CG_SUPPORT_GFX_CGLS |
1400 AMD_CG_SUPPORT_BIF_LS |
1401 AMD_CG_SUPPORT_HDP_LS |
1402 AMD_CG_SUPPORT_MC_MGCG |
1403 AMD_CG_SUPPORT_MC_LS |
1404 AMD_CG_SUPPORT_SDMA_MGCG |
1405 AMD_CG_SUPPORT_SDMA_LS |
1406 AMD_CG_SUPPORT_VCN_MGCG;
1408 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1409 AMD_PG_SUPPORT_MMHUB |
1412 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1413 AMD_CG_SUPPORT_GFX_MGLS |
1414 AMD_CG_SUPPORT_GFX_RLC_LS |
1415 AMD_CG_SUPPORT_GFX_CP_LS |
1416 AMD_CG_SUPPORT_GFX_3D_CGCG |
1417 AMD_CG_SUPPORT_GFX_3D_CGLS |
1418 AMD_CG_SUPPORT_GFX_CGCG |
1419 AMD_CG_SUPPORT_GFX_CGLS |
1420 AMD_CG_SUPPORT_BIF_MGCG |
1421 AMD_CG_SUPPORT_BIF_LS |
1422 AMD_CG_SUPPORT_HDP_MGCG |
1423 AMD_CG_SUPPORT_HDP_LS |
1424 AMD_CG_SUPPORT_DRM_MGCG |
1425 AMD_CG_SUPPORT_DRM_LS |
1426 AMD_CG_SUPPORT_MC_MGCG |
1427 AMD_CG_SUPPORT_MC_LS |
1428 AMD_CG_SUPPORT_SDMA_MGCG |
1429 AMD_CG_SUPPORT_SDMA_LS |
1430 AMD_CG_SUPPORT_VCN_MGCG;
1432 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1436 adev->asic_funcs = &vega20_asic_funcs;
1437 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1438 AMD_CG_SUPPORT_GFX_MGLS |
1439 AMD_CG_SUPPORT_GFX_CGCG |
1440 AMD_CG_SUPPORT_GFX_CGLS |
1441 AMD_CG_SUPPORT_GFX_CP_LS |
1442 AMD_CG_SUPPORT_HDP_MGCG |
1443 AMD_CG_SUPPORT_HDP_LS |
1444 AMD_CG_SUPPORT_SDMA_MGCG |
1445 AMD_CG_SUPPORT_SDMA_LS |
1446 AMD_CG_SUPPORT_MC_MGCG |
1447 AMD_CG_SUPPORT_MC_LS |
1448 AMD_CG_SUPPORT_IH_CG |
1449 AMD_CG_SUPPORT_VCN_MGCG |
1450 AMD_CG_SUPPORT_JPEG_MGCG;
1451 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG;
1452 adev->external_rev_id = adev->rev_id + 0x32;
1455 adev->asic_funcs = &soc15_asic_funcs;
1456 if ((adev->pdev->device == 0x1636) ||
1457 (adev->pdev->device == 0x164c))
1458 adev->apu_flags |= AMD_APU_IS_RENOIR;
1460 adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE;
1462 if (adev->apu_flags & AMD_APU_IS_RENOIR)
1463 adev->external_rev_id = adev->rev_id + 0x91;
1465 adev->external_rev_id = adev->rev_id + 0xa1;
1466 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1467 AMD_CG_SUPPORT_GFX_MGLS |
1468 AMD_CG_SUPPORT_GFX_3D_CGCG |
1469 AMD_CG_SUPPORT_GFX_3D_CGLS |
1470 AMD_CG_SUPPORT_GFX_CGCG |
1471 AMD_CG_SUPPORT_GFX_CGLS |
1472 AMD_CG_SUPPORT_GFX_CP_LS |
1473 AMD_CG_SUPPORT_MC_MGCG |
1474 AMD_CG_SUPPORT_MC_LS |
1475 AMD_CG_SUPPORT_SDMA_MGCG |
1476 AMD_CG_SUPPORT_SDMA_LS |
1477 AMD_CG_SUPPORT_BIF_LS |
1478 AMD_CG_SUPPORT_HDP_LS |
1479 AMD_CG_SUPPORT_VCN_MGCG |
1480 AMD_CG_SUPPORT_JPEG_MGCG |
1481 AMD_CG_SUPPORT_IH_CG |
1482 AMD_CG_SUPPORT_ATHUB_LS |
1483 AMD_CG_SUPPORT_ATHUB_MGCG |
1484 AMD_CG_SUPPORT_DF_MGCG;
1485 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1486 AMD_PG_SUPPORT_VCN |
1487 AMD_PG_SUPPORT_JPEG |
1488 AMD_PG_SUPPORT_VCN_DPG;
1490 case CHIP_ALDEBARAN:
1491 adev->asic_funcs = &vega20_asic_funcs;
1492 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1493 AMD_CG_SUPPORT_GFX_MGLS |
1494 AMD_CG_SUPPORT_GFX_CGCG |
1495 AMD_CG_SUPPORT_GFX_CGLS |
1496 AMD_CG_SUPPORT_GFX_CP_LS |
1497 AMD_CG_SUPPORT_HDP_LS |
1498 AMD_CG_SUPPORT_SDMA_MGCG |
1499 AMD_CG_SUPPORT_SDMA_LS |
1500 AMD_CG_SUPPORT_IH_CG |
1501 AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG;
1502 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG;
1503 adev->external_rev_id = adev->rev_id + 0x3c;
1506 /* FIXME: not supported yet */
1510 if (amdgpu_sriov_vf(adev)) {
1511 amdgpu_virt_init_setting(adev);
1512 xgpu_ai_mailbox_set_irq_funcs(adev);
1518 static int soc15_common_late_init(void *handle)
1520 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1523 if (amdgpu_sriov_vf(adev))
1524 xgpu_ai_mailbox_get_irq(adev);
1526 if (adev->nbio.ras_funcs &&
1527 adev->nbio.ras_funcs->ras_late_init)
1528 r = adev->nbio.ras_funcs->ras_late_init(adev);
1533 static int soc15_common_sw_init(void *handle)
1535 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1537 if (amdgpu_sriov_vf(adev))
1538 xgpu_ai_mailbox_add_irq_id(adev);
1540 adev->df.funcs->sw_init(adev);
1545 static int soc15_common_sw_fini(void *handle)
1547 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1549 if (adev->nbio.ras_funcs &&
1550 adev->nbio.ras_funcs->ras_fini)
1551 adev->nbio.ras_funcs->ras_fini(adev);
1552 adev->df.funcs->sw_fini(adev);
1556 static void soc15_doorbell_range_init(struct amdgpu_device *adev)
1559 struct amdgpu_ring *ring;
1561 /* sdma/ih doorbell range are programed by hypervisor */
1562 if (!amdgpu_sriov_vf(adev)) {
1563 for (i = 0; i < adev->sdma.num_instances; i++) {
1564 ring = &adev->sdma.instance[i].ring;
1565 adev->nbio.funcs->sdma_doorbell_range(adev, i,
1566 ring->use_doorbell, ring->doorbell_index,
1567 adev->doorbell_index.sdma_doorbell_range);
1570 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
1571 adev->irq.ih.doorbell_index);
1575 static int soc15_common_hw_init(void *handle)
1577 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1579 /* enable pcie gen2/3 link */
1580 soc15_pcie_gen3_enable(adev);
1582 soc15_program_aspm(adev);
1583 /* setup nbio registers */
1584 adev->nbio.funcs->init_registers(adev);
1585 /* remap HDP registers to a hole in mmio space,
1586 * for the purpose of expose those registers
1589 if (adev->nbio.funcs->remap_hdp_registers)
1590 adev->nbio.funcs->remap_hdp_registers(adev);
1592 /* enable the doorbell aperture */
1593 soc15_enable_doorbell_aperture(adev, true);
1594 /* HW doorbell routing policy: doorbell writing not
1595 * in SDMA/IH/MM/ACV range will be routed to CP. So
1596 * we need to init SDMA/IH/MM/ACV doorbell range prior
1597 * to CP ip block init and ring test.
1599 soc15_doorbell_range_init(adev);
1604 static int soc15_common_hw_fini(void *handle)
1606 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1608 /* disable the doorbell aperture */
1609 soc15_enable_doorbell_aperture(adev, false);
1610 if (amdgpu_sriov_vf(adev))
1611 xgpu_ai_mailbox_put_irq(adev);
1613 if (adev->nbio.ras_if &&
1614 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
1615 if (adev->nbio.ras_funcs &&
1616 adev->nbio.ras_funcs->init_ras_controller_interrupt)
1617 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);
1618 if (adev->nbio.ras_funcs &&
1619 adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt)
1620 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
1626 static int soc15_common_suspend(void *handle)
1628 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1630 return soc15_common_hw_fini(adev);
1633 static int soc15_common_resume(void *handle)
1635 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1637 return soc15_common_hw_init(adev);
1640 static bool soc15_common_is_idle(void *handle)
1645 static int soc15_common_wait_for_idle(void *handle)
1650 static int soc15_common_soft_reset(void *handle)
1655 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1659 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1661 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1662 data &= ~(0x01000000 |
1671 data |= (0x01000000 |
1681 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1684 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1688 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1690 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1696 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1699 static int soc15_common_set_clockgating_state(void *handle,
1700 enum amd_clockgating_state state)
1702 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1704 if (amdgpu_sriov_vf(adev))
1707 switch (adev->asic_type) {
1711 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1712 state == AMD_CG_STATE_GATE);
1713 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1714 state == AMD_CG_STATE_GATE);
1715 adev->hdp.funcs->update_clock_gating(adev,
1716 state == AMD_CG_STATE_GATE);
1717 soc15_update_drm_clock_gating(adev,
1718 state == AMD_CG_STATE_GATE);
1719 soc15_update_drm_light_sleep(adev,
1720 state == AMD_CG_STATE_GATE);
1721 adev->smuio.funcs->update_rom_clock_gating(adev,
1722 state == AMD_CG_STATE_GATE);
1723 adev->df.funcs->update_medium_grain_clock_gating(adev,
1724 state == AMD_CG_STATE_GATE);
1728 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1729 state == AMD_CG_STATE_GATE);
1730 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1731 state == AMD_CG_STATE_GATE);
1732 adev->hdp.funcs->update_clock_gating(adev,
1733 state == AMD_CG_STATE_GATE);
1734 soc15_update_drm_clock_gating(adev,
1735 state == AMD_CG_STATE_GATE);
1736 soc15_update_drm_light_sleep(adev,
1737 state == AMD_CG_STATE_GATE);
1740 case CHIP_ALDEBARAN:
1741 adev->hdp.funcs->update_clock_gating(adev,
1742 state == AMD_CG_STATE_GATE);
1750 static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
1752 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1755 if (amdgpu_sriov_vf(adev))
1758 adev->nbio.funcs->get_clockgating_state(adev, flags);
1760 adev->hdp.funcs->get_clock_gating_state(adev, flags);
1762 if (adev->asic_type != CHIP_ALDEBARAN) {
1764 /* AMD_CG_SUPPORT_DRM_MGCG */
1765 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1766 if (!(data & 0x01000000))
1767 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1769 /* AMD_CG_SUPPORT_DRM_LS */
1770 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1772 *flags |= AMD_CG_SUPPORT_DRM_LS;
1775 /* AMD_CG_SUPPORT_ROM_MGCG */
1776 adev->smuio.funcs->get_clock_gating_state(adev, flags);
1778 adev->df.funcs->get_clockgating_state(adev, flags);
1781 static int soc15_common_set_powergating_state(void *handle,
1782 enum amd_powergating_state state)
1788 const struct amd_ip_funcs soc15_common_ip_funcs = {
1789 .name = "soc15_common",
1790 .early_init = soc15_common_early_init,
1791 .late_init = soc15_common_late_init,
1792 .sw_init = soc15_common_sw_init,
1793 .sw_fini = soc15_common_sw_fini,
1794 .hw_init = soc15_common_hw_init,
1795 .hw_fini = soc15_common_hw_fini,
1796 .suspend = soc15_common_suspend,
1797 .resume = soc15_common_resume,
1798 .is_idle = soc15_common_is_idle,
1799 .wait_for_idle = soc15_common_wait_for_idle,
1800 .soft_reset = soc15_common_soft_reset,
1801 .set_clockgating_state = soc15_common_set_clockgating_state,
1802 .set_powergating_state = soc15_common_set_powergating_state,
1803 .get_clockgating_state= soc15_common_get_clockgating_state,