drivers/gpu/drm/amd/amdgpu/soc15.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_atombios.h"
  30 #include "amdgpu_ih.h"
  31 #include "amdgpu_uvd.h"
  32 #include "amdgpu_vce.h"
  33 #include "amdgpu_ucode.h"
  34 #include "amdgpu_psp.h"
  35 #include "atom.h"
  36 #include "amd_pcie.h"
  37
  38 #include "uvd/uvd_7_0_offset.h"
  39 #include "gc/gc_9_0_offset.h"
  40 #include "gc/gc_9_0_sh_mask.h"
  41 #include "sdma0/sdma0_4_0_offset.h"
  42 #include "sdma1/sdma1_4_0_offset.h"
  43 #include "hdp/hdp_4_0_offset.h"
  44 #include "hdp/hdp_4_0_sh_mask.h"
  45 #include "smuio/smuio_9_0_offset.h"
  46 #include "smuio/smuio_9_0_sh_mask.h"
  47 #include "nbio/nbio_7_0_default.h"
  48 #include "nbio/nbio_7_0_offset.h"
  49 #include "nbio/nbio_7_0_sh_mask.h"
  50 #include "nbio/nbio_7_0_smn.h"
  51 #include "mp/mp_9_0_offset.h"
  52
  53 #include "soc15.h"
  54 #include "soc15_common.h"
  55 #include "gfx_v9_0.h"
  56 #include "gmc_v9_0.h"
  57 #include "gfxhub_v1_0.h"
  58 #include "mmhub_v1_0.h"
  59 #include "df_v1_7.h"
  60 #include "df_v3_6.h"
  61 #include "vega10_ih.h"
  62 #include "sdma_v4_0.h"
  63 #include "uvd_v7_0.h"
  64 #include "vce_v4_0.h"
  65 #include "vcn_v1_0.h"
  66 #include "vcn_v2_5.h"
  67 #include "dce_virtual.h"
  68 #include "mxgpu_ai.h"
  69 #include "amdgpu_smu.h"
  70 #include "amdgpu_ras.h"
  71 #include "amdgpu_xgmi.h"
  72 #include <uapi/linux/kfd_ioctl.h>
  73
  74 #define mmMP0_MISC_CGTT_CTRL0                                                                   0x01b9
  75 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX                                                          0
  76 #define mmMP0_MISC_LIGHT_SLEEP_CTRL                                                             0x01ba
  77 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX                                                    0
  78
  79 /* for Vega20 register name change */
  80 #define mmHDP_MEM_POWER_CTRL    0x00d4
  81 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK  0x00000001L
  82 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK    0x00000002L
  83 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK   0x00010000L
  84 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK             0x00020000L
  85 #define mmHDP_MEM_POWER_CTRL_BASE_IDX   0
  86 /*
  87  * Indirect registers accessor
  88  */
  89 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
  90 {
  91         unsigned long flags, address, data;
  92         u32 r;
  93         address = adev->nbio_funcs->get_pcie_index_offset(adev);
  94         data = adev->nbio_funcs->get_pcie_data_offset(adev);
  95
  96         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  97         WREG32(address, reg);
  98         (void)RREG32(address);
  99         r = RREG32(data);
 100         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 101         return r;
 102 }
 103
 104 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 105 {
 106         unsigned long flags, address, data;
 107
 108         address = adev->nbio_funcs->get_pcie_index_offset(adev);
 109         data = adev->nbio_funcs->get_pcie_data_offset(adev);
 110
 111         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 112         WREG32(address, reg);
 113         (void)RREG32(address);
 114         WREG32(data, v);
 115         (void)RREG32(data);
 116         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 117 }
 118
 119 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
 120 {
 121         unsigned long flags, address, data;
 122         u32 r;
 123
 124         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 125         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 126
 127         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 128         WREG32(address, ((reg) & 0x1ff));
 129         r = RREG32(data);
 130         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 131         return r;
 132 }
 133
 134 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 135 {
 136         unsigned long flags, address, data;
 137
 138         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 139         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 140
 141         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 142         WREG32(address, ((reg) & 0x1ff));
 143         WREG32(data, (v));
 144         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 145 }
 146
 147 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
 148 {
 149         unsigned long flags, address, data;
 150         u32 r;
 151
 152         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 153         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 154
 155         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 156         WREG32(address, (reg));
 157         r = RREG32(data);
 158         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 159         return r;
 160 }
 161
 162 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 163 {
 164         unsigned long flags, address, data;
 165
 166         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 167         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 168
 169         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 170         WREG32(address, (reg));
 171         WREG32(data, (v));
 172         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 173 }
 174
 175 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
 176 {
 177         unsigned long flags;
 178         u32 r;
 179
 180         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 181         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
 182         r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
 183         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 184         return r;
 185 }
 186
 187 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 188 {
 189         unsigned long flags;
 190
 191         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 192         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
 193         WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
 194         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 195 }
 196
 197 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
 198 {
 199         unsigned long flags;
 200         u32 r;
 201
 202         spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
 203         WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
 204         r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
 205         spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
 206         return r;
 207 }
 208
 209 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 210 {
 211         unsigned long flags;
 212
 213         spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
 214         WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
 215         WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
 216         spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
 217 }
 218
 219 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
 220 {
 221         return adev->nbio_funcs->get_memsize(adev);
 222 }
 223
 224 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 225 {
 226         return adev->clock.spll.reference_freq;
 227 }
 228
 229
 230 void soc15_grbm_select(struct amdgpu_device *adev,
 231                      u32 me, u32 pipe, u32 queue, u32 vmid)
 232 {
 233         u32 grbm_gfx_cntl = 0;
 234         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 235         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 236         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 237         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 238
 239         WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
 240 }
 241
 242 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
 243 {
 244         /* todo */
 245 }
 246
 247 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
 248 {
 249         /* todo */
 250         return false;
 251 }
 252
 253 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
 254                                      u8 *bios, u32 length_bytes)
 255 {
 256         u32 *dw_ptr;
 257         u32 i, length_dw;
 258
 259         if (bios == NULL)
 260                 return false;
 261         if (length_bytes == 0)
 262                 return false;
 263         /* APU vbios image is part of sbios image */
 264         if (adev->flags & AMD_IS_APU)
 265                 return false;
 266
 267         dw_ptr = (u32 *)bios;
 268         length_dw = ALIGN(length_bytes, 4) / 4;
 269
 270         /* set rom index to 0 */
 271         WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
 272         /* read out the rom data */
 273         for (i = 0; i < length_dw; i++)
 274                 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
 275
 276         return true;
 277 }
 278
 279 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
 280         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 281         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
 282         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
 283         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
 284         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
 285         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
 286         { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
 287         { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
 288         { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
 289         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
 290         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
 291         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
 292         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
 293         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
 294         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
 295         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 296         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 297         { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 298         { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
 299 };
 300
 301 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 302                                          u32 sh_num, u32 reg_offset)
 303 {
 304         uint32_t val;
 305
 306         mutex_lock(&adev->grbm_idx_mutex);
 307         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 308                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 309
 310         val = RREG32(reg_offset);
 311
 312         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 313                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 314         mutex_unlock(&adev->grbm_idx_mutex);
 315         return val;
 316 }
 317
 318 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
 319                                          bool indexed, u32 se_num,
 320                                          u32 sh_num, u32 reg_offset)
 321 {
 322         if (indexed) {
 323                 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
 324         } else {
 325                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 326                         return adev->gfx.config.gb_addr_config;
 327                 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
 328                         return adev->gfx.config.db_debug2;
 329                 return RREG32(reg_offset);
 330         }
 331 }
 332
 333 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
 334                             u32 sh_num, u32 reg_offset, u32 *value)
 335 {
 336         uint32_t i;
 337         struct soc15_allowed_register_entry  *en;
 338
 339         *value = 0;
 340         for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
 341                 en = &soc15_allowed_read_registers[i];
 342                 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
 343                                         + en->reg_offset))
 344                         continue;
 345
 346                 *value = soc15_get_register_value(adev,
 347                                                   soc15_allowed_read_registers[i].grbm_indexed,
 348                                                   se_num, sh_num, reg_offset);
 349                 return 0;
 350         }
 351         return -EINVAL;
 352 }
 353
 354
 355 /**
 356  * soc15_program_register_sequence - program an array of registers.
 357  *
 358  * @adev: amdgpu_device pointer
 359  * @regs: pointer to the register array
 360  * @array_size: size of the register array
 361  *
 362  * Programs an array or registers with and and or masks.
 363  * This is a helper for setting golden registers.
 364  */
 365
 366 void soc15_program_register_sequence(struct amdgpu_device *adev,
 367                                              const struct soc15_reg_golden *regs,
 368                                              const u32 array_size)
 369 {
 370         const struct soc15_reg_golden *entry;
 371         u32 tmp, reg;
 372         int i;
 373
 374         for (i = 0; i < array_size; ++i) {
 375                 entry = &regs[i];
 376                 reg =  adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
 377
 378                 if (entry->and_mask == 0xffffffff) {
 379                         tmp = entry->or_mask;
 380                 } else {
 381                         tmp = RREG32(reg);
 382                         tmp &= ~(entry->and_mask);
 383                         tmp |= (entry->or_mask & entry->and_mask);
 384                 }
 385
 386                 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
 387                         reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
 388                         reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
 389                         reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
 390                         WREG32_RLC(reg, tmp);
 391                 else
 392                         WREG32(reg, tmp);
 393
 394         }
 395
 396 }
 397
 398 static int soc15_asic_mode1_reset(struct amdgpu_device *adev)
 399 {
 400         u32 i;
 401         int ret = 0;
 402
 403         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 404
 405         dev_info(adev->dev, "GPU mode1 reset\n");
 406
 407         /* disable BM */
 408         pci_clear_master(adev->pdev);
 409
 410         pci_save_state(adev->pdev);
 411
 412         ret = psp_gpu_reset(adev);
 413         if (ret)
 414                 dev_err(adev->dev, "GPU mode1 reset failed\n");
 415
 416         pci_restore_state(adev->pdev);
 417
 418         /* wait for asic to come out of reset */
 419         for (i = 0; i < adev->usec_timeout; i++) {
 420                 u32 memsize = adev->nbio_funcs->get_memsize(adev);
 421
 422                 if (memsize != 0xffffffff)
 423                         break;
 424                 udelay(1);
 425         }
 426
 427         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 428
 429         return ret;
 430 }
 431
 432 static int soc15_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap)
 433 {
 434         void *pp_handle = adev->powerplay.pp_handle;
 435         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 436
 437         if (!pp_funcs || !pp_funcs->get_asic_baco_capability) {
 438                 *cap = false;
 439                 return -ENOENT;
 440         }
 441
 442         return pp_funcs->get_asic_baco_capability(pp_handle, cap);
 443 }
 444
 445 static int soc15_asic_baco_reset(struct amdgpu_device *adev)
 446 {
 447         void *pp_handle = adev->powerplay.pp_handle;
 448         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 449
 450         if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state)
 451                 return -ENOENT;
 452
 453         /* enter BACO state */
 454         if (pp_funcs->set_asic_baco_state(pp_handle, 1))
 455                 return -EIO;
 456
 457         /* exit BACO state */
 458         if (pp_funcs->set_asic_baco_state(pp_handle, 0))
 459                 return -EIO;
 460
 461         dev_info(adev->dev, "GPU BACO reset\n");
 462
 463         adev->in_baco_reset = 1;
 464
 465         return 0;
 466 }
 467
 468 static enum amd_reset_method
 469 soc15_asic_reset_method(struct amdgpu_device *adev)
 470 {
 471         bool baco_reset;
 472
 473         switch (adev->asic_type) {
 474         case CHIP_RAVEN:
 475                 return AMD_RESET_METHOD_MODE2;
 476         case CHIP_VEGA10:
 477         case CHIP_VEGA12:
 478                 soc15_asic_get_baco_capability(adev, &baco_reset);
 479                 break;
 480         case CHIP_VEGA20:
 481                 if (adev->psp.sos_fw_version >= 0x80067)
 482                         soc15_asic_get_baco_capability(adev, &baco_reset);
 483                 else
 484                         baco_reset = false;
 485                 if (baco_reset) {
 486                         struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, 0);
 487                         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 488
 489                         if (hive || (ras && ras->supported))
 490                                 baco_reset = false;
 491                 }
 492                 break;
 493         default:
 494                 baco_reset = false;
 495                 break;
 496         }
 497
 498         if (baco_reset)
 499                 return AMD_RESET_METHOD_BACO;
 500         else
 501                 return AMD_RESET_METHOD_MODE1;
 502 }
 503
 504 static int soc15_asic_reset(struct amdgpu_device *adev)
 505 {
 506         int ret;
 507
 508         if (soc15_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)
 509                 ret = soc15_asic_baco_reset(adev);
 510         else
 511                 ret = soc15_asic_mode1_reset(adev);
 512
 513         return ret;
 514 }
 515
 516 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
 517                         u32 cntl_reg, u32 status_reg)
 518 {
 519         return 0;
 520 }*/
 521
 522 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 523 {
 524         /*int r;
 525
 526         r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
 527         if (r)
 528                 return r;
 529
 530         r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
 531         */
 532         return 0;
 533 }
 534
 535 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 536 {
 537         /* todo */
 538
 539         return 0;
 540 }
 541
 542 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
 543 {
 544         if (pci_is_root_bus(adev->pdev->bus))
 545                 return;
 546
 547         if (amdgpu_pcie_gen2 == 0)
 548                 return;
 549
 550         if (adev->flags & AMD_IS_APU)
 551                 return;
 552
 553         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 554                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 555                 return;
 556
 557         /* todo */
 558 }
 559
 560 static void soc15_program_aspm(struct amdgpu_device *adev)
 561 {
 562
 563         if (amdgpu_aspm == 0)
 564                 return;
 565
 566         /* todo */
 567 }
 568
 569 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
 570                                            bool enable)
 571 {
 572         adev->nbio_funcs->enable_doorbell_aperture(adev, enable);
 573         adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable);
 574 }
 575
 576 static const struct amdgpu_ip_block_version vega10_common_ip_block =
 577 {
 578         .type = AMD_IP_BLOCK_TYPE_COMMON,
 579         .major = 2,
 580         .minor = 0,
 581         .rev = 0,
 582         .funcs = &soc15_common_ip_funcs,
 583 };
 584
 585 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
 586 {
 587         return adev->nbio_funcs->get_rev_id(adev);
 588 }
 589
 590 int soc15_set_ip_blocks(struct amdgpu_device *adev)
 591 {
 592         /* Set IP register base before any HW register access */
 593         switch (adev->asic_type) {
 594         case CHIP_VEGA10:
 595         case CHIP_VEGA12:
 596         case CHIP_RAVEN:
 597                 vega10_reg_base_init(adev);
 598                 break;
 599         case CHIP_VEGA20:
 600                 vega20_reg_base_init(adev);
 601                 break;
 602         case CHIP_ARCTURUS:
 603                 arct_reg_base_init(adev);
 604                 break;
 605         default:
 606                 return -EINVAL;
 607         }
 608
 609         if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
 610                 adev->gmc.xgmi.supported = true;
 611
 612         if (adev->flags & AMD_IS_APU)
 613                 adev->nbio_funcs = &nbio_v7_0_funcs;
 614         else if (adev->asic_type == CHIP_VEGA20 ||
 615                 adev->asic_type == CHIP_ARCTURUS)
 616                 adev->nbio_funcs = &nbio_v7_4_funcs;
 617         else
 618                 adev->nbio_funcs = &nbio_v6_1_funcs;
 619
 620         if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
 621                 adev->df_funcs = &df_v3_6_funcs;
 622         else
 623                 adev->df_funcs = &df_v1_7_funcs;
 624
 625         adev->rev_id = soc15_get_rev_id(adev);
 626         adev->nbio_funcs->detect_hw_virt(adev);
 627
 628         if (amdgpu_sriov_vf(adev))
 629                 adev->virt.ops = &xgpu_ai_virt_ops;
 630
 631         switch (adev->asic_type) {
 632         case CHIP_VEGA10:
 633         case CHIP_VEGA12:
 634         case CHIP_VEGA20:
 635                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 636                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 637
 638                 /* For Vega10 SR-IOV, PSP need to be initialized before IH */
 639                 if (amdgpu_sriov_vf(adev)) {
 640                         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
 641                                 if (adev->asic_type == CHIP_VEGA20)
 642                                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 643                                 else
 644                                         amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
 645                         }
 646                         amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 647                 } else {
 648                         amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 649                         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
 650                                 if (adev->asic_type == CHIP_VEGA20)
 651                                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 652                                 else
 653                                         amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
 654                         }
 655                 }
 656                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 657                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 658                 if (!amdgpu_sriov_vf(adev)) {
 659                         if (is_support_sw_smu(adev))
 660                                 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 661                         else
 662                                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
 663                 }
 664                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 665                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 666 #if defined(CONFIG_DRM_AMD_DC)
 667                 else if (amdgpu_device_has_dc_support(adev))
 668                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 669 #endif
 670                 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) {
 671                         amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
 672                         amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
 673                 }
 674                 break;
 675         case CHIP_RAVEN:
 676                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 677                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 678                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 679                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 680                         amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
 681                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 682                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 683                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
 684                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 685                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 686 #if defined(CONFIG_DRM_AMD_DC)
 687                 else if (amdgpu_device_has_dc_support(adev))
 688                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 689 #endif
 690                 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
 691                 break;
 692         case CHIP_ARCTURUS:
 693                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 694                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 695                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 696                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 697                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 698                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 699                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 700                 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
 701                 break;
 702         default:
 703                 return -EINVAL;
 704         }
 705
 706         return 0;
 707 }
 708
 709 static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
 710 {
 711         adev->nbio_funcs->hdp_flush(adev, ring);
 712 }
 713
 714 static void soc15_invalidate_hdp(struct amdgpu_device *adev,
 715                                  struct amdgpu_ring *ring)
 716 {
 717         if (!ring || !ring->funcs->emit_wreg)
 718                 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
 719         else
 720                 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
 721                         HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
 722 }
 723
 724 static bool soc15_need_full_reset(struct amdgpu_device *adev)
 725 {
 726         /* change this when we implement soft reset */
 727         return true;
 728 }
 729 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
 730                                  uint64_t *count1)
 731 {
 732         uint32_t perfctr = 0;
 733         uint64_t cnt0_of, cnt1_of;
 734         int tmp;
 735
 736         /* This reports 0 on APUs, so return to avoid writing/reading registers
 737          * that may or may not be different from their GPU counterparts
 738          */
 739         if (adev->flags & AMD_IS_APU)
 740                 return;
 741
 742         /* Set the 2 events that we wish to watch, defined above */
 743         /* Reg 40 is # received msgs */
 744         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
 745         /* Pre-VG20, Reg 104 is # of posted requests sent. On VG20 it's 108 */
 746         if (adev->asic_type == CHIP_VEGA20)
 747                 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK,
 748                                         EVENT1_SEL, 108);
 749         else
 750                 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK,
 751                                         EVENT1_SEL, 104);
 752
 753         /* Write to enable desired perf counters */
 754         WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
 755         /* Zero out and enable the perf counters
 756          * Write 0x5:
 757          * Bit 0 = Start all counters(1)
 758          * Bit 2 = Global counter reset enable(1)
 759          */
 760         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
 761
 762         msleep(1000);
 763
 764         /* Load the shadow and disable the perf counters
 765          * Write 0x2:
 766          * Bit 0 = Stop counters(0)
 767          * Bit 1 = Load the shadow counters(1)
 768          */
 769         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
 770
 771         /* Read register values to get any >32bit overflow */
 772         tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
 773         cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
 774         cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
 775
 776         /* Get the values and add the overflow */
 777         *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
 778         *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
 779 }
 780
 781 static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
 782 {
 783         u32 sol_reg;
 784
 785         /* Just return false for soc15 GPUs.  Reset does not seem to
 786          * be necessary.
 787          */
 788         if (!amdgpu_passthrough(adev))
 789                 return false;
 790
 791         if (adev->flags & AMD_IS_APU)
 792                 return false;
 793
 794         /* Check sOS sign of life register to confirm sys driver and sOS
 795          * are already been loaded.
 796          */
 797         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 798         if (sol_reg)
 799                 return true;
 800
 801         return false;
 802 }
 803
 804 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
 805 {
 806         uint64_t nak_r, nak_g;
 807
 808         /* Get the number of NAKs received and generated */
 809         nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
 810         nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
 811
 812         /* Add the total number of NAKs, i.e the number of replays */
 813         return (nak_r + nak_g);
 814 }
 815
 816 static const struct amdgpu_asic_funcs soc15_asic_funcs =
 817 {
 818         .read_disabled_bios = &soc15_read_disabled_bios,
 819         .read_bios_from_rom = &soc15_read_bios_from_rom,
 820         .read_register = &soc15_read_register,
 821         .reset = &soc15_asic_reset,
 822         .reset_method = &soc15_asic_reset_method,
 823         .set_vga_state = &soc15_vga_set_state,
 824         .get_xclk = &soc15_get_xclk,
 825         .set_uvd_clocks = &soc15_set_uvd_clocks,
 826         .set_vce_clocks = &soc15_set_vce_clocks,
 827         .get_config_memsize = &soc15_get_config_memsize,
 828         .flush_hdp = &soc15_flush_hdp,
 829         .invalidate_hdp = &soc15_invalidate_hdp,
 830         .need_full_reset = &soc15_need_full_reset,
 831         .init_doorbell_index = &vega10_doorbell_index_init,
 832         .get_pcie_usage = &soc15_get_pcie_usage,
 833         .need_reset_on_init = &soc15_need_reset_on_init,
 834         .get_pcie_replay_count = &soc15_get_pcie_replay_count,
 835 };
 836
 837 static const struct amdgpu_asic_funcs vega20_asic_funcs =
 838 {
 839         .read_disabled_bios = &soc15_read_disabled_bios,
 840         .read_bios_from_rom = &soc15_read_bios_from_rom,
 841         .read_register = &soc15_read_register,
 842         .reset = &soc15_asic_reset,
 843         .set_vga_state = &soc15_vga_set_state,
 844         .get_xclk = &soc15_get_xclk,
 845         .set_uvd_clocks = &soc15_set_uvd_clocks,
 846         .set_vce_clocks = &soc15_set_vce_clocks,
 847         .get_config_memsize = &soc15_get_config_memsize,
 848         .flush_hdp = &soc15_flush_hdp,
 849         .invalidate_hdp = &soc15_invalidate_hdp,
 850         .need_full_reset = &soc15_need_full_reset,
 851         .init_doorbell_index = &vega20_doorbell_index_init,
 852         .get_pcie_usage = &soc15_get_pcie_usage,
 853         .need_reset_on_init = &soc15_need_reset_on_init,
 854         .get_pcie_replay_count = &soc15_get_pcie_replay_count,
 855 };
 856
 857 static int soc15_common_early_init(void *handle)
 858 {
 859 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
 860         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 861
 862         adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
 863         adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
 864         adev->smc_rreg = NULL;
 865         adev->smc_wreg = NULL;
 866         adev->pcie_rreg = &soc15_pcie_rreg;
 867         adev->pcie_wreg = &soc15_pcie_wreg;
 868         adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
 869         adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
 870         adev->didt_rreg = &soc15_didt_rreg;
 871         adev->didt_wreg = &soc15_didt_wreg;
 872         adev->gc_cac_rreg = &soc15_gc_cac_rreg;
 873         adev->gc_cac_wreg = &soc15_gc_cac_wreg;
 874         adev->se_cac_rreg = &soc15_se_cac_rreg;
 875         adev->se_cac_wreg = &soc15_se_cac_wreg;
 876
 877
 878         adev->external_rev_id = 0xFF;
 879         switch (adev->asic_type) {
 880         case CHIP_VEGA10:
 881                 adev->asic_funcs = &soc15_asic_funcs;
 882                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 883                         AMD_CG_SUPPORT_GFX_MGLS |
 884                         AMD_CG_SUPPORT_GFX_RLC_LS |
 885                         AMD_CG_SUPPORT_GFX_CP_LS |
 886                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 887                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 888                         AMD_CG_SUPPORT_GFX_CGCG |
 889                         AMD_CG_SUPPORT_GFX_CGLS |
 890                         AMD_CG_SUPPORT_BIF_MGCG |
 891                         AMD_CG_SUPPORT_BIF_LS |
 892                         AMD_CG_SUPPORT_HDP_LS |
 893                         AMD_CG_SUPPORT_DRM_MGCG |
 894                         AMD_CG_SUPPORT_DRM_LS |
 895                         AMD_CG_SUPPORT_ROM_MGCG |
 896                         AMD_CG_SUPPORT_DF_MGCG |
 897                         AMD_CG_SUPPORT_SDMA_MGCG |
 898                         AMD_CG_SUPPORT_SDMA_LS |
 899                         AMD_CG_SUPPORT_MC_MGCG |
 900                         AMD_CG_SUPPORT_MC_LS;
 901                 adev->pg_flags = 0;
 902                 adev->external_rev_id = 0x1;
 903                 break;
 904         case CHIP_VEGA12:
 905                 adev->asic_funcs = &soc15_asic_funcs;
 906                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 907                         AMD_CG_SUPPORT_GFX_MGLS |
 908                         AMD_CG_SUPPORT_GFX_CGCG |
 909                         AMD_CG_SUPPORT_GFX_CGLS |
 910                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 911                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 912                         AMD_CG_SUPPORT_GFX_CP_LS |
 913                         AMD_CG_SUPPORT_MC_LS |
 914                         AMD_CG_SUPPORT_MC_MGCG |
 915                         AMD_CG_SUPPORT_SDMA_MGCG |
 916                         AMD_CG_SUPPORT_SDMA_LS |
 917                         AMD_CG_SUPPORT_BIF_MGCG |
 918                         AMD_CG_SUPPORT_BIF_LS |
 919                         AMD_CG_SUPPORT_HDP_MGCG |
 920                         AMD_CG_SUPPORT_HDP_LS |
 921                         AMD_CG_SUPPORT_ROM_MGCG |
 922                         AMD_CG_SUPPORT_VCE_MGCG |
 923                         AMD_CG_SUPPORT_UVD_MGCG;
 924                 adev->pg_flags = 0;
 925                 adev->external_rev_id = adev->rev_id + 0x14;
 926                 break;
 927         case CHIP_VEGA20:
 928                 adev->asic_funcs = &vega20_asic_funcs;
 929                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 930                         AMD_CG_SUPPORT_GFX_MGLS |
 931                         AMD_CG_SUPPORT_GFX_CGCG |
 932                         AMD_CG_SUPPORT_GFX_CGLS |
 933                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 934                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 935                         AMD_CG_SUPPORT_GFX_CP_LS |
 936                         AMD_CG_SUPPORT_MC_LS |
 937                         AMD_CG_SUPPORT_MC_MGCG |
 938                         AMD_CG_SUPPORT_SDMA_MGCG |
 939                         AMD_CG_SUPPORT_SDMA_LS |
 940                         AMD_CG_SUPPORT_BIF_MGCG |
 941                         AMD_CG_SUPPORT_BIF_LS |
 942                         AMD_CG_SUPPORT_HDP_MGCG |
 943                         AMD_CG_SUPPORT_HDP_LS |
 944                         AMD_CG_SUPPORT_ROM_MGCG |
 945                         AMD_CG_SUPPORT_VCE_MGCG |
 946                         AMD_CG_SUPPORT_UVD_MGCG;
 947                 adev->pg_flags = 0;
 948                 adev->external_rev_id = adev->rev_id + 0x28;
 949                 break;
 950         case CHIP_RAVEN:
 951                 adev->asic_funcs = &soc15_asic_funcs;
 952                 if (adev->rev_id >= 0x8)
 953                         adev->external_rev_id = adev->rev_id + 0x79;
 954                 else if (adev->pdev->device == 0x15d8)
 955                         adev->external_rev_id = adev->rev_id + 0x41;
 956                 else if (adev->rev_id == 1)
 957                         adev->external_rev_id = adev->rev_id + 0x20;
 958                 else
 959                         adev->external_rev_id = adev->rev_id + 0x01;
 960
 961                 if (adev->rev_id >= 0x8) {
 962                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 963                                 AMD_CG_SUPPORT_GFX_MGLS |
 964                                 AMD_CG_SUPPORT_GFX_CP_LS |
 965                                 AMD_CG_SUPPORT_GFX_3D_CGCG |
 966                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
 967                                 AMD_CG_SUPPORT_GFX_CGCG |
 968                                 AMD_CG_SUPPORT_GFX_CGLS |
 969                                 AMD_CG_SUPPORT_BIF_LS |
 970                                 AMD_CG_SUPPORT_HDP_LS |
 971                                 AMD_CG_SUPPORT_ROM_MGCG |
 972                                 AMD_CG_SUPPORT_MC_MGCG |
 973                                 AMD_CG_SUPPORT_MC_LS |
 974                                 AMD_CG_SUPPORT_SDMA_MGCG |
 975                                 AMD_CG_SUPPORT_SDMA_LS |
 976                                 AMD_CG_SUPPORT_VCN_MGCG;
 977
 978                         adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
 979                 } else if (adev->pdev->device == 0x15d8) {
 980                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 981                                 AMD_CG_SUPPORT_GFX_MGLS |
 982                                 AMD_CG_SUPPORT_GFX_CP_LS |
 983                                 AMD_CG_SUPPORT_GFX_3D_CGCG |
 984                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
 985                                 AMD_CG_SUPPORT_GFX_CGCG |
 986                                 AMD_CG_SUPPORT_GFX_CGLS |
 987                                 AMD_CG_SUPPORT_BIF_LS |
 988                                 AMD_CG_SUPPORT_HDP_LS |
 989                                 AMD_CG_SUPPORT_ROM_MGCG |
 990                                 AMD_CG_SUPPORT_MC_MGCG |
 991                                 AMD_CG_SUPPORT_MC_LS |
 992                                 AMD_CG_SUPPORT_SDMA_MGCG |
 993                                 AMD_CG_SUPPORT_SDMA_LS;
 994
 995                         adev->pg_flags = AMD_PG_SUPPORT_SDMA |
 996                                 AMD_PG_SUPPORT_MMHUB |
 997                                 AMD_PG_SUPPORT_VCN |
 998                                 AMD_PG_SUPPORT_VCN_DPG;
 999                 } else {
1000                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1001                                 AMD_CG_SUPPORT_GFX_MGLS |
1002                                 AMD_CG_SUPPORT_GFX_RLC_LS |
1003                                 AMD_CG_SUPPORT_GFX_CP_LS |
1004                                 AMD_CG_SUPPORT_GFX_3D_CGCG |
1005                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
1006                                 AMD_CG_SUPPORT_GFX_CGCG |
1007                                 AMD_CG_SUPPORT_GFX_CGLS |
1008                                 AMD_CG_SUPPORT_BIF_MGCG |
1009                                 AMD_CG_SUPPORT_BIF_LS |
1010                                 AMD_CG_SUPPORT_HDP_MGCG |
1011                                 AMD_CG_SUPPORT_HDP_LS |
1012                                 AMD_CG_SUPPORT_DRM_MGCG |
1013                                 AMD_CG_SUPPORT_DRM_LS |
1014                                 AMD_CG_SUPPORT_ROM_MGCG |
1015                                 AMD_CG_SUPPORT_MC_MGCG |
1016                                 AMD_CG_SUPPORT_MC_LS |
1017                                 AMD_CG_SUPPORT_SDMA_MGCG |
1018                                 AMD_CG_SUPPORT_SDMA_LS |
1019                                 AMD_CG_SUPPORT_VCN_MGCG;
1020
1021                         adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1022                 }
1023
1024                 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
1025                         adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
1026                                 AMD_PG_SUPPORT_CP |
1027                                 AMD_PG_SUPPORT_RLC_SMU_HS;
1028                 break;
1029         case CHIP_ARCTURUS:
1030                 adev->asic_funcs = &vega20_asic_funcs;
1031                 adev->cg_flags = 0;
1032                 adev->pg_flags = 0;
1033                 adev->external_rev_id = adev->rev_id + 0x32;
1034                 break;
1035         default:
1036                 /* FIXME: not supported yet */
1037                 return -EINVAL;
1038         }
1039
1040         if (amdgpu_sriov_vf(adev)) {
1041                 amdgpu_virt_init_setting(adev);
1042                 xgpu_ai_mailbox_set_irq_funcs(adev);
1043         }
1044
1045         return 0;
1046 }
1047
1048 static int soc15_common_late_init(void *handle)
1049 {
1050         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1051
1052         if (amdgpu_sriov_vf(adev))
1053                 xgpu_ai_mailbox_get_irq(adev);
1054
1055         return 0;
1056 }
1057
1058 static int soc15_common_sw_init(void *handle)
1059 {
1060         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1061
1062         if (amdgpu_sriov_vf(adev))
1063                 xgpu_ai_mailbox_add_irq_id(adev);
1064
1065         adev->df_funcs->sw_init(adev);
1066
1067         return 0;
1068 }
1069
1070 static int soc15_common_sw_fini(void *handle)
1071 {
1072         return 0;
1073 }
1074
1075 static void soc15_doorbell_range_init(struct amdgpu_device *adev)
1076 {
1077         int i;
1078         struct amdgpu_ring *ring;
1079
1080         /*  Two reasons to skip
1081         *               1, Host driver already programmed them
1082         *               2, To avoid registers program violations in SR-IOV
1083         */
1084         if (!amdgpu_virt_support_skip_setting(adev)) {
1085                 for (i = 0; i < adev->sdma.num_instances; i++) {
1086                         ring = &adev->sdma.instance[i].ring;
1087                         adev->nbio_funcs->sdma_doorbell_range(adev, i,
1088                                 ring->use_doorbell, ring->doorbell_index,
1089                                 adev->doorbell_index.sdma_doorbell_range);
1090                 }
1091         }
1092
1093         adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
1094                                                 adev->irq.ih.doorbell_index);
1095 }
1096
1097 static int soc15_common_hw_init(void *handle)
1098 {
1099         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1100
1101         /* enable pcie gen2/3 link */
1102         soc15_pcie_gen3_enable(adev);
1103         /* enable aspm */
1104         soc15_program_aspm(adev);
1105         /* setup nbio registers */
1106         adev->nbio_funcs->init_registers(adev);
1107         /* remap HDP registers to a hole in mmio space,
1108          * for the purpose of expose those registers
1109          * to process space
1110          */
1111         if (adev->nbio_funcs->remap_hdp_registers)
1112                 adev->nbio_funcs->remap_hdp_registers(adev);
1113
1114         /* enable the doorbell aperture */
1115         soc15_enable_doorbell_aperture(adev, true);
1116         /* HW doorbell routing policy: doorbell writing not
1117          * in SDMA/IH/MM/ACV range will be routed to CP. So
1118          * we need to init SDMA/IH/MM/ACV doorbell range prior
1119          * to CP ip block init and ring test.
1120          */
1121         soc15_doorbell_range_init(adev);
1122
1123         return 0;
1124 }
1125
1126 static int soc15_common_hw_fini(void *handle)
1127 {
1128         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1129
1130         /* disable the doorbell aperture */
1131         soc15_enable_doorbell_aperture(adev, false);
1132         if (amdgpu_sriov_vf(adev))
1133                 xgpu_ai_mailbox_put_irq(adev);
1134
1135         return 0;
1136 }
1137
1138 static int soc15_common_suspend(void *handle)
1139 {
1140         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1141
1142         return soc15_common_hw_fini(adev);
1143 }
1144
1145 static int soc15_common_resume(void *handle)
1146 {
1147         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1148
1149         return soc15_common_hw_init(adev);
1150 }
1151
1152 static bool soc15_common_is_idle(void *handle)
1153 {
1154         return true;
1155 }
1156
1157 static int soc15_common_wait_for_idle(void *handle)
1158 {
1159         return 0;
1160 }
1161
1162 static int soc15_common_soft_reset(void *handle)
1163 {
1164         return 0;
1165 }
1166
1167 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
1168 {
1169         uint32_t def, data;
1170
1171         if (adev->asic_type == CHIP_VEGA20) {
1172                 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
1173
1174                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1175                         data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1176                                 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1177                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1178                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
1179                 else
1180                         data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1181                                 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1182                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1183                                 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
1184
1185                 if (def != data)
1186                         WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
1187         } else {
1188                 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1189
1190                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1191                         data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1192                 else
1193                         data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1194
1195                 if (def != data)
1196                         WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
1197         }
1198 }
1199
1200 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1201 {
1202         uint32_t def, data;
1203
1204         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1205
1206         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1207                 data &= ~(0x01000000 |
1208                           0x02000000 |
1209                           0x04000000 |
1210                           0x08000000 |
1211                           0x10000000 |
1212                           0x20000000 |
1213                           0x40000000 |
1214                           0x80000000);
1215         else
1216                 data |= (0x01000000 |
1217                          0x02000000 |
1218                          0x04000000 |
1219                          0x08000000 |
1220                          0x10000000 |
1221                          0x20000000 |
1222                          0x40000000 |
1223                          0x80000000);
1224
1225         if (def != data)
1226                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1227 }
1228
1229 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1230 {
1231         uint32_t def, data;
1232
1233         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1234
1235         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1236                 data |= 1;
1237         else
1238                 data &= ~1;
1239
1240         if (def != data)
1241                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1242 }
1243
1244 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1245                                                        bool enable)
1246 {
1247         uint32_t def, data;
1248
1249         def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1250
1251         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1252                 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1253                         CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1254         else
1255                 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1256                         CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1257
1258         if (def != data)
1259                 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
1260 }
1261
1262 static int soc15_common_set_clockgating_state(void *handle,
1263                                             enum amd_clockgating_state state)
1264 {
1265         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1266
1267         if (amdgpu_sriov_vf(adev))
1268                 return 0;
1269
1270         switch (adev->asic_type) {
1271         case CHIP_VEGA10:
1272         case CHIP_VEGA12:
1273         case CHIP_VEGA20:
1274                 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
1275                                 state == AMD_CG_STATE_GATE ? true : false);
1276                 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
1277                                 state == AMD_CG_STATE_GATE ? true : false);
1278                 soc15_update_hdp_light_sleep(adev,
1279                                 state == AMD_CG_STATE_GATE ? true : false);
1280                 soc15_update_drm_clock_gating(adev,
1281                                 state == AMD_CG_STATE_GATE ? true : false);
1282                 soc15_update_drm_light_sleep(adev,
1283                                 state == AMD_CG_STATE_GATE ? true : false);
1284                 soc15_update_rom_medium_grain_clock_gating(adev,
1285                                 state == AMD_CG_STATE_GATE ? true : false);
1286                 adev->df_funcs->update_medium_grain_clock_gating(adev,
1287                                 state == AMD_CG_STATE_GATE ? true : false);
1288                 break;
1289         case CHIP_RAVEN:
1290                 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
1291                                 state == AMD_CG_STATE_GATE ? true : false);
1292                 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
1293                                 state == AMD_CG_STATE_GATE ? true : false);
1294                 soc15_update_hdp_light_sleep(adev,
1295                                 state == AMD_CG_STATE_GATE ? true : false);
1296                 soc15_update_drm_clock_gating(adev,
1297                                 state == AMD_CG_STATE_GATE ? true : false);
1298                 soc15_update_drm_light_sleep(adev,
1299                                 state == AMD_CG_STATE_GATE ? true : false);
1300                 soc15_update_rom_medium_grain_clock_gating(adev,
1301                                 state == AMD_CG_STATE_GATE ? true : false);
1302                 break;
1303         default:
1304                 break;
1305         }
1306         return 0;
1307 }
1308
1309 static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
1310 {
1311         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1312         int data;
1313
1314         if (amdgpu_sriov_vf(adev))
1315                 *flags = 0;
1316
1317         adev->nbio_funcs->get_clockgating_state(adev, flags);
1318
1319         /* AMD_CG_SUPPORT_HDP_LS */
1320         data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1321         if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1322                 *flags |= AMD_CG_SUPPORT_HDP_LS;
1323
1324         /* AMD_CG_SUPPORT_DRM_MGCG */
1325         data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1326         if (!(data & 0x01000000))
1327                 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1328
1329         /* AMD_CG_SUPPORT_DRM_LS */
1330         data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1331         if (data & 0x1)
1332                 *flags |= AMD_CG_SUPPORT_DRM_LS;
1333
1334         /* AMD_CG_SUPPORT_ROM_MGCG */
1335         data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1336         if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
1337                 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
1338
1339         adev->df_funcs->get_clockgating_state(adev, flags);
1340 }
1341
1342 static int soc15_common_set_powergating_state(void *handle,
1343                                             enum amd_powergating_state state)
1344 {
1345         /* todo */
1346         return 0;
1347 }
1348
1349 const struct amd_ip_funcs soc15_common_ip_funcs = {
1350         .name = "soc15_common",
1351         .early_init = soc15_common_early_init,
1352         .late_init = soc15_common_late_init,
1353         .sw_init = soc15_common_sw_init,
1354         .sw_fini = soc15_common_sw_fini,
1355         .hw_init = soc15_common_hw_init,
1356         .hw_fini = soc15_common_hw_fini,
1357         .suspend = soc15_common_suspend,
1358         .resume = soc15_common_resume,
1359         .is_idle = soc15_common_is_idle,
1360         .wait_for_idle = soc15_common_wait_for_idle,
1361         .soft_reset = soc15_common_soft_reset,
1362         .set_clockgating_state = soc15_common_set_clockgating_state,
1363         .set_powergating_state = soc15_common_set_powergating_state,
1364         .get_clockgating_state= soc15_common_get_clockgating_state,
1365 };