2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
29 #include "amdgpu_atombios.h"
30 #include "amdgpu_ih.h"
31 #include "amdgpu_uvd.h"
32 #include "amdgpu_vce.h"
33 #include "amdgpu_ucode.h"
34 #include "amdgpu_psp.h"
38 #include "uvd/uvd_7_0_offset.h"
39 #include "gc/gc_9_0_offset.h"
40 #include "gc/gc_9_0_sh_mask.h"
41 #include "sdma0/sdma0_4_0_offset.h"
42 #include "sdma1/sdma1_4_0_offset.h"
43 #include "nbio/nbio_7_0_default.h"
44 #include "nbio/nbio_7_0_offset.h"
45 #include "nbio/nbio_7_0_sh_mask.h"
46 #include "nbio/nbio_7_0_smn.h"
47 #include "mp/mp_9_0_offset.h"
50 #include "soc15_common.h"
53 #include "gfxhub_v1_0.h"
54 #include "mmhub_v1_0.h"
57 #include "nbio_v6_1.h"
58 #include "nbio_v7_0.h"
59 #include "nbio_v7_4.h"
61 #include "vega10_ih.h"
62 #include "vega20_ih.h"
63 #include "navi10_ih.h"
64 #include "sdma_v4_0.h"
69 #include "jpeg_v2_0.h"
71 #include "jpeg_v2_5.h"
72 #include "smuio_v9_0.h"
73 #include "smuio_v11_0.h"
74 #include "dce_virtual.h"
76 #include "amdgpu_smu.h"
77 #include "amdgpu_ras.h"
78 #include "amdgpu_xgmi.h"
79 #include <uapi/linux/kfd_ioctl.h>
81 #define mmMP0_MISC_CGTT_CTRL0 0x01b9
82 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
83 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
84 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
87 * Indirect registers accessor
89 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
91 unsigned long address, data;
92 address = adev->nbio.funcs->get_pcie_index_offset(adev);
93 data = adev->nbio.funcs->get_pcie_data_offset(adev);
95 return amdgpu_device_indirect_rreg(adev, address, data, reg);
98 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
100 unsigned long address, data;
102 address = adev->nbio.funcs->get_pcie_index_offset(adev);
103 data = adev->nbio.funcs->get_pcie_data_offset(adev);
105 amdgpu_device_indirect_wreg(adev, address, data, reg, v);
108 static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
110 unsigned long address, data;
111 address = adev->nbio.funcs->get_pcie_index_offset(adev);
112 data = adev->nbio.funcs->get_pcie_data_offset(adev);
114 return amdgpu_device_indirect_rreg64(adev, address, data, reg);
117 static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
119 unsigned long address, data;
121 address = adev->nbio.funcs->get_pcie_index_offset(adev);
122 data = adev->nbio.funcs->get_pcie_data_offset(adev);
124 amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
127 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
129 unsigned long flags, address, data;
132 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
133 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
135 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
136 WREG32(address, ((reg) & 0x1ff));
138 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
142 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
144 unsigned long flags, address, data;
146 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
147 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
149 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
150 WREG32(address, ((reg) & 0x1ff));
152 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
155 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
157 unsigned long flags, address, data;
160 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
161 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
163 spin_lock_irqsave(&adev->didt_idx_lock, flags);
164 WREG32(address, (reg));
166 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
170 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
172 unsigned long flags, address, data;
174 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
175 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
177 spin_lock_irqsave(&adev->didt_idx_lock, flags);
178 WREG32(address, (reg));
180 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
183 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
188 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
189 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
190 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
191 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
195 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
199 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
200 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
201 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
202 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
205 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
210 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
211 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
212 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
213 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
217 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
221 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
222 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
223 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
224 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
227 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
229 return adev->nbio.funcs->get_memsize(adev);
232 static u32 soc15_get_xclk(struct amdgpu_device *adev)
234 u32 reference_clock = adev->clock.spll.reference_freq;
236 if (adev->asic_type == CHIP_RENOIR)
238 if (adev->asic_type == CHIP_RAVEN)
239 return reference_clock / 4;
241 return reference_clock;
245 void soc15_grbm_select(struct amdgpu_device *adev,
246 u32 me, u32 pipe, u32 queue, u32 vmid)
248 u32 grbm_gfx_cntl = 0;
249 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
250 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
251 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
252 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
254 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
257 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
262 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
268 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
269 u8 *bios, u32 length_bytes)
273 uint32_t rom_index_offset;
274 uint32_t rom_data_offset;
278 if (length_bytes == 0)
280 /* APU vbios image is part of sbios image */
281 if (adev->flags & AMD_IS_APU)
284 dw_ptr = (u32 *)bios;
285 length_dw = ALIGN(length_bytes, 4) / 4;
288 adev->smuio.funcs->get_rom_index_offset(adev);
290 adev->smuio.funcs->get_rom_data_offset(adev);
292 /* set rom index to 0 */
293 WREG32(rom_index_offset, 0);
294 /* read out the rom data */
295 for (i = 0; i < length_dw; i++)
296 dw_ptr[i] = RREG32(rom_data_offset);
301 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
302 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
303 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
304 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
305 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
306 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
307 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
308 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
309 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
310 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
311 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
312 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
313 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
314 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
315 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
316 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
317 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
318 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
319 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
320 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
321 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
324 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
325 u32 sh_num, u32 reg_offset)
329 mutex_lock(&adev->grbm_idx_mutex);
330 if (se_num != 0xffffffff || sh_num != 0xffffffff)
331 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
333 val = RREG32(reg_offset);
335 if (se_num != 0xffffffff || sh_num != 0xffffffff)
336 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
337 mutex_unlock(&adev->grbm_idx_mutex);
341 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
342 bool indexed, u32 se_num,
343 u32 sh_num, u32 reg_offset)
346 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
348 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
349 return adev->gfx.config.gb_addr_config;
350 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
351 return adev->gfx.config.db_debug2;
352 return RREG32(reg_offset);
356 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
357 u32 sh_num, u32 reg_offset, u32 *value)
360 struct soc15_allowed_register_entry *en;
363 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
364 en = &soc15_allowed_read_registers[i];
365 if (adev->reg_offset[en->hwip][en->inst] &&
366 reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
370 *value = soc15_get_register_value(adev,
371 soc15_allowed_read_registers[i].grbm_indexed,
372 se_num, sh_num, reg_offset);
380 * soc15_program_register_sequence - program an array of registers.
382 * @adev: amdgpu_device pointer
383 * @regs: pointer to the register array
384 * @array_size: size of the register array
386 * Programs an array or registers with and and or masks.
387 * This is a helper for setting golden registers.
390 void soc15_program_register_sequence(struct amdgpu_device *adev,
391 const struct soc15_reg_golden *regs,
392 const u32 array_size)
394 const struct soc15_reg_golden *entry;
398 for (i = 0; i < array_size; ++i) {
400 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
402 if (entry->and_mask == 0xffffffff) {
403 tmp = entry->or_mask;
406 tmp &= ~(entry->and_mask);
407 tmp |= (entry->or_mask & entry->and_mask);
410 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
411 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
412 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
413 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
414 WREG32_RLC(reg, tmp);
422 static int soc15_asic_mode1_reset(struct amdgpu_device *adev)
427 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
429 dev_info(adev->dev, "GPU mode1 reset\n");
432 pci_clear_master(adev->pdev);
434 amdgpu_device_cache_pci_state(adev->pdev);
436 ret = psp_gpu_reset(adev);
438 dev_err(adev->dev, "GPU mode1 reset failed\n");
440 amdgpu_device_load_pci_state(adev->pdev);
442 /* wait for asic to come out of reset */
443 for (i = 0; i < adev->usec_timeout; i++) {
444 u32 memsize = adev->nbio.funcs->get_memsize(adev);
446 if (memsize != 0xffffffff)
451 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
456 static int soc15_asic_baco_reset(struct amdgpu_device *adev)
458 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
461 /* avoid NBIF got stuck when do RAS recovery in BACO reset */
462 if (ras && ras->supported)
463 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
465 ret = amdgpu_dpm_baco_reset(adev);
469 /* re-enable doorbell interrupt after BACO exit */
470 if (ras && ras->supported)
471 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
476 static enum amd_reset_method
477 soc15_asic_reset_method(struct amdgpu_device *adev)
479 bool baco_reset = false;
480 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
482 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
483 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
484 amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
485 amdgpu_reset_method == AMD_RESET_METHOD_PCI)
486 return amdgpu_reset_method;
488 if (amdgpu_reset_method != -1)
489 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
490 amdgpu_reset_method);
492 switch (adev->asic_type) {
495 return AMD_RESET_METHOD_MODE2;
499 baco_reset = amdgpu_dpm_is_baco_supported(adev);
502 if (adev->psp.sos_fw_version >= 0x80067)
503 baco_reset = amdgpu_dpm_is_baco_supported(adev);
506 * 1. PMFW version > 0x284300: all cases use baco
507 * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco
509 if ((ras && ras->supported) && adev->pm.fw_version <= 0x283400)
517 return AMD_RESET_METHOD_BACO;
519 return AMD_RESET_METHOD_MODE1;
522 static int soc15_asic_reset(struct amdgpu_device *adev)
524 /* original raven doesn't have full asic reset */
525 if ((adev->apu_flags & AMD_APU_IS_RAVEN) &&
526 !(adev->apu_flags & AMD_APU_IS_RAVEN2))
529 switch (soc15_asic_reset_method(adev)) {
530 case AMD_RESET_METHOD_PCI:
531 dev_info(adev->dev, "PCI reset\n");
532 return amdgpu_device_pci_reset(adev);
533 case AMD_RESET_METHOD_BACO:
534 dev_info(adev->dev, "BACO reset\n");
535 return soc15_asic_baco_reset(adev);
536 case AMD_RESET_METHOD_MODE2:
537 dev_info(adev->dev, "MODE2 reset\n");
538 return amdgpu_dpm_mode2_reset(adev);
540 dev_info(adev->dev, "MODE1 reset\n");
541 return soc15_asic_mode1_reset(adev);
545 static bool soc15_supports_baco(struct amdgpu_device *adev)
547 switch (adev->asic_type) {
551 return amdgpu_dpm_is_baco_supported(adev);
553 if (adev->psp.sos_fw_version >= 0x80067)
554 return amdgpu_dpm_is_baco_supported(adev);
561 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
562 u32 cntl_reg, u32 status_reg)
567 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
571 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
575 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
580 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
587 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
589 if (pci_is_root_bus(adev->pdev->bus))
592 if (amdgpu_pcie_gen2 == 0)
595 if (adev->flags & AMD_IS_APU)
598 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
599 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
605 static void soc15_program_aspm(struct amdgpu_device *adev)
608 if (amdgpu_aspm == 0)
614 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
617 adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
618 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
621 static const struct amdgpu_ip_block_version vega10_common_ip_block =
623 .type = AMD_IP_BLOCK_TYPE_COMMON,
627 .funcs = &soc15_common_ip_funcs,
630 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
632 return adev->nbio.funcs->get_rev_id(adev);
635 static void soc15_reg_base_init(struct amdgpu_device *adev)
639 /* Set IP register base before any HW register access */
640 switch (adev->asic_type) {
644 vega10_reg_base_init(adev);
647 /* It's safe to do ip discovery here for Renior,
648 * it doesn't support SRIOV. */
649 if (amdgpu_discovery) {
650 r = amdgpu_discovery_reg_base_init(adev);
653 DRM_WARN("failed to init reg base from ip discovery table, "
654 "fallback to legacy init method\n");
656 vega10_reg_base_init(adev);
659 vega20_reg_base_init(adev);
662 arct_reg_base_init(adev);
665 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type);
670 void soc15_set_virt_ops(struct amdgpu_device *adev)
672 adev->virt.ops = &xgpu_ai_virt_ops;
674 /* init soc15 reg base early enough so we can
675 * request request full access for sriov before
677 soc15_reg_base_init(adev);
680 int soc15_set_ip_blocks(struct amdgpu_device *adev)
682 /* for bare metal case */
683 if (!amdgpu_sriov_vf(adev))
684 soc15_reg_base_init(adev);
686 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
687 adev->gmc.xgmi.supported = true;
689 if (adev->flags & AMD_IS_APU) {
690 adev->nbio.funcs = &nbio_v7_0_funcs;
691 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
692 } else if (adev->asic_type == CHIP_VEGA20 ||
693 adev->asic_type == CHIP_ARCTURUS) {
694 adev->nbio.funcs = &nbio_v7_4_funcs;
695 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
697 adev->nbio.funcs = &nbio_v6_1_funcs;
698 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
700 adev->hdp.funcs = &hdp_v4_0_funcs;
702 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
703 adev->df.funcs = &df_v3_6_funcs;
705 adev->df.funcs = &df_v1_7_funcs;
707 if (adev->asic_type == CHIP_VEGA20 ||
708 adev->asic_type == CHIP_ARCTURUS)
709 adev->smuio.funcs = &smuio_v11_0_funcs;
711 adev->smuio.funcs = &smuio_v9_0_funcs;
713 adev->rev_id = soc15_get_rev_id(adev);
715 switch (adev->asic_type) {
719 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
720 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
722 /* For Vega10 SR-IOV, PSP need to be initialized before IH */
723 if (amdgpu_sriov_vf(adev)) {
724 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
725 if (adev->asic_type == CHIP_VEGA20)
726 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
728 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
730 if (adev->asic_type == CHIP_VEGA20)
731 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
733 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
735 if (adev->asic_type == CHIP_VEGA20)
736 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
738 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
739 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
740 if (adev->asic_type == CHIP_VEGA20)
741 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
743 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
746 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
747 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
748 if (is_support_sw_smu(adev)) {
749 if (!amdgpu_sriov_vf(adev))
750 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
752 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
754 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
755 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
756 #if defined(CONFIG_DRM_AMD_DC)
757 else if (amdgpu_device_has_dc_support(adev))
758 amdgpu_device_ip_block_add(adev, &dm_ip_block);
760 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) {
761 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
762 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
766 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
767 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
768 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
769 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
770 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
771 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
772 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
773 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
774 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
775 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
776 #if defined(CONFIG_DRM_AMD_DC)
777 else if (amdgpu_device_has_dc_support(adev))
778 amdgpu_device_ip_block_add(adev, &dm_ip_block);
780 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
783 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
784 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
786 if (amdgpu_sriov_vf(adev)) {
787 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
788 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
789 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
791 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
792 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
793 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
796 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
797 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
798 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
799 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
800 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
802 if (amdgpu_sriov_vf(adev)) {
803 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
804 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
806 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
808 if (!amdgpu_sriov_vf(adev))
809 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
812 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
813 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
814 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
815 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
816 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
817 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
818 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
819 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
820 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
821 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
822 #if defined(CONFIG_DRM_AMD_DC)
823 else if (amdgpu_device_has_dc_support(adev))
824 amdgpu_device_ip_block_add(adev, &dm_ip_block);
826 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
827 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
836 static bool soc15_need_full_reset(struct amdgpu_device *adev)
838 /* change this when we implement soft reset */
842 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
845 uint32_t perfctr = 0;
846 uint64_t cnt0_of, cnt1_of;
849 /* This reports 0 on APUs, so return to avoid writing/reading registers
850 * that may or may not be different from their GPU counterparts
852 if (adev->flags & AMD_IS_APU)
855 /* Set the 2 events that we wish to watch, defined above */
856 /* Reg 40 is # received msgs */
857 /* Reg 104 is # of posted requests sent */
858 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
859 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
861 /* Write to enable desired perf counters */
862 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
863 /* Zero out and enable the perf counters
865 * Bit 0 = Start all counters(1)
866 * Bit 2 = Global counter reset enable(1)
868 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
872 /* Load the shadow and disable the perf counters
874 * Bit 0 = Stop counters(0)
875 * Bit 1 = Load the shadow counters(1)
877 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
879 /* Read register values to get any >32bit overflow */
880 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
881 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
882 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
884 /* Get the values and add the overflow */
885 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
886 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
889 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
892 uint32_t perfctr = 0;
893 uint64_t cnt0_of, cnt1_of;
896 /* This reports 0 on APUs, so return to avoid writing/reading registers
897 * that may or may not be different from their GPU counterparts
899 if (adev->flags & AMD_IS_APU)
902 /* Set the 2 events that we wish to watch, defined above */
903 /* Reg 40 is # received msgs */
904 /* Reg 108 is # of posted requests sent on VG20 */
905 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
907 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
910 /* Write to enable desired perf counters */
911 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr);
912 /* Zero out and enable the perf counters
914 * Bit 0 = Start all counters(1)
915 * Bit 2 = Global counter reset enable(1)
917 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
921 /* Load the shadow and disable the perf counters
923 * Bit 0 = Stop counters(0)
924 * Bit 1 = Load the shadow counters(1)
926 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
928 /* Read register values to get any >32bit overflow */
929 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3);
930 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER);
931 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER);
933 /* Get the values and add the overflow */
934 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32);
935 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32);
938 static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
942 /* Just return false for soc15 GPUs. Reset does not seem to
945 if (!amdgpu_passthrough(adev))
948 if (adev->flags & AMD_IS_APU)
951 /* Check sOS sign of life register to confirm sys driver and sOS
952 * are already been loaded.
954 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
961 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
963 uint64_t nak_r, nak_g;
965 /* Get the number of NAKs received and generated */
966 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
967 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
969 /* Add the total number of NAKs, i.e the number of replays */
970 return (nak_r + nak_g);
973 static void soc15_pre_asic_init(struct amdgpu_device *adev)
975 gmc_v9_0_restore_registers(adev);
978 static const struct amdgpu_asic_funcs soc15_asic_funcs =
980 .read_disabled_bios = &soc15_read_disabled_bios,
981 .read_bios_from_rom = &soc15_read_bios_from_rom,
982 .read_register = &soc15_read_register,
983 .reset = &soc15_asic_reset,
984 .reset_method = &soc15_asic_reset_method,
985 .set_vga_state = &soc15_vga_set_state,
986 .get_xclk = &soc15_get_xclk,
987 .set_uvd_clocks = &soc15_set_uvd_clocks,
988 .set_vce_clocks = &soc15_set_vce_clocks,
989 .get_config_memsize = &soc15_get_config_memsize,
990 .need_full_reset = &soc15_need_full_reset,
991 .init_doorbell_index = &vega10_doorbell_index_init,
992 .get_pcie_usage = &soc15_get_pcie_usage,
993 .need_reset_on_init = &soc15_need_reset_on_init,
994 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
995 .supports_baco = &soc15_supports_baco,
996 .pre_asic_init = &soc15_pre_asic_init,
999 static const struct amdgpu_asic_funcs vega20_asic_funcs =
1001 .read_disabled_bios = &soc15_read_disabled_bios,
1002 .read_bios_from_rom = &soc15_read_bios_from_rom,
1003 .read_register = &soc15_read_register,
1004 .reset = &soc15_asic_reset,
1005 .reset_method = &soc15_asic_reset_method,
1006 .set_vga_state = &soc15_vga_set_state,
1007 .get_xclk = &soc15_get_xclk,
1008 .set_uvd_clocks = &soc15_set_uvd_clocks,
1009 .set_vce_clocks = &soc15_set_vce_clocks,
1010 .get_config_memsize = &soc15_get_config_memsize,
1011 .need_full_reset = &soc15_need_full_reset,
1012 .init_doorbell_index = &vega20_doorbell_index_init,
1013 .get_pcie_usage = &vega20_get_pcie_usage,
1014 .need_reset_on_init = &soc15_need_reset_on_init,
1015 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
1016 .supports_baco = &soc15_supports_baco,
1017 .pre_asic_init = &soc15_pre_asic_init,
1020 static int soc15_common_early_init(void *handle)
1022 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
1023 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1025 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
1026 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
1027 adev->smc_rreg = NULL;
1028 adev->smc_wreg = NULL;
1029 adev->pcie_rreg = &soc15_pcie_rreg;
1030 adev->pcie_wreg = &soc15_pcie_wreg;
1031 adev->pcie_rreg64 = &soc15_pcie_rreg64;
1032 adev->pcie_wreg64 = &soc15_pcie_wreg64;
1033 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
1034 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
1035 adev->didt_rreg = &soc15_didt_rreg;
1036 adev->didt_wreg = &soc15_didt_wreg;
1037 adev->gc_cac_rreg = &soc15_gc_cac_rreg;
1038 adev->gc_cac_wreg = &soc15_gc_cac_wreg;
1039 adev->se_cac_rreg = &soc15_se_cac_rreg;
1040 adev->se_cac_wreg = &soc15_se_cac_wreg;
1043 adev->external_rev_id = 0xFF;
1044 switch (adev->asic_type) {
1046 adev->asic_funcs = &soc15_asic_funcs;
1047 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1048 AMD_CG_SUPPORT_GFX_MGLS |
1049 AMD_CG_SUPPORT_GFX_RLC_LS |
1050 AMD_CG_SUPPORT_GFX_CP_LS |
1051 AMD_CG_SUPPORT_GFX_3D_CGCG |
1052 AMD_CG_SUPPORT_GFX_3D_CGLS |
1053 AMD_CG_SUPPORT_GFX_CGCG |
1054 AMD_CG_SUPPORT_GFX_CGLS |
1055 AMD_CG_SUPPORT_BIF_MGCG |
1056 AMD_CG_SUPPORT_BIF_LS |
1057 AMD_CG_SUPPORT_HDP_LS |
1058 AMD_CG_SUPPORT_DRM_MGCG |
1059 AMD_CG_SUPPORT_DRM_LS |
1060 AMD_CG_SUPPORT_ROM_MGCG |
1061 AMD_CG_SUPPORT_DF_MGCG |
1062 AMD_CG_SUPPORT_SDMA_MGCG |
1063 AMD_CG_SUPPORT_SDMA_LS |
1064 AMD_CG_SUPPORT_MC_MGCG |
1065 AMD_CG_SUPPORT_MC_LS;
1067 adev->external_rev_id = 0x1;
1070 adev->asic_funcs = &soc15_asic_funcs;
1071 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1072 AMD_CG_SUPPORT_GFX_MGLS |
1073 AMD_CG_SUPPORT_GFX_CGCG |
1074 AMD_CG_SUPPORT_GFX_CGLS |
1075 AMD_CG_SUPPORT_GFX_3D_CGCG |
1076 AMD_CG_SUPPORT_GFX_3D_CGLS |
1077 AMD_CG_SUPPORT_GFX_CP_LS |
1078 AMD_CG_SUPPORT_MC_LS |
1079 AMD_CG_SUPPORT_MC_MGCG |
1080 AMD_CG_SUPPORT_SDMA_MGCG |
1081 AMD_CG_SUPPORT_SDMA_LS |
1082 AMD_CG_SUPPORT_BIF_MGCG |
1083 AMD_CG_SUPPORT_BIF_LS |
1084 AMD_CG_SUPPORT_HDP_MGCG |
1085 AMD_CG_SUPPORT_HDP_LS |
1086 AMD_CG_SUPPORT_ROM_MGCG |
1087 AMD_CG_SUPPORT_VCE_MGCG |
1088 AMD_CG_SUPPORT_UVD_MGCG;
1090 adev->external_rev_id = adev->rev_id + 0x14;
1093 adev->asic_funcs = &vega20_asic_funcs;
1094 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1095 AMD_CG_SUPPORT_GFX_MGLS |
1096 AMD_CG_SUPPORT_GFX_CGCG |
1097 AMD_CG_SUPPORT_GFX_CGLS |
1098 AMD_CG_SUPPORT_GFX_3D_CGCG |
1099 AMD_CG_SUPPORT_GFX_3D_CGLS |
1100 AMD_CG_SUPPORT_GFX_CP_LS |
1101 AMD_CG_SUPPORT_MC_LS |
1102 AMD_CG_SUPPORT_MC_MGCG |
1103 AMD_CG_SUPPORT_SDMA_MGCG |
1104 AMD_CG_SUPPORT_SDMA_LS |
1105 AMD_CG_SUPPORT_BIF_MGCG |
1106 AMD_CG_SUPPORT_BIF_LS |
1107 AMD_CG_SUPPORT_HDP_MGCG |
1108 AMD_CG_SUPPORT_HDP_LS |
1109 AMD_CG_SUPPORT_ROM_MGCG |
1110 AMD_CG_SUPPORT_VCE_MGCG |
1111 AMD_CG_SUPPORT_UVD_MGCG;
1113 adev->external_rev_id = adev->rev_id + 0x28;
1116 adev->asic_funcs = &soc15_asic_funcs;
1117 if (adev->pdev->device == 0x15dd)
1118 adev->apu_flags |= AMD_APU_IS_RAVEN;
1119 if (adev->pdev->device == 0x15d8)
1120 adev->apu_flags |= AMD_APU_IS_PICASSO;
1121 if (adev->rev_id >= 0x8)
1122 adev->apu_flags |= AMD_APU_IS_RAVEN2;
1124 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1125 adev->external_rev_id = adev->rev_id + 0x79;
1126 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1127 adev->external_rev_id = adev->rev_id + 0x41;
1128 else if (adev->rev_id == 1)
1129 adev->external_rev_id = adev->rev_id + 0x20;
1131 adev->external_rev_id = adev->rev_id + 0x01;
1133 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
1134 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1135 AMD_CG_SUPPORT_GFX_MGLS |
1136 AMD_CG_SUPPORT_GFX_CP_LS |
1137 AMD_CG_SUPPORT_GFX_3D_CGCG |
1138 AMD_CG_SUPPORT_GFX_3D_CGLS |
1139 AMD_CG_SUPPORT_GFX_CGCG |
1140 AMD_CG_SUPPORT_GFX_CGLS |
1141 AMD_CG_SUPPORT_BIF_LS |
1142 AMD_CG_SUPPORT_HDP_LS |
1143 AMD_CG_SUPPORT_MC_MGCG |
1144 AMD_CG_SUPPORT_MC_LS |
1145 AMD_CG_SUPPORT_SDMA_MGCG |
1146 AMD_CG_SUPPORT_SDMA_LS |
1147 AMD_CG_SUPPORT_VCN_MGCG;
1149 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1150 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) {
1151 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1152 AMD_CG_SUPPORT_GFX_MGLS |
1153 AMD_CG_SUPPORT_GFX_CP_LS |
1154 AMD_CG_SUPPORT_GFX_3D_CGCG |
1155 AMD_CG_SUPPORT_GFX_3D_CGLS |
1156 AMD_CG_SUPPORT_GFX_CGCG |
1157 AMD_CG_SUPPORT_GFX_CGLS |
1158 AMD_CG_SUPPORT_BIF_LS |
1159 AMD_CG_SUPPORT_HDP_LS |
1160 AMD_CG_SUPPORT_MC_MGCG |
1161 AMD_CG_SUPPORT_MC_LS |
1162 AMD_CG_SUPPORT_SDMA_MGCG |
1163 AMD_CG_SUPPORT_SDMA_LS;
1165 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1166 AMD_PG_SUPPORT_MMHUB |
1169 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1170 AMD_CG_SUPPORT_GFX_MGLS |
1171 AMD_CG_SUPPORT_GFX_RLC_LS |
1172 AMD_CG_SUPPORT_GFX_CP_LS |
1173 AMD_CG_SUPPORT_GFX_3D_CGCG |
1174 AMD_CG_SUPPORT_GFX_3D_CGLS |
1175 AMD_CG_SUPPORT_GFX_CGCG |
1176 AMD_CG_SUPPORT_GFX_CGLS |
1177 AMD_CG_SUPPORT_BIF_MGCG |
1178 AMD_CG_SUPPORT_BIF_LS |
1179 AMD_CG_SUPPORT_HDP_MGCG |
1180 AMD_CG_SUPPORT_HDP_LS |
1181 AMD_CG_SUPPORT_DRM_MGCG |
1182 AMD_CG_SUPPORT_DRM_LS |
1183 AMD_CG_SUPPORT_MC_MGCG |
1184 AMD_CG_SUPPORT_MC_LS |
1185 AMD_CG_SUPPORT_SDMA_MGCG |
1186 AMD_CG_SUPPORT_SDMA_LS |
1187 AMD_CG_SUPPORT_VCN_MGCG;
1189 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1193 adev->asic_funcs = &vega20_asic_funcs;
1194 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1195 AMD_CG_SUPPORT_GFX_MGLS |
1196 AMD_CG_SUPPORT_GFX_CGCG |
1197 AMD_CG_SUPPORT_GFX_CGLS |
1198 AMD_CG_SUPPORT_GFX_CP_LS |
1199 AMD_CG_SUPPORT_HDP_MGCG |
1200 AMD_CG_SUPPORT_HDP_LS |
1201 AMD_CG_SUPPORT_SDMA_MGCG |
1202 AMD_CG_SUPPORT_SDMA_LS |
1203 AMD_CG_SUPPORT_MC_MGCG |
1204 AMD_CG_SUPPORT_MC_LS |
1205 AMD_CG_SUPPORT_IH_CG |
1206 AMD_CG_SUPPORT_VCN_MGCG |
1207 AMD_CG_SUPPORT_JPEG_MGCG;
1208 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG;
1209 adev->external_rev_id = adev->rev_id + 0x32;
1212 adev->asic_funcs = &soc15_asic_funcs;
1213 if ((adev->pdev->device == 0x1636) ||
1214 (adev->pdev->device == 0x164c))
1215 adev->apu_flags |= AMD_APU_IS_RENOIR;
1217 adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE;
1219 if (adev->apu_flags & AMD_APU_IS_RENOIR)
1220 adev->external_rev_id = adev->rev_id + 0x91;
1222 adev->external_rev_id = adev->rev_id + 0xa1;
1223 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1224 AMD_CG_SUPPORT_GFX_MGLS |
1225 AMD_CG_SUPPORT_GFX_3D_CGCG |
1226 AMD_CG_SUPPORT_GFX_3D_CGLS |
1227 AMD_CG_SUPPORT_GFX_CGCG |
1228 AMD_CG_SUPPORT_GFX_CGLS |
1229 AMD_CG_SUPPORT_GFX_CP_LS |
1230 AMD_CG_SUPPORT_MC_MGCG |
1231 AMD_CG_SUPPORT_MC_LS |
1232 AMD_CG_SUPPORT_SDMA_MGCG |
1233 AMD_CG_SUPPORT_SDMA_LS |
1234 AMD_CG_SUPPORT_BIF_LS |
1235 AMD_CG_SUPPORT_HDP_LS |
1236 AMD_CG_SUPPORT_VCN_MGCG |
1237 AMD_CG_SUPPORT_JPEG_MGCG |
1238 AMD_CG_SUPPORT_IH_CG |
1239 AMD_CG_SUPPORT_ATHUB_LS |
1240 AMD_CG_SUPPORT_ATHUB_MGCG |
1241 AMD_CG_SUPPORT_DF_MGCG;
1242 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1243 AMD_PG_SUPPORT_VCN |
1244 AMD_PG_SUPPORT_JPEG |
1245 AMD_PG_SUPPORT_VCN_DPG;
1248 /* FIXME: not supported yet */
1252 if (amdgpu_sriov_vf(adev)) {
1253 amdgpu_virt_init_setting(adev);
1254 xgpu_ai_mailbox_set_irq_funcs(adev);
1260 static int soc15_common_late_init(void *handle)
1262 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1265 if (amdgpu_sriov_vf(adev))
1266 xgpu_ai_mailbox_get_irq(adev);
1268 if (adev->hdp.funcs->reset_ras_error_count)
1269 adev->hdp.funcs->reset_ras_error_count(adev);
1271 if (adev->nbio.funcs->ras_late_init)
1272 r = adev->nbio.funcs->ras_late_init(adev);
1277 static int soc15_common_sw_init(void *handle)
1279 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1281 if (amdgpu_sriov_vf(adev))
1282 xgpu_ai_mailbox_add_irq_id(adev);
1284 adev->df.funcs->sw_init(adev);
1289 static int soc15_common_sw_fini(void *handle)
1291 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1293 amdgpu_nbio_ras_fini(adev);
1294 adev->df.funcs->sw_fini(adev);
1298 static void soc15_doorbell_range_init(struct amdgpu_device *adev)
1301 struct amdgpu_ring *ring;
1303 /* sdma/ih doorbell range are programed by hypervisor */
1304 if (!amdgpu_sriov_vf(adev)) {
1305 for (i = 0; i < adev->sdma.num_instances; i++) {
1306 ring = &adev->sdma.instance[i].ring;
1307 adev->nbio.funcs->sdma_doorbell_range(adev, i,
1308 ring->use_doorbell, ring->doorbell_index,
1309 adev->doorbell_index.sdma_doorbell_range);
1312 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
1313 adev->irq.ih.doorbell_index);
1317 static int soc15_common_hw_init(void *handle)
1319 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1321 /* enable pcie gen2/3 link */
1322 soc15_pcie_gen3_enable(adev);
1324 soc15_program_aspm(adev);
1325 /* setup nbio registers */
1326 adev->nbio.funcs->init_registers(adev);
1327 /* remap HDP registers to a hole in mmio space,
1328 * for the purpose of expose those registers
1331 if (adev->nbio.funcs->remap_hdp_registers)
1332 adev->nbio.funcs->remap_hdp_registers(adev);
1334 /* enable the doorbell aperture */
1335 soc15_enable_doorbell_aperture(adev, true);
1336 /* HW doorbell routing policy: doorbell writing not
1337 * in SDMA/IH/MM/ACV range will be routed to CP. So
1338 * we need to init SDMA/IH/MM/ACV doorbell range prior
1339 * to CP ip block init and ring test.
1341 soc15_doorbell_range_init(adev);
1346 static int soc15_common_hw_fini(void *handle)
1348 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1350 /* disable the doorbell aperture */
1351 soc15_enable_doorbell_aperture(adev, false);
1352 if (amdgpu_sriov_vf(adev))
1353 xgpu_ai_mailbox_put_irq(adev);
1355 if (adev->nbio.ras_if &&
1356 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
1357 if (adev->nbio.funcs->init_ras_controller_interrupt)
1358 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);
1359 if (adev->nbio.funcs->init_ras_err_event_athub_interrupt)
1360 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
1366 static int soc15_common_suspend(void *handle)
1368 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1370 return soc15_common_hw_fini(adev);
1373 static int soc15_common_resume(void *handle)
1375 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1377 return soc15_common_hw_init(adev);
1380 static bool soc15_common_is_idle(void *handle)
1385 static int soc15_common_wait_for_idle(void *handle)
1390 static int soc15_common_soft_reset(void *handle)
1395 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1399 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1401 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1402 data &= ~(0x01000000 |
1411 data |= (0x01000000 |
1421 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1424 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1428 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1430 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1436 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1439 static int soc15_common_set_clockgating_state(void *handle,
1440 enum amd_clockgating_state state)
1442 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1444 if (amdgpu_sriov_vf(adev))
1447 switch (adev->asic_type) {
1451 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1452 state == AMD_CG_STATE_GATE);
1453 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1454 state == AMD_CG_STATE_GATE);
1455 adev->hdp.funcs->update_clock_gating(adev,
1456 state == AMD_CG_STATE_GATE);
1457 soc15_update_drm_clock_gating(adev,
1458 state == AMD_CG_STATE_GATE);
1459 soc15_update_drm_light_sleep(adev,
1460 state == AMD_CG_STATE_GATE);
1461 adev->smuio.funcs->update_rom_clock_gating(adev,
1462 state == AMD_CG_STATE_GATE);
1463 adev->df.funcs->update_medium_grain_clock_gating(adev,
1464 state == AMD_CG_STATE_GATE);
1468 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1469 state == AMD_CG_STATE_GATE);
1470 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1471 state == AMD_CG_STATE_GATE);
1472 adev->hdp.funcs->update_clock_gating(adev,
1473 state == AMD_CG_STATE_GATE);
1474 soc15_update_drm_clock_gating(adev,
1475 state == AMD_CG_STATE_GATE);
1476 soc15_update_drm_light_sleep(adev,
1477 state == AMD_CG_STATE_GATE);
1480 adev->hdp.funcs->update_clock_gating(adev,
1481 state == AMD_CG_STATE_GATE);
1489 static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
1491 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1494 if (amdgpu_sriov_vf(adev))
1497 adev->nbio.funcs->get_clockgating_state(adev, flags);
1499 adev->hdp.funcs->get_clock_gating_state(adev, flags);
1501 /* AMD_CG_SUPPORT_DRM_MGCG */
1502 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1503 if (!(data & 0x01000000))
1504 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1506 /* AMD_CG_SUPPORT_DRM_LS */
1507 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1509 *flags |= AMD_CG_SUPPORT_DRM_LS;
1511 /* AMD_CG_SUPPORT_ROM_MGCG */
1512 adev->smuio.funcs->get_clock_gating_state(adev, flags);
1514 adev->df.funcs->get_clockgating_state(adev, flags);
1517 static int soc15_common_set_powergating_state(void *handle,
1518 enum amd_powergating_state state)
1524 const struct amd_ip_funcs soc15_common_ip_funcs = {
1525 .name = "soc15_common",
1526 .early_init = soc15_common_early_init,
1527 .late_init = soc15_common_late_init,
1528 .sw_init = soc15_common_sw_init,
1529 .sw_fini = soc15_common_sw_fini,
1530 .hw_init = soc15_common_hw_init,
1531 .hw_fini = soc15_common_hw_fini,
1532 .suspend = soc15_common_suspend,
1533 .resume = soc15_common_resume,
1534 .is_idle = soc15_common_is_idle,
1535 .wait_for_idle = soc15_common_wait_for_idle,
1536 .soft_reset = soc15_common_soft_reset,
1537 .set_clockgating_state = soc15_common_set_clockgating_state,
1538 .set_powergating_state = soc15_common_set_powergating_state,
1539 .get_clockgating_state= soc15_common_get_clockgating_state,