2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include "smuio/smuio_11_0_0_offset.h"
25 #include "smuio/smuio_11_0_0_sh_mask.h"
27 #include "smu_v11_0_i2c.h"
29 #include "soc15_common.h"
30 #include <drm/drm_fixed.h>
31 #include <drm/drm_drv.h>
32 #include "amdgpu_amdkfd.h"
33 #include <linux/i2c.h>
34 #include <linux/pci.h>
38 #define I2C_NAK_7B_ADDR_NOACK 1
39 #define I2C_NAK_TXDATA_NOACK 2
41 #define I2C_SW_TIMEOUT 8
42 #define I2C_ABORT 0x10
44 /* I2C transaction flags */
48 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
50 static void smu_v11_0_i2c_set_clock_gating(struct i2c_adapter *control, bool en)
52 struct amdgpu_device *adev = to_amdgpu_device(control);
53 uint32_t reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT);
55 reg = REG_SET_FIELD(reg, SMUIO_PWRMGT, i2c_clk_gate_en, en ? 1 : 0);
56 WREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT, reg);
60 static void smu_v11_0_i2c_enable(struct i2c_adapter *control, bool enable)
62 struct amdgpu_device *adev = to_amdgpu_device(control);
64 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, enable ? 1 : 0);
67 static void smu_v11_0_i2c_clear_status(struct i2c_adapter *control)
69 struct amdgpu_device *adev = to_amdgpu_device(control);
72 RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_INTR);
74 } /* while (reg_CKSVII2C_ic_clr_intr == 0) */
77 static void smu_v11_0_i2c_configure(struct i2c_adapter *control)
79 struct amdgpu_device *adev = to_amdgpu_device(control);
82 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_SLAVE_DISABLE, 1);
83 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_RESTART_EN, 1);
84 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_10BITADDR_MASTER, 0);
85 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_10BITADDR_SLAVE, 0);
87 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_MAX_SPEED_MODE, 2);
88 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_MASTER_MODE, 1);
90 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CON, reg);
93 static void smu_v11_0_i2c_set_clock(struct i2c_adapter *control)
95 struct amdgpu_device *adev = to_amdgpu_device(control);
98 * Standard mode speed, These values are taken from SMUIO MAS,
99 * but are different from what is given is
100 * Synopsys spec. The values here are based on assumption
101 * that refclock is 100MHz
103 * Configuration for standard mode; Speed = 100kbps
104 * Scale linearly, for now only support standard speed clock
105 * This will work only with 100M ref clock
107 * TBD:Change the calculation to take into account ref clock values also.
110 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_FS_SPKLEN, 2);
111 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SS_SCL_HCNT, 120);
112 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SS_SCL_LCNT, 130);
113 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SDA_HOLD, 20);
116 static void smu_v11_0_i2c_set_address(struct i2c_adapter *control, uint8_t address)
118 struct amdgpu_device *adev = to_amdgpu_device(control);
120 /* Convert fromr 8-bit to 7-bit address */
122 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TAR, (address & 0xFF));
125 static uint32_t smu_v11_0_i2c_poll_tx_status(struct i2c_adapter *control)
127 struct amdgpu_device *adev = to_amdgpu_device(control);
128 uint32_t ret = I2C_OK;
129 uint32_t reg, reg_c_tx_abrt_source;
131 /*Check if transmission is completed */
132 unsigned long timeout_counter = jiffies + msecs_to_jiffies(20);
135 if (time_after(jiffies, timeout_counter)) {
136 ret |= I2C_SW_TIMEOUT;
140 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
142 } while (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFE) == 0);
147 /* This only checks if NAK is received and transaction got aborted */
148 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_INTR_STAT);
150 if (REG_GET_FIELD(reg, CKSVII2C_IC_INTR_STAT, R_TX_ABRT) == 1) {
151 reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE);
152 DRM_INFO("TX was terminated, IC_TX_ABRT_SOURCE val is:%x", reg_c_tx_abrt_source);
154 /* Check for stop due to NACK */
155 if (REG_GET_FIELD(reg_c_tx_abrt_source,
156 CKSVII2C_IC_TX_ABRT_SOURCE,
157 ABRT_TXDATA_NOACK) == 1) {
159 ret |= I2C_NAK_TXDATA_NOACK;
161 } else if (REG_GET_FIELD(reg_c_tx_abrt_source,
162 CKSVII2C_IC_TX_ABRT_SOURCE,
163 ABRT_7B_ADDR_NOACK) == 1) {
165 ret |= I2C_NAK_7B_ADDR_NOACK;
170 smu_v11_0_i2c_clear_status(control);
176 static uint32_t smu_v11_0_i2c_poll_rx_status(struct i2c_adapter *control)
178 struct amdgpu_device *adev = to_amdgpu_device(control);
179 uint32_t ret = I2C_OK;
180 uint32_t reg_ic_status, reg_c_tx_abrt_source;
182 reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE);
184 /* If slave is not present */
185 if (REG_GET_FIELD(reg_c_tx_abrt_source,
186 CKSVII2C_IC_TX_ABRT_SOURCE,
187 ABRT_7B_ADDR_NOACK) == 1) {
188 ret |= I2C_NAK_7B_ADDR_NOACK;
190 smu_v11_0_i2c_clear_status(control);
191 } else { /* wait till some data is there in RXFIFO */
192 /* Poll for some byte in RXFIFO */
193 unsigned long timeout_counter = jiffies + msecs_to_jiffies(20);
196 if (time_after(jiffies, timeout_counter)) {
197 ret |= I2C_SW_TIMEOUT;
201 reg_ic_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
203 } while (REG_GET_FIELD(reg_ic_status, CKSVII2C_IC_STATUS, RFNE) == 0);
213 * smu_v11_0_i2c_transmit - Send a block of data over the I2C bus to a slave device.
215 * @control: I2C adapter reference
216 * @address: The I2C address of the slave device.
217 * @data: The data to transmit over the bus.
218 * @numbytes: The amount of data to transmit.
219 * @i2c_flag: Flags for transmission
221 * Returns 0 on success or error.
223 static uint32_t smu_v11_0_i2c_transmit(struct i2c_adapter *control,
224 uint8_t address, uint8_t *data,
225 uint32_t numbytes, uint32_t i2c_flag)
227 struct amdgpu_device *adev = to_amdgpu_device(control);
228 uint32_t bytes_sent, reg, ret = 0;
229 unsigned long timeout_counter;
233 DRM_DEBUG_DRIVER("I2C_Transmit(), address = %x, bytes = %d , data: ",
234 (uint16_t)address, numbytes);
236 if (drm_debug_enabled(DRM_UT_DRIVER)) {
237 print_hex_dump(KERN_INFO, "data: ", DUMP_PREFIX_NONE,
238 16, 1, data, numbytes, false);
241 /* Set the I2C slave address */
242 smu_v11_0_i2c_set_address(control, address);
244 smu_v11_0_i2c_enable(control, true);
246 /* Clear status bits */
247 smu_v11_0_i2c_clear_status(control);
250 timeout_counter = jiffies + msecs_to_jiffies(20);
252 while (numbytes > 0) {
253 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
254 if (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF)) {
258 * Prepare transaction, no need to set RESTART. I2C engine will send
259 * START as soon as it sees data in TXFIFO
262 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, RESTART,
263 (i2c_flag & I2C_RESTART) ? 1 : 0);
264 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT, data[bytes_sent]);
266 /* determine if we need to send STOP bit or not */
268 /* Final transaction, so send stop unless I2C_NO_STOP */
269 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, STOP,
270 (i2c_flag & I2C_NO_STOP) ? 0 : 1);
272 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, CMD, 0);
273 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD, reg);
275 /* Record that the bytes were transmitted */
279 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
281 } while (numbytes && REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF));
285 * We waited too long for the transmission FIFO to become not-full.
286 * Exit the loop with error.
288 if (time_after(jiffies, timeout_counter)) {
289 ret |= I2C_SW_TIMEOUT;
294 ret = smu_v11_0_i2c_poll_tx_status(control);
297 /* Any error, no point in proceeding */
299 if (ret & I2C_SW_TIMEOUT)
300 DRM_ERROR("TIMEOUT ERROR !!!");
302 if (ret & I2C_NAK_7B_ADDR_NOACK)
303 DRM_ERROR("Received I2C_NAK_7B_ADDR_NOACK !!!");
306 if (ret & I2C_NAK_TXDATA_NOACK)
307 DRM_ERROR("Received I2C_NAK_TXDATA_NOACK !!!");
315 * smu_v11_0_i2c_receive - Receive a block of data over the I2C bus from a slave device.
317 * @control: I2C adapter reference
318 * @address: The I2C address of the slave device.
319 * @data: Placeholder to store received data.
320 * @numbytes: The amount of data to transmit.
321 * @i2c_flag: Flags for transmission
323 * Returns 0 on success or error.
325 static uint32_t smu_v11_0_i2c_receive(struct i2c_adapter *control,
326 uint8_t address, uint8_t *data,
327 uint32_t numbytes, uint8_t i2c_flag)
329 struct amdgpu_device *adev = to_amdgpu_device(control);
330 uint32_t bytes_received, ret = I2C_OK;
334 /* Set the I2C slave address */
335 smu_v11_0_i2c_set_address(control, address);
338 smu_v11_0_i2c_enable(control, true);
340 while (numbytes > 0) {
343 smu_v11_0_i2c_clear_status(control);
346 /* Prepare transaction */
348 /* Each time we disable I2C, so this is not a restart */
349 if (bytes_received == 0)
350 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, RESTART,
351 (i2c_flag & I2C_RESTART) ? 1 : 0);
353 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT, 0);
355 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, CMD, 1);
357 /* Transmitting last byte */
359 /* Final transaction, so send stop if requested */
360 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, STOP,
361 (i2c_flag & I2C_NO_STOP) ? 0 : 1);
363 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD, reg);
365 ret = smu_v11_0_i2c_poll_rx_status(control);
367 /* Any error, no point in proceeding */
369 if (ret & I2C_SW_TIMEOUT)
370 DRM_ERROR("TIMEOUT ERROR !!!");
372 if (ret & I2C_NAK_7B_ADDR_NOACK)
373 DRM_ERROR("Received I2C_NAK_7B_ADDR_NOACK !!!");
375 if (ret & I2C_NAK_TXDATA_NOACK)
376 DRM_ERROR("Received I2C_NAK_TXDATA_NOACK !!!");
381 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD);
382 data[bytes_received] = REG_GET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT);
384 /* Record that the bytes were received */
389 DRM_DEBUG_DRIVER("I2C_Receive(), address = %x, bytes = %d, data :",
390 (uint16_t)address, bytes_received);
392 if (drm_debug_enabled(DRM_UT_DRIVER)) {
393 print_hex_dump(KERN_INFO, "data: ", DUMP_PREFIX_NONE,
394 16, 1, data, bytes_received, false);
400 static void smu_v11_0_i2c_abort(struct i2c_adapter *control)
402 struct amdgpu_device *adev = to_amdgpu_device(control);
405 /* Enable I2C engine; */
406 reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ENABLE, 1);
407 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, reg);
409 /* Abort previous transaction */
410 reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ABORT, 1);
411 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, reg);
413 DRM_DEBUG_DRIVER("I2C_Abort() Done.");
417 static bool smu_v11_0_i2c_activity_done(struct i2c_adapter *control)
419 struct amdgpu_device *adev = to_amdgpu_device(control);
421 const uint32_t IDLE_TIMEOUT = 1024;
422 uint32_t timeout_count = 0;
423 uint32_t reg_ic_enable, reg_ic_enable_status, reg_ic_clr_activity;
425 reg_ic_enable_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE_STATUS);
426 reg_ic_enable = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE);
429 if ((REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) &&
430 (REG_GET_FIELD(reg_ic_enable_status, CKSVII2C_IC_ENABLE_STATUS, IC_EN) == 1)) {
432 * Nobody is using I2C engine, but engine remains active because
433 * someone missed to send STOP
435 smu_v11_0_i2c_abort(control);
436 } else if (REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) {
437 /* Nobody is using I2C engine */
441 /* Keep reading activity bit until it's cleared */
443 reg_ic_clr_activity = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_ACTIVITY);
445 if (REG_GET_FIELD(reg_ic_clr_activity,
446 CKSVII2C_IC_CLR_ACTIVITY, CLR_ACTIVITY) == 0)
451 } while (timeout_count < IDLE_TIMEOUT);
456 static void smu_v11_0_i2c_init(struct i2c_adapter *control)
458 /* Disable clock gating */
459 smu_v11_0_i2c_set_clock_gating(control, false);
461 if (!smu_v11_0_i2c_activity_done(control))
462 DRM_WARN("I2C busy !");
465 smu_v11_0_i2c_enable(control, false);
467 /* Configure I2C to operate as master and in standard mode */
468 smu_v11_0_i2c_configure(control);
470 /* Initialize the clock to 50 kHz default */
471 smu_v11_0_i2c_set_clock(control);
475 static void smu_v11_0_i2c_fini(struct i2c_adapter *control)
477 struct amdgpu_device *adev = to_amdgpu_device(control);
478 uint32_t reg_ic_enable_status, reg_ic_enable;
480 smu_v11_0_i2c_enable(control, false);
482 /* Double check if disabled, else force abort */
483 reg_ic_enable_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE_STATUS);
484 reg_ic_enable = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE);
486 if ((REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) &&
487 (REG_GET_FIELD(reg_ic_enable_status,
488 CKSVII2C_IC_ENABLE_STATUS, IC_EN) == 1)) {
490 * Nobody is using I2C engine, but engine remains active because
491 * someone missed to send STOP
493 smu_v11_0_i2c_abort(control);
496 /* Restore clock gating */
499 * TODO Reenabling clock gating seems to break subsequent SMU operation
500 * on the I2C bus. My guess is that SMU doesn't disable clock gating like
501 * we do here before working with the bus. So for now just don't restore
502 * it but later work with SMU to see if they have this issue and can
503 * update their code appropriately
505 /* smu_v11_0_i2c_set_clock_gating(control, true); */
509 static bool smu_v11_0_i2c_bus_lock(struct i2c_adapter *control)
511 struct amdgpu_device *adev = to_amdgpu_device(control);
513 /* Send PPSMC_MSG_RequestI2CBus */
514 if (!amdgpu_dpm_smu_i2c_bus_access(adev, true))
520 static bool smu_v11_0_i2c_bus_unlock(struct i2c_adapter *control)
522 struct amdgpu_device *adev = to_amdgpu_device(control);
524 /* Send PPSMC_MSG_ReleaseI2CBus */
525 if (!amdgpu_dpm_smu_i2c_bus_access(adev, false))
531 /***************************** I2C GLUE ****************************/
533 static uint32_t smu_v11_0_i2c_read_data(struct i2c_adapter *control,
540 /* First 2 bytes are dummy write to set EEPROM address */
541 ret = smu_v11_0_i2c_transmit(control, address, data, 2, I2C_NO_STOP);
545 /* Now read data starting with that address */
546 ret = smu_v11_0_i2c_receive(control, address, data + 2, numbytes - 2,
551 DRM_ERROR("ReadData() - I2C error occurred :%x", ret);
556 static uint32_t smu_v11_0_i2c_write_data(struct i2c_adapter *control,
563 ret = smu_v11_0_i2c_transmit(control, address, data, numbytes, 0);
566 DRM_ERROR("WriteI2CData() - I2C error occurred :%x", ret);
569 * According to EEPROM spec there is a MAX of 10 ms required for
570 * EEPROM to flush internal RX buffer after STOP was issued at the
571 * end of write transaction. During this time the EEPROM will not be
572 * responsive to any more commands - so wait a bit more.
574 * TODO Improve to wait for first ACK for slave address after
575 * internal write cycle done.
583 static void lock_bus(struct i2c_adapter *i2c, unsigned int flags)
585 struct amdgpu_device *adev = to_amdgpu_device(i2c);
587 if (!smu_v11_0_i2c_bus_lock(i2c)) {
588 DRM_ERROR("Failed to lock the bus from SMU");
592 adev->pm.bus_locked = true;
595 static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags)
597 WARN_ONCE(1, "This operation not supposed to run in atomic context!");
601 static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags)
603 struct amdgpu_device *adev = to_amdgpu_device(i2c);
605 if (!smu_v11_0_i2c_bus_unlock(i2c)) {
606 DRM_ERROR("Failed to unlock the bus from SMU");
610 adev->pm.bus_locked = false;
613 static const struct i2c_lock_operations smu_v11_0_i2c_i2c_lock_ops = {
614 .lock_bus = lock_bus,
615 .trylock_bus = trylock_bus,
616 .unlock_bus = unlock_bus,
619 static int smu_v11_0_i2c_xfer(struct i2c_adapter *i2c_adap,
620 struct i2c_msg *msgs, int num)
623 struct amdgpu_device *adev = to_amdgpu_device(i2c_adap);
625 if (!adev->pm.bus_locked) {
626 DRM_ERROR("I2C bus unlocked, stopping transaction!");
630 smu_v11_0_i2c_init(i2c_adap);
632 for (i = 0; i < num; i++) {
633 if (msgs[i].flags & I2C_M_RD)
634 ret = smu_v11_0_i2c_read_data(i2c_adap,
635 (uint8_t)msgs[i].addr,
636 msgs[i].buf, msgs[i].len);
638 ret = smu_v11_0_i2c_write_data(i2c_adap,
639 (uint8_t)msgs[i].addr,
640 msgs[i].buf, msgs[i].len);
648 smu_v11_0_i2c_fini(i2c_adap);
652 static u32 smu_v11_0_i2c_func(struct i2c_adapter *adap)
654 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
658 static const struct i2c_algorithm smu_v11_0_i2c_algo = {
659 .master_xfer = smu_v11_0_i2c_xfer,
660 .functionality = smu_v11_0_i2c_func,
663 int smu_v11_0_i2c_control_init(struct i2c_adapter *control)
665 struct amdgpu_device *adev = to_amdgpu_device(control);
668 control->owner = THIS_MODULE;
669 control->class = I2C_CLASS_SPD;
670 control->dev.parent = &adev->pdev->dev;
671 control->algo = &smu_v11_0_i2c_algo;
672 snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
673 control->lock_ops = &smu_v11_0_i2c_i2c_lock_ops;
675 res = i2c_add_adapter(control);
677 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
682 void smu_v11_0_i2c_control_fini(struct i2c_adapter *control)
684 i2c_del_adapter(control);
688 * Keep this for future unit test if bugs arise
691 #define I2C_TARGET_ADDR 0xA0
693 bool smu_v11_0_i2c_test_bus(struct i2c_adapter *control)
696 uint32_t ret = I2C_OK;
697 uint8_t data[6] = {0xf, 0, 0xde, 0xad, 0xbe, 0xef};
702 if (!smu_v11_0_i2c_bus_lock(control)) {
703 DRM_ERROR("Failed to lock the bus!.");
707 smu_v11_0_i2c_init(control);
709 /* Write 0xde to address 0x0000 on the EEPROM */
710 ret = smu_v11_0_i2c_write_data(control, I2C_TARGET_ADDR, data, 6);
712 ret = smu_v11_0_i2c_read_data(control, I2C_TARGET_ADDR, data, 6);
714 smu_v11_0_i2c_fini(control);
716 smu_v11_0_i2c_bus_unlock(control);