2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include "smuio/smuio_11_0_0_offset.h"
25 #include "smuio/smuio_11_0_0_sh_mask.h"
27 #include "smu_v11_0_i2c.h"
29 #include "soc15_common.h"
30 #include <drm/drm_fixed.h>
31 #include <drm/drm_drv.h>
32 #include "amdgpu_amdkfd.h"
33 #include <linux/i2c.h>
34 #include <linux/pci.h>
35 #include "amdgpu_ras.h"
39 #define I2C_NAK_7B_ADDR_NOACK 1
40 #define I2C_NAK_TXDATA_NOACK 2
42 #define I2C_SW_TIMEOUT 8
43 #define I2C_ABORT 0x10
45 /* I2C transaction flags */
49 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
51 static void smu_v11_0_i2c_set_clock_gating(struct i2c_adapter *control, bool en)
53 struct amdgpu_device *adev = to_amdgpu_device(control);
54 uint32_t reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT);
56 reg = REG_SET_FIELD(reg, SMUIO_PWRMGT, i2c_clk_gate_en, en ? 1 : 0);
57 WREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT, reg);
61 static void smu_v11_0_i2c_enable(struct i2c_adapter *control, bool enable)
63 struct amdgpu_device *adev = to_amdgpu_device(control);
65 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, enable ? 1 : 0);
68 static void smu_v11_0_i2c_clear_status(struct i2c_adapter *control)
70 struct amdgpu_device *adev = to_amdgpu_device(control);
73 RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_INTR);
75 } /* while (reg_CKSVII2C_ic_clr_intr == 0) */
78 static void smu_v11_0_i2c_configure(struct i2c_adapter *control)
80 struct amdgpu_device *adev = to_amdgpu_device(control);
83 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_SLAVE_DISABLE, 1);
84 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_RESTART_EN, 1);
85 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_10BITADDR_MASTER, 0);
86 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_10BITADDR_SLAVE, 0);
88 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_MAX_SPEED_MODE, 2);
89 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_MASTER_MODE, 1);
91 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CON, reg);
94 static void smu_v11_0_i2c_set_clock(struct i2c_adapter *control)
96 struct amdgpu_device *adev = to_amdgpu_device(control);
99 * Standard mode speed, These values are taken from SMUIO MAS,
100 * but are different from what is given is
101 * Synopsys spec. The values here are based on assumption
102 * that refclock is 100MHz
104 * Configuration for standard mode; Speed = 100kbps
105 * Scale linearly, for now only support standard speed clock
106 * This will work only with 100M ref clock
108 * TBD:Change the calculation to take into account ref clock values also.
111 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_FS_SPKLEN, 2);
112 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SS_SCL_HCNT, 120);
113 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SS_SCL_LCNT, 130);
114 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SDA_HOLD, 20);
117 static void smu_v11_0_i2c_set_address(struct i2c_adapter *control, uint8_t address)
119 struct amdgpu_device *adev = to_amdgpu_device(control);
121 /* Convert fromr 8-bit to 7-bit address */
123 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TAR, (address & 0xFF));
126 static uint32_t smu_v11_0_i2c_poll_tx_status(struct i2c_adapter *control)
128 struct amdgpu_device *adev = to_amdgpu_device(control);
129 uint32_t ret = I2C_OK;
130 uint32_t reg, reg_c_tx_abrt_source;
132 /*Check if transmission is completed */
133 unsigned long timeout_counter = jiffies + msecs_to_jiffies(20);
136 if (time_after(jiffies, timeout_counter)) {
137 ret |= I2C_SW_TIMEOUT;
141 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
143 } while (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFE) == 0);
148 /* This only checks if NAK is received and transaction got aborted */
149 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_INTR_STAT);
151 if (REG_GET_FIELD(reg, CKSVII2C_IC_INTR_STAT, R_TX_ABRT) == 1) {
152 reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE);
153 DRM_INFO("TX was terminated, IC_TX_ABRT_SOURCE val is:%x", reg_c_tx_abrt_source);
155 /* Check for stop due to NACK */
156 if (REG_GET_FIELD(reg_c_tx_abrt_source,
157 CKSVII2C_IC_TX_ABRT_SOURCE,
158 ABRT_TXDATA_NOACK) == 1) {
160 ret |= I2C_NAK_TXDATA_NOACK;
162 } else if (REG_GET_FIELD(reg_c_tx_abrt_source,
163 CKSVII2C_IC_TX_ABRT_SOURCE,
164 ABRT_7B_ADDR_NOACK) == 1) {
166 ret |= I2C_NAK_7B_ADDR_NOACK;
171 smu_v11_0_i2c_clear_status(control);
177 static uint32_t smu_v11_0_i2c_poll_rx_status(struct i2c_adapter *control)
179 struct amdgpu_device *adev = to_amdgpu_device(control);
180 uint32_t ret = I2C_OK;
181 uint32_t reg_ic_status, reg_c_tx_abrt_source;
183 reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE);
185 /* If slave is not present */
186 if (REG_GET_FIELD(reg_c_tx_abrt_source,
187 CKSVII2C_IC_TX_ABRT_SOURCE,
188 ABRT_7B_ADDR_NOACK) == 1) {
189 ret |= I2C_NAK_7B_ADDR_NOACK;
191 smu_v11_0_i2c_clear_status(control);
192 } else { /* wait till some data is there in RXFIFO */
193 /* Poll for some byte in RXFIFO */
194 unsigned long timeout_counter = jiffies + msecs_to_jiffies(20);
197 if (time_after(jiffies, timeout_counter)) {
198 ret |= I2C_SW_TIMEOUT;
202 reg_ic_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
204 } while (REG_GET_FIELD(reg_ic_status, CKSVII2C_IC_STATUS, RFNE) == 0);
214 * smu_v11_0_i2c_transmit - Send a block of data over the I2C bus to a slave device.
216 * @address: The I2C address of the slave device.
217 * @data: The data to transmit over the bus.
218 * @numbytes: The amount of data to transmit.
219 * @i2c_flag: Flags for transmission
221 * Returns 0 on success or error.
223 static uint32_t smu_v11_0_i2c_transmit(struct i2c_adapter *control,
224 uint8_t address, uint8_t *data,
225 uint32_t numbytes, uint32_t i2c_flag)
227 struct amdgpu_device *adev = to_amdgpu_device(control);
228 uint32_t bytes_sent, reg, ret = 0;
229 unsigned long timeout_counter;
233 DRM_DEBUG_DRIVER("I2C_Transmit(), address = %x, bytes = %d , data: ",
234 (uint16_t)address, numbytes);
236 if (drm_debug_enabled(DRM_UT_DRIVER)) {
237 print_hex_dump(KERN_INFO, "data: ", DUMP_PREFIX_NONE,
238 16, 1, data, numbytes, false);
241 /* Set the I2C slave address */
242 smu_v11_0_i2c_set_address(control, address);
244 smu_v11_0_i2c_enable(control, true);
246 /* Clear status bits */
247 smu_v11_0_i2c_clear_status(control);
250 timeout_counter = jiffies + msecs_to_jiffies(20);
252 while (numbytes > 0) {
253 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
254 if (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF)) {
258 * Prepare transaction, no need to set RESTART. I2C engine will send
259 * START as soon as it sees data in TXFIFO
262 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, RESTART,
263 (i2c_flag & I2C_RESTART) ? 1 : 0);
264 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT, data[bytes_sent]);
266 /* determine if we need to send STOP bit or not */
268 /* Final transaction, so send stop unless I2C_NO_STOP */
269 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, STOP,
270 (i2c_flag & I2C_NO_STOP) ? 0 : 1);
272 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, CMD, 0);
273 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD, reg);
275 /* Record that the bytes were transmitted */
279 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
281 } while (numbytes && REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF));
285 * We waited too long for the transmission FIFO to become not-full.
286 * Exit the loop with error.
288 if (time_after(jiffies, timeout_counter)) {
289 ret |= I2C_SW_TIMEOUT;
294 ret = smu_v11_0_i2c_poll_tx_status(control);
297 /* Any error, no point in proceeding */
299 if (ret & I2C_SW_TIMEOUT)
300 DRM_ERROR("TIMEOUT ERROR !!!");
302 if (ret & I2C_NAK_7B_ADDR_NOACK)
303 DRM_ERROR("Received I2C_NAK_7B_ADDR_NOACK !!!");
306 if (ret & I2C_NAK_TXDATA_NOACK)
307 DRM_ERROR("Received I2C_NAK_TXDATA_NOACK !!!");
315 * smu_v11_0_i2c_receive - Receive a block of data over the I2C bus from a slave device.
317 * @address: The I2C address of the slave device.
318 * @numbytes: The amount of data to transmit.
319 * @i2c_flag: Flags for transmission
321 * Returns 0 on success or error.
323 static uint32_t smu_v11_0_i2c_receive(struct i2c_adapter *control,
324 uint8_t address, uint8_t *data,
325 uint32_t numbytes, uint8_t i2c_flag)
327 struct amdgpu_device *adev = to_amdgpu_device(control);
328 uint32_t bytes_received, ret = I2C_OK;
332 /* Set the I2C slave address */
333 smu_v11_0_i2c_set_address(control, address);
336 smu_v11_0_i2c_enable(control, true);
338 while (numbytes > 0) {
341 smu_v11_0_i2c_clear_status(control);
344 /* Prepare transaction */
346 /* Each time we disable I2C, so this is not a restart */
347 if (bytes_received == 0)
348 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, RESTART,
349 (i2c_flag & I2C_RESTART) ? 1 : 0);
351 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT, 0);
353 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, CMD, 1);
355 /* Transmitting last byte */
357 /* Final transaction, so send stop if requested */
358 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, STOP,
359 (i2c_flag & I2C_NO_STOP) ? 0 : 1);
361 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD, reg);
363 ret = smu_v11_0_i2c_poll_rx_status(control);
365 /* Any error, no point in proceeding */
367 if (ret & I2C_SW_TIMEOUT)
368 DRM_ERROR("TIMEOUT ERROR !!!");
370 if (ret & I2C_NAK_7B_ADDR_NOACK)
371 DRM_ERROR("Received I2C_NAK_7B_ADDR_NOACK !!!");
373 if (ret & I2C_NAK_TXDATA_NOACK)
374 DRM_ERROR("Received I2C_NAK_TXDATA_NOACK !!!");
379 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD);
380 data[bytes_received] = REG_GET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT);
382 /* Record that the bytes were received */
387 DRM_DEBUG_DRIVER("I2C_Receive(), address = %x, bytes = %d, data :",
388 (uint16_t)address, bytes_received);
390 if (drm_debug_enabled(DRM_UT_DRIVER)) {
391 print_hex_dump(KERN_INFO, "data: ", DUMP_PREFIX_NONE,
392 16, 1, data, bytes_received, false);
398 static void smu_v11_0_i2c_abort(struct i2c_adapter *control)
400 struct amdgpu_device *adev = to_amdgpu_device(control);
403 /* Enable I2C engine; */
404 reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ENABLE, 1);
405 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, reg);
407 /* Abort previous transaction */
408 reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ABORT, 1);
409 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, reg);
411 DRM_DEBUG_DRIVER("I2C_Abort() Done.");
415 static bool smu_v11_0_i2c_activity_done(struct i2c_adapter *control)
417 struct amdgpu_device *adev = to_amdgpu_device(control);
419 const uint32_t IDLE_TIMEOUT = 1024;
420 uint32_t timeout_count = 0;
421 uint32_t reg_ic_enable, reg_ic_enable_status, reg_ic_clr_activity;
423 reg_ic_enable_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE_STATUS);
424 reg_ic_enable = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE);
427 if ((REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) &&
428 (REG_GET_FIELD(reg_ic_enable_status, CKSVII2C_IC_ENABLE_STATUS, IC_EN) == 1)) {
430 * Nobody is using I2C engine, but engine remains active because
431 * someone missed to send STOP
433 smu_v11_0_i2c_abort(control);
434 } else if (REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) {
435 /* Nobody is using I2C engine */
439 /* Keep reading activity bit until it's cleared */
441 reg_ic_clr_activity = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_ACTIVITY);
443 if (REG_GET_FIELD(reg_ic_clr_activity,
444 CKSVII2C_IC_CLR_ACTIVITY, CLR_ACTIVITY) == 0)
449 } while (timeout_count < IDLE_TIMEOUT);
454 static void smu_v11_0_i2c_init(struct i2c_adapter *control)
456 /* Disable clock gating */
457 smu_v11_0_i2c_set_clock_gating(control, false);
459 if (!smu_v11_0_i2c_activity_done(control))
460 DRM_WARN("I2C busy !");
463 smu_v11_0_i2c_enable(control, false);
465 /* Configure I2C to operate as master and in standard mode */
466 smu_v11_0_i2c_configure(control);
468 /* Initialize the clock to 50 kHz default */
469 smu_v11_0_i2c_set_clock(control);
473 static void smu_v11_0_i2c_fini(struct i2c_adapter *control)
475 struct amdgpu_device *adev = to_amdgpu_device(control);
476 uint32_t reg_ic_enable_status, reg_ic_enable;
478 smu_v11_0_i2c_enable(control, false);
480 /* Double check if disabled, else force abort */
481 reg_ic_enable_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE_STATUS);
482 reg_ic_enable = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE);
484 if ((REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) &&
485 (REG_GET_FIELD(reg_ic_enable_status,
486 CKSVII2C_IC_ENABLE_STATUS, IC_EN) == 1)) {
488 * Nobody is using I2C engine, but engine remains active because
489 * someone missed to send STOP
491 smu_v11_0_i2c_abort(control);
494 /* Restore clock gating */
497 * TODO Reenabling clock gating seems to break subsequent SMU operation
498 * on the I2C bus. My guess is that SMU doesn't disable clock gating like
499 * we do here before working with the bus. So for now just don't restore
500 * it but later work with SMU to see if they have this issue and can
501 * update their code appropriately
503 /* smu_v11_0_i2c_set_clock_gating(control, true); */
507 static bool smu_v11_0_i2c_bus_lock(struct i2c_adapter *control)
509 struct amdgpu_device *adev = to_amdgpu_device(control);
511 /* Send PPSMC_MSG_RequestI2CBus */
512 if (!adev->powerplay.pp_funcs->smu_i2c_bus_access)
516 if (!adev->powerplay.pp_funcs->smu_i2c_bus_access(adev->powerplay.pp_handle, true))
523 static bool smu_v11_0_i2c_bus_unlock(struct i2c_adapter *control)
525 struct amdgpu_device *adev = to_amdgpu_device(control);
527 /* Send PPSMC_MSG_RequestI2CBus */
528 if (!adev->powerplay.pp_funcs->smu_i2c_bus_access)
531 /* Send PPSMC_MSG_ReleaseI2CBus */
532 if (!adev->powerplay.pp_funcs->smu_i2c_bus_access(adev->powerplay.pp_handle,
540 /***************************** EEPROM I2C GLUE ****************************/
542 static uint32_t smu_v11_0_i2c_eeprom_read_data(struct i2c_adapter *control,
549 /* First 2 bytes are dummy write to set EEPROM address */
550 ret = smu_v11_0_i2c_transmit(control, address, data, 2, I2C_NO_STOP);
554 /* Now read data starting with that address */
555 ret = smu_v11_0_i2c_receive(control, address, data + 2, numbytes - 2,
560 DRM_ERROR("ReadData() - I2C error occurred :%x", ret);
565 static uint32_t smu_v11_0_i2c_eeprom_write_data(struct i2c_adapter *control,
572 ret = smu_v11_0_i2c_transmit(control, address, data, numbytes, 0);
575 DRM_ERROR("WriteI2CData() - I2C error occurred :%x", ret);
578 * According to EEPROM spec there is a MAX of 10 ms required for
579 * EEPROM to flush internal RX buffer after STOP was issued at the
580 * end of write transaction. During this time the EEPROM will not be
581 * responsive to any more commands - so wait a bit more.
583 * TODO Improve to wait for first ACK for slave address after
584 * internal write cycle done.
592 static void lock_bus(struct i2c_adapter *i2c, unsigned int flags)
594 struct amdgpu_device *adev = to_amdgpu_device(i2c);
595 struct amdgpu_ras_eeprom_control *control = &adev->psp.ras.ras->eeprom_control;
597 if (!smu_v11_0_i2c_bus_lock(i2c)) {
598 DRM_ERROR("Failed to lock the bus from SMU");
602 control->bus_locked = true;
605 static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags)
607 WARN_ONCE(1, "This operation not supposed to run in atomic context!");
611 static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags)
613 struct amdgpu_device *adev = to_amdgpu_device(i2c);
614 struct amdgpu_ras_eeprom_control *control = &adev->psp.ras.ras->eeprom_control;
616 if (!smu_v11_0_i2c_bus_unlock(i2c)) {
617 DRM_ERROR("Failed to unlock the bus from SMU");
621 control->bus_locked = false;
624 static const struct i2c_lock_operations smu_v11_0_i2c_i2c_lock_ops = {
625 .lock_bus = lock_bus,
626 .trylock_bus = trylock_bus,
627 .unlock_bus = unlock_bus,
630 static int smu_v11_0_i2c_eeprom_i2c_xfer(struct i2c_adapter *i2c_adap,
631 struct i2c_msg *msgs, int num)
634 struct amdgpu_device *adev = to_amdgpu_device(i2c_adap);
635 struct amdgpu_ras_eeprom_control *control = &adev->psp.ras.ras->eeprom_control;
637 if (!control->bus_locked) {
638 DRM_ERROR("I2C bus unlocked, stopping transaction!");
642 smu_v11_0_i2c_init(i2c_adap);
644 for (i = 0; i < num; i++) {
645 if (msgs[i].flags & I2C_M_RD)
646 ret = smu_v11_0_i2c_eeprom_read_data(i2c_adap,
647 (uint8_t)msgs[i].addr,
648 msgs[i].buf, msgs[i].len);
650 ret = smu_v11_0_i2c_eeprom_write_data(i2c_adap,
651 (uint8_t)msgs[i].addr,
652 msgs[i].buf, msgs[i].len);
660 smu_v11_0_i2c_fini(i2c_adap);
664 static u32 smu_v11_0_i2c_eeprom_i2c_func(struct i2c_adapter *adap)
666 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
670 static const struct i2c_algorithm smu_v11_0_i2c_eeprom_i2c_algo = {
671 .master_xfer = smu_v11_0_i2c_eeprom_i2c_xfer,
672 .functionality = smu_v11_0_i2c_eeprom_i2c_func,
675 int smu_v11_0_i2c_eeprom_control_init(struct i2c_adapter *control)
677 struct amdgpu_device *adev = to_amdgpu_device(control);
680 control->owner = THIS_MODULE;
681 control->class = I2C_CLASS_SPD;
682 control->dev.parent = &adev->pdev->dev;
683 control->algo = &smu_v11_0_i2c_eeprom_i2c_algo;
684 snprintf(control->name, sizeof(control->name), "AMDGPU EEPROM");
685 control->lock_ops = &smu_v11_0_i2c_i2c_lock_ops;
687 res = i2c_add_adapter(control);
689 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
694 void smu_v11_0_i2c_eeprom_control_fini(struct i2c_adapter *control)
696 i2c_del_adapter(control);
700 * Keep this for future unit test if bugs arise
703 #define I2C_TARGET_ADDR 0xA0
705 bool smu_v11_0_i2c_test_bus(struct i2c_adapter *control)
708 uint32_t ret = I2C_OK;
709 uint8_t data[6] = {0xf, 0, 0xde, 0xad, 0xbe, 0xef};
714 if (!smu_v11_0_i2c_bus_lock(control)) {
715 DRM_ERROR("Failed to lock the bus!.");
719 smu_v11_0_i2c_init(control);
721 /* Write 0xde to address 0x0000 on the EEPROM */
722 ret = smu_v11_0_i2c_eeprom_write_data(control, I2C_TARGET_ADDR, data, 6);
724 ret = smu_v11_0_i2c_eeprom_read_data(control, I2C_TARGET_ADDR, data, 6);
726 smu_v11_0_i2c_fini(control);
728 smu_v11_0_i2c_bus_unlock(control);