drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_ucode.h"
  31 #include "amdgpu_trace.h"
  32
  33 #include "gc/gc_11_0_0_offset.h"
  34 #include "gc/gc_11_0_0_sh_mask.h"
  35 #include "gc/gc_11_0_0_default.h"
  36 #include "hdp/hdp_6_0_0_offset.h"
  37 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"
  38
  39 #include "soc15_common.h"
  40 #include "soc15.h"
  41 #include "sdma_v6_0_0_pkt_open.h"
  42 #include "nbio_v4_3.h"
  43 #include "sdma_common.h"
  44 #include "sdma_v6_0.h"
  45 #include "v11_structs.h"
  46
  47 MODULE_FIRMWARE("amdgpu/sdma_6_0_0.bin");
  48 MODULE_FIRMWARE("amdgpu/sdma_6_0_1.bin");
  49 MODULE_FIRMWARE("amdgpu/sdma_6_0_2.bin");
  50 MODULE_FIRMWARE("amdgpu/sdma_6_0_3.bin");
  51 MODULE_FIRMWARE("amdgpu/sdma_6_1_0.bin");
  52
  53 #define SDMA1_REG_OFFSET 0x600
  54 #define SDMA0_HYP_DEC_REG_START 0x5880
  55 #define SDMA0_HYP_DEC_REG_END 0x589a
  56 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
  57
  58 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev);
  59 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev);
  60 static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  61 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev);
  62 static int sdma_v6_0_start(struct amdgpu_device *adev);
  63
  64 static u32 sdma_v6_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
  65 {
  66         u32 base;
  67
  68         if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
  69             internal_offset <= SDMA0_HYP_DEC_REG_END) {
  70                 base = adev->reg_offset[GC_HWIP][0][1];
  71                 if (instance != 0)
  72                         internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
  73         } else {
  74                 base = adev->reg_offset[GC_HWIP][0][0];
  75                 if (instance == 1)
  76                         internal_offset += SDMA1_REG_OFFSET;
  77         }
  78
  79         return base + internal_offset;
  80 }
  81
  82 static unsigned sdma_v6_0_ring_init_cond_exec(struct amdgpu_ring *ring)
  83 {
  84         unsigned ret;
  85
  86         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE));
  87         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
  88         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
  89         amdgpu_ring_write(ring, 1);
  90         ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
  91         amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
  92
  93         return ret;
  94 }
  95
  96 static void sdma_v6_0_ring_patch_cond_exec(struct amdgpu_ring *ring,
  97                                            unsigned offset)
  98 {
  99         unsigned cur;
 100
 101         BUG_ON(offset > ring->buf_mask);
 102         BUG_ON(ring->ring[offset] != 0x55aa55aa);
 103
 104         cur = (ring->wptr - 1) & ring->buf_mask;
 105         if (cur > offset)
 106                 ring->ring[offset] = cur - offset;
 107         else
 108                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
 109 }
 110
 111 /**
 112  * sdma_v6_0_ring_get_rptr - get the current read pointer
 113  *
 114  * @ring: amdgpu ring pointer
 115  *
 116  * Get the current rptr from the hardware.
 117  */
 118 static uint64_t sdma_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
 119 {
 120         u64 *rptr;
 121
 122         /* XXX check if swapping is necessary on BE */
 123         rptr = (u64 *)ring->rptr_cpu_addr;
 124
 125         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 126         return ((*rptr) >> 2);
 127 }
 128
 129 /**
 130  * sdma_v6_0_ring_get_wptr - get the current write pointer
 131  *
 132  * @ring: amdgpu ring pointer
 133  *
 134  * Get the current wptr from the hardware.
 135  */
 136 static uint64_t sdma_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
 137 {
 138         u64 wptr = 0;
 139
 140         if (ring->use_doorbell) {
 141                 /* XXX check if swapping is necessary on BE */
 142                 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
 143                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 144         }
 145
 146         return wptr >> 2;
 147 }
 148
 149 /**
 150  * sdma_v6_0_ring_set_wptr - commit the write pointer
 151  *
 152  * @ring: amdgpu ring pointer
 153  *
 154  * Write the wptr back to the hardware.
 155  */
 156 static void sdma_v6_0_ring_set_wptr(struct amdgpu_ring *ring)
 157 {
 158         struct amdgpu_device *adev = ring->adev;
 159
 160         if (ring->use_doorbell) {
 161                 DRM_DEBUG("Using doorbell -- "
 162                           "wptr_offs == 0x%08x "
 163                           "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 164                           "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 165                           ring->wptr_offs,
 166                           lower_32_bits(ring->wptr << 2),
 167                           upper_32_bits(ring->wptr << 2));
 168                 /* XXX check if swapping is necessary on BE */
 169                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
 170                              ring->wptr << 2);
 171                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 172                           ring->doorbell_index, ring->wptr << 2);
 173                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 174         } else {
 175                 DRM_DEBUG("Not using doorbell -- "
 176                           "regSDMA%i_GFX_RB_WPTR == 0x%08x "
 177                           "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 178                           ring->me,
 179                           lower_32_bits(ring->wptr << 2),
 180                           ring->me,
 181                           upper_32_bits(ring->wptr << 2));
 182                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev,
 183                                                              ring->me, regSDMA0_QUEUE0_RB_WPTR),
 184                                 lower_32_bits(ring->wptr << 2));
 185                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev,
 186                                                              ring->me, regSDMA0_QUEUE0_RB_WPTR_HI),
 187                                 upper_32_bits(ring->wptr << 2));
 188         }
 189 }
 190
 191 static void sdma_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 192 {
 193         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 194         int i;
 195
 196         for (i = 0; i < count; i++)
 197                 if (sdma && sdma->burst_nop && (i == 0))
 198                         amdgpu_ring_write(ring, ring->funcs->nop |
 199                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 200                 else
 201                         amdgpu_ring_write(ring, ring->funcs->nop);
 202 }
 203
 204 /*
 205  * sdma_v6_0_ring_emit_ib - Schedule an IB on the DMA engine
 206  *
 207  * @ring: amdgpu ring pointer
 208  * @ib: IB object to schedule
 209  * @flags: unused
 210  * @job: job to retrieve vmid from
 211  *
 212  * Schedule an IB in the DMA ring.
 213  */
 214 static void sdma_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
 215                                    struct amdgpu_job *job,
 216                                    struct amdgpu_ib *ib,
 217                                    uint32_t flags)
 218 {
 219         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 220         uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
 221
 222         /* An IB packet must end on a 8 DW boundary--the next dword
 223          * must be on a 8-dword boundary. Our IB packet below is 6
 224          * dwords long, thus add x number of NOPs, such that, in
 225          * modular arithmetic,
 226          * wptr + 6 + x = 8k, k >= 0, which in C is,
 227          * (wptr + 6 + x) % 8 = 0.
 228          * The expression below, is a solution of x.
 229          */
 230         sdma_v6_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 231
 232         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) |
 233                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 234         /* base must be 32 byte aligned */
 235         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 236         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 237         amdgpu_ring_write(ring, ib->length_dw);
 238         amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
 239         amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
 240 }
 241
 242 /**
 243  * sdma_v6_0_ring_emit_mem_sync - flush the IB by graphics cache rinse
 244  *
 245  * @ring: amdgpu ring pointer
 246  *
 247  * flush the IB by graphics cache rinse.
 248  */
 249 static void sdma_v6_0_ring_emit_mem_sync(struct amdgpu_ring *ring)
 250 {
 251         uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
 252                             SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
 253                             SDMA_GCR_GLI_INV(1);
 254
 255         /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
 256         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_GCR_REQ));
 257         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
 258         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
 259                           SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
 260         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
 261                           SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
 262         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
 263                           SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
 264 }
 265
 266
 267 /**
 268  * sdma_v6_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 269  *
 270  * @ring: amdgpu ring pointer
 271  *
 272  * Emit an hdp flush packet on the requested DMA ring.
 273  */
 274 static void sdma_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 275 {
 276         struct amdgpu_device *adev = ring->adev;
 277         u32 ref_and_mask = 0;
 278         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 279
 280         ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
 281
 282         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 283                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 284                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 285         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
 286         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
 287         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 288         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 289         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 290                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 291 }
 292
 293 /**
 294  * sdma_v6_0_ring_emit_fence - emit a fence on the DMA ring
 295  *
 296  * @ring: amdgpu ring pointer
 297  * @addr: address
 298  * @seq: fence seq number
 299  * @flags: fence flags
 300  *
 301  * Add a DMA fence packet to the ring to write
 302  * the fence seq number and DMA trap packet to generate
 303  * an interrupt if needed.
 304  */
 305 static void sdma_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 306                                       unsigned flags)
 307 {
 308         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 309         /* write the fence */
 310         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) |
 311                           SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
 312         /* zero in first two bits */
 313         BUG_ON(addr & 0x3);
 314         amdgpu_ring_write(ring, lower_32_bits(addr));
 315         amdgpu_ring_write(ring, upper_32_bits(addr));
 316         amdgpu_ring_write(ring, lower_32_bits(seq));
 317
 318         /* optionally write high bits as well */
 319         if (write64bit) {
 320                 addr += 4;
 321                 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) |
 322                                   SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
 323                 /* zero in first two bits */
 324                 BUG_ON(addr & 0x3);
 325                 amdgpu_ring_write(ring, lower_32_bits(addr));
 326                 amdgpu_ring_write(ring, upper_32_bits(addr));
 327                 amdgpu_ring_write(ring, upper_32_bits(seq));
 328         }
 329
 330         if (flags & AMDGPU_FENCE_FLAG_INT) {
 331                 uint32_t ctx = ring->is_mes_queue ?
 332                         (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0;
 333                 /* generate an interrupt */
 334                 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_TRAP));
 335                 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx));
 336         }
 337 }
 338
 339 /**
 340  * sdma_v6_0_gfx_stop - stop the gfx async dma engines
 341  *
 342  * @adev: amdgpu_device pointer
 343  *
 344  * Stop the gfx async dma ring buffers.
 345  */
 346 static void sdma_v6_0_gfx_stop(struct amdgpu_device *adev)
 347 {
 348         u32 rb_cntl, ib_cntl;
 349         int i;
 350
 351         for (i = 0; i < adev->sdma.num_instances; i++) {
 352                 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));
 353                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0);
 354                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
 355                 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));
 356                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 0);
 357                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);
 358         }
 359 }
 360
 361 /**
 362  * sdma_v6_0_rlc_stop - stop the compute async dma engines
 363  *
 364  * @adev: amdgpu_device pointer
 365  *
 366  * Stop the compute async dma queues.
 367  */
 368 static void sdma_v6_0_rlc_stop(struct amdgpu_device *adev)
 369 {
 370         /* XXX todo */
 371 }
 372
 373 /**
 374  * sdma_v6_0_ctxempty_int_enable - enable or disable context empty interrupts
 375  *
 376  * @adev: amdgpu_device pointer
 377  * @enable: enable/disable context switching due to queue empty conditions
 378  *
 379  * Enable or disable the async dma engines queue empty context switch.
 380  */
 381 static void sdma_v6_0_ctxempty_int_enable(struct amdgpu_device *adev, bool enable)
 382 {
 383         u32 f32_cntl;
 384         int i;
 385
 386         if (!amdgpu_sriov_vf(adev)) {
 387                 for (i = 0; i < adev->sdma.num_instances; i++) {
 388                         f32_cntl = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL));
 389                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 390                                         CTXEMPTY_INT_ENABLE, enable ? 1 : 0);
 391                         WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL), f32_cntl);
 392                 }
 393         }
 394 }
 395
 396 /**
 397  * sdma_v6_0_enable - stop the async dma engines
 398  *
 399  * @adev: amdgpu_device pointer
 400  * @enable: enable/disable the DMA MEs.
 401  *
 402  * Halt or unhalt the async dma engines.
 403  */
 404 static void sdma_v6_0_enable(struct amdgpu_device *adev, bool enable)
 405 {
 406         u32 f32_cntl;
 407         int i;
 408
 409         if (!enable) {
 410                 sdma_v6_0_gfx_stop(adev);
 411                 sdma_v6_0_rlc_stop(adev);
 412         }
 413
 414         if (amdgpu_sriov_vf(adev))
 415                 return;
 416
 417         for (i = 0; i < adev->sdma.num_instances; i++) {
 418                 f32_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));
 419                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 420                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), f32_cntl);
 421         }
 422 }
 423
 424 /**
 425  * sdma_v6_0_gfx_resume - setup and start the async dma engines
 426  *
 427  * @adev: amdgpu_device pointer
 428  *
 429  * Set up the gfx DMA ring buffers and enable them.
 430  * Returns 0 for success, error for failure.
 431  */
 432 static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev)
 433 {
 434         struct amdgpu_ring *ring;
 435         u32 rb_cntl, ib_cntl;
 436         u32 rb_bufsz;
 437         u32 doorbell;
 438         u32 doorbell_offset;
 439         u32 temp;
 440         u64 wptr_gpu_addr;
 441         int i, r;
 442
 443         for (i = 0; i < adev->sdma.num_instances; i++) {
 444                 ring = &adev->sdma.instance[i].ring;
 445
 446                 if (!amdgpu_sriov_vf(adev))
 447                         WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 448
 449                 /* Set ring buffer size in dwords */
 450                 rb_bufsz = order_base_2(ring->ring_size / 4);
 451                 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));
 452                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz);
 453 #ifdef __BIG_ENDIAN
 454                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1);
 455                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL,
 456                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 457 #endif
 458                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1);
 459                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
 460
 461                 /* Initialize the ring buffer's read and write pointers */
 462                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0);
 463                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0);
 464                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0);
 465                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0);
 466
 467                 /* setup the wptr shadow polling */
 468                 wptr_gpu_addr = ring->wptr_gpu_addr;
 469                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO),
 470                        lower_32_bits(wptr_gpu_addr));
 471                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI),
 472                        upper_32_bits(wptr_gpu_addr));
 473
 474                 /* set the wb address whether it's enabled or not */
 475                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI),
 476                        upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
 477                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO),
 478                        lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
 479
 480                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 481                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0);
 482                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, F32_WPTR_POLL_ENABLE, 1);
 483
 484                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8);
 485                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);
 486
 487                 ring->wptr = 0;
 488
 489                 /* before programing wptr to a less value, need set minor_ptr_update first */
 490                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1);
 491
 492                 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 493                         WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);
 494                         WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
 495                 }
 496
 497                 doorbell = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL));
 498                 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET));
 499
 500                 if (ring->use_doorbell) {
 501                         doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);
 502                         doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET,
 503                                         OFFSET, ring->doorbell_index);
 504                 } else {
 505                         doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0);
 506                 }
 507                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell);
 508                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset);
 509
 510                 if (i == 0)
 511                         adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 512                                                       ring->doorbell_index,
 513                                                       adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances);
 514
 515                 if (amdgpu_sriov_vf(adev))
 516                         sdma_v6_0_ring_set_wptr(ring);
 517
 518                 /* set minor_ptr_update to 0 after wptr programed */
 519                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0);
 520
 521                 /* Set up RESP_MODE to non-copy addresses */
 522                 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL));
 523                 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
 524                 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
 525                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp);
 526
 527                 /* program default cache read and write policy */
 528                 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE));
 529                 /* clean read policy and write policy bits */
 530                 temp &= 0xFF0FFF;
 531                 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
 532                          (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
 533                          SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
 534                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp);
 535
 536                 if (!amdgpu_sriov_vf(adev)) {
 537                         /* unhalt engine */
 538                         temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));
 539                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 540                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, TH1_RESET, 0);
 541                         WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), temp);
 542                 }
 543
 544                 /* enable DMA RB */
 545                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1);
 546                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
 547
 548                 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));
 549                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1);
 550 #ifdef __BIG_ENDIAN
 551                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1);
 552 #endif
 553                 /* enable DMA IBs */
 554                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);
 555
 556                 if (amdgpu_sriov_vf(adev))
 557                         sdma_v6_0_enable(adev, true);
 558
 559                 r = amdgpu_ring_test_helper(ring);
 560                 if (r)
 561                         return r;
 562         }
 563
 564         return 0;
 565 }
 566
 567 /**
 568  * sdma_v6_0_rlc_resume - setup and start the async dma engines
 569  *
 570  * @adev: amdgpu_device pointer
 571  *
 572  * Set up the compute DMA queues and enable them.
 573  * Returns 0 for success, error for failure.
 574  */
 575 static int sdma_v6_0_rlc_resume(struct amdgpu_device *adev)
 576 {
 577         return 0;
 578 }
 579
 580 /**
 581  * sdma_v6_0_load_microcode - load the sDMA ME ucode
 582  *
 583  * @adev: amdgpu_device pointer
 584  *
 585  * Loads the sDMA0/1 ucode.
 586  * Returns 0 for success, -EINVAL if the ucode is not available.
 587  */
 588 static int sdma_v6_0_load_microcode(struct amdgpu_device *adev)
 589 {
 590         const struct sdma_firmware_header_v2_0 *hdr;
 591         const __le32 *fw_data;
 592         u32 fw_size;
 593         int i, j;
 594         bool use_broadcast;
 595
 596         /* halt the MEs */
 597         sdma_v6_0_enable(adev, false);
 598
 599         if (!adev->sdma.instance[0].fw)
 600                 return -EINVAL;
 601
 602         /* use broadcast mode to load SDMA microcode by default */
 603         use_broadcast = true;
 604
 605         if (use_broadcast) {
 606                 dev_info(adev->dev, "Use broadcast method to load SDMA firmware\n");
 607                 /* load Control Thread microcode */
 608                 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data;
 609                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 610                 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4;
 611
 612                 fw_data = (const __le32 *)
 613                         (adev->sdma.instance[0].fw->data +
 614                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 615
 616                 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0);
 617
 618                 for (j = 0; j < fw_size; j++) {
 619                         if (amdgpu_emu_mode == 1 && j % 500 == 0)
 620                                 msleep(1);
 621                         WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++));
 622                 }
 623
 624                 /* load Context Switch microcode */
 625                 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4;
 626
 627                 fw_data = (const __le32 *)
 628                         (adev->sdma.instance[0].fw->data +
 629                                 le32_to_cpu(hdr->ctl_ucode_offset));
 630
 631                 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0x8000);
 632
 633                 for (j = 0; j < fw_size; j++) {
 634                         if (amdgpu_emu_mode == 1 && j % 500 == 0)
 635                                 msleep(1);
 636                         WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++));
 637                 }
 638         } else {
 639                 dev_info(adev->dev, "Use legacy method to load SDMA firmware\n");
 640                 for (i = 0; i < adev->sdma.num_instances; i++) {
 641                         /* load Control Thread microcode */
 642                         hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data;
 643                         amdgpu_ucode_print_sdma_hdr(&hdr->header);
 644                         fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4;
 645
 646                         fw_data = (const __le32 *)
 647                                 (adev->sdma.instance[0].fw->data +
 648                                         le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 649
 650                         WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0);
 651
 652                         for (j = 0; j < fw_size; j++) {
 653                                 if (amdgpu_emu_mode == 1 && j % 500 == 0)
 654                                         msleep(1);
 655                                 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 656                         }
 657
 658                         WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version);
 659
 660                         /* load Context Switch microcode */
 661                         fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4;
 662
 663                         fw_data = (const __le32 *)
 664                                 (adev->sdma.instance[0].fw->data +
 665                                         le32_to_cpu(hdr->ctl_ucode_offset));
 666
 667                         WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0x8000);
 668
 669                         for (j = 0; j < fw_size; j++) {
 670                                 if (amdgpu_emu_mode == 1 && j % 500 == 0)
 671                                         msleep(1);
 672                                 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 673                         }
 674
 675                         WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version);
 676                 }
 677         }
 678
 679         return 0;
 680 }
 681
 682 static int sdma_v6_0_soft_reset(void *handle)
 683 {
 684         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 685         u32 tmp;
 686         int i;
 687
 688         sdma_v6_0_gfx_stop(adev);
 689
 690         for (i = 0; i < adev->sdma.num_instances; i++) {
 691                 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE));
 692                 tmp |= SDMA0_FREEZE__FREEZE_MASK;
 693                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp);
 694                 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));
 695                 tmp |= SDMA0_F32_CNTL__HALT_MASK;
 696                 tmp |= SDMA0_F32_CNTL__TH1_RESET_MASK;
 697                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), tmp);
 698
 699                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_PREEMPT), 0);
 700
 701                 udelay(100);
 702
 703                 tmp = GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK << i;
 704                 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp);
 705                 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
 706
 707                 udelay(100);
 708
 709                 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, 0);
 710                 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
 711
 712                 udelay(100);
 713         }
 714
 715         return sdma_v6_0_start(adev);
 716 }
 717
 718 static bool sdma_v6_0_check_soft_reset(void *handle)
 719 {
 720         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 721         struct amdgpu_ring *ring;
 722         int i, r;
 723         long tmo = msecs_to_jiffies(1000);
 724
 725         for (i = 0; i < adev->sdma.num_instances; i++) {
 726                 ring = &adev->sdma.instance[i].ring;
 727                 r = amdgpu_ring_test_ib(ring, tmo);
 728                 if (r)
 729                         return true;
 730         }
 731
 732         return false;
 733 }
 734
 735 /**
 736  * sdma_v6_0_start - setup and start the async dma engines
 737  *
 738  * @adev: amdgpu_device pointer
 739  *
 740  * Set up the DMA engines and enable them.
 741  * Returns 0 for success, error for failure.
 742  */
 743 static int sdma_v6_0_start(struct amdgpu_device *adev)
 744 {
 745         int r = 0;
 746
 747         if (amdgpu_sriov_vf(adev)) {
 748                 sdma_v6_0_enable(adev, false);
 749
 750                 /* set RB registers */
 751                 r = sdma_v6_0_gfx_resume(adev);
 752                 return r;
 753         }
 754
 755         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 756                 r = sdma_v6_0_load_microcode(adev);
 757                 if (r)
 758                         return r;
 759
 760                 /* The value of regSDMA_F32_CNTL is invalid the moment after loading fw */
 761                 if (amdgpu_emu_mode == 1)
 762                         msleep(1000);
 763         }
 764
 765         /* unhalt the MEs */
 766         sdma_v6_0_enable(adev, true);
 767         /* enable sdma ring preemption */
 768         sdma_v6_0_ctxempty_int_enable(adev, true);
 769
 770         /* start the gfx rings and rlc compute queues */
 771         r = sdma_v6_0_gfx_resume(adev);
 772         if (r)
 773                 return r;
 774         r = sdma_v6_0_rlc_resume(adev);
 775
 776         return r;
 777 }
 778
 779 static int sdma_v6_0_mqd_init(struct amdgpu_device *adev, void *mqd,
 780                               struct amdgpu_mqd_prop *prop)
 781 {
 782         struct v11_sdma_mqd *m = mqd;
 783         uint64_t wb_gpu_addr;
 784
 785         m->sdmax_rlcx_rb_cntl =
 786                 order_base_2(prop->queue_size / 4) << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT |
 787                 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
 788                 4 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |
 789                 1 << SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT;
 790
 791         m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8);
 792         m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8);
 793
 794         wb_gpu_addr = prop->wptr_gpu_addr;
 795         m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr);
 796         m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr);
 797
 798         wb_gpu_addr = prop->rptr_gpu_addr;
 799         m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr);
 800         m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr);
 801
 802         m->sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 0,
 803                                                         regSDMA0_QUEUE0_IB_CNTL));
 804
 805         m->sdmax_rlcx_doorbell_offset =
 806                 prop->doorbell_index << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT;
 807
 808         m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);
 809
 810         m->sdmax_rlcx_skip_cntl = 0;
 811         m->sdmax_rlcx_context_status = 0;
 812         m->sdmax_rlcx_doorbell_log = 0;
 813
 814         m->sdmax_rlcx_rb_aql_cntl = regSDMA0_QUEUE0_RB_AQL_CNTL_DEFAULT;
 815         m->sdmax_rlcx_dummy_reg = regSDMA0_QUEUE0_DUMMY_REG_DEFAULT;
 816
 817         return 0;
 818 }
 819
 820 static void sdma_v6_0_set_mqd_funcs(struct amdgpu_device *adev)
 821 {
 822         adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v11_sdma_mqd);
 823         adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v6_0_mqd_init;
 824 }
 825
 826 /**
 827  * sdma_v6_0_ring_test_ring - simple async dma engine test
 828  *
 829  * @ring: amdgpu_ring structure holding ring information
 830  *
 831  * Test the DMA engine by writing using it to write an
 832  * value to memory.
 833  * Returns 0 for success, error for failure.
 834  */
 835 static int sdma_v6_0_ring_test_ring(struct amdgpu_ring *ring)
 836 {
 837         struct amdgpu_device *adev = ring->adev;
 838         unsigned i;
 839         unsigned index;
 840         int r;
 841         u32 tmp;
 842         u64 gpu_addr;
 843         volatile uint32_t *cpu_ptr = NULL;
 844
 845         tmp = 0xCAFEDEAD;
 846
 847         if (ring->is_mes_queue) {
 848                 uint32_t offset = 0;
 849                 offset = amdgpu_mes_ctx_get_offs(ring,
 850                                          AMDGPU_MES_CTX_PADDING_OFFS);
 851                 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
 852                 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
 853                 *cpu_ptr = tmp;
 854         } else {
 855                 r = amdgpu_device_wb_get(adev, &index);
 856                 if (r) {
 857                         dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 858                         return r;
 859                 }
 860
 861                 gpu_addr = adev->wb.gpu_addr + (index * 4);
 862                 adev->wb.wb[index] = cpu_to_le32(tmp);
 863         }
 864
 865         r = amdgpu_ring_alloc(ring, 5);
 866         if (r) {
 867                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 868                 amdgpu_device_wb_free(adev, index);
 869                 return r;
 870         }
 871
 872         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
 873                           SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 874         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 875         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 876         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 877         amdgpu_ring_write(ring, 0xDEADBEEF);
 878         amdgpu_ring_commit(ring);
 879
 880         for (i = 0; i < adev->usec_timeout; i++) {
 881                 if (ring->is_mes_queue)
 882                         tmp = le32_to_cpu(*cpu_ptr);
 883                 else
 884                         tmp = le32_to_cpu(adev->wb.wb[index]);
 885                 if (tmp == 0xDEADBEEF)
 886                         break;
 887                 if (amdgpu_emu_mode == 1)
 888                         msleep(1);
 889                 else
 890                         udelay(1);
 891         }
 892
 893         if (i >= adev->usec_timeout)
 894                 r = -ETIMEDOUT;
 895
 896         if (!ring->is_mes_queue)
 897                 amdgpu_device_wb_free(adev, index);
 898
 899         return r;
 900 }
 901
 902 /*
 903  * sdma_v6_0_ring_test_ib - test an IB on the DMA engine
 904  *
 905  * @ring: amdgpu_ring structure holding ring information
 906  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
 907  *
 908  * Test a simple IB in the DMA ring.
 909  * Returns 0 on success, error on failure.
 910  */
 911 static int sdma_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 912 {
 913         struct amdgpu_device *adev = ring->adev;
 914         struct amdgpu_ib ib;
 915         struct dma_fence *f = NULL;
 916         unsigned index;
 917         long r;
 918         u32 tmp = 0;
 919         u64 gpu_addr;
 920         volatile uint32_t *cpu_ptr = NULL;
 921
 922         tmp = 0xCAFEDEAD;
 923         memset(&ib, 0, sizeof(ib));
 924
 925         if (ring->is_mes_queue) {
 926                 uint32_t offset = 0;
 927                 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
 928                 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
 929                 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
 930
 931                 offset = amdgpu_mes_ctx_get_offs(ring,
 932                                          AMDGPU_MES_CTX_PADDING_OFFS);
 933                 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
 934                 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
 935                 *cpu_ptr = tmp;
 936         } else {
 937                 r = amdgpu_device_wb_get(adev, &index);
 938                 if (r) {
 939                         dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 940                         return r;
 941                 }
 942
 943                 gpu_addr = adev->wb.gpu_addr + (index * 4);
 944                 adev->wb.wb[index] = cpu_to_le32(tmp);
 945
 946                 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
 947                 if (r) {
 948                         DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 949                         goto err0;
 950                 }
 951         }
 952
 953         ib.ptr[0] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
 954                 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 955         ib.ptr[1] = lower_32_bits(gpu_addr);
 956         ib.ptr[2] = upper_32_bits(gpu_addr);
 957         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
 958         ib.ptr[4] = 0xDEADBEEF;
 959         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 960         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 961         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 962         ib.length_dw = 8;
 963
 964         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 965         if (r)
 966                 goto err1;
 967
 968         r = dma_fence_wait_timeout(f, false, timeout);
 969         if (r == 0) {
 970                 DRM_ERROR("amdgpu: IB test timed out\n");
 971                 r = -ETIMEDOUT;
 972                 goto err1;
 973         } else if (r < 0) {
 974                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 975                 goto err1;
 976         }
 977
 978         if (ring->is_mes_queue)
 979                 tmp = le32_to_cpu(*cpu_ptr);
 980         else
 981                 tmp = le32_to_cpu(adev->wb.wb[index]);
 982
 983         if (tmp == 0xDEADBEEF)
 984                 r = 0;
 985         else
 986                 r = -EINVAL;
 987
 988 err1:
 989         amdgpu_ib_free(adev, &ib, NULL);
 990         dma_fence_put(f);
 991 err0:
 992         if (!ring->is_mes_queue)
 993                 amdgpu_device_wb_free(adev, index);
 994         return r;
 995 }
 996
 997
 998 /**
 999  * sdma_v6_0_vm_copy_pte - update PTEs by copying them from the GART
1000  *
1001  * @ib: indirect buffer to fill with commands
1002  * @pe: addr of the page entry
1003  * @src: src addr to copy from
1004  * @count: number of page entries to update
1005  *
1006  * Update PTEs by copying them from the GART using sDMA.
1007  */
1008 static void sdma_v6_0_vm_copy_pte(struct amdgpu_ib *ib,
1009                                   uint64_t pe, uint64_t src,
1010                                   unsigned count)
1011 {
1012         unsigned bytes = count * 8;
1013
1014         ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) |
1015                 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1016         ib->ptr[ib->length_dw++] = bytes - 1;
1017         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1018         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1019         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1020         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1021         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1022
1023 }
1024
1025 /**
1026  * sdma_v6_0_vm_write_pte - update PTEs by writing them manually
1027  *
1028  * @ib: indirect buffer to fill with commands
1029  * @pe: addr of the page entry
1030  * @value: dst addr to write into pe
1031  * @count: number of page entries to update
1032  * @incr: increase next addr by incr bytes
1033  *
1034  * Update PTEs by writing them manually using sDMA.
1035  */
1036 static void sdma_v6_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1037                                    uint64_t value, unsigned count,
1038                                    uint32_t incr)
1039 {
1040         unsigned ndw = count * 2;
1041
1042         ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
1043                 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1044         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1045         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1046         ib->ptr[ib->length_dw++] = ndw - 1;
1047         for (; ndw > 0; ndw -= 2) {
1048                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1049                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1050                 value += incr;
1051         }
1052 }
1053
1054 /**
1055  * sdma_v6_0_vm_set_pte_pde - update the page tables using sDMA
1056  *
1057  * @ib: indirect buffer to fill with commands
1058  * @pe: addr of the page entry
1059  * @addr: dst addr to write into pe
1060  * @count: number of page entries to update
1061  * @incr: increase next addr by incr bytes
1062  * @flags: access flags
1063  *
1064  * Update the page tables using sDMA.
1065  */
1066 static void sdma_v6_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1067                                      uint64_t pe,
1068                                      uint64_t addr, unsigned count,
1069                                      uint32_t incr, uint64_t flags)
1070 {
1071         /* for physically contiguous pages (vram) */
1072         ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_PTEPDE);
1073         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1074         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1075         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1076         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1077         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1078         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1079         ib->ptr[ib->length_dw++] = incr; /* increment size */
1080         ib->ptr[ib->length_dw++] = 0;
1081         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1082 }
1083
1084 /*
1085  * sdma_v6_0_ring_pad_ib - pad the IB
1086  * @ib: indirect buffer to fill with padding
1087  * @ring: amdgpu ring pointer
1088  *
1089  * Pad the IB with NOPs to a boundary multiple of 8.
1090  */
1091 static void sdma_v6_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1092 {
1093         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1094         u32 pad_count;
1095         int i;
1096
1097         pad_count = (-ib->length_dw) & 0x7;
1098         for (i = 0; i < pad_count; i++)
1099                 if (sdma && sdma->burst_nop && (i == 0))
1100                         ib->ptr[ib->length_dw++] =
1101                                 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP) |
1102                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1103                 else
1104                         ib->ptr[ib->length_dw++] =
1105                                 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP);
1106 }
1107
1108 /**
1109  * sdma_v6_0_ring_emit_pipeline_sync - sync the pipeline
1110  *
1111  * @ring: amdgpu_ring pointer
1112  *
1113  * Make sure all previous operations are completed (CIK).
1114  */
1115 static void sdma_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1116 {
1117         uint32_t seq = ring->fence_drv.sync_seq;
1118         uint64_t addr = ring->fence_drv.gpu_addr;
1119
1120         /* wait for idle */
1121         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1122                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1123                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1124                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1125         amdgpu_ring_write(ring, addr & 0xfffffffc);
1126         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1127         amdgpu_ring_write(ring, seq); /* reference */
1128         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1129         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1130                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1131 }
1132
1133 /*
1134  * sdma_v6_0_ring_emit_vm_flush - vm flush using sDMA
1135  *
1136  * @ring: amdgpu_ring pointer
1137  * @vmid: vmid number to use
1138  * @pd_addr: address
1139  *
1140  * Update the page table base and flush the VM TLB
1141  * using sDMA.
1142  */
1143 static void sdma_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1144                                          unsigned vmid, uint64_t pd_addr)
1145 {
1146         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
1147         uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0);
1148
1149         /* Update the PD address for this VMID. */
1150         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
1151                               (hub->ctx_addr_distance * vmid),
1152                               lower_32_bits(pd_addr));
1153         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
1154                               (hub->ctx_addr_distance * vmid),
1155                               upper_32_bits(pd_addr));
1156
1157         /* Trigger invalidation. */
1158         amdgpu_ring_write(ring,
1159                           SDMA_PKT_VM_INVALIDATION_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1160                           SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(SDMA_SUBOP_VM_INVALIDATION) |
1161                           SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(ring->vm_inv_eng) |
1162                           SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(0x1f));
1163         amdgpu_ring_write(ring, req);
1164         amdgpu_ring_write(ring, 0xFFFFFFFF);
1165         amdgpu_ring_write(ring,
1166                           SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(1 << vmid) |
1167                           SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(0x1F));
1168 }
1169
1170 static void sdma_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
1171                                      uint32_t reg, uint32_t val)
1172 {
1173         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1174                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1175         amdgpu_ring_write(ring, reg);
1176         amdgpu_ring_write(ring, val);
1177 }
1178
1179 static void sdma_v6_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1180                                          uint32_t val, uint32_t mask)
1181 {
1182         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1183                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1184                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1185         amdgpu_ring_write(ring, reg << 2);
1186         amdgpu_ring_write(ring, 0);
1187         amdgpu_ring_write(ring, val); /* reference */
1188         amdgpu_ring_write(ring, mask); /* mask */
1189         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1190                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1191 }
1192
1193 static void sdma_v6_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1194                                                    uint32_t reg0, uint32_t reg1,
1195                                                    uint32_t ref, uint32_t mask)
1196 {
1197         amdgpu_ring_emit_wreg(ring, reg0, ref);
1198         /* wait for a cycle to reset vm_inv_eng*_ack */
1199         amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1200         amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1201 }
1202
1203 static struct amdgpu_sdma_ras sdma_v6_0_3_ras = {
1204         .ras_block = {
1205                 .ras_late_init = amdgpu_ras_block_late_init,
1206         },
1207 };
1208
1209 static void sdma_v6_0_set_ras_funcs(struct amdgpu_device *adev)
1210 {
1211         switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
1212         case IP_VERSION(6, 0, 3):
1213                 adev->sdma.ras = &sdma_v6_0_3_ras;
1214                 break;
1215         default:
1216                 break;
1217         }
1218 }
1219
1220 static int sdma_v6_0_early_init(void *handle)
1221 {
1222         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1223         int r;
1224
1225         r = amdgpu_sdma_init_microcode(adev, 0, true);
1226         if (r)
1227                 return r;
1228
1229         sdma_v6_0_set_ring_funcs(adev);
1230         sdma_v6_0_set_buffer_funcs(adev);
1231         sdma_v6_0_set_vm_pte_funcs(adev);
1232         sdma_v6_0_set_irq_funcs(adev);
1233         sdma_v6_0_set_mqd_funcs(adev);
1234         sdma_v6_0_set_ras_funcs(adev);
1235
1236         return 0;
1237 }
1238
1239 static int sdma_v6_0_sw_init(void *handle)
1240 {
1241         struct amdgpu_ring *ring;
1242         int r, i;
1243         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1244
1245         /* SDMA trap event */
1246         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX,
1247                               GFX_11_0_0__SRCID__SDMA_TRAP,
1248                               &adev->sdma.trap_irq);
1249         if (r)
1250                 return r;
1251
1252         for (i = 0; i < adev->sdma.num_instances; i++) {
1253                 ring = &adev->sdma.instance[i].ring;
1254                 ring->ring_obj = NULL;
1255                 ring->use_doorbell = true;
1256                 ring->me = i;
1257
1258                 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1259                                 ring->use_doorbell?"true":"false");
1260
1261                 ring->doorbell_index =
1262                         (adev->doorbell_index.sdma_engine[i] << 1); // get DWORD offset
1263
1264                 ring->vm_hub = AMDGPU_GFXHUB(0);
1265                 sprintf(ring->name, "sdma%d", i);
1266                 r = amdgpu_ring_init(adev, ring, 1024,
1267                                      &adev->sdma.trap_irq,
1268                                      AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1269                                      AMDGPU_RING_PRIO_DEFAULT, NULL);
1270                 if (r)
1271                         return r;
1272         }
1273
1274         if (amdgpu_sdma_ras_sw_init(adev)) {
1275                 dev_err(adev->dev, "Failed to initialize sdma ras block!\n");
1276                 return -EINVAL;
1277         }
1278
1279         return r;
1280 }
1281
1282 static int sdma_v6_0_sw_fini(void *handle)
1283 {
1284         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1285         int i;
1286
1287         for (i = 0; i < adev->sdma.num_instances; i++)
1288                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1289
1290         amdgpu_sdma_destroy_inst_ctx(adev, true);
1291
1292         return 0;
1293 }
1294
1295 static int sdma_v6_0_hw_init(void *handle)
1296 {
1297         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1298
1299         return sdma_v6_0_start(adev);
1300 }
1301
1302 static int sdma_v6_0_hw_fini(void *handle)
1303 {
1304         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1305
1306         if (amdgpu_sriov_vf(adev))
1307                 return 0;
1308
1309         sdma_v6_0_ctxempty_int_enable(adev, false);
1310         sdma_v6_0_enable(adev, false);
1311
1312         return 0;
1313 }
1314
1315 static int sdma_v6_0_suspend(void *handle)
1316 {
1317         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1318
1319         return sdma_v6_0_hw_fini(adev);
1320 }
1321
1322 static int sdma_v6_0_resume(void *handle)
1323 {
1324         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1325
1326         return sdma_v6_0_hw_init(adev);
1327 }
1328
1329 static bool sdma_v6_0_is_idle(void *handle)
1330 {
1331         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1332         u32 i;
1333
1334         for (i = 0; i < adev->sdma.num_instances; i++) {
1335                 u32 tmp = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG));
1336
1337                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1338                         return false;
1339         }
1340
1341         return true;
1342 }
1343
1344 static int sdma_v6_0_wait_for_idle(void *handle)
1345 {
1346         unsigned i;
1347         u32 sdma0, sdma1;
1348         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1349
1350         for (i = 0; i < adev->usec_timeout; i++) {
1351                 sdma0 = RREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG));
1352                 sdma1 = RREG32(sdma_v6_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG));
1353
1354                 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1355                         return 0;
1356                 udelay(1);
1357         }
1358         return -ETIMEDOUT;
1359 }
1360
1361 static int sdma_v6_0_ring_preempt_ib(struct amdgpu_ring *ring)
1362 {
1363         int i, r = 0;
1364         struct amdgpu_device *adev = ring->adev;
1365         u32 index = 0;
1366         u64 sdma_gfx_preempt;
1367
1368         amdgpu_sdma_get_index_from_ring(ring, &index);
1369         sdma_gfx_preempt =
1370                 sdma_v6_0_get_reg_offset(adev, index, regSDMA0_QUEUE0_PREEMPT);
1371
1372         /* assert preemption condition */
1373         amdgpu_ring_set_preempt_cond_exec(ring, false);
1374
1375         /* emit the trailing fence */
1376         ring->trail_seq += 1;
1377         amdgpu_ring_alloc(ring, 10);
1378         sdma_v6_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1379                                   ring->trail_seq, 0);
1380         amdgpu_ring_commit(ring);
1381
1382         /* assert IB preemption */
1383         WREG32(sdma_gfx_preempt, 1);
1384
1385         /* poll the trailing fence */
1386         for (i = 0; i < adev->usec_timeout; i++) {
1387                 if (ring->trail_seq ==
1388                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1389                         break;
1390                 udelay(1);
1391         }
1392
1393         if (i >= adev->usec_timeout) {
1394                 r = -EINVAL;
1395                 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1396         }
1397
1398         /* deassert IB preemption */
1399         WREG32(sdma_gfx_preempt, 0);
1400
1401         /* deassert the preemption condition */
1402         amdgpu_ring_set_preempt_cond_exec(ring, true);
1403         return r;
1404 }
1405
1406 static int sdma_v6_0_set_trap_irq_state(struct amdgpu_device *adev,
1407                                         struct amdgpu_irq_src *source,
1408                                         unsigned type,
1409                                         enum amdgpu_interrupt_state state)
1410 {
1411         u32 sdma_cntl;
1412
1413         u32 reg_offset = sdma_v6_0_get_reg_offset(adev, type, regSDMA0_CNTL);
1414
1415         if (!amdgpu_sriov_vf(adev)) {
1416                 sdma_cntl = RREG32(reg_offset);
1417                 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1418                                 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1419                 WREG32(reg_offset, sdma_cntl);
1420         }
1421
1422         return 0;
1423 }
1424
1425 static int sdma_v6_0_process_trap_irq(struct amdgpu_device *adev,
1426                                       struct amdgpu_irq_src *source,
1427                                       struct amdgpu_iv_entry *entry)
1428 {
1429         int instances, queue;
1430         uint32_t mes_queue_id = entry->src_data[0];
1431
1432         DRM_DEBUG("IH: SDMA trap\n");
1433
1434         if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
1435                 struct amdgpu_mes_queue *queue;
1436
1437                 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
1438
1439                 spin_lock(&adev->mes.queue_id_lock);
1440                 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
1441                 if (queue) {
1442                         DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);
1443                         amdgpu_fence_process(queue->ring);
1444                 }
1445                 spin_unlock(&adev->mes.queue_id_lock);
1446                 return 0;
1447         }
1448
1449         queue = entry->ring_id & 0xf;
1450         instances = (entry->ring_id & 0xf0) >> 4;
1451         if (instances > 1) {
1452                 DRM_ERROR("IH: wrong ring_ID detected, as wrong sdma instance\n");
1453                 return -EINVAL;
1454         }
1455
1456         switch (entry->client_id) {
1457         case SOC21_IH_CLIENTID_GFX:
1458                 switch (queue) {
1459                 case 0:
1460                         amdgpu_fence_process(&adev->sdma.instance[instances].ring);
1461                         break;
1462                 default:
1463                         break;
1464                 }
1465                 break;
1466         }
1467         return 0;
1468 }
1469
1470 static int sdma_v6_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1471                                               struct amdgpu_irq_src *source,
1472                                               struct amdgpu_iv_entry *entry)
1473 {
1474         return 0;
1475 }
1476
1477 static int sdma_v6_0_set_clockgating_state(void *handle,
1478                                            enum amd_clockgating_state state)
1479 {
1480         return 0;
1481 }
1482
1483 static int sdma_v6_0_set_powergating_state(void *handle,
1484                                           enum amd_powergating_state state)
1485 {
1486         return 0;
1487 }
1488
1489 static void sdma_v6_0_get_clockgating_state(void *handle, u64 *flags)
1490 {
1491 }
1492
1493 const struct amd_ip_funcs sdma_v6_0_ip_funcs = {
1494         .name = "sdma_v6_0",
1495         .early_init = sdma_v6_0_early_init,
1496         .late_init = NULL,
1497         .sw_init = sdma_v6_0_sw_init,
1498         .sw_fini = sdma_v6_0_sw_fini,
1499         .hw_init = sdma_v6_0_hw_init,
1500         .hw_fini = sdma_v6_0_hw_fini,
1501         .suspend = sdma_v6_0_suspend,
1502         .resume = sdma_v6_0_resume,
1503         .is_idle = sdma_v6_0_is_idle,
1504         .wait_for_idle = sdma_v6_0_wait_for_idle,
1505         .soft_reset = sdma_v6_0_soft_reset,
1506         .check_soft_reset = sdma_v6_0_check_soft_reset,
1507         .set_clockgating_state = sdma_v6_0_set_clockgating_state,
1508         .set_powergating_state = sdma_v6_0_set_powergating_state,
1509         .get_clockgating_state = sdma_v6_0_get_clockgating_state,
1510 };
1511
1512 static const struct amdgpu_ring_funcs sdma_v6_0_ring_funcs = {
1513         .type = AMDGPU_RING_TYPE_SDMA,
1514         .align_mask = 0xf,
1515         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1516         .support_64bit_ptrs = true,
1517         .secure_submission_supported = true,
1518         .get_rptr = sdma_v6_0_ring_get_rptr,
1519         .get_wptr = sdma_v6_0_ring_get_wptr,
1520         .set_wptr = sdma_v6_0_ring_set_wptr,
1521         .emit_frame_size =
1522                 5 + /* sdma_v6_0_ring_init_cond_exec */
1523                 6 + /* sdma_v6_0_ring_emit_hdp_flush */
1524                 6 + /* sdma_v6_0_ring_emit_pipeline_sync */
1525                 /* sdma_v6_0_ring_emit_vm_flush */
1526                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1527                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1528                 10 + 10 + 10, /* sdma_v6_0_ring_emit_fence x3 for user fence, vm fence */
1529         .emit_ib_size = 5 + 7 + 6, /* sdma_v6_0_ring_emit_ib */
1530         .emit_ib = sdma_v6_0_ring_emit_ib,
1531         .emit_mem_sync = sdma_v6_0_ring_emit_mem_sync,
1532         .emit_fence = sdma_v6_0_ring_emit_fence,
1533         .emit_pipeline_sync = sdma_v6_0_ring_emit_pipeline_sync,
1534         .emit_vm_flush = sdma_v6_0_ring_emit_vm_flush,
1535         .emit_hdp_flush = sdma_v6_0_ring_emit_hdp_flush,
1536         .test_ring = sdma_v6_0_ring_test_ring,
1537         .test_ib = sdma_v6_0_ring_test_ib,
1538         .insert_nop = sdma_v6_0_ring_insert_nop,
1539         .pad_ib = sdma_v6_0_ring_pad_ib,
1540         .emit_wreg = sdma_v6_0_ring_emit_wreg,
1541         .emit_reg_wait = sdma_v6_0_ring_emit_reg_wait,
1542         .emit_reg_write_reg_wait = sdma_v6_0_ring_emit_reg_write_reg_wait,
1543         .init_cond_exec = sdma_v6_0_ring_init_cond_exec,
1544         .patch_cond_exec = sdma_v6_0_ring_patch_cond_exec,
1545         .preempt_ib = sdma_v6_0_ring_preempt_ib,
1546 };
1547
1548 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev)
1549 {
1550         int i;
1551
1552         for (i = 0; i < adev->sdma.num_instances; i++) {
1553                 adev->sdma.instance[i].ring.funcs = &sdma_v6_0_ring_funcs;
1554                 adev->sdma.instance[i].ring.me = i;
1555         }
1556 }
1557
1558 static const struct amdgpu_irq_src_funcs sdma_v6_0_trap_irq_funcs = {
1559         .set = sdma_v6_0_set_trap_irq_state,
1560         .process = sdma_v6_0_process_trap_irq,
1561 };
1562
1563 static const struct amdgpu_irq_src_funcs sdma_v6_0_illegal_inst_irq_funcs = {
1564         .process = sdma_v6_0_process_illegal_inst_irq,
1565 };
1566
1567 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1568 {
1569         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1570                                         adev->sdma.num_instances;
1571         adev->sdma.trap_irq.funcs = &sdma_v6_0_trap_irq_funcs;
1572         adev->sdma.illegal_inst_irq.funcs = &sdma_v6_0_illegal_inst_irq_funcs;
1573 }
1574
1575 /**
1576  * sdma_v6_0_emit_copy_buffer - copy buffer using the sDMA engine
1577  *
1578  * @ib: indirect buffer to fill with commands
1579  * @src_offset: src GPU address
1580  * @dst_offset: dst GPU address
1581  * @byte_count: number of bytes to xfer
1582  * @tmz: if a secure copy should be used
1583  *
1584  * Copy GPU buffers using the DMA engine.
1585  * Used by the amdgpu ttm implementation to move pages if
1586  * registered as the asic copy callback.
1587  */
1588 static void sdma_v6_0_emit_copy_buffer(struct amdgpu_ib *ib,
1589                                        uint64_t src_offset,
1590                                        uint64_t dst_offset,
1591                                        uint32_t byte_count,
1592                                        bool tmz)
1593 {
1594         ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) |
1595                 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1596                 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1597         ib->ptr[ib->length_dw++] = byte_count - 1;
1598         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1599         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1600         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1601         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1602         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1603 }
1604
1605 /**
1606  * sdma_v6_0_emit_fill_buffer - fill buffer using the sDMA engine
1607  *
1608  * @ib: indirect buffer to fill
1609  * @src_data: value to write to buffer
1610  * @dst_offset: dst GPU address
1611  * @byte_count: number of bytes to xfer
1612  *
1613  * Fill GPU buffers using the DMA engine.
1614  */
1615 static void sdma_v6_0_emit_fill_buffer(struct amdgpu_ib *ib,
1616                                        uint32_t src_data,
1617                                        uint64_t dst_offset,
1618                                        uint32_t byte_count)
1619 {
1620         ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_CONST_FILL);
1621         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1622         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1623         ib->ptr[ib->length_dw++] = src_data;
1624         ib->ptr[ib->length_dw++] = byte_count - 1;
1625 }
1626
1627 static const struct amdgpu_buffer_funcs sdma_v6_0_buffer_funcs = {
1628         .copy_max_bytes = 0x400000,
1629         .copy_num_dw = 7,
1630         .emit_copy_buffer = sdma_v6_0_emit_copy_buffer,
1631
1632         .fill_max_bytes = 0x400000,
1633         .fill_num_dw = 5,
1634         .emit_fill_buffer = sdma_v6_0_emit_fill_buffer,
1635 };
1636
1637 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev)
1638 {
1639         adev->mman.buffer_funcs = &sdma_v6_0_buffer_funcs;
1640         adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1641 }
1642
1643 static const struct amdgpu_vm_pte_funcs sdma_v6_0_vm_pte_funcs = {
1644         .copy_pte_num_dw = 7,
1645         .copy_pte = sdma_v6_0_vm_copy_pte,
1646         .write_pte = sdma_v6_0_vm_write_pte,
1647         .set_pte_pde = sdma_v6_0_vm_set_pte_pde,
1648 };
1649
1650 static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1651 {
1652         unsigned i;
1653
1654         adev->vm_manager.vm_pte_funcs = &sdma_v6_0_vm_pte_funcs;
1655         for (i = 0; i < adev->sdma.num_instances; i++) {
1656                 adev->vm_manager.vm_pte_scheds[i] =
1657                         &adev->sdma.instance[i].ring.sched;
1658         }
1659         adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1660 }
1661
1662 const struct amdgpu_ip_block_version sdma_v6_0_ip_block = {
1663         .type = AMD_IP_BLOCK_TYPE_SDMA,
1664         .major = 6,
1665         .minor = 0,
1666         .rev = 0,
1667         .funcs = &sdma_v6_0_ip_funcs,
1668 };