drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_ucode.h"
  31 #include "amdgpu_trace.h"
  32
  33 #include "gc/gc_10_3_0_offset.h"
  34 #include "gc/gc_10_3_0_sh_mask.h"
  35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
  36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
  37 #include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h"
  38 #include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h"
  39
  40 #include "soc15_common.h"
  41 #include "soc15.h"
  42 #include "navi10_sdma_pkt_open.h"
  43 #include "nbio_v2_3.h"
  44 #include "sdma_common.h"
  45 #include "sdma_v5_2.h"
  46
  47 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin");
  48 MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin");
  49 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin");
  50
  51 MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin");
  52
  53 #define SDMA1_REG_OFFSET 0x600
  54 #define SDMA3_REG_OFFSET 0x400
  55 #define SDMA0_HYP_DEC_REG_START 0x5880
  56 #define SDMA0_HYP_DEC_REG_END 0x5893
  57 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
  58
  59 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev);
  60 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev);
  61 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev);
  62 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev);
  63
  64 static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
  65 {
  66         u32 base;
  67
  68         if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
  69             internal_offset <= SDMA0_HYP_DEC_REG_END) {
  70                 base = adev->reg_offset[GC_HWIP][0][1];
  71                 if (instance != 0)
  72                         internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
  73         } else {
  74                 if (instance < 2) {
  75                         base = adev->reg_offset[GC_HWIP][0][0];
  76                         if (instance == 1)
  77                                 internal_offset += SDMA1_REG_OFFSET;
  78                 } else {
  79                         base = adev->reg_offset[GC_HWIP][0][2];
  80                         if (instance == 3)
  81                                 internal_offset += SDMA3_REG_OFFSET;
  82                 }
  83         }
  84
  85         return base + internal_offset;
  86 }
  87
  88 static void sdma_v5_2_init_golden_registers(struct amdgpu_device *adev)
  89 {
  90         switch (adev->asic_type) {
  91         case CHIP_SIENNA_CICHLID:
  92         case CHIP_NAVY_FLOUNDER:
  93         case CHIP_VANGOGH:
  94         case CHIP_DIMGREY_CAVEFISH:
  95                 break;
  96         default:
  97                 break;
  98         }
  99 }
 100
 101 static int sdma_v5_2_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
 102 {
 103         int err = 0;
 104         const struct sdma_firmware_header_v1_0 *hdr;
 105
 106         err = amdgpu_ucode_validate(sdma_inst->fw);
 107         if (err)
 108                 return err;
 109
 110         hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
 111         sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
 112         sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
 113
 114         if (sdma_inst->feature_version >= 20)
 115                 sdma_inst->burst_nop = true;
 116
 117         return 0;
 118 }
 119
 120 static void sdma_v5_2_destroy_inst_ctx(struct amdgpu_device *adev)
 121 {
 122         int i;
 123
 124         for (i = 0; i < adev->sdma.num_instances; i++) {
 125                 release_firmware(adev->sdma.instance[i].fw);
 126                 adev->sdma.instance[i].fw = NULL;
 127
 128                 if (adev->asic_type == CHIP_SIENNA_CICHLID)
 129                         break;
 130         }
 131
 132         memset((void *)adev->sdma.instance, 0,
 133                sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
 134 }
 135
 136 /**
 137  * sdma_v5_2_init_microcode - load ucode images from disk
 138  *
 139  * @adev: amdgpu_device pointer
 140  *
 141  * Use the firmware interface to load the ucode images into
 142  * the driver (not loaded into hw).
 143  * Returns 0 on success, error on failure.
 144  */
 145
 146 // emulation only, won't work on real chip
 147 // navi10 real chip need to use PSP to load firmware
 148 static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
 149 {
 150         const char *chip_name;
 151         char fw_name[40];
 152         int err = 0, i;
 153         struct amdgpu_firmware_info *info = NULL;
 154         const struct common_firmware_header *header = NULL;
 155
 156         if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_SIENNA_CICHLID))
 157                 return 0;
 158
 159         DRM_DEBUG("\n");
 160
 161         switch (adev->asic_type) {
 162         case CHIP_SIENNA_CICHLID:
 163                 chip_name = "sienna_cichlid";
 164                 break;
 165         case CHIP_NAVY_FLOUNDER:
 166                 chip_name = "navy_flounder";
 167                 break;
 168         case CHIP_VANGOGH:
 169                 chip_name = "vangogh";
 170                 break;
 171         case CHIP_DIMGREY_CAVEFISH:
 172                 chip_name = "dimgrey_cavefish";
 173                 break;
 174         default:
 175                 BUG();
 176         }
 177
 178         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 179
 180         err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);
 181         if (err)
 182                 goto out;
 183
 184         err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]);
 185         if (err)
 186                 goto out;
 187
 188         for (i = 1; i < adev->sdma.num_instances; i++) {
 189                 if (adev->asic_type >= CHIP_SIENNA_CICHLID &&
 190                     adev->asic_type <= CHIP_DIMGREY_CAVEFISH) {
 191                         memcpy((void *)&adev->sdma.instance[i],
 192                                (void *)&adev->sdma.instance[0],
 193                                sizeof(struct amdgpu_sdma_instance));
 194                 } else {
 195                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i);
 196                         err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 197                         if (err)
 198                                 goto out;
 199
 200                         err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[i]);
 201                         if (err)
 202                                 goto out;
 203                 }
 204         }
 205
 206         DRM_DEBUG("psp_load == '%s'\n",
 207                   adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
 208
 209         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 210                 for (i = 0; i < adev->sdma.num_instances; i++) {
 211                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 212                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 213                         info->fw = adev->sdma.instance[i].fw;
 214                         header = (const struct common_firmware_header *)info->fw->data;
 215                         adev->firmware.fw_size +=
 216                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 217                 }
 218         }
 219
 220 out:
 221         if (err) {
 222                 DRM_ERROR("sdma_v5_2: Failed to load firmware \"%s\"\n", fw_name);
 223                 sdma_v5_2_destroy_inst_ctx(adev);
 224         }
 225         return err;
 226 }
 227
 228 static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring)
 229 {
 230         unsigned ret;
 231
 232         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
 233         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
 234         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
 235         amdgpu_ring_write(ring, 1);
 236         ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
 237         amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
 238
 239         return ret;
 240 }
 241
 242 static void sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring *ring,
 243                                            unsigned offset)
 244 {
 245         unsigned cur;
 246
 247         BUG_ON(offset > ring->buf_mask);
 248         BUG_ON(ring->ring[offset] != 0x55aa55aa);
 249
 250         cur = (ring->wptr - 1) & ring->buf_mask;
 251         if (cur > offset)
 252                 ring->ring[offset] = cur - offset;
 253         else
 254                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
 255 }
 256
 257 /**
 258  * sdma_v5_2_ring_get_rptr - get the current read pointer
 259  *
 260  * @ring: amdgpu ring pointer
 261  *
 262  * Get the current rptr from the hardware (NAVI10+).
 263  */
 264 static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring)
 265 {
 266         u64 *rptr;
 267
 268         /* XXX check if swapping is necessary on BE */
 269         rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
 270
 271         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 272         return ((*rptr) >> 2);
 273 }
 274
 275 /**
 276  * sdma_v5_2_ring_get_wptr - get the current write pointer
 277  *
 278  * @ring: amdgpu ring pointer
 279  *
 280  * Get the current wptr from the hardware (NAVI10+).
 281  */
 282 static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring)
 283 {
 284         struct amdgpu_device *adev = ring->adev;
 285         u64 wptr;
 286
 287         if (ring->use_doorbell) {
 288                 /* XXX check if swapping is necessary on BE */
 289                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 290                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 291         } else {
 292                 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
 293                 wptr = wptr << 32;
 294                 wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
 295                 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
 296         }
 297
 298         return wptr >> 2;
 299 }
 300
 301 /**
 302  * sdma_v5_2_ring_set_wptr - commit the write pointer
 303  *
 304  * @ring: amdgpu ring pointer
 305  *
 306  * Write the wptr back to the hardware (NAVI10+).
 307  */
 308 static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring)
 309 {
 310         struct amdgpu_device *adev = ring->adev;
 311
 312         DRM_DEBUG("Setting write pointer\n");
 313         if (ring->use_doorbell) {
 314                 DRM_DEBUG("Using doorbell -- "
 315                                 "wptr_offs == 0x%08x "
 316                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 317                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 318                                 ring->wptr_offs,
 319                                 lower_32_bits(ring->wptr << 2),
 320                                 upper_32_bits(ring->wptr << 2));
 321                 /* XXX check if swapping is necessary on BE */
 322                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
 323                 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
 324                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 325                                 ring->doorbell_index, ring->wptr << 2);
 326                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 327         } else {
 328                 DRM_DEBUG("Not using doorbell -- "
 329                                 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 330                                 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 331                                 ring->me,
 332                                 lower_32_bits(ring->wptr << 2),
 333                                 ring->me,
 334                                 upper_32_bits(ring->wptr << 2));
 335                 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
 336                         lower_32_bits(ring->wptr << 2));
 337                 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
 338                         upper_32_bits(ring->wptr << 2));
 339         }
 340 }
 341
 342 static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 343 {
 344         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 345         int i;
 346
 347         for (i = 0; i < count; i++)
 348                 if (sdma && sdma->burst_nop && (i == 0))
 349                         amdgpu_ring_write(ring, ring->funcs->nop |
 350                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 351                 else
 352                         amdgpu_ring_write(ring, ring->funcs->nop);
 353 }
 354
 355 /**
 356  * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine
 357  *
 358  * @ring: amdgpu ring pointer
 359  * @job: job to retrieve vmid from
 360  * @ib: IB object to schedule
 361  * @flags: unused
 362  *
 363  * Schedule an IB in the DMA ring.
 364  */
 365 static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring,
 366                                    struct amdgpu_job *job,
 367                                    struct amdgpu_ib *ib,
 368                                    uint32_t flags)
 369 {
 370         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 371         uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
 372
 373         /* An IB packet must end on a 8 DW boundary--the next dword
 374          * must be on a 8-dword boundary. Our IB packet below is 6
 375          * dwords long, thus add x number of NOPs, such that, in
 376          * modular arithmetic,
 377          * wptr + 6 + x = 8k, k >= 0, which in C is,
 378          * (wptr + 6 + x) % 8 = 0.
 379          * The expression below, is a solution of x.
 380          */
 381         sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 382
 383         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 384                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 385         /* base must be 32 byte aligned */
 386         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 387         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 388         amdgpu_ring_write(ring, ib->length_dw);
 389         amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
 390         amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
 391 }
 392
 393 /**
 394  * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 395  *
 396  * @ring: amdgpu ring pointer
 397  *
 398  * Emit an hdp flush packet on the requested DMA ring.
 399  */
 400 static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 401 {
 402         struct amdgpu_device *adev = ring->adev;
 403         u32 ref_and_mask = 0;
 404         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 405
 406         ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
 407
 408         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 409                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 410                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 411         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
 412         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
 413         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 414         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 415         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 416                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 417 }
 418
 419 /**
 420  * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring
 421  *
 422  * @ring: amdgpu ring pointer
 423  * @addr: address
 424  * @seq: sequence number
 425  * @flags: fence related flags
 426  *
 427  * Add a DMA fence packet to the ring to write
 428  * the fence seq number and DMA trap packet to generate
 429  * an interrupt if needed.
 430  */
 431 static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 432                                       unsigned flags)
 433 {
 434         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 435         /* write the fence */
 436         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 437                           SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
 438         /* zero in first two bits */
 439         BUG_ON(addr & 0x3);
 440         amdgpu_ring_write(ring, lower_32_bits(addr));
 441         amdgpu_ring_write(ring, upper_32_bits(addr));
 442         amdgpu_ring_write(ring, lower_32_bits(seq));
 443
 444         /* optionally write high bits as well */
 445         if (write64bit) {
 446                 addr += 4;
 447                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 448                                   SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
 449                 /* zero in first two bits */
 450                 BUG_ON(addr & 0x3);
 451                 amdgpu_ring_write(ring, lower_32_bits(addr));
 452                 amdgpu_ring_write(ring, upper_32_bits(addr));
 453                 amdgpu_ring_write(ring, upper_32_bits(seq));
 454         }
 455
 456         if (flags & AMDGPU_FENCE_FLAG_INT) {
 457                 /* generate an interrupt */
 458                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 459                 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 460         }
 461 }
 462
 463
 464 /**
 465  * sdma_v5_2_gfx_stop - stop the gfx async dma engines
 466  *
 467  * @adev: amdgpu_device pointer
 468  *
 469  * Stop the gfx async dma ring buffers.
 470  */
 471 static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev)
 472 {
 473         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 474         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 475         struct amdgpu_ring *sdma2 = &adev->sdma.instance[2].ring;
 476         struct amdgpu_ring *sdma3 = &adev->sdma.instance[3].ring;
 477         u32 rb_cntl, ib_cntl;
 478         int i;
 479
 480         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 481             (adev->mman.buffer_funcs_ring == sdma1) ||
 482             (adev->mman.buffer_funcs_ring == sdma2) ||
 483             (adev->mman.buffer_funcs_ring == sdma3))
 484                 amdgpu_ttm_set_buffer_funcs_status(adev, false);
 485
 486         for (i = 0; i < adev->sdma.num_instances; i++) {
 487                 rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 488                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 489                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 490                 ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 491                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 492                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 493         }
 494
 495         sdma0->sched.ready = false;
 496         sdma1->sched.ready = false;
 497         sdma2->sched.ready = false;
 498         sdma3->sched.ready = false;
 499 }
 500
 501 /**
 502  * sdma_v5_2_rlc_stop - stop the compute async dma engines
 503  *
 504  * @adev: amdgpu_device pointer
 505  *
 506  * Stop the compute async dma queues.
 507  */
 508 static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev)
 509 {
 510         /* XXX todo */
 511 }
 512
 513 /**
 514  * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
 515  *
 516  * @adev: amdgpu_device pointer
 517  * @enable: enable/disable the DMA MEs context switch.
 518  *
 519  * Halt or unhalt the async dma engines context switch.
 520  */
 521 static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 522 {
 523         u32 f32_cntl, phase_quantum = 0;
 524         int i;
 525
 526         if (amdgpu_sdma_phase_quantum) {
 527                 unsigned value = amdgpu_sdma_phase_quantum;
 528                 unsigned unit = 0;
 529
 530                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 531                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 532                         value = (value + 1) >> 1;
 533                         unit++;
 534                 }
 535                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 536                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 537                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 538                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 539                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 540                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 541                         WARN_ONCE(1,
 542                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 543                                   value << unit);
 544                 }
 545                 phase_quantum =
 546                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 547                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 548         }
 549
 550         for (i = 0; i < adev->sdma.num_instances; i++) {
 551                 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
 552                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 553                                 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 554                 if (enable && amdgpu_sdma_phase_quantum) {
 555                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
 556                                phase_quantum);
 557                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
 558                                phase_quantum);
 559                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
 560                                phase_quantum);
 561                 }
 562                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
 563         }
 564
 565 }
 566
 567 /**
 568  * sdma_v5_2_enable - stop the async dma engines
 569  *
 570  * @adev: amdgpu_device pointer
 571  * @enable: enable/disable the DMA MEs.
 572  *
 573  * Halt or unhalt the async dma engines.
 574  */
 575 static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable)
 576 {
 577         u32 f32_cntl;
 578         int i;
 579
 580         if (!enable) {
 581                 sdma_v5_2_gfx_stop(adev);
 582                 sdma_v5_2_rlc_stop(adev);
 583         }
 584
 585         for (i = 0; i < adev->sdma.num_instances; i++) {
 586                 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 587                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 588                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
 589         }
 590 }
 591
 592 /**
 593  * sdma_v5_2_gfx_resume - setup and start the async dma engines
 594  *
 595  * @adev: amdgpu_device pointer
 596  *
 597  * Set up the gfx DMA ring buffers and enable them.
 598  * Returns 0 for success, error for failure.
 599  */
 600 static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
 601 {
 602         struct amdgpu_ring *ring;
 603         u32 rb_cntl, ib_cntl;
 604         u32 rb_bufsz;
 605         u32 wb_offset;
 606         u32 doorbell;
 607         u32 doorbell_offset;
 608         u32 temp;
 609         u32 wptr_poll_cntl;
 610         u64 wptr_gpu_addr;
 611         int i, r;
 612
 613         for (i = 0; i < adev->sdma.num_instances; i++) {
 614                 ring = &adev->sdma.instance[i].ring;
 615                 wb_offset = (ring->rptr_offs * 4);
 616
 617                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 618
 619                 /* Set ring buffer size in dwords */
 620                 rb_bufsz = order_base_2(ring->ring_size / 4);
 621                 rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 622                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 623 #ifdef __BIG_ENDIAN
 624                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 625                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 626                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 627 #endif
 628                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 629
 630                 /* Initialize the ring buffer's read and write pointers */
 631                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
 632                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
 633                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
 634                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 635
 636                 /* setup the wptr shadow polling */
 637                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 638                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
 639                        lower_32_bits(wptr_gpu_addr));
 640                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
 641                        upper_32_bits(wptr_gpu_addr));
 642                 wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i,
 643                                                          mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 644                 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 645                                                SDMA0_GFX_RB_WPTR_POLL_CNTL,
 646                                                F32_POLL_ENABLE, 1);
 647                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
 648                        wptr_poll_cntl);
 649
 650                 /* set the wb address whether it's enabled or not */
 651                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
 652                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 653                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
 654                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 655
 656                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 657
 658                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
 659                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
 660
 661                 ring->wptr = 0;
 662
 663                 /* before programing wptr to a less value, need set minor_ptr_update first */
 664                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
 665
 666                 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 667                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
 668                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
 669                 }
 670
 671                 doorbell = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
 672                 doorbell_offset = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
 673
 674                 if (ring->use_doorbell) {
 675                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 676                         doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
 677                                         OFFSET, ring->doorbell_index);
 678                 } else {
 679                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 680                 }
 681                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
 682                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
 683
 684                 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 685                                                       ring->doorbell_index,
 686                                                       adev->doorbell_index.sdma_doorbell_range);
 687
 688                 if (amdgpu_sriov_vf(adev))
 689                         sdma_v5_2_ring_set_wptr(ring);
 690
 691                 /* set minor_ptr_update to 0 after wptr programed */
 692                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
 693
 694                 /* set utc l1 enable flag always to 1 */
 695                 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
 696                 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
 697
 698                 /* enable MCBP */
 699                 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
 700                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
 701
 702                 /* Set up RESP_MODE to non-copy addresses */
 703                 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
 704                 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
 705                 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
 706                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
 707
 708                 /* program default cache read and write policy */
 709                 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
 710                 /* clean read policy and write policy bits */
 711                 temp &= 0xFF0FFF;
 712                 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
 713                          (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
 714                          SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
 715                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
 716
 717                 if (!amdgpu_sriov_vf(adev)) {
 718                         /* unhalt engine */
 719                         temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 720                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 721                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
 722                 }
 723
 724                 /* enable DMA RB */
 725                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 726                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 727
 728                 ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 729                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 730 #ifdef __BIG_ENDIAN
 731                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 732 #endif
 733                 /* enable DMA IBs */
 734                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 735
 736                 ring->sched.ready = true;
 737
 738                 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
 739                         sdma_v5_2_ctx_switch_enable(adev, true);
 740                         sdma_v5_2_enable(adev, true);
 741                 }
 742
 743                 r = amdgpu_ring_test_ring(ring);
 744                 if (r) {
 745                         ring->sched.ready = false;
 746                         return r;
 747                 }
 748
 749                 if (adev->mman.buffer_funcs_ring == ring)
 750                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 751         }
 752
 753         return 0;
 754 }
 755
 756 /**
 757  * sdma_v5_2_rlc_resume - setup and start the async dma engines
 758  *
 759  * @adev: amdgpu_device pointer
 760  *
 761  * Set up the compute DMA queues and enable them.
 762  * Returns 0 for success, error for failure.
 763  */
 764 static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev)
 765 {
 766         return 0;
 767 }
 768
 769 /**
 770  * sdma_v5_2_load_microcode - load the sDMA ME ucode
 771  *
 772  * @adev: amdgpu_device pointer
 773  *
 774  * Loads the sDMA0/1/2/3 ucode.
 775  * Returns 0 for success, -EINVAL if the ucode is not available.
 776  */
 777 static int sdma_v5_2_load_microcode(struct amdgpu_device *adev)
 778 {
 779         const struct sdma_firmware_header_v1_0 *hdr;
 780         const __le32 *fw_data;
 781         u32 fw_size;
 782         int i, j;
 783
 784         /* halt the MEs */
 785         sdma_v5_2_enable(adev, false);
 786
 787         for (i = 0; i < adev->sdma.num_instances; i++) {
 788                 if (!adev->sdma.instance[i].fw)
 789                         return -EINVAL;
 790
 791                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 792                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 793                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 794
 795                 fw_data = (const __le32 *)
 796                         (adev->sdma.instance[i].fw->data +
 797                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 798
 799                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
 800
 801                 for (j = 0; j < fw_size; j++) {
 802                         if (amdgpu_emu_mode == 1 && j % 500 == 0)
 803                                 msleep(1);
 804                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 805                 }
 806
 807                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
 808         }
 809
 810         return 0;
 811 }
 812
 813 static int sdma_v5_2_soft_reset(void *handle)
 814 {
 815         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 816         u32 grbm_soft_reset;
 817         u32 tmp;
 818         int i;
 819
 820         for (i = 0; i < adev->sdma.num_instances; i++) {
 821                 grbm_soft_reset = REG_SET_FIELD(0,
 822                                                 GRBM_SOFT_RESET, SOFT_RESET_SDMA0,
 823                                                 1);
 824                 grbm_soft_reset <<= i;
 825
 826                 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
 827                 tmp |= grbm_soft_reset;
 828                 DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp);
 829                 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
 830                 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
 831
 832                 udelay(50);
 833
 834                 tmp &= ~grbm_soft_reset;
 835                 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
 836                 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
 837
 838                 udelay(50);
 839         }
 840
 841         return 0;
 842 }
 843
 844 /**
 845  * sdma_v5_2_start - setup and start the async dma engines
 846  *
 847  * @adev: amdgpu_device pointer
 848  *
 849  * Set up the DMA engines and enable them.
 850  * Returns 0 for success, error for failure.
 851  */
 852 static int sdma_v5_2_start(struct amdgpu_device *adev)
 853 {
 854         int r = 0;
 855
 856         if (amdgpu_sriov_vf(adev)) {
 857                 sdma_v5_2_ctx_switch_enable(adev, false);
 858                 sdma_v5_2_enable(adev, false);
 859
 860                 /* set RB registers */
 861                 r = sdma_v5_2_gfx_resume(adev);
 862                 return r;
 863         }
 864
 865         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 866                 r = sdma_v5_2_load_microcode(adev);
 867                 if (r)
 868                         return r;
 869
 870                 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */
 871                 if (amdgpu_emu_mode == 1)
 872                         msleep(1000);
 873         }
 874
 875         sdma_v5_2_soft_reset(adev);
 876         /* unhalt the MEs */
 877         sdma_v5_2_enable(adev, true);
 878         /* enable sdma ring preemption */
 879         sdma_v5_2_ctx_switch_enable(adev, true);
 880
 881         /* start the gfx rings and rlc compute queues */
 882         r = sdma_v5_2_gfx_resume(adev);
 883         if (r)
 884                 return r;
 885         r = sdma_v5_2_rlc_resume(adev);
 886
 887         return r;
 888 }
 889
 890 /**
 891  * sdma_v5_2_ring_test_ring - simple async dma engine test
 892  *
 893  * @ring: amdgpu_ring structure holding ring information
 894  *
 895  * Test the DMA engine by writing using it to write an
 896  * value to memory.
 897  * Returns 0 for success, error for failure.
 898  */
 899 static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring)
 900 {
 901         struct amdgpu_device *adev = ring->adev;
 902         unsigned i;
 903         unsigned index;
 904         int r;
 905         u32 tmp;
 906         u64 gpu_addr;
 907
 908         r = amdgpu_device_wb_get(adev, &index);
 909         if (r) {
 910                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 911                 return r;
 912         }
 913
 914         gpu_addr = adev->wb.gpu_addr + (index * 4);
 915         tmp = 0xCAFEDEAD;
 916         adev->wb.wb[index] = cpu_to_le32(tmp);
 917
 918         r = amdgpu_ring_alloc(ring, 5);
 919         if (r) {
 920                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 921                 amdgpu_device_wb_free(adev, index);
 922                 return r;
 923         }
 924
 925         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 926                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 927         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 928         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 929         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 930         amdgpu_ring_write(ring, 0xDEADBEEF);
 931         amdgpu_ring_commit(ring);
 932
 933         for (i = 0; i < adev->usec_timeout; i++) {
 934                 tmp = le32_to_cpu(adev->wb.wb[index]);
 935                 if (tmp == 0xDEADBEEF)
 936                         break;
 937                 if (amdgpu_emu_mode == 1)
 938                         msleep(1);
 939                 else
 940                         udelay(1);
 941         }
 942
 943         if (i >= adev->usec_timeout)
 944                 r = -ETIMEDOUT;
 945
 946         amdgpu_device_wb_free(adev, index);
 947
 948         return r;
 949 }
 950
 951 /**
 952  * sdma_v5_2_ring_test_ib - test an IB on the DMA engine
 953  *
 954  * @ring: amdgpu_ring structure holding ring information
 955  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
 956  *
 957  * Test a simple IB in the DMA ring.
 958  * Returns 0 on success, error on failure.
 959  */
 960 static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 961 {
 962         struct amdgpu_device *adev = ring->adev;
 963         struct amdgpu_ib ib;
 964         struct dma_fence *f = NULL;
 965         unsigned index;
 966         long r;
 967         u32 tmp = 0;
 968         u64 gpu_addr;
 969
 970         r = amdgpu_device_wb_get(adev, &index);
 971         if (r) {
 972                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 973                 return r;
 974         }
 975
 976         gpu_addr = adev->wb.gpu_addr + (index * 4);
 977         tmp = 0xCAFEDEAD;
 978         adev->wb.wb[index] = cpu_to_le32(tmp);
 979         memset(&ib, 0, sizeof(ib));
 980         r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
 981         if (r) {
 982                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 983                 goto err0;
 984         }
 985
 986         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 987                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 988         ib.ptr[1] = lower_32_bits(gpu_addr);
 989         ib.ptr[2] = upper_32_bits(gpu_addr);
 990         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
 991         ib.ptr[4] = 0xDEADBEEF;
 992         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 993         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 994         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 995         ib.length_dw = 8;
 996
 997         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 998         if (r)
 999                 goto err1;
1000
1001         r = dma_fence_wait_timeout(f, false, timeout);
1002         if (r == 0) {
1003                 DRM_ERROR("amdgpu: IB test timed out\n");
1004                 r = -ETIMEDOUT;
1005                 goto err1;
1006         } else if (r < 0) {
1007                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1008                 goto err1;
1009         }
1010         tmp = le32_to_cpu(adev->wb.wb[index]);
1011         if (tmp == 0xDEADBEEF)
1012                 r = 0;
1013         else
1014                 r = -EINVAL;
1015
1016 err1:
1017         amdgpu_ib_free(adev, &ib, NULL);
1018         dma_fence_put(f);
1019 err0:
1020         amdgpu_device_wb_free(adev, index);
1021         return r;
1022 }
1023
1024
1025 /**
1026  * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART
1027  *
1028  * @ib: indirect buffer to fill with commands
1029  * @pe: addr of the page entry
1030  * @src: src addr to copy from
1031  * @count: number of page entries to update
1032  *
1033  * Update PTEs by copying them from the GART using sDMA.
1034  */
1035 static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib,
1036                                   uint64_t pe, uint64_t src,
1037                                   unsigned count)
1038 {
1039         unsigned bytes = count * 8;
1040
1041         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1042                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1043         ib->ptr[ib->length_dw++] = bytes - 1;
1044         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1045         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1046         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1047         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1048         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1049
1050 }
1051
1052 /**
1053  * sdma_v5_2_vm_write_pte - update PTEs by writing them manually
1054  *
1055  * @ib: indirect buffer to fill with commands
1056  * @pe: addr of the page entry
1057  * @value: dst addr to write into pe
1058  * @count: number of page entries to update
1059  * @incr: increase next addr by incr bytes
1060  *
1061  * Update PTEs by writing them manually using sDMA.
1062  */
1063 static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1064                                    uint64_t value, unsigned count,
1065                                    uint32_t incr)
1066 {
1067         unsigned ndw = count * 2;
1068
1069         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1070                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1071         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1072         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1073         ib->ptr[ib->length_dw++] = ndw - 1;
1074         for (; ndw > 0; ndw -= 2) {
1075                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1076                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1077                 value += incr;
1078         }
1079 }
1080
1081 /**
1082  * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA
1083  *
1084  * @ib: indirect buffer to fill with commands
1085  * @pe: addr of the page entry
1086  * @addr: dst addr to write into pe
1087  * @count: number of page entries to update
1088  * @incr: increase next addr by incr bytes
1089  * @flags: access flags
1090  *
1091  * Update the page tables using sDMA.
1092  */
1093 static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib,
1094                                      uint64_t pe,
1095                                      uint64_t addr, unsigned count,
1096                                      uint32_t incr, uint64_t flags)
1097 {
1098         /* for physically contiguous pages (vram) */
1099         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1100         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1101         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1102         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1103         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1104         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1105         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1106         ib->ptr[ib->length_dw++] = incr; /* increment size */
1107         ib->ptr[ib->length_dw++] = 0;
1108         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1109 }
1110
1111 /**
1112  * sdma_v5_2_ring_pad_ib - pad the IB
1113  *
1114  * @ib: indirect buffer to fill with padding
1115  * @ring: amdgpu_ring structure holding ring information
1116  *
1117  * Pad the IB with NOPs to a boundary multiple of 8.
1118  */
1119 static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1120 {
1121         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1122         u32 pad_count;
1123         int i;
1124
1125         pad_count = (-ib->length_dw) & 0x7;
1126         for (i = 0; i < pad_count; i++)
1127                 if (sdma && sdma->burst_nop && (i == 0))
1128                         ib->ptr[ib->length_dw++] =
1129                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1130                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1131                 else
1132                         ib->ptr[ib->length_dw++] =
1133                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1134 }
1135
1136
1137 /**
1138  * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline
1139  *
1140  * @ring: amdgpu_ring pointer
1141  *
1142  * Make sure all previous operations are completed (CIK).
1143  */
1144 static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1145 {
1146         uint32_t seq = ring->fence_drv.sync_seq;
1147         uint64_t addr = ring->fence_drv.gpu_addr;
1148
1149         /* wait for idle */
1150         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1151                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1152                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1153                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1154         amdgpu_ring_write(ring, addr & 0xfffffffc);
1155         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1156         amdgpu_ring_write(ring, seq); /* reference */
1157         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1158         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1159                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1160 }
1161
1162
1163 /**
1164  * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA
1165  *
1166  * @ring: amdgpu_ring pointer
1167  * @vmid: vmid number to use
1168  * @pd_addr: address
1169  *
1170  * Update the page table base and flush the VM TLB
1171  * using sDMA.
1172  */
1173 static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
1174                                          unsigned vmid, uint64_t pd_addr)
1175 {
1176         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1177 }
1178
1179 static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring,
1180                                      uint32_t reg, uint32_t val)
1181 {
1182         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1183                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1184         amdgpu_ring_write(ring, reg);
1185         amdgpu_ring_write(ring, val);
1186 }
1187
1188 static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1189                                          uint32_t val, uint32_t mask)
1190 {
1191         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1192                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1193                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1194         amdgpu_ring_write(ring, reg << 2);
1195         amdgpu_ring_write(ring, 0);
1196         amdgpu_ring_write(ring, val); /* reference */
1197         amdgpu_ring_write(ring, mask); /* mask */
1198         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1199                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1200 }
1201
1202 static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1203                                                    uint32_t reg0, uint32_t reg1,
1204                                                    uint32_t ref, uint32_t mask)
1205 {
1206         amdgpu_ring_emit_wreg(ring, reg0, ref);
1207         /* wait for a cycle to reset vm_inv_eng*_ack */
1208         amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1209         amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1210 }
1211
1212 static int sdma_v5_2_early_init(void *handle)
1213 {
1214         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1215
1216         switch (adev->asic_type) {
1217         case CHIP_SIENNA_CICHLID:
1218                 adev->sdma.num_instances = 4;
1219                 break;
1220         case CHIP_NAVY_FLOUNDER:
1221         case CHIP_DIMGREY_CAVEFISH:
1222                 adev->sdma.num_instances = 2;
1223                 break;
1224         case CHIP_VANGOGH:
1225                 adev->sdma.num_instances = 1;
1226                 break;
1227         default:
1228                 break;
1229         }
1230
1231         sdma_v5_2_set_ring_funcs(adev);
1232         sdma_v5_2_set_buffer_funcs(adev);
1233         sdma_v5_2_set_vm_pte_funcs(adev);
1234         sdma_v5_2_set_irq_funcs(adev);
1235
1236         return 0;
1237 }
1238
1239 static unsigned sdma_v5_2_seq_to_irq_id(int seq_num)
1240 {
1241         switch (seq_num) {
1242         case 0:
1243                 return SOC15_IH_CLIENTID_SDMA0;
1244         case 1:
1245                 return SOC15_IH_CLIENTID_SDMA1;
1246         case 2:
1247                 return SOC15_IH_CLIENTID_SDMA2;
1248         case 3:
1249                 return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid;
1250         default:
1251                 break;
1252         }
1253         return -EINVAL;
1254 }
1255
1256 static unsigned sdma_v5_2_seq_to_trap_id(int seq_num)
1257 {
1258         switch (seq_num) {
1259         case 0:
1260                 return SDMA0_5_0__SRCID__SDMA_TRAP;
1261         case 1:
1262                 return SDMA1_5_0__SRCID__SDMA_TRAP;
1263         case 2:
1264                 return SDMA2_5_0__SRCID__SDMA_TRAP;
1265         case 3:
1266                 return SDMA3_5_0__SRCID__SDMA_TRAP;
1267         default:
1268                 break;
1269         }
1270         return -EINVAL;
1271 }
1272
1273 static int sdma_v5_2_sw_init(void *handle)
1274 {
1275         struct amdgpu_ring *ring;
1276         int r, i;
1277         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1278
1279         /* SDMA trap event */
1280         for (i = 0; i < adev->sdma.num_instances; i++) {
1281                 r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i),
1282                                       sdma_v5_2_seq_to_trap_id(i),
1283                                       &adev->sdma.trap_irq);
1284                 if (r)
1285                         return r;
1286         }
1287
1288         r = sdma_v5_2_init_microcode(adev);
1289         if (r) {
1290                 DRM_ERROR("Failed to load sdma firmware!\n");
1291                 return r;
1292         }
1293
1294         for (i = 0; i < adev->sdma.num_instances; i++) {
1295                 ring = &adev->sdma.instance[i].ring;
1296                 ring->ring_obj = NULL;
1297                 ring->use_doorbell = true;
1298                 ring->me = i;
1299
1300                 DRM_INFO("use_doorbell being set to: [%s]\n",
1301                                 ring->use_doorbell?"true":"false");
1302
1303                 ring->doorbell_index =
1304                         (adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset
1305
1306                 sprintf(ring->name, "sdma%d", i);
1307                 r = amdgpu_ring_init(adev, ring, 1024,
1308                                      &adev->sdma.trap_irq,
1309                                      AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1310                                      AMDGPU_RING_PRIO_DEFAULT);
1311                 if (r)
1312                         return r;
1313         }
1314
1315         return r;
1316 }
1317
1318 static int sdma_v5_2_sw_fini(void *handle)
1319 {
1320         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1321         int i;
1322
1323         for (i = 0; i < adev->sdma.num_instances; i++)
1324                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1325
1326         sdma_v5_2_destroy_inst_ctx(adev);
1327
1328         return 0;
1329 }
1330
1331 static int sdma_v5_2_hw_init(void *handle)
1332 {
1333         int r;
1334         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1335
1336         sdma_v5_2_init_golden_registers(adev);
1337
1338         r = sdma_v5_2_start(adev);
1339
1340         return r;
1341 }
1342
1343 static int sdma_v5_2_hw_fini(void *handle)
1344 {
1345         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1346
1347         if (amdgpu_sriov_vf(adev))
1348                 return 0;
1349
1350         sdma_v5_2_ctx_switch_enable(adev, false);
1351         sdma_v5_2_enable(adev, false);
1352
1353         return 0;
1354 }
1355
1356 static int sdma_v5_2_suspend(void *handle)
1357 {
1358         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1359
1360         return sdma_v5_2_hw_fini(adev);
1361 }
1362
1363 static int sdma_v5_2_resume(void *handle)
1364 {
1365         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1366
1367         return sdma_v5_2_hw_init(adev);
1368 }
1369
1370 static bool sdma_v5_2_is_idle(void *handle)
1371 {
1372         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1373         u32 i;
1374
1375         for (i = 0; i < adev->sdma.num_instances; i++) {
1376                 u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1377
1378                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1379                         return false;
1380         }
1381
1382         return true;
1383 }
1384
1385 static int sdma_v5_2_wait_for_idle(void *handle)
1386 {
1387         unsigned i;
1388         u32 sdma0, sdma1, sdma2, sdma3;
1389         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1390
1391         for (i = 0; i < adev->usec_timeout; i++) {
1392                 sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1393                 sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1394                 sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG));
1395                 sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG));
1396
1397                 if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK)
1398                         return 0;
1399                 udelay(1);
1400         }
1401         return -ETIMEDOUT;
1402 }
1403
1404 static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring)
1405 {
1406         int i, r = 0;
1407         struct amdgpu_device *adev = ring->adev;
1408         u32 index = 0;
1409         u64 sdma_gfx_preempt;
1410
1411         amdgpu_sdma_get_index_from_ring(ring, &index);
1412         sdma_gfx_preempt =
1413                 sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT);
1414
1415         /* assert preemption condition */
1416         amdgpu_ring_set_preempt_cond_exec(ring, false);
1417
1418         /* emit the trailing fence */
1419         ring->trail_seq += 1;
1420         amdgpu_ring_alloc(ring, 10);
1421         sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1422                                   ring->trail_seq, 0);
1423         amdgpu_ring_commit(ring);
1424
1425         /* assert IB preemption */
1426         WREG32(sdma_gfx_preempt, 1);
1427
1428         /* poll the trailing fence */
1429         for (i = 0; i < adev->usec_timeout; i++) {
1430                 if (ring->trail_seq ==
1431                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1432                         break;
1433                 udelay(1);
1434         }
1435
1436         if (i >= adev->usec_timeout) {
1437                 r = -EINVAL;
1438                 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1439         }
1440
1441         /* deassert IB preemption */
1442         WREG32(sdma_gfx_preempt, 0);
1443
1444         /* deassert the preemption condition */
1445         amdgpu_ring_set_preempt_cond_exec(ring, true);
1446         return r;
1447 }
1448
1449 static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev,
1450                                         struct amdgpu_irq_src *source,
1451                                         unsigned type,
1452                                         enum amdgpu_interrupt_state state)
1453 {
1454         u32 sdma_cntl;
1455
1456         u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL);
1457
1458         sdma_cntl = RREG32(reg_offset);
1459         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1460                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1461         WREG32(reg_offset, sdma_cntl);
1462
1463         return 0;
1464 }
1465
1466 static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev,
1467                                       struct amdgpu_irq_src *source,
1468                                       struct amdgpu_iv_entry *entry)
1469 {
1470         DRM_DEBUG("IH: SDMA trap\n");
1471         switch (entry->client_id) {
1472         case SOC15_IH_CLIENTID_SDMA0:
1473                 switch (entry->ring_id) {
1474                 case 0:
1475                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1476                         break;
1477                 case 1:
1478                         /* XXX compute */
1479                         break;
1480                 case 2:
1481                         /* XXX compute */
1482                         break;
1483                 case 3:
1484                         /* XXX page queue*/
1485                         break;
1486                 }
1487                 break;
1488         case SOC15_IH_CLIENTID_SDMA1:
1489                 switch (entry->ring_id) {
1490                 case 0:
1491                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1492                         break;
1493                 case 1:
1494                         /* XXX compute */
1495                         break;
1496                 case 2:
1497                         /* XXX compute */
1498                         break;
1499                 case 3:
1500                         /* XXX page queue*/
1501                         break;
1502                 }
1503                 break;
1504         case SOC15_IH_CLIENTID_SDMA2:
1505                 switch (entry->ring_id) {
1506                 case 0:
1507                         amdgpu_fence_process(&adev->sdma.instance[2].ring);
1508                         break;
1509                 case 1:
1510                         /* XXX compute */
1511                         break;
1512                 case 2:
1513                         /* XXX compute */
1514                         break;
1515                 case 3:
1516                         /* XXX page queue*/
1517                         break;
1518                 }
1519                 break;
1520         case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid:
1521                 switch (entry->ring_id) {
1522                 case 0:
1523                         amdgpu_fence_process(&adev->sdma.instance[3].ring);
1524                         break;
1525                 case 1:
1526                         /* XXX compute */
1527                         break;
1528                 case 2:
1529                         /* XXX compute */
1530                         break;
1531                 case 3:
1532                         /* XXX page queue*/
1533                         break;
1534                 }
1535                 break;
1536         }
1537         return 0;
1538 }
1539
1540 static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev,
1541                                               struct amdgpu_irq_src *source,
1542                                               struct amdgpu_iv_entry *entry)
1543 {
1544         return 0;
1545 }
1546
1547 static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1548                                                        bool enable)
1549 {
1550         uint32_t data, def;
1551         int i;
1552
1553         for (i = 0; i < adev->sdma.num_instances; i++) {
1554                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1555                         /* Enable sdma clock gating */
1556                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1557                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1558                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1559                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1560                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1561                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1562                                   SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1563                         if (def != data)
1564                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1565                 } else {
1566                         /* Disable sdma clock gating */
1567                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1568                         data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1569                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1570                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1571                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1572                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1573                                  SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1574                         if (def != data)
1575                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1576                 }
1577         }
1578 }
1579
1580 static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1581                                                       bool enable)
1582 {
1583         uint32_t data, def;
1584         int i;
1585
1586         for (i = 0; i < adev->sdma.num_instances; i++) {
1587                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1588                         /* Enable sdma mem light sleep */
1589                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1590                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1591                         if (def != data)
1592                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1593
1594                 } else {
1595                         /* Disable sdma mem light sleep */
1596                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1597                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1598                         if (def != data)
1599                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1600
1601                 }
1602         }
1603 }
1604
1605 static int sdma_v5_2_set_clockgating_state(void *handle,
1606                                            enum amd_clockgating_state state)
1607 {
1608         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1609
1610         if (amdgpu_sriov_vf(adev))
1611                 return 0;
1612
1613         switch (adev->asic_type) {
1614         case CHIP_SIENNA_CICHLID:
1615         case CHIP_NAVY_FLOUNDER:
1616         case CHIP_VANGOGH:
1617         case CHIP_DIMGREY_CAVEFISH:
1618                 sdma_v5_2_update_medium_grain_clock_gating(adev,
1619                                 state == AMD_CG_STATE_GATE ? true : false);
1620                 sdma_v5_2_update_medium_grain_light_sleep(adev,
1621                                 state == AMD_CG_STATE_GATE ? true : false);
1622                 break;
1623         default:
1624                 break;
1625         }
1626
1627         return 0;
1628 }
1629
1630 static int sdma_v5_2_set_powergating_state(void *handle,
1631                                           enum amd_powergating_state state)
1632 {
1633         return 0;
1634 }
1635
1636 static void sdma_v5_2_get_clockgating_state(void *handle, u32 *flags)
1637 {
1638         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1639         int data;
1640
1641         if (amdgpu_sriov_vf(adev))
1642                 *flags = 0;
1643
1644         /* AMD_CG_SUPPORT_SDMA_LS */
1645         data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1646         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1647                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1648 }
1649
1650 const struct amd_ip_funcs sdma_v5_2_ip_funcs = {
1651         .name = "sdma_v5_2",
1652         .early_init = sdma_v5_2_early_init,
1653         .late_init = NULL,
1654         .sw_init = sdma_v5_2_sw_init,
1655         .sw_fini = sdma_v5_2_sw_fini,
1656         .hw_init = sdma_v5_2_hw_init,
1657         .hw_fini = sdma_v5_2_hw_fini,
1658         .suspend = sdma_v5_2_suspend,
1659         .resume = sdma_v5_2_resume,
1660         .is_idle = sdma_v5_2_is_idle,
1661         .wait_for_idle = sdma_v5_2_wait_for_idle,
1662         .soft_reset = sdma_v5_2_soft_reset,
1663         .set_clockgating_state = sdma_v5_2_set_clockgating_state,
1664         .set_powergating_state = sdma_v5_2_set_powergating_state,
1665         .get_clockgating_state = sdma_v5_2_get_clockgating_state,
1666 };
1667
1668 static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {
1669         .type = AMDGPU_RING_TYPE_SDMA,
1670         .align_mask = 0xf,
1671         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1672         .support_64bit_ptrs = true,
1673         .vmhub = AMDGPU_GFXHUB_0,
1674         .get_rptr = sdma_v5_2_ring_get_rptr,
1675         .get_wptr = sdma_v5_2_ring_get_wptr,
1676         .set_wptr = sdma_v5_2_ring_set_wptr,
1677         .emit_frame_size =
1678                 5 + /* sdma_v5_2_ring_init_cond_exec */
1679                 6 + /* sdma_v5_2_ring_emit_hdp_flush */
1680                 3 + /* hdp_invalidate */
1681                 6 + /* sdma_v5_2_ring_emit_pipeline_sync */
1682                 /* sdma_v5_2_ring_emit_vm_flush */
1683                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1684                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1685                 10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */
1686         .emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */
1687         .emit_ib = sdma_v5_2_ring_emit_ib,
1688         .emit_fence = sdma_v5_2_ring_emit_fence,
1689         .emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync,
1690         .emit_vm_flush = sdma_v5_2_ring_emit_vm_flush,
1691         .emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush,
1692         .test_ring = sdma_v5_2_ring_test_ring,
1693         .test_ib = sdma_v5_2_ring_test_ib,
1694         .insert_nop = sdma_v5_2_ring_insert_nop,
1695         .pad_ib = sdma_v5_2_ring_pad_ib,
1696         .emit_wreg = sdma_v5_2_ring_emit_wreg,
1697         .emit_reg_wait = sdma_v5_2_ring_emit_reg_wait,
1698         .emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait,
1699         .init_cond_exec = sdma_v5_2_ring_init_cond_exec,
1700         .patch_cond_exec = sdma_v5_2_ring_patch_cond_exec,
1701         .preempt_ib = sdma_v5_2_ring_preempt_ib,
1702 };
1703
1704 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev)
1705 {
1706         int i;
1707
1708         for (i = 0; i < adev->sdma.num_instances; i++) {
1709                 adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs;
1710                 adev->sdma.instance[i].ring.me = i;
1711         }
1712 }
1713
1714 static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = {
1715         .set = sdma_v5_2_set_trap_irq_state,
1716         .process = sdma_v5_2_process_trap_irq,
1717 };
1718
1719 static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = {
1720         .process = sdma_v5_2_process_illegal_inst_irq,
1721 };
1722
1723 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev)
1724 {
1725         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1726                                         adev->sdma.num_instances;
1727         adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs;
1728         adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs;
1729 }
1730
1731 /**
1732  * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine
1733  *
1734  * @ib: indirect buffer to copy to
1735  * @src_offset: src GPU address
1736  * @dst_offset: dst GPU address
1737  * @byte_count: number of bytes to xfer
1738  * @tmz: if a secure copy should be used
1739  *
1740  * Copy GPU buffers using the DMA engine.
1741  * Used by the amdgpu ttm implementation to move pages if
1742  * registered as the asic copy callback.
1743  */
1744 static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib,
1745                                        uint64_t src_offset,
1746                                        uint64_t dst_offset,
1747                                        uint32_t byte_count,
1748                                        bool tmz)
1749 {
1750         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1751                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1752                 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1753         ib->ptr[ib->length_dw++] = byte_count - 1;
1754         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1755         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1756         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1757         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1758         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1759 }
1760
1761 /**
1762  * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine
1763  *
1764  * @ib: indirect buffer to fill
1765  * @src_data: value to write to buffer
1766  * @dst_offset: dst GPU address
1767  * @byte_count: number of bytes to xfer
1768  *
1769  * Fill GPU buffers using the DMA engine.
1770  */
1771 static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
1772                                        uint32_t src_data,
1773                                        uint64_t dst_offset,
1774                                        uint32_t byte_count)
1775 {
1776         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1777         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1778         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1779         ib->ptr[ib->length_dw++] = src_data;
1780         ib->ptr[ib->length_dw++] = byte_count - 1;
1781 }
1782
1783 static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = {
1784         .copy_max_bytes = 0x400000,
1785         .copy_num_dw = 7,
1786         .emit_copy_buffer = sdma_v5_2_emit_copy_buffer,
1787
1788         .fill_max_bytes = 0x400000,
1789         .fill_num_dw = 5,
1790         .emit_fill_buffer = sdma_v5_2_emit_fill_buffer,
1791 };
1792
1793 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev)
1794 {
1795         if (adev->mman.buffer_funcs == NULL) {
1796                 adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs;
1797                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1798         }
1799 }
1800
1801 static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = {
1802         .copy_pte_num_dw = 7,
1803         .copy_pte = sdma_v5_2_vm_copy_pte,
1804         .write_pte = sdma_v5_2_vm_write_pte,
1805         .set_pte_pde = sdma_v5_2_vm_set_pte_pde,
1806 };
1807
1808 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev)
1809 {
1810         unsigned i;
1811
1812         if (adev->vm_manager.vm_pte_funcs == NULL) {
1813                 adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs;
1814                 for (i = 0; i < adev->sdma.num_instances; i++) {
1815                         adev->vm_manager.vm_pte_scheds[i] =
1816                                 &adev->sdma.instance[i].ring.sched;
1817                 }
1818                 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1819         }
1820 }
1821
1822 const struct amdgpu_ip_block_version sdma_v5_2_ip_block = {
1823         .type = AMD_IP_BLOCK_TYPE_SDMA,
1824         .major = 5,
1825         .minor = 2,
1826         .rev = 0,
1827         .funcs = &sdma_v5_2_ip_funcs,
1828 };