drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_ucode.h"
  31 #include "amdgpu_trace.h"
  32
  33 #include "gc/gc_10_3_0_offset.h"
  34 #include "gc/gc_10_3_0_sh_mask.h"
  35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
  36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
  37 #include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h"
  38 #include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h"
  39
  40 #include "soc15_common.h"
  41 #include "soc15.h"
  42 #include "navi10_sdma_pkt_open.h"
  43 #include "nbio_v2_3.h"
  44 #include "sdma_common.h"
  45 #include "sdma_v5_2.h"
  46
  47 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin");
  48
  49 #define SDMA1_REG_OFFSET 0x600
  50 #define SDMA3_REG_OFFSET 0x400
  51 #define SDMA0_HYP_DEC_REG_START 0x5880
  52 #define SDMA0_HYP_DEC_REG_END 0x5893
  53 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
  54
  55 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev);
  56 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev);
  57 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev);
  58 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev);
  59
  60 static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
  61 {
  62         u32 base;
  63
  64         if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
  65             internal_offset <= SDMA0_HYP_DEC_REG_END) {
  66                 base = adev->reg_offset[GC_HWIP][0][1];
  67                 if (instance != 0)
  68                         internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
  69         } else {
  70                 if (instance < 2) {
  71                         base = adev->reg_offset[GC_HWIP][0][0];
  72                         if (instance == 1)
  73                                 internal_offset += SDMA1_REG_OFFSET;
  74                 } else {
  75                         base = adev->reg_offset[GC_HWIP][0][2];
  76                         if (instance == 3)
  77                                 internal_offset += SDMA3_REG_OFFSET;
  78                 }
  79         }
  80
  81         return base + internal_offset;
  82 }
  83
  84 static void sdma_v5_2_init_golden_registers(struct amdgpu_device *adev)
  85 {
  86         switch (adev->asic_type) {
  87         case CHIP_SIENNA_CICHLID:
  88                 break;
  89         default:
  90                 break;
  91         }
  92 }
  93
  94 static int sdma_v5_2_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
  95 {
  96         int err = 0;
  97         const struct sdma_firmware_header_v1_0 *hdr;
  98
  99         err = amdgpu_ucode_validate(sdma_inst->fw);
 100         if (err)
 101                 return err;
 102
 103         hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
 104         sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
 105         sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
 106
 107         if (sdma_inst->feature_version >= 20)
 108                 sdma_inst->burst_nop = true;
 109
 110         return 0;
 111 }
 112
 113 static void sdma_v5_2_destroy_inst_ctx(struct amdgpu_device *adev)
 114 {
 115         int i;
 116
 117         for (i = 0; i < adev->sdma.num_instances; i++) {
 118                 if (adev->sdma.instance[i].fw != NULL)
 119                         release_firmware(adev->sdma.instance[i].fw);
 120
 121                 if (adev->asic_type == CHIP_SIENNA_CICHLID)
 122                         break;
 123         }
 124
 125         memset((void*)adev->sdma.instance, 0,
 126                sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
 127 }
 128
 129 /**
 130  * sdma_v5_2_init_microcode - load ucode images from disk
 131  *
 132  * @adev: amdgpu_device pointer
 133  *
 134  * Use the firmware interface to load the ucode images into
 135  * the driver (not loaded into hw).
 136  * Returns 0 on success, error on failure.
 137  */
 138
 139 // emulation only, won't work on real chip
 140 // navi10 real chip need to use PSP to load firmware
 141 static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
 142 {
 143         const char *chip_name;
 144         char fw_name[40];
 145         int err = 0, i;
 146         struct amdgpu_firmware_info *info = NULL;
 147         const struct common_firmware_header *header = NULL;
 148
 149         DRM_DEBUG("\n");
 150
 151         switch (adev->asic_type) {
 152         case CHIP_SIENNA_CICHLID:
 153                 chip_name = "sienna_cichlid";
 154                 break;
 155         default:
 156                 BUG();
 157         }
 158
 159         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 160
 161         err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);
 162         if (err)
 163                 goto out;
 164
 165         err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]);
 166         if (err)
 167                 goto out;
 168
 169         for (i = 1; i < adev->sdma.num_instances; i++) {
 170                 if (adev->asic_type == CHIP_SIENNA_CICHLID) {
 171                         memcpy((void*)&adev->sdma.instance[i],
 172                                (void*)&adev->sdma.instance[0],
 173                                sizeof(struct amdgpu_sdma_instance));
 174                 } else {
 175                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i);
 176                         err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 177                         if (err)
 178                                 goto out;
 179
 180                         err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]);
 181                         if (err)
 182                                 goto out;
 183                 }
 184         }
 185
 186         DRM_DEBUG("psp_load == '%s'\n",
 187                   adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
 188
 189         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 190                 for (i = 0; i < adev->sdma.num_instances; i++) {
 191                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 192                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 193                         info->fw = adev->sdma.instance[i].fw;
 194                         header = (const struct common_firmware_header *)info->fw->data;
 195                         adev->firmware.fw_size +=
 196                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 197                 }
 198         }
 199
 200 out:
 201         if (err) {
 202                 DRM_ERROR("sdma_v5_2: Failed to load firmware \"%s\"\n", fw_name);
 203                 sdma_v5_2_destroy_inst_ctx(adev);
 204         }
 205         return err;
 206 }
 207
 208 static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring)
 209 {
 210         unsigned ret;
 211
 212         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
 213         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
 214         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
 215         amdgpu_ring_write(ring, 1);
 216         ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
 217         amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
 218
 219         return ret;
 220 }
 221
 222 static void sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring *ring,
 223                                            unsigned offset)
 224 {
 225         unsigned cur;
 226
 227         BUG_ON(offset > ring->buf_mask);
 228         BUG_ON(ring->ring[offset] != 0x55aa55aa);
 229
 230         cur = (ring->wptr - 1) & ring->buf_mask;
 231         if (cur > offset)
 232                 ring->ring[offset] = cur - offset;
 233         else
 234                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
 235 }
 236
 237 /**
 238  * sdma_v5_2_ring_get_rptr - get the current read pointer
 239  *
 240  * @ring: amdgpu ring pointer
 241  *
 242  * Get the current rptr from the hardware (NAVI10+).
 243  */
 244 static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring)
 245 {
 246         u64 *rptr;
 247
 248         /* XXX check if swapping is necessary on BE */
 249         rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
 250
 251         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 252         return ((*rptr) >> 2);
 253 }
 254
 255 /**
 256  * sdma_v5_2_ring_get_wptr - get the current write pointer
 257  *
 258  * @ring: amdgpu ring pointer
 259  *
 260  * Get the current wptr from the hardware (NAVI10+).
 261  */
 262 static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring)
 263 {
 264         struct amdgpu_device *adev = ring->adev;
 265         u64 *wptr = NULL;
 266         uint64_t local_wptr = 0;
 267
 268         if (ring->use_doorbell) {
 269                 /* XXX check if swapping is necessary on BE */
 270                 wptr = ((u64 *)&adev->wb.wb[ring->wptr_offs]);
 271                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", *wptr);
 272                 *wptr = (*wptr) >> 2;
 273                 DRM_DEBUG("wptr/doorbell after shift == 0x%016llx\n", *wptr);
 274         } else {
 275                 u32 lowbit, highbit;
 276
 277                 wptr = &local_wptr;
 278                 lowbit = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)) >> 2;
 279                 highbit = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
 280
 281                 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",
 282                                 ring->me, highbit, lowbit);
 283                 *wptr = highbit;
 284                 *wptr = (*wptr) << 32;
 285                 *wptr |= lowbit;
 286         }
 287
 288         return *wptr;
 289 }
 290
 291 /**
 292  * sdma_v5_2_ring_set_wptr - commit the write pointer
 293  *
 294  * @ring: amdgpu ring pointer
 295  *
 296  * Write the wptr back to the hardware (NAVI10+).
 297  */
 298 static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring)
 299 {
 300         struct amdgpu_device *adev = ring->adev;
 301
 302         DRM_DEBUG("Setting write pointer\n");
 303         if (ring->use_doorbell) {
 304                 DRM_DEBUG("Using doorbell -- "
 305                                 "wptr_offs == 0x%08x "
 306                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 307                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 308                                 ring->wptr_offs,
 309                                 lower_32_bits(ring->wptr << 2),
 310                                 upper_32_bits(ring->wptr << 2));
 311                 /* XXX check if swapping is necessary on BE */
 312                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
 313                 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
 314                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 315                                 ring->doorbell_index, ring->wptr << 2);
 316                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 317         } else {
 318                 DRM_DEBUG("Not using doorbell -- "
 319                                 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 320                                 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 321                                 ring->me,
 322                                 lower_32_bits(ring->wptr << 2),
 323                                 ring->me,
 324                                 upper_32_bits(ring->wptr << 2));
 325                 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
 326                         lower_32_bits(ring->wptr << 2));
 327                 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
 328                         upper_32_bits(ring->wptr << 2));
 329         }
 330 }
 331
 332 static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 333 {
 334         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 335         int i;
 336
 337         for (i = 0; i < count; i++)
 338                 if (sdma && sdma->burst_nop && (i == 0))
 339                         amdgpu_ring_write(ring, ring->funcs->nop |
 340                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 341                 else
 342                         amdgpu_ring_write(ring, ring->funcs->nop);
 343 }
 344
 345 /**
 346  * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine
 347  *
 348  * @ring: amdgpu ring pointer
 349  * @ib: IB object to schedule
 350  *
 351  * Schedule an IB in the DMA ring.
 352  */
 353 static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring,
 354                                    struct amdgpu_job *job,
 355                                    struct amdgpu_ib *ib,
 356                                    uint32_t flags)
 357 {
 358         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 359         uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
 360
 361         /* An IB packet must end on a 8 DW boundary--the next dword
 362          * must be on a 8-dword boundary. Our IB packet below is 6
 363          * dwords long, thus add x number of NOPs, such that, in
 364          * modular arithmetic,
 365          * wptr + 6 + x = 8k, k >= 0, which in C is,
 366          * (wptr + 6 + x) % 8 = 0.
 367          * The expression below, is a solution of x.
 368          */
 369         sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 370
 371         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 372                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 373         /* base must be 32 byte aligned */
 374         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 375         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 376         amdgpu_ring_write(ring, ib->length_dw);
 377         amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
 378         amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
 379 }
 380
 381 /**
 382  * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 383  *
 384  * @ring: amdgpu ring pointer
 385  *
 386  * Emit an hdp flush packet on the requested DMA ring.
 387  */
 388 static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 389 {
 390         struct amdgpu_device *adev = ring->adev;
 391         u32 ref_and_mask = 0;
 392         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 393
 394         ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
 395
 396         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 397                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 398                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 399         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
 400         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
 401         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 402         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 403         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 404                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 405 }
 406
 407 /**
 408  * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring
 409  *
 410  * @ring: amdgpu ring pointer
 411  * @fence: amdgpu fence object
 412  *
 413  * Add a DMA fence packet to the ring to write
 414  * the fence seq number and DMA trap packet to generate
 415  * an interrupt if needed.
 416  */
 417 static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 418                                       unsigned flags)
 419 {
 420         struct amdgpu_device *adev = ring->adev;
 421         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 422         /* write the fence */
 423         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 424                           SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
 425         /* zero in first two bits */
 426         BUG_ON(addr & 0x3);
 427         amdgpu_ring_write(ring, lower_32_bits(addr));
 428         amdgpu_ring_write(ring, upper_32_bits(addr));
 429         amdgpu_ring_write(ring, lower_32_bits(seq));
 430
 431         /* optionally write high bits as well */
 432         if (write64bit) {
 433                 addr += 4;
 434                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 435                                   SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
 436                 /* zero in first two bits */
 437                 BUG_ON(addr & 0x3);
 438                 amdgpu_ring_write(ring, lower_32_bits(addr));
 439                 amdgpu_ring_write(ring, upper_32_bits(addr));
 440                 amdgpu_ring_write(ring, upper_32_bits(seq));
 441         }
 442
 443         /* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */
 444         if ((flags & AMDGPU_FENCE_FLAG_INT) && adev->pdev->device != 0x50) {
 445                 /* generate an interrupt */
 446                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 447                 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 448         }
 449 }
 450
 451
 452 /**
 453  * sdma_v5_2_gfx_stop - stop the gfx async dma engines
 454  *
 455  * @adev: amdgpu_device pointer
 456  *
 457  * Stop the gfx async dma ring buffers.
 458  */
 459 static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev)
 460 {
 461         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 462         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 463         struct amdgpu_ring *sdma2 = &adev->sdma.instance[2].ring;
 464         struct amdgpu_ring *sdma3 = &adev->sdma.instance[3].ring;
 465         u32 rb_cntl, ib_cntl;
 466         int i;
 467
 468         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 469             (adev->mman.buffer_funcs_ring == sdma1) ||
 470             (adev->mman.buffer_funcs_ring == sdma2) ||
 471             (adev->mman.buffer_funcs_ring == sdma3))
 472                 amdgpu_ttm_set_buffer_funcs_status(adev, false);
 473
 474         for (i = 0; i < adev->sdma.num_instances; i++) {
 475                 rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 476                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 477                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 478                 ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 479                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 480                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 481         }
 482
 483         sdma0->sched.ready = false;
 484         sdma1->sched.ready = false;
 485         sdma2->sched.ready = false;
 486         sdma3->sched.ready = false;
 487 }
 488
 489 /**
 490  * sdma_v5_2_rlc_stop - stop the compute async dma engines
 491  *
 492  * @adev: amdgpu_device pointer
 493  *
 494  * Stop the compute async dma queues.
 495  */
 496 static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev)
 497 {
 498         /* XXX todo */
 499 }
 500
 501 /**
 502  * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
 503  *
 504  * @adev: amdgpu_device pointer
 505  * @enable: enable/disable the DMA MEs context switch.
 506  *
 507  * Halt or unhalt the async dma engines context switch.
 508  */
 509 static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 510 {
 511         u32 f32_cntl, phase_quantum = 0;
 512         int i;
 513
 514         if (amdgpu_sdma_phase_quantum) {
 515                 unsigned value = amdgpu_sdma_phase_quantum;
 516                 unsigned unit = 0;
 517
 518                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 519                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 520                         value = (value + 1) >> 1;
 521                         unit++;
 522                 }
 523                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 524                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 525                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 526                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 527                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 528                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 529                         WARN_ONCE(1,
 530                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 531                                   value << unit);
 532                 }
 533                 phase_quantum =
 534                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 535                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 536         }
 537
 538         for (i = 0; i < adev->sdma.num_instances; i++) {
 539                 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
 540                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 541                                 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 542                 if (enable && amdgpu_sdma_phase_quantum) {
 543                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
 544                                phase_quantum);
 545                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
 546                                phase_quantum);
 547                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
 548                                phase_quantum);
 549                 }
 550                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
 551         }
 552
 553 }
 554
 555 /**
 556  * sdma_v5_2_enable - stop the async dma engines
 557  *
 558  * @adev: amdgpu_device pointer
 559  * @enable: enable/disable the DMA MEs.
 560  *
 561  * Halt or unhalt the async dma engines.
 562  */
 563 static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable)
 564 {
 565         u32 f32_cntl;
 566         int i;
 567
 568         if (enable == false) {
 569                 sdma_v5_2_gfx_stop(adev);
 570                 sdma_v5_2_rlc_stop(adev);
 571         }
 572
 573         for (i = 0; i < adev->sdma.num_instances; i++) {
 574                 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 575                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 576                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
 577         }
 578 }
 579
 580 /**
 581  * sdma_v5_2_gfx_resume - setup and start the async dma engines
 582  *
 583  * @adev: amdgpu_device pointer
 584  *
 585  * Set up the gfx DMA ring buffers and enable them.
 586  * Returns 0 for success, error for failure.
 587  */
 588 static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
 589 {
 590         struct amdgpu_ring *ring;
 591         u32 rb_cntl, ib_cntl;
 592         u32 rb_bufsz;
 593         u32 wb_offset;
 594         u32 doorbell;
 595         u32 doorbell_offset;
 596         u32 temp;
 597         u32 wptr_poll_cntl;
 598         u64 wptr_gpu_addr;
 599         int i, r;
 600
 601         for (i = 0; i < adev->sdma.num_instances; i++) {
 602                 ring = &adev->sdma.instance[i].ring;
 603                 wb_offset = (ring->rptr_offs * 4);
 604
 605                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 606
 607                 /* Set ring buffer size in dwords */
 608                 rb_bufsz = order_base_2(ring->ring_size / 4);
 609                 rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 610                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 611 #ifdef __BIG_ENDIAN
 612                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 613                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 614                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 615 #endif
 616                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 617
 618                 /* Initialize the ring buffer's read and write pointers */
 619                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
 620                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
 621                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
 622                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 623
 624                 /* setup the wptr shadow polling */
 625                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 626                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
 627                        lower_32_bits(wptr_gpu_addr));
 628                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
 629                        upper_32_bits(wptr_gpu_addr));
 630                 wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i,
 631                                                          mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 632                 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 633                                                SDMA0_GFX_RB_WPTR_POLL_CNTL,
 634                                                F32_POLL_ENABLE, 1);
 635                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
 636                        wptr_poll_cntl);
 637
 638                 /* set the wb address whether it's enabled or not */
 639                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
 640                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 641                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
 642                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 643
 644                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 645
 646                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
 647                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
 648
 649                 ring->wptr = 0;
 650
 651                 /* before programing wptr to a less value, need set minor_ptr_update first */
 652                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
 653
 654                 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 655                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
 656                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
 657                 }
 658
 659                 doorbell = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
 660                 doorbell_offset = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
 661
 662                 if (ring->use_doorbell) {
 663                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 664                         doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
 665                                         OFFSET, ring->doorbell_index);
 666                 } else {
 667                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 668                 }
 669                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
 670                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
 671
 672                 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 673                                                       ring->doorbell_index,
 674                                                       adev->doorbell_index.sdma_doorbell_range);
 675
 676                 if (amdgpu_sriov_vf(adev))
 677                         sdma_v5_2_ring_set_wptr(ring);
 678
 679                 /* set minor_ptr_update to 0 after wptr programed */
 680                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
 681
 682                 /* set utc l1 enable flag always to 1 */
 683                 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
 684                 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
 685
 686                 /* enable MCBP */
 687                 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
 688                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
 689
 690                 /* Set up RESP_MODE to non-copy addresses */
 691                 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
 692                 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
 693                 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
 694                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
 695
 696                 /* program default cache read and write policy */
 697                 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
 698                 /* clean read policy and write policy bits */
 699                 temp &= 0xFF0FFF;
 700                 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
 701                          (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
 702                          0x01000000);
 703                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
 704
 705                 if (!amdgpu_sriov_vf(adev)) {
 706                         /* unhalt engine */
 707                         temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 708                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 709                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
 710                 }
 711
 712                 /* enable DMA RB */
 713                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 714                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 715
 716                 ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 717                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 718 #ifdef __BIG_ENDIAN
 719                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 720 #endif
 721                 /* enable DMA IBs */
 722                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 723
 724                 ring->sched.ready = true;
 725
 726                 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
 727                         sdma_v5_2_ctx_switch_enable(adev, true);
 728                         sdma_v5_2_enable(adev, true);
 729                 }
 730
 731                 r = amdgpu_ring_test_ring(ring);
 732                 if (r) {
 733                         ring->sched.ready = false;
 734                         return r;
 735                 }
 736
 737                 if (adev->mman.buffer_funcs_ring == ring)
 738                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 739         }
 740
 741         return 0;
 742 }
 743
 744 /**
 745  * sdma_v5_2_rlc_resume - setup and start the async dma engines
 746  *
 747  * @adev: amdgpu_device pointer
 748  *
 749  * Set up the compute DMA queues and enable them.
 750  * Returns 0 for success, error for failure.
 751  */
 752 static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev)
 753 {
 754         return 0;
 755 }
 756
 757 /**
 758  * sdma_v5_2_load_microcode - load the sDMA ME ucode
 759  *
 760  * @adev: amdgpu_device pointer
 761  *
 762  * Loads the sDMA0/1/2/3 ucode.
 763  * Returns 0 for success, -EINVAL if the ucode is not available.
 764  */
 765 static int sdma_v5_2_load_microcode(struct amdgpu_device *adev)
 766 {
 767         const struct sdma_firmware_header_v1_0 *hdr;
 768         const __le32 *fw_data;
 769         u32 fw_size;
 770         int i, j;
 771
 772         /* halt the MEs */
 773         sdma_v5_2_enable(adev, false);
 774
 775         for (i = 0; i < adev->sdma.num_instances; i++) {
 776                 if (!adev->sdma.instance[i].fw)
 777                         return -EINVAL;
 778
 779                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 780                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 781                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 782
 783                 fw_data = (const __le32 *)
 784                         (adev->sdma.instance[i].fw->data +
 785                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 786
 787                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
 788
 789                 for (j = 0; j < fw_size; j++) {
 790                         if (amdgpu_emu_mode == 1 && j % 500 == 0)
 791                                 msleep(1);
 792                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 793                 }
 794
 795                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
 796         }
 797
 798         return 0;
 799 }
 800
 801 /**
 802  * sdma_v5_2_start - setup and start the async dma engines
 803  *
 804  * @adev: amdgpu_device pointer
 805  *
 806  * Set up the DMA engines and enable them.
 807  * Returns 0 for success, error for failure.
 808  */
 809 static int sdma_v5_2_start(struct amdgpu_device *adev)
 810 {
 811         int r = 0;
 812
 813         if (amdgpu_sriov_vf(adev)) {
 814                 sdma_v5_2_ctx_switch_enable(adev, false);
 815                 sdma_v5_2_enable(adev, false);
 816
 817                 /* set RB registers */
 818                 r = sdma_v5_2_gfx_resume(adev);
 819                 return r;
 820         }
 821
 822         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 823                 r = sdma_v5_2_load_microcode(adev);
 824                 if (r)
 825                         return r;
 826
 827                 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */
 828                 if (amdgpu_emu_mode == 1)
 829                         msleep(1000);
 830         }
 831
 832         /* unhalt the MEs */
 833         sdma_v5_2_enable(adev, true);
 834         /* enable sdma ring preemption */
 835         sdma_v5_2_ctx_switch_enable(adev, true);
 836
 837         /* start the gfx rings and rlc compute queues */
 838         r = sdma_v5_2_gfx_resume(adev);
 839         if (r)
 840                 return r;
 841         r = sdma_v5_2_rlc_resume(adev);
 842
 843         return r;
 844 }
 845
 846 /**
 847  * sdma_v5_2_ring_test_ring - simple async dma engine test
 848  *
 849  * @ring: amdgpu_ring structure holding ring information
 850  *
 851  * Test the DMA engine by writing using it to write an
 852  * value to memory.
 853  * Returns 0 for success, error for failure.
 854  */
 855 static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring)
 856 {
 857         struct amdgpu_device *adev = ring->adev;
 858         unsigned i;
 859         unsigned index;
 860         int r;
 861         u32 tmp;
 862         u64 gpu_addr;
 863
 864         r = amdgpu_device_wb_get(adev, &index);
 865         if (r) {
 866                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 867                 return r;
 868         }
 869
 870         gpu_addr = adev->wb.gpu_addr + (index * 4);
 871         tmp = 0xCAFEDEAD;
 872         adev->wb.wb[index] = cpu_to_le32(tmp);
 873
 874         r = amdgpu_ring_alloc(ring, 5);
 875         if (r) {
 876                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 877                 amdgpu_device_wb_free(adev, index);
 878                 return r;
 879         }
 880
 881         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 882                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 883         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 884         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 885         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 886         amdgpu_ring_write(ring, 0xDEADBEEF);
 887         amdgpu_ring_commit(ring);
 888
 889         for (i = 0; i < adev->usec_timeout; i++) {
 890                 tmp = le32_to_cpu(adev->wb.wb[index]);
 891                 if (tmp == 0xDEADBEEF)
 892                         break;
 893                 if (amdgpu_emu_mode == 1)
 894                         msleep(1);
 895                 else
 896                         udelay(1);
 897         }
 898
 899         if (i >= adev->usec_timeout)
 900                 r = -ETIMEDOUT;
 901
 902         amdgpu_device_wb_free(adev, index);
 903
 904         return r;
 905 }
 906
 907 /**
 908  * sdma_v5_2_ring_test_ib - test an IB on the DMA engine
 909  *
 910  * @ring: amdgpu_ring structure holding ring information
 911  *
 912  * Test a simple IB in the DMA ring.
 913  * Returns 0 on success, error on failure.
 914  */
 915 static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 916 {
 917         struct amdgpu_device *adev = ring->adev;
 918         struct amdgpu_ib ib;
 919         struct dma_fence *f = NULL;
 920         unsigned index;
 921         long r;
 922         u32 tmp = 0;
 923         u64 gpu_addr;
 924
 925         r = amdgpu_device_wb_get(adev, &index);
 926         if (r) {
 927                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 928                 return r;
 929         }
 930
 931         gpu_addr = adev->wb.gpu_addr + (index * 4);
 932         tmp = 0xCAFEDEAD;
 933         adev->wb.wb[index] = cpu_to_le32(tmp);
 934         memset(&ib, 0, sizeof(ib));
 935         r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
 936         if (r) {
 937                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 938                 goto err0;
 939         }
 940
 941         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 942                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 943         ib.ptr[1] = lower_32_bits(gpu_addr);
 944         ib.ptr[2] = upper_32_bits(gpu_addr);
 945         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
 946         ib.ptr[4] = 0xDEADBEEF;
 947         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 948         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 949         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 950         ib.length_dw = 8;
 951
 952         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 953         if (r)
 954                 goto err1;
 955
 956         r = dma_fence_wait_timeout(f, false, timeout);
 957         if (r == 0) {
 958                 DRM_ERROR("amdgpu: IB test timed out\n");
 959                 r = -ETIMEDOUT;
 960                 goto err1;
 961         } else if (r < 0) {
 962                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 963                 goto err1;
 964         }
 965         tmp = le32_to_cpu(adev->wb.wb[index]);
 966         if (tmp == 0xDEADBEEF)
 967                 r = 0;
 968         else
 969                 r = -EINVAL;
 970
 971 err1:
 972         amdgpu_ib_free(adev, &ib, NULL);
 973         dma_fence_put(f);
 974 err0:
 975         amdgpu_device_wb_free(adev, index);
 976         return r;
 977 }
 978
 979
 980 /**
 981  * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART
 982  *
 983  * @ib: indirect buffer to fill with commands
 984  * @pe: addr of the page entry
 985  * @src: src addr to copy from
 986  * @count: number of page entries to update
 987  *
 988  * Update PTEs by copying them from the GART using sDMA.
 989  */
 990 static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib,
 991                                   uint64_t pe, uint64_t src,
 992                                   unsigned count)
 993 {
 994         unsigned bytes = count * 8;
 995
 996         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
 997                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 998         ib->ptr[ib->length_dw++] = bytes - 1;
 999         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1000         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1001         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1002         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1003         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1004
1005 }
1006
1007 /**
1008  * sdma_v5_2_vm_write_pte - update PTEs by writing them manually
1009  *
1010  * @ib: indirect buffer to fill with commands
1011  * @pe: addr of the page entry
1012  * @addr: dst addr to write into pe
1013  * @count: number of page entries to update
1014  * @incr: increase next addr by incr bytes
1015  * @flags: access flags
1016  *
1017  * Update PTEs by writing them manually using sDMA.
1018  */
1019 static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1020                                    uint64_t value, unsigned count,
1021                                    uint32_t incr)
1022 {
1023         unsigned ndw = count * 2;
1024
1025         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1026                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1027         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1028         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1029         ib->ptr[ib->length_dw++] = ndw - 1;
1030         for (; ndw > 0; ndw -= 2) {
1031                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1032                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1033                 value += incr;
1034         }
1035 }
1036
1037 /**
1038  * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA
1039  *
1040  * @ib: indirect buffer to fill with commands
1041  * @pe: addr of the page entry
1042  * @addr: dst addr to write into pe
1043  * @count: number of page entries to update
1044  * @incr: increase next addr by incr bytes
1045  * @flags: access flags
1046  *
1047  * Update the page tables using sDMA.
1048  */
1049 static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib,
1050                                      uint64_t pe,
1051                                      uint64_t addr, unsigned count,
1052                                      uint32_t incr, uint64_t flags)
1053 {
1054         /* for physically contiguous pages (vram) */
1055         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1056         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1057         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1058         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1059         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1060         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1061         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1062         ib->ptr[ib->length_dw++] = incr; /* increment size */
1063         ib->ptr[ib->length_dw++] = 0;
1064         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1065 }
1066
1067 /**
1068  * sdma_v5_2_ring_pad_ib - pad the IB
1069  *
1070  * @ib: indirect buffer to fill with padding
1071  *
1072  * Pad the IB with NOPs to a boundary multiple of 8.
1073  */
1074 static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1075 {
1076         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1077         u32 pad_count;
1078         int i;
1079
1080         pad_count = (-ib->length_dw) & 0x7;
1081         for (i = 0; i < pad_count; i++)
1082                 if (sdma && sdma->burst_nop && (i == 0))
1083                         ib->ptr[ib->length_dw++] =
1084                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1085                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1086                 else
1087                         ib->ptr[ib->length_dw++] =
1088                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1089 }
1090
1091
1092 /**
1093  * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline
1094  *
1095  * @ring: amdgpu_ring pointer
1096  *
1097  * Make sure all previous operations are completed (CIK).
1098  */
1099 static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1100 {
1101         uint32_t seq = ring->fence_drv.sync_seq;
1102         uint64_t addr = ring->fence_drv.gpu_addr;
1103
1104         /* wait for idle */
1105         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1106                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1107                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1108                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1109         amdgpu_ring_write(ring, addr & 0xfffffffc);
1110         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1111         amdgpu_ring_write(ring, seq); /* reference */
1112         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1113         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1114                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1115 }
1116
1117
1118 /**
1119  * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA
1120  *
1121  * @ring: amdgpu_ring pointer
1122  * @vm: amdgpu_vm pointer
1123  *
1124  * Update the page table base and flush the VM TLB
1125  * using sDMA.
1126  */
1127 static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
1128                                          unsigned vmid, uint64_t pd_addr)
1129 {
1130         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1131 }
1132
1133 static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring,
1134                                      uint32_t reg, uint32_t val)
1135 {
1136         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1137                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1138         amdgpu_ring_write(ring, reg);
1139         amdgpu_ring_write(ring, val);
1140 }
1141
1142 static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1143                                          uint32_t val, uint32_t mask)
1144 {
1145         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1146                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1147                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1148         amdgpu_ring_write(ring, reg << 2);
1149         amdgpu_ring_write(ring, 0);
1150         amdgpu_ring_write(ring, val); /* reference */
1151         amdgpu_ring_write(ring, mask); /* mask */
1152         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1153                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1154 }
1155
1156 static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1157                                                    uint32_t reg0, uint32_t reg1,
1158                                                    uint32_t ref, uint32_t mask)
1159 {
1160         amdgpu_ring_emit_wreg(ring, reg0, ref);
1161         /* wait for a cycle to reset vm_inv_eng*_ack */
1162         amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1163         amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1164 }
1165
1166 static int sdma_v5_2_early_init(void *handle)
1167 {
1168         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1169
1170         adev->sdma.num_instances = 4;
1171
1172         sdma_v5_2_set_ring_funcs(adev);
1173         sdma_v5_2_set_buffer_funcs(adev);
1174         sdma_v5_2_set_vm_pte_funcs(adev);
1175         sdma_v5_2_set_irq_funcs(adev);
1176
1177         return 0;
1178 }
1179
1180 static int sdma_v5_2_sw_init(void *handle)
1181 {
1182         struct amdgpu_ring *ring;
1183         int r, i;
1184         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1185
1186         /* SDMA trap event */
1187         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0,
1188                               SDMA0_5_0__SRCID__SDMA_TRAP,
1189                               &adev->sdma.trap_irq);
1190         if (r)
1191                 return r;
1192
1193         /* SDMA trap event */
1194         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1,
1195                               SDMA1_5_0__SRCID__SDMA_TRAP,
1196                               &adev->sdma.trap_irq);
1197         if (r)
1198                 return r;
1199
1200         /* SDMA trap event */
1201         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA2,
1202                               SDMA2_5_0__SRCID__SDMA_TRAP,
1203                               &adev->sdma.trap_irq);
1204         if (r)
1205                 return r;
1206
1207         /* SDMA trap event */
1208         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid,
1209                               SDMA3_5_0__SRCID__SDMA_TRAP,
1210                               &adev->sdma.trap_irq);
1211         if (r)
1212                 return r;
1213
1214         r = sdma_v5_2_init_microcode(adev);
1215         if (r) {
1216                 DRM_ERROR("Failed to load sdma firmware!\n");
1217                 return r;
1218         }
1219
1220         for (i = 0; i < adev->sdma.num_instances; i++) {
1221                 ring = &adev->sdma.instance[i].ring;
1222                 ring->ring_obj = NULL;
1223                 ring->use_doorbell = true;
1224                 ring->me = i;
1225
1226                 DRM_INFO("use_doorbell being set to: [%s]\n",
1227                                 ring->use_doorbell?"true":"false");
1228
1229                 ring->doorbell_index =
1230                         (adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset
1231
1232                 sprintf(ring->name, "sdma%d", i);
1233                 r = amdgpu_ring_init(adev, ring, 1024,
1234                                      &adev->sdma.trap_irq,
1235                                      AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1236                                      AMDGPU_RING_PRIO_DEFAULT);
1237                 if (r)
1238                         return r;
1239         }
1240
1241         return r;
1242 }
1243
1244 static int sdma_v5_2_sw_fini(void *handle)
1245 {
1246         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1247
1248         sdma_v5_2_destroy_inst_ctx(adev);
1249
1250         return 0;
1251 }
1252
1253 static int sdma_v5_2_hw_init(void *handle)
1254 {
1255         int r;
1256         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1257
1258         sdma_v5_2_init_golden_registers(adev);
1259
1260         r = sdma_v5_2_start(adev);
1261
1262         return r;
1263 }
1264
1265 static int sdma_v5_2_hw_fini(void *handle)
1266 {
1267         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1268
1269         if (amdgpu_sriov_vf(adev))
1270                 return 0;
1271
1272         sdma_v5_2_ctx_switch_enable(adev, false);
1273         sdma_v5_2_enable(adev, false);
1274
1275         return 0;
1276 }
1277
1278 static int sdma_v5_2_suspend(void *handle)
1279 {
1280         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1281
1282         return sdma_v5_2_hw_fini(adev);
1283 }
1284
1285 static int sdma_v5_2_resume(void *handle)
1286 {
1287         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1288
1289         return sdma_v5_2_hw_init(adev);
1290 }
1291
1292 static bool sdma_v5_2_is_idle(void *handle)
1293 {
1294         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1295         u32 i;
1296
1297         for (i = 0; i < adev->sdma.num_instances; i++) {
1298                 u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1299
1300                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1301                         return false;
1302         }
1303
1304         return true;
1305 }
1306
1307 static int sdma_v5_2_wait_for_idle(void *handle)
1308 {
1309         unsigned i;
1310         u32 sdma0, sdma1, sdma2, sdma3;
1311         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1312
1313         for (i = 0; i < adev->usec_timeout; i++) {
1314                 sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1315                 sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1316                 sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG));
1317                 sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG));
1318
1319                 if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK)
1320                         return 0;
1321                 udelay(1);
1322         }
1323         return -ETIMEDOUT;
1324 }
1325
1326 static int sdma_v5_2_soft_reset(void *handle)
1327 {
1328         /* todo */
1329
1330         return 0;
1331 }
1332
1333 static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring)
1334 {
1335         int i, r = 0;
1336         struct amdgpu_device *adev = ring->adev;
1337         u32 index = 0;
1338         u64 sdma_gfx_preempt;
1339
1340         amdgpu_sdma_get_index_from_ring(ring, &index);
1341         sdma_gfx_preempt =
1342                 sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT);
1343
1344         /* assert preemption condition */
1345         amdgpu_ring_set_preempt_cond_exec(ring, false);
1346
1347         /* emit the trailing fence */
1348         ring->trail_seq += 1;
1349         amdgpu_ring_alloc(ring, 10);
1350         sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1351                                   ring->trail_seq, 0);
1352         amdgpu_ring_commit(ring);
1353
1354         /* assert IB preemption */
1355         WREG32(sdma_gfx_preempt, 1);
1356
1357         /* poll the trailing fence */
1358         for (i = 0; i < adev->usec_timeout; i++) {
1359                 if (ring->trail_seq ==
1360                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1361                         break;
1362                 udelay(1);
1363         }
1364
1365         if (i >= adev->usec_timeout) {
1366                 r = -EINVAL;
1367                 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1368         }
1369
1370         /* deassert IB preemption */
1371         WREG32(sdma_gfx_preempt, 0);
1372
1373         /* deassert the preemption condition */
1374         amdgpu_ring_set_preempt_cond_exec(ring, true);
1375         return r;
1376 }
1377
1378 static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev,
1379                                         struct amdgpu_irq_src *source,
1380                                         unsigned type,
1381                                         enum amdgpu_interrupt_state state)
1382 {
1383         u32 sdma_cntl;
1384
1385         u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL);
1386
1387         sdma_cntl = RREG32(reg_offset);
1388         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1389                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1390         WREG32(reg_offset, sdma_cntl);
1391
1392         return 0;
1393 }
1394
1395 static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev,
1396                                       struct amdgpu_irq_src *source,
1397                                       struct amdgpu_iv_entry *entry)
1398 {
1399         DRM_DEBUG("IH: SDMA trap\n");
1400         switch (entry->client_id) {
1401         case SOC15_IH_CLIENTID_SDMA0:
1402                 switch (entry->ring_id) {
1403                 case 0:
1404                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1405                         break;
1406                 case 1:
1407                         /* XXX compute */
1408                         break;
1409                 case 2:
1410                         /* XXX compute */
1411                         break;
1412                 case 3:
1413                         /* XXX page queue*/
1414                         break;
1415                 }
1416                 break;
1417         case SOC15_IH_CLIENTID_SDMA1:
1418                 switch (entry->ring_id) {
1419                 case 0:
1420                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1421                         break;
1422                 case 1:
1423                         /* XXX compute */
1424                         break;
1425                 case 2:
1426                         /* XXX compute */
1427                         break;
1428                 case 3:
1429                         /* XXX page queue*/
1430                         break;
1431                 }
1432                 break;
1433         case SOC15_IH_CLIENTID_SDMA2:
1434                 switch (entry->ring_id) {
1435                 case 0:
1436                         amdgpu_fence_process(&adev->sdma.instance[2].ring);
1437                         break;
1438                 case 1:
1439                         /* XXX compute */
1440                         break;
1441                 case 2:
1442                         /* XXX compute */
1443                         break;
1444                 case 3:
1445                         /* XXX page queue*/
1446                         break;
1447                 }
1448                 break;
1449         case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid:
1450                 switch (entry->ring_id) {
1451                 case 0:
1452                         amdgpu_fence_process(&adev->sdma.instance[3].ring);
1453                         break;
1454                 case 1:
1455                         /* XXX compute */
1456                         break;
1457                 case 2:
1458                         /* XXX compute */
1459                         break;
1460                 case 3:
1461                         /* XXX page queue*/
1462                         break;
1463                 }
1464                 break;
1465         }
1466         return 0;
1467 }
1468
1469 static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev,
1470                                               struct amdgpu_irq_src *source,
1471                                               struct amdgpu_iv_entry *entry)
1472 {
1473         return 0;
1474 }
1475
1476 static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1477                                                        bool enable)
1478 {
1479         uint32_t data, def;
1480         int i;
1481
1482         for (i = 0; i < adev->sdma.num_instances; i++) {
1483                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1484                         /* Enable sdma clock gating */
1485                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1486                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1487                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1488                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1489                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1490                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1491                                   SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1492                         if (def != data)
1493                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1494                 } else {
1495                         /* Disable sdma clock gating */
1496                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1497                         data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1498                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1499                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1500                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1501                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1502                                  SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1503                         if (def != data)
1504                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1505                 }
1506         }
1507 }
1508
1509 static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1510                                                       bool enable)
1511 {
1512         uint32_t data, def;
1513         int i;
1514
1515         for (i = 0; i < adev->sdma.num_instances; i++) {
1516                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1517                         /* Enable sdma mem light sleep */
1518                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1519                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1520                         if (def != data)
1521                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1522
1523                 } else {
1524                         /* Disable sdma mem light sleep */
1525                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1526                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1527                         if (def != data)
1528                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1529
1530                 }
1531         }
1532 }
1533
1534 static int sdma_v5_2_set_clockgating_state(void *handle,
1535                                            enum amd_clockgating_state state)
1536 {
1537         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1538
1539         if (amdgpu_sriov_vf(adev))
1540                 return 0;
1541
1542         switch (adev->asic_type) {
1543         case CHIP_SIENNA_CICHLID:
1544                 sdma_v5_2_update_medium_grain_clock_gating(adev,
1545                                 state == AMD_CG_STATE_GATE ? true : false);
1546                 sdma_v5_2_update_medium_grain_light_sleep(adev,
1547                                 state == AMD_CG_STATE_GATE ? true : false);
1548                 break;
1549         default:
1550                 break;
1551         }
1552
1553         return 0;
1554 }
1555
1556 static int sdma_v5_2_set_powergating_state(void *handle,
1557                                           enum amd_powergating_state state)
1558 {
1559         return 0;
1560 }
1561
1562 static void sdma_v5_2_get_clockgating_state(void *handle, u32 *flags)
1563 {
1564         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1565         int data;
1566
1567         if (amdgpu_sriov_vf(adev))
1568                 *flags = 0;
1569
1570         /* AMD_CG_SUPPORT_SDMA_LS */
1571         data = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1572         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1573                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1574 }
1575
1576 const struct amd_ip_funcs sdma_v5_2_ip_funcs = {
1577         .name = "sdma_v5_2",
1578         .early_init = sdma_v5_2_early_init,
1579         .late_init = NULL,
1580         .sw_init = sdma_v5_2_sw_init,
1581         .sw_fini = sdma_v5_2_sw_fini,
1582         .hw_init = sdma_v5_2_hw_init,
1583         .hw_fini = sdma_v5_2_hw_fini,
1584         .suspend = sdma_v5_2_suspend,
1585         .resume = sdma_v5_2_resume,
1586         .is_idle = sdma_v5_2_is_idle,
1587         .wait_for_idle = sdma_v5_2_wait_for_idle,
1588         .soft_reset = sdma_v5_2_soft_reset,
1589         .set_clockgating_state = sdma_v5_2_set_clockgating_state,
1590         .set_powergating_state = sdma_v5_2_set_powergating_state,
1591         .get_clockgating_state = sdma_v5_2_get_clockgating_state,
1592 };
1593
1594 static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {
1595         .type = AMDGPU_RING_TYPE_SDMA,
1596         .align_mask = 0xf,
1597         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1598         .support_64bit_ptrs = true,
1599         .vmhub = AMDGPU_GFXHUB_0,
1600         .get_rptr = sdma_v5_2_ring_get_rptr,
1601         .get_wptr = sdma_v5_2_ring_get_wptr,
1602         .set_wptr = sdma_v5_2_ring_set_wptr,
1603         .emit_frame_size =
1604                 5 + /* sdma_v5_2_ring_init_cond_exec */
1605                 6 + /* sdma_v5_2_ring_emit_hdp_flush */
1606                 3 + /* hdp_invalidate */
1607                 6 + /* sdma_v5_2_ring_emit_pipeline_sync */
1608                 /* sdma_v5_2_ring_emit_vm_flush */
1609                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1610                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1611                 10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */
1612         .emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */
1613         .emit_ib = sdma_v5_2_ring_emit_ib,
1614         .emit_fence = sdma_v5_2_ring_emit_fence,
1615         .emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync,
1616         .emit_vm_flush = sdma_v5_2_ring_emit_vm_flush,
1617         .emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush,
1618         .test_ring = sdma_v5_2_ring_test_ring,
1619         .test_ib = sdma_v5_2_ring_test_ib,
1620         .insert_nop = sdma_v5_2_ring_insert_nop,
1621         .pad_ib = sdma_v5_2_ring_pad_ib,
1622         .emit_wreg = sdma_v5_2_ring_emit_wreg,
1623         .emit_reg_wait = sdma_v5_2_ring_emit_reg_wait,
1624         .emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait,
1625         .init_cond_exec = sdma_v5_2_ring_init_cond_exec,
1626         .patch_cond_exec = sdma_v5_2_ring_patch_cond_exec,
1627         .preempt_ib = sdma_v5_2_ring_preempt_ib,
1628 };
1629
1630 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev)
1631 {
1632         int i;
1633
1634         for (i = 0; i < adev->sdma.num_instances; i++) {
1635                 adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs;
1636                 adev->sdma.instance[i].ring.me = i;
1637         }
1638 }
1639
1640 static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = {
1641         .set = sdma_v5_2_set_trap_irq_state,
1642         .process = sdma_v5_2_process_trap_irq,
1643 };
1644
1645 static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = {
1646         .process = sdma_v5_2_process_illegal_inst_irq,
1647 };
1648
1649 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev)
1650 {
1651         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1652                                         adev->sdma.num_instances;
1653         adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs;
1654         adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs;
1655 }
1656
1657 /**
1658  * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine
1659  *
1660  * @ring: amdgpu_ring structure holding ring information
1661  * @src_offset: src GPU address
1662  * @dst_offset: dst GPU address
1663  * @byte_count: number of bytes to xfer
1664  *
1665  * Copy GPU buffers using the DMA engine.
1666  * Used by the amdgpu ttm implementation to move pages if
1667  * registered as the asic copy callback.
1668  */
1669 static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib,
1670                                        uint64_t src_offset,
1671                                        uint64_t dst_offset,
1672                                        uint32_t byte_count,
1673                                        bool tmz)
1674 {
1675         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1676                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1677                 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1678         ib->ptr[ib->length_dw++] = byte_count - 1;
1679         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1680         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1681         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1682         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1683         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1684 }
1685
1686 /**
1687  * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine
1688  *
1689  * @ring: amdgpu_ring structure holding ring information
1690  * @src_data: value to write to buffer
1691  * @dst_offset: dst GPU address
1692  * @byte_count: number of bytes to xfer
1693  *
1694  * Fill GPU buffers using the DMA engine.
1695  */
1696 static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
1697                                        uint32_t src_data,
1698                                        uint64_t dst_offset,
1699                                        uint32_t byte_count)
1700 {
1701         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1702         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1703         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1704         ib->ptr[ib->length_dw++] = src_data;
1705         ib->ptr[ib->length_dw++] = byte_count - 1;
1706 }
1707
1708 static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = {
1709         .copy_max_bytes = 0x400000,
1710         .copy_num_dw = 7,
1711         .emit_copy_buffer = sdma_v5_2_emit_copy_buffer,
1712
1713         .fill_max_bytes = 0x400000,
1714         .fill_num_dw = 5,
1715         .emit_fill_buffer = sdma_v5_2_emit_fill_buffer,
1716 };
1717
1718 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev)
1719 {
1720         if (adev->mman.buffer_funcs == NULL) {
1721                 adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs;
1722                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1723         }
1724 }
1725
1726 static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = {
1727         .copy_pte_num_dw = 7,
1728         .copy_pte = sdma_v5_2_vm_copy_pte,
1729         .write_pte = sdma_v5_2_vm_write_pte,
1730         .set_pte_pde = sdma_v5_2_vm_set_pte_pde,
1731 };
1732
1733 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev)
1734 {
1735         unsigned i;
1736
1737         if (adev->vm_manager.vm_pte_funcs == NULL) {
1738                 adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs;
1739                 for (i = 0; i < adev->sdma.num_instances; i++) {
1740                         adev->vm_manager.vm_pte_scheds[i] =
1741                                 &adev->sdma.instance[i].ring.sched;
1742                 }
1743                 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1744         }
1745 }
1746
1747 const struct amdgpu_ip_block_version sdma_v5_2_ip_block = {
1748         .type = AMD_IP_BLOCK_TYPE_SDMA,
1749         .major = 5,
1750         .minor = 2,
1751         .rev = 0,
1752         .funcs = &sdma_v5_2_ip_funcs,
1753 };