drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_ucode.h"
  31 #include "amdgpu_trace.h"
  32
  33 #include "gc/gc_10_3_0_offset.h"
  34 #include "gc/gc_10_3_0_sh_mask.h"
  35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
  36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
  37 #include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h"
  38 #include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h"
  39
  40 #include "soc15_common.h"
  41 #include "soc15.h"
  42 #include "navi10_sdma_pkt_open.h"
  43 #include "nbio_v2_3.h"
  44 #include "sdma_common.h"
  45 #include "sdma_v5_2.h"
  46
  47 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin");
  48 MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin");
  49 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin");
  50
  51 MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin");
  52
  53 #define SDMA1_REG_OFFSET 0x600
  54 #define SDMA3_REG_OFFSET 0x400
  55 #define SDMA0_HYP_DEC_REG_START 0x5880
  56 #define SDMA0_HYP_DEC_REG_END 0x5893
  57 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
  58
  59 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev);
  60 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev);
  61 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev);
  62 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev);
  63
  64 static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
  65 {
  66         u32 base;
  67
  68         if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
  69             internal_offset <= SDMA0_HYP_DEC_REG_END) {
  70                 base = adev->reg_offset[GC_HWIP][0][1];
  71                 if (instance != 0)
  72                         internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
  73         } else {
  74                 if (instance < 2) {
  75                         base = adev->reg_offset[GC_HWIP][0][0];
  76                         if (instance == 1)
  77                                 internal_offset += SDMA1_REG_OFFSET;
  78                 } else {
  79                         base = adev->reg_offset[GC_HWIP][0][2];
  80                         if (instance == 3)
  81                                 internal_offset += SDMA3_REG_OFFSET;
  82                 }
  83         }
  84
  85         return base + internal_offset;
  86 }
  87
  88 static void sdma_v5_2_init_golden_registers(struct amdgpu_device *adev)
  89 {
  90         switch (adev->asic_type) {
  91         case CHIP_SIENNA_CICHLID:
  92         case CHIP_NAVY_FLOUNDER:
  93         case CHIP_VANGOGH:
  94         case CHIP_DIMGREY_CAVEFISH:
  95                 break;
  96         default:
  97                 break;
  98         }
  99 }
 100
 101 static int sdma_v5_2_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
 102 {
 103         int err = 0;
 104         const struct sdma_firmware_header_v1_0 *hdr;
 105
 106         err = amdgpu_ucode_validate(sdma_inst->fw);
 107         if (err)
 108                 return err;
 109
 110         hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
 111         sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
 112         sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
 113
 114         if (sdma_inst->feature_version >= 20)
 115                 sdma_inst->burst_nop = true;
 116
 117         return 0;
 118 }
 119
 120 static void sdma_v5_2_destroy_inst_ctx(struct amdgpu_device *adev)
 121 {
 122         int i;
 123
 124         for (i = 0; i < adev->sdma.num_instances; i++) {
 125                 release_firmware(adev->sdma.instance[i].fw);
 126                 adev->sdma.instance[i].fw = NULL;
 127
 128                 if (adev->asic_type == CHIP_SIENNA_CICHLID)
 129                         break;
 130         }
 131
 132         memset((void *)adev->sdma.instance, 0,
 133                sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
 134 }
 135
 136 /**
 137  * sdma_v5_2_init_microcode - load ucode images from disk
 138  *
 139  * @adev: amdgpu_device pointer
 140  *
 141  * Use the firmware interface to load the ucode images into
 142  * the driver (not loaded into hw).
 143  * Returns 0 on success, error on failure.
 144  */
 145
 146 // emulation only, won't work on real chip
 147 // navi10 real chip need to use PSP to load firmware
 148 static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
 149 {
 150         const char *chip_name;
 151         char fw_name[40];
 152         int err = 0, i;
 153         struct amdgpu_firmware_info *info = NULL;
 154         const struct common_firmware_header *header = NULL;
 155
 156         if (amdgpu_sriov_vf(adev))
 157                 return 0;
 158
 159         DRM_DEBUG("\n");
 160
 161         switch (adev->asic_type) {
 162         case CHIP_SIENNA_CICHLID:
 163                 chip_name = "sienna_cichlid";
 164                 break;
 165         case CHIP_NAVY_FLOUNDER:
 166                 chip_name = "navy_flounder";
 167                 break;
 168         case CHIP_VANGOGH:
 169                 chip_name = "vangogh";
 170                 break;
 171         case CHIP_DIMGREY_CAVEFISH:
 172                 chip_name = "dimgrey_cavefish";
 173                 break;
 174         default:
 175                 BUG();
 176         }
 177
 178         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 179
 180         err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);
 181         if (err)
 182                 goto out;
 183
 184         err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]);
 185         if (err)
 186                 goto out;
 187
 188         for (i = 1; i < adev->sdma.num_instances; i++) {
 189                 if (adev->asic_type >= CHIP_SIENNA_CICHLID &&
 190                     adev->asic_type <= CHIP_DIMGREY_CAVEFISH) {
 191                         memcpy((void *)&adev->sdma.instance[i],
 192                                (void *)&adev->sdma.instance[0],
 193                                sizeof(struct amdgpu_sdma_instance));
 194                 } else {
 195                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i);
 196                         err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 197                         if (err)
 198                                 goto out;
 199
 200                         err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]);
 201                         if (err)
 202                                 goto out;
 203                 }
 204         }
 205
 206         DRM_DEBUG("psp_load == '%s'\n",
 207                   adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
 208
 209         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 210                 for (i = 0; i < adev->sdma.num_instances; i++) {
 211                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 212                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 213                         info->fw = adev->sdma.instance[i].fw;
 214                         header = (const struct common_firmware_header *)info->fw->data;
 215                         adev->firmware.fw_size +=
 216                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 217                 }
 218         }
 219
 220 out:
 221         if (err) {
 222                 DRM_ERROR("sdma_v5_2: Failed to load firmware \"%s\"\n", fw_name);
 223                 sdma_v5_2_destroy_inst_ctx(adev);
 224         }
 225         return err;
 226 }
 227
 228 static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring)
 229 {
 230         unsigned ret;
 231
 232         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
 233         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
 234         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
 235         amdgpu_ring_write(ring, 1);
 236         ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
 237         amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
 238
 239         return ret;
 240 }
 241
 242 static void sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring *ring,
 243                                            unsigned offset)
 244 {
 245         unsigned cur;
 246
 247         BUG_ON(offset > ring->buf_mask);
 248         BUG_ON(ring->ring[offset] != 0x55aa55aa);
 249
 250         cur = (ring->wptr - 1) & ring->buf_mask;
 251         if (cur > offset)
 252                 ring->ring[offset] = cur - offset;
 253         else
 254                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
 255 }
 256
 257 /**
 258  * sdma_v5_2_ring_get_rptr - get the current read pointer
 259  *
 260  * @ring: amdgpu ring pointer
 261  *
 262  * Get the current rptr from the hardware (NAVI10+).
 263  */
 264 static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring)
 265 {
 266         u64 *rptr;
 267
 268         /* XXX check if swapping is necessary on BE */
 269         rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
 270
 271         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 272         return ((*rptr) >> 2);
 273 }
 274
 275 /**
 276  * sdma_v5_2_ring_get_wptr - get the current write pointer
 277  *
 278  * @ring: amdgpu ring pointer
 279  *
 280  * Get the current wptr from the hardware (NAVI10+).
 281  */
 282 static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring)
 283 {
 284         struct amdgpu_device *adev = ring->adev;
 285         u64 wptr;
 286
 287         if (ring->use_doorbell) {
 288                 /* XXX check if swapping is necessary on BE */
 289                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 290                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 291         } else {
 292                 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
 293                 wptr = wptr << 32;
 294                 wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
 295                 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
 296         }
 297
 298         return wptr >> 2;
 299 }
 300
 301 /**
 302  * sdma_v5_2_ring_set_wptr - commit the write pointer
 303  *
 304  * @ring: amdgpu ring pointer
 305  *
 306  * Write the wptr back to the hardware (NAVI10+).
 307  */
 308 static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring)
 309 {
 310         struct amdgpu_device *adev = ring->adev;
 311
 312         DRM_DEBUG("Setting write pointer\n");
 313         if (ring->use_doorbell) {
 314                 DRM_DEBUG("Using doorbell -- "
 315                                 "wptr_offs == 0x%08x "
 316                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 317                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 318                                 ring->wptr_offs,
 319                                 lower_32_bits(ring->wptr << 2),
 320                                 upper_32_bits(ring->wptr << 2));
 321                 /* XXX check if swapping is necessary on BE */
 322                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
 323                 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
 324                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 325                                 ring->doorbell_index, ring->wptr << 2);
 326                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 327         } else {
 328                 DRM_DEBUG("Not using doorbell -- "
 329                                 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 330                                 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 331                                 ring->me,
 332                                 lower_32_bits(ring->wptr << 2),
 333                                 ring->me,
 334                                 upper_32_bits(ring->wptr << 2));
 335                 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
 336                         lower_32_bits(ring->wptr << 2));
 337                 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
 338                         upper_32_bits(ring->wptr << 2));
 339         }
 340 }
 341
 342 static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 343 {
 344         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 345         int i;
 346
 347         for (i = 0; i < count; i++)
 348                 if (sdma && sdma->burst_nop && (i == 0))
 349                         amdgpu_ring_write(ring, ring->funcs->nop |
 350                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 351                 else
 352                         amdgpu_ring_write(ring, ring->funcs->nop);
 353 }
 354
 355 /**
 356  * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine
 357  *
 358  * @ring: amdgpu ring pointer
 359  * @ib: IB object to schedule
 360  *
 361  * Schedule an IB in the DMA ring.
 362  */
 363 static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring,
 364                                    struct amdgpu_job *job,
 365                                    struct amdgpu_ib *ib,
 366                                    uint32_t flags)
 367 {
 368         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 369         uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
 370
 371         /* An IB packet must end on a 8 DW boundary--the next dword
 372          * must be on a 8-dword boundary. Our IB packet below is 6
 373          * dwords long, thus add x number of NOPs, such that, in
 374          * modular arithmetic,
 375          * wptr + 6 + x = 8k, k >= 0, which in C is,
 376          * (wptr + 6 + x) % 8 = 0.
 377          * The expression below, is a solution of x.
 378          */
 379         sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 380
 381         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 382                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 383         /* base must be 32 byte aligned */
 384         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 385         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 386         amdgpu_ring_write(ring, ib->length_dw);
 387         amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
 388         amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
 389 }
 390
 391 /**
 392  * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 393  *
 394  * @ring: amdgpu ring pointer
 395  *
 396  * Emit an hdp flush packet on the requested DMA ring.
 397  */
 398 static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 399 {
 400         struct amdgpu_device *adev = ring->adev;
 401         u32 ref_and_mask = 0;
 402         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 403
 404         ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
 405
 406         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 407                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 408                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 409         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
 410         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
 411         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 412         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 413         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 414                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 415 }
 416
 417 /**
 418  * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring
 419  *
 420  * @ring: amdgpu ring pointer
 421  * @fence: amdgpu fence object
 422  *
 423  * Add a DMA fence packet to the ring to write
 424  * the fence seq number and DMA trap packet to generate
 425  * an interrupt if needed.
 426  */
 427 static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 428                                       unsigned flags)
 429 {
 430         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 431         /* write the fence */
 432         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 433                           SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
 434         /* zero in first two bits */
 435         BUG_ON(addr & 0x3);
 436         amdgpu_ring_write(ring, lower_32_bits(addr));
 437         amdgpu_ring_write(ring, upper_32_bits(addr));
 438         amdgpu_ring_write(ring, lower_32_bits(seq));
 439
 440         /* optionally write high bits as well */
 441         if (write64bit) {
 442                 addr += 4;
 443                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 444                                   SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
 445                 /* zero in first two bits */
 446                 BUG_ON(addr & 0x3);
 447                 amdgpu_ring_write(ring, lower_32_bits(addr));
 448                 amdgpu_ring_write(ring, upper_32_bits(addr));
 449                 amdgpu_ring_write(ring, upper_32_bits(seq));
 450         }
 451
 452         if (flags & AMDGPU_FENCE_FLAG_INT) {
 453                 /* generate an interrupt */
 454                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 455                 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 456         }
 457 }
 458
 459
 460 /**
 461  * sdma_v5_2_gfx_stop - stop the gfx async dma engines
 462  *
 463  * @adev: amdgpu_device pointer
 464  *
 465  * Stop the gfx async dma ring buffers.
 466  */
 467 static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev)
 468 {
 469         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 470         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 471         struct amdgpu_ring *sdma2 = &adev->sdma.instance[2].ring;
 472         struct amdgpu_ring *sdma3 = &adev->sdma.instance[3].ring;
 473         u32 rb_cntl, ib_cntl;
 474         int i;
 475
 476         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 477             (adev->mman.buffer_funcs_ring == sdma1) ||
 478             (adev->mman.buffer_funcs_ring == sdma2) ||
 479             (adev->mman.buffer_funcs_ring == sdma3))
 480                 amdgpu_ttm_set_buffer_funcs_status(adev, false);
 481
 482         for (i = 0; i < adev->sdma.num_instances; i++) {
 483                 rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 484                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 485                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 486                 ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 487                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 488                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 489         }
 490
 491         sdma0->sched.ready = false;
 492         sdma1->sched.ready = false;
 493         sdma2->sched.ready = false;
 494         sdma3->sched.ready = false;
 495 }
 496
 497 /**
 498  * sdma_v5_2_rlc_stop - stop the compute async dma engines
 499  *
 500  * @adev: amdgpu_device pointer
 501  *
 502  * Stop the compute async dma queues.
 503  */
 504 static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev)
 505 {
 506         /* XXX todo */
 507 }
 508
 509 /**
 510  * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
 511  *
 512  * @adev: amdgpu_device pointer
 513  * @enable: enable/disable the DMA MEs context switch.
 514  *
 515  * Halt or unhalt the async dma engines context switch.
 516  */
 517 static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 518 {
 519         u32 f32_cntl, phase_quantum = 0;
 520         int i;
 521
 522         if (amdgpu_sdma_phase_quantum) {
 523                 unsigned value = amdgpu_sdma_phase_quantum;
 524                 unsigned unit = 0;
 525
 526                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 527                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 528                         value = (value + 1) >> 1;
 529                         unit++;
 530                 }
 531                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 532                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 533                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 534                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 535                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 536                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 537                         WARN_ONCE(1,
 538                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 539                                   value << unit);
 540                 }
 541                 phase_quantum =
 542                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 543                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 544         }
 545
 546         for (i = 0; i < adev->sdma.num_instances; i++) {
 547                 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
 548                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 549                                 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 550                 if (enable && amdgpu_sdma_phase_quantum) {
 551                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
 552                                phase_quantum);
 553                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
 554                                phase_quantum);
 555                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
 556                                phase_quantum);
 557                 }
 558                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
 559         }
 560
 561 }
 562
 563 /**
 564  * sdma_v5_2_enable - stop the async dma engines
 565  *
 566  * @adev: amdgpu_device pointer
 567  * @enable: enable/disable the DMA MEs.
 568  *
 569  * Halt or unhalt the async dma engines.
 570  */
 571 static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable)
 572 {
 573         u32 f32_cntl;
 574         int i;
 575
 576         if (!enable) {
 577                 sdma_v5_2_gfx_stop(adev);
 578                 sdma_v5_2_rlc_stop(adev);
 579         }
 580
 581         for (i = 0; i < adev->sdma.num_instances; i++) {
 582                 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 583                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 584                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
 585         }
 586 }
 587
 588 /**
 589  * sdma_v5_2_gfx_resume - setup and start the async dma engines
 590  *
 591  * @adev: amdgpu_device pointer
 592  *
 593  * Set up the gfx DMA ring buffers and enable them.
 594  * Returns 0 for success, error for failure.
 595  */
 596 static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
 597 {
 598         struct amdgpu_ring *ring;
 599         u32 rb_cntl, ib_cntl;
 600         u32 rb_bufsz;
 601         u32 wb_offset;
 602         u32 doorbell;
 603         u32 doorbell_offset;
 604         u32 temp;
 605         u32 wptr_poll_cntl;
 606         u64 wptr_gpu_addr;
 607         int i, r;
 608
 609         for (i = 0; i < adev->sdma.num_instances; i++) {
 610                 ring = &adev->sdma.instance[i].ring;
 611                 wb_offset = (ring->rptr_offs * 4);
 612
 613                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 614
 615                 /* Set ring buffer size in dwords */
 616                 rb_bufsz = order_base_2(ring->ring_size / 4);
 617                 rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 618                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 619 #ifdef __BIG_ENDIAN
 620                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 621                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 622                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 623 #endif
 624                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 625
 626                 /* Initialize the ring buffer's read and write pointers */
 627                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
 628                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
 629                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
 630                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 631
 632                 /* setup the wptr shadow polling */
 633                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 634                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
 635                        lower_32_bits(wptr_gpu_addr));
 636                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
 637                        upper_32_bits(wptr_gpu_addr));
 638                 wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i,
 639                                                          mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 640                 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 641                                                SDMA0_GFX_RB_WPTR_POLL_CNTL,
 642                                                F32_POLL_ENABLE, 1);
 643                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
 644                        wptr_poll_cntl);
 645
 646                 /* set the wb address whether it's enabled or not */
 647                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
 648                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 649                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
 650                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 651
 652                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 653
 654                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
 655                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
 656
 657                 ring->wptr = 0;
 658
 659                 /* before programing wptr to a less value, need set minor_ptr_update first */
 660                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
 661
 662                 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 663                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
 664                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
 665                 }
 666
 667                 doorbell = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
 668                 doorbell_offset = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
 669
 670                 if (ring->use_doorbell) {
 671                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 672                         doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
 673                                         OFFSET, ring->doorbell_index);
 674                 } else {
 675                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 676                 }
 677                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
 678                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
 679
 680                 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 681                                                       ring->doorbell_index,
 682                                                       adev->doorbell_index.sdma_doorbell_range);
 683
 684                 if (amdgpu_sriov_vf(adev))
 685                         sdma_v5_2_ring_set_wptr(ring);
 686
 687                 /* set minor_ptr_update to 0 after wptr programed */
 688                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
 689
 690                 /* set utc l1 enable flag always to 1 */
 691                 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
 692                 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
 693
 694                 /* enable MCBP */
 695                 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
 696                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
 697
 698                 /* Set up RESP_MODE to non-copy addresses */
 699                 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
 700                 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
 701                 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
 702                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
 703
 704                 /* program default cache read and write policy */
 705                 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
 706                 /* clean read policy and write policy bits */
 707                 temp &= 0xFF0FFF;
 708                 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
 709                          (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
 710                          SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
 711                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
 712
 713                 if (!amdgpu_sriov_vf(adev)) {
 714                         /* unhalt engine */
 715                         temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 716                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 717                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
 718                 }
 719
 720                 /* enable DMA RB */
 721                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 722                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 723
 724                 ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 725                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 726 #ifdef __BIG_ENDIAN
 727                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 728 #endif
 729                 /* enable DMA IBs */
 730                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 731
 732                 ring->sched.ready = true;
 733
 734                 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
 735                         sdma_v5_2_ctx_switch_enable(adev, true);
 736                         sdma_v5_2_enable(adev, true);
 737                 }
 738
 739                 r = amdgpu_ring_test_ring(ring);
 740                 if (r) {
 741                         ring->sched.ready = false;
 742                         return r;
 743                 }
 744
 745                 if (adev->mman.buffer_funcs_ring == ring)
 746                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 747         }
 748
 749         return 0;
 750 }
 751
 752 /**
 753  * sdma_v5_2_rlc_resume - setup and start the async dma engines
 754  *
 755  * @adev: amdgpu_device pointer
 756  *
 757  * Set up the compute DMA queues and enable them.
 758  * Returns 0 for success, error for failure.
 759  */
 760 static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev)
 761 {
 762         return 0;
 763 }
 764
 765 /**
 766  * sdma_v5_2_load_microcode - load the sDMA ME ucode
 767  *
 768  * @adev: amdgpu_device pointer
 769  *
 770  * Loads the sDMA0/1/2/3 ucode.
 771  * Returns 0 for success, -EINVAL if the ucode is not available.
 772  */
 773 static int sdma_v5_2_load_microcode(struct amdgpu_device *adev)
 774 {
 775         const struct sdma_firmware_header_v1_0 *hdr;
 776         const __le32 *fw_data;
 777         u32 fw_size;
 778         int i, j;
 779
 780         /* halt the MEs */
 781         sdma_v5_2_enable(adev, false);
 782
 783         for (i = 0; i < adev->sdma.num_instances; i++) {
 784                 if (!adev->sdma.instance[i].fw)
 785                         return -EINVAL;
 786
 787                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 788                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 789                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 790
 791                 fw_data = (const __le32 *)
 792                         (adev->sdma.instance[i].fw->data +
 793                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 794
 795                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
 796
 797                 for (j = 0; j < fw_size; j++) {
 798                         if (amdgpu_emu_mode == 1 && j % 500 == 0)
 799                                 msleep(1);
 800                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 801                 }
 802
 803                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
 804         }
 805
 806         return 0;
 807 }
 808
 809 /**
 810  * sdma_v5_2_start - setup and start the async dma engines
 811  *
 812  * @adev: amdgpu_device pointer
 813  *
 814  * Set up the DMA engines and enable them.
 815  * Returns 0 for success, error for failure.
 816  */
 817 static int sdma_v5_2_start(struct amdgpu_device *adev)
 818 {
 819         int r = 0;
 820
 821         if (amdgpu_sriov_vf(adev)) {
 822                 sdma_v5_2_ctx_switch_enable(adev, false);
 823                 sdma_v5_2_enable(adev, false);
 824
 825                 /* set RB registers */
 826                 r = sdma_v5_2_gfx_resume(adev);
 827                 return r;
 828         }
 829
 830         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 831                 r = sdma_v5_2_load_microcode(adev);
 832                 if (r)
 833                         return r;
 834
 835                 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */
 836                 if (amdgpu_emu_mode == 1)
 837                         msleep(1000);
 838         }
 839
 840         /* unhalt the MEs */
 841         sdma_v5_2_enable(adev, true);
 842         /* enable sdma ring preemption */
 843         sdma_v5_2_ctx_switch_enable(adev, true);
 844
 845         /* start the gfx rings and rlc compute queues */
 846         r = sdma_v5_2_gfx_resume(adev);
 847         if (r)
 848                 return r;
 849         r = sdma_v5_2_rlc_resume(adev);
 850
 851         return r;
 852 }
 853
 854 /**
 855  * sdma_v5_2_ring_test_ring - simple async dma engine test
 856  *
 857  * @ring: amdgpu_ring structure holding ring information
 858  *
 859  * Test the DMA engine by writing using it to write an
 860  * value to memory.
 861  * Returns 0 for success, error for failure.
 862  */
 863 static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring)
 864 {
 865         struct amdgpu_device *adev = ring->adev;
 866         unsigned i;
 867         unsigned index;
 868         int r;
 869         u32 tmp;
 870         u64 gpu_addr;
 871
 872         r = amdgpu_device_wb_get(adev, &index);
 873         if (r) {
 874                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 875                 return r;
 876         }
 877
 878         gpu_addr = adev->wb.gpu_addr + (index * 4);
 879         tmp = 0xCAFEDEAD;
 880         adev->wb.wb[index] = cpu_to_le32(tmp);
 881
 882         r = amdgpu_ring_alloc(ring, 5);
 883         if (r) {
 884                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 885                 amdgpu_device_wb_free(adev, index);
 886                 return r;
 887         }
 888
 889         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 890                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 891         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 892         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 893         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 894         amdgpu_ring_write(ring, 0xDEADBEEF);
 895         amdgpu_ring_commit(ring);
 896
 897         for (i = 0; i < adev->usec_timeout; i++) {
 898                 tmp = le32_to_cpu(adev->wb.wb[index]);
 899                 if (tmp == 0xDEADBEEF)
 900                         break;
 901                 if (amdgpu_emu_mode == 1)
 902                         msleep(1);
 903                 else
 904                         udelay(1);
 905         }
 906
 907         if (i >= adev->usec_timeout)
 908                 r = -ETIMEDOUT;
 909
 910         amdgpu_device_wb_free(adev, index);
 911
 912         return r;
 913 }
 914
 915 /**
 916  * sdma_v5_2_ring_test_ib - test an IB on the DMA engine
 917  *
 918  * @ring: amdgpu_ring structure holding ring information
 919  *
 920  * Test a simple IB in the DMA ring.
 921  * Returns 0 on success, error on failure.
 922  */
 923 static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 924 {
 925         struct amdgpu_device *adev = ring->adev;
 926         struct amdgpu_ib ib;
 927         struct dma_fence *f = NULL;
 928         unsigned index;
 929         long r;
 930         u32 tmp = 0;
 931         u64 gpu_addr;
 932
 933         r = amdgpu_device_wb_get(adev, &index);
 934         if (r) {
 935                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 936                 return r;
 937         }
 938
 939         gpu_addr = adev->wb.gpu_addr + (index * 4);
 940         tmp = 0xCAFEDEAD;
 941         adev->wb.wb[index] = cpu_to_le32(tmp);
 942         memset(&ib, 0, sizeof(ib));
 943         r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
 944         if (r) {
 945                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 946                 goto err0;
 947         }
 948
 949         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 950                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 951         ib.ptr[1] = lower_32_bits(gpu_addr);
 952         ib.ptr[2] = upper_32_bits(gpu_addr);
 953         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
 954         ib.ptr[4] = 0xDEADBEEF;
 955         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 956         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 957         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 958         ib.length_dw = 8;
 959
 960         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 961         if (r)
 962                 goto err1;
 963
 964         r = dma_fence_wait_timeout(f, false, timeout);
 965         if (r == 0) {
 966                 DRM_ERROR("amdgpu: IB test timed out\n");
 967                 r = -ETIMEDOUT;
 968                 goto err1;
 969         } else if (r < 0) {
 970                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 971                 goto err1;
 972         }
 973         tmp = le32_to_cpu(adev->wb.wb[index]);
 974         if (tmp == 0xDEADBEEF)
 975                 r = 0;
 976         else
 977                 r = -EINVAL;
 978
 979 err1:
 980         amdgpu_ib_free(adev, &ib, NULL);
 981         dma_fence_put(f);
 982 err0:
 983         amdgpu_device_wb_free(adev, index);
 984         return r;
 985 }
 986
 987
 988 /**
 989  * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART
 990  *
 991  * @ib: indirect buffer to fill with commands
 992  * @pe: addr of the page entry
 993  * @src: src addr to copy from
 994  * @count: number of page entries to update
 995  *
 996  * Update PTEs by copying them from the GART using sDMA.
 997  */
 998 static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib,
 999                                   uint64_t pe, uint64_t src,
1000                                   unsigned count)
1001 {
1002         unsigned bytes = count * 8;
1003
1004         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1005                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1006         ib->ptr[ib->length_dw++] = bytes - 1;
1007         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1008         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1009         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1010         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1011         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1012
1013 }
1014
1015 /**
1016  * sdma_v5_2_vm_write_pte - update PTEs by writing them manually
1017  *
1018  * @ib: indirect buffer to fill with commands
1019  * @pe: addr of the page entry
1020  * @addr: dst addr to write into pe
1021  * @count: number of page entries to update
1022  * @incr: increase next addr by incr bytes
1023  * @flags: access flags
1024  *
1025  * Update PTEs by writing them manually using sDMA.
1026  */
1027 static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1028                                    uint64_t value, unsigned count,
1029                                    uint32_t incr)
1030 {
1031         unsigned ndw = count * 2;
1032
1033         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1034                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1035         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1036         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1037         ib->ptr[ib->length_dw++] = ndw - 1;
1038         for (; ndw > 0; ndw -= 2) {
1039                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1040                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1041                 value += incr;
1042         }
1043 }
1044
1045 /**
1046  * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA
1047  *
1048  * @ib: indirect buffer to fill with commands
1049  * @pe: addr of the page entry
1050  * @addr: dst addr to write into pe
1051  * @count: number of page entries to update
1052  * @incr: increase next addr by incr bytes
1053  * @flags: access flags
1054  *
1055  * Update the page tables using sDMA.
1056  */
1057 static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib,
1058                                      uint64_t pe,
1059                                      uint64_t addr, unsigned count,
1060                                      uint32_t incr, uint64_t flags)
1061 {
1062         /* for physically contiguous pages (vram) */
1063         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1064         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1065         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1066         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1067         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1068         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1069         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1070         ib->ptr[ib->length_dw++] = incr; /* increment size */
1071         ib->ptr[ib->length_dw++] = 0;
1072         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1073 }
1074
1075 /**
1076  * sdma_v5_2_ring_pad_ib - pad the IB
1077  *
1078  * @ib: indirect buffer to fill with padding
1079  *
1080  * Pad the IB with NOPs to a boundary multiple of 8.
1081  */
1082 static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1083 {
1084         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1085         u32 pad_count;
1086         int i;
1087
1088         pad_count = (-ib->length_dw) & 0x7;
1089         for (i = 0; i < pad_count; i++)
1090                 if (sdma && sdma->burst_nop && (i == 0))
1091                         ib->ptr[ib->length_dw++] =
1092                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1093                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1094                 else
1095                         ib->ptr[ib->length_dw++] =
1096                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1097 }
1098
1099
1100 /**
1101  * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline
1102  *
1103  * @ring: amdgpu_ring pointer
1104  *
1105  * Make sure all previous operations are completed (CIK).
1106  */
1107 static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1108 {
1109         uint32_t seq = ring->fence_drv.sync_seq;
1110         uint64_t addr = ring->fence_drv.gpu_addr;
1111
1112         /* wait for idle */
1113         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1114                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1115                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1116                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1117         amdgpu_ring_write(ring, addr & 0xfffffffc);
1118         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1119         amdgpu_ring_write(ring, seq); /* reference */
1120         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1121         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1122                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1123 }
1124
1125
1126 /**
1127  * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA
1128  *
1129  * @ring: amdgpu_ring pointer
1130  * @vm: amdgpu_vm pointer
1131  *
1132  * Update the page table base and flush the VM TLB
1133  * using sDMA.
1134  */
1135 static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
1136                                          unsigned vmid, uint64_t pd_addr)
1137 {
1138         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1139 }
1140
1141 static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring,
1142                                      uint32_t reg, uint32_t val)
1143 {
1144         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1145                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1146         amdgpu_ring_write(ring, reg);
1147         amdgpu_ring_write(ring, val);
1148 }
1149
1150 static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1151                                          uint32_t val, uint32_t mask)
1152 {
1153         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1154                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1155                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1156         amdgpu_ring_write(ring, reg << 2);
1157         amdgpu_ring_write(ring, 0);
1158         amdgpu_ring_write(ring, val); /* reference */
1159         amdgpu_ring_write(ring, mask); /* mask */
1160         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1161                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1162 }
1163
1164 static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1165                                                    uint32_t reg0, uint32_t reg1,
1166                                                    uint32_t ref, uint32_t mask)
1167 {
1168         amdgpu_ring_emit_wreg(ring, reg0, ref);
1169         /* wait for a cycle to reset vm_inv_eng*_ack */
1170         amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1171         amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1172 }
1173
1174 static int sdma_v5_2_early_init(void *handle)
1175 {
1176         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1177
1178         switch (adev->asic_type) {
1179         case CHIP_SIENNA_CICHLID:
1180                 adev->sdma.num_instances = 4;
1181                 break;
1182         case CHIP_NAVY_FLOUNDER:
1183         case CHIP_DIMGREY_CAVEFISH:
1184                 adev->sdma.num_instances = 2;
1185                 break;
1186         case CHIP_VANGOGH:
1187                 adev->sdma.num_instances = 1;
1188                 break;
1189         default:
1190                 break;
1191         }
1192
1193         sdma_v5_2_set_ring_funcs(adev);
1194         sdma_v5_2_set_buffer_funcs(adev);
1195         sdma_v5_2_set_vm_pte_funcs(adev);
1196         sdma_v5_2_set_irq_funcs(adev);
1197
1198         return 0;
1199 }
1200
1201 static unsigned sdma_v5_2_seq_to_irq_id(int seq_num)
1202 {
1203         switch (seq_num) {
1204         case 0:
1205                 return SOC15_IH_CLIENTID_SDMA0;
1206         case 1:
1207                 return SOC15_IH_CLIENTID_SDMA1;
1208         case 2:
1209                 return SOC15_IH_CLIENTID_SDMA2;
1210         case 3:
1211                 return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid;
1212         default:
1213                 break;
1214         }
1215         return -EINVAL;
1216 }
1217
1218 static unsigned sdma_v5_2_seq_to_trap_id(int seq_num)
1219 {
1220         switch (seq_num) {
1221         case 0:
1222                 return SDMA0_5_0__SRCID__SDMA_TRAP;
1223         case 1:
1224                 return SDMA1_5_0__SRCID__SDMA_TRAP;
1225         case 2:
1226                 return SDMA2_5_0__SRCID__SDMA_TRAP;
1227         case 3:
1228                 return SDMA3_5_0__SRCID__SDMA_TRAP;
1229         default:
1230                 break;
1231         }
1232         return -EINVAL;
1233 }
1234
1235 static int sdma_v5_2_sw_init(void *handle)
1236 {
1237         struct amdgpu_ring *ring;
1238         int r, i;
1239         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1240
1241         /* SDMA trap event */
1242         for (i = 0; i < adev->sdma.num_instances; i++) {
1243                 r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i),
1244                                       sdma_v5_2_seq_to_trap_id(i),
1245                                       &adev->sdma.trap_irq);
1246                 if (r)
1247                         return r;
1248         }
1249
1250         r = sdma_v5_2_init_microcode(adev);
1251         if (r) {
1252                 DRM_ERROR("Failed to load sdma firmware!\n");
1253                 return r;
1254         }
1255
1256         for (i = 0; i < adev->sdma.num_instances; i++) {
1257                 ring = &adev->sdma.instance[i].ring;
1258                 ring->ring_obj = NULL;
1259                 ring->use_doorbell = true;
1260                 ring->me = i;
1261
1262                 DRM_INFO("use_doorbell being set to: [%s]\n",
1263                                 ring->use_doorbell?"true":"false");
1264
1265                 ring->doorbell_index =
1266                         (adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset
1267
1268                 sprintf(ring->name, "sdma%d", i);
1269                 r = amdgpu_ring_init(adev, ring, 1024,
1270                                      &adev->sdma.trap_irq,
1271                                      AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1272                                      AMDGPU_RING_PRIO_DEFAULT);
1273                 if (r)
1274                         return r;
1275         }
1276
1277         return r;
1278 }
1279
1280 static int sdma_v5_2_sw_fini(void *handle)
1281 {
1282         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1283         int i;
1284
1285         for (i = 0; i < adev->sdma.num_instances; i++)
1286                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1287
1288         sdma_v5_2_destroy_inst_ctx(adev);
1289
1290         return 0;
1291 }
1292
1293 static int sdma_v5_2_hw_init(void *handle)
1294 {
1295         int r;
1296         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1297
1298         sdma_v5_2_init_golden_registers(adev);
1299
1300         r = sdma_v5_2_start(adev);
1301
1302         return r;
1303 }
1304
1305 static int sdma_v5_2_hw_fini(void *handle)
1306 {
1307         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1308
1309         if (amdgpu_sriov_vf(adev))
1310                 return 0;
1311
1312         sdma_v5_2_ctx_switch_enable(adev, false);
1313         sdma_v5_2_enable(adev, false);
1314
1315         return 0;
1316 }
1317
1318 static int sdma_v5_2_suspend(void *handle)
1319 {
1320         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1321
1322         return sdma_v5_2_hw_fini(adev);
1323 }
1324
1325 static int sdma_v5_2_resume(void *handle)
1326 {
1327         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1328
1329         return sdma_v5_2_hw_init(adev);
1330 }
1331
1332 static bool sdma_v5_2_is_idle(void *handle)
1333 {
1334         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1335         u32 i;
1336
1337         for (i = 0; i < adev->sdma.num_instances; i++) {
1338                 u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1339
1340                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1341                         return false;
1342         }
1343
1344         return true;
1345 }
1346
1347 static int sdma_v5_2_wait_for_idle(void *handle)
1348 {
1349         unsigned i;
1350         u32 sdma0, sdma1, sdma2, sdma3;
1351         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1352
1353         for (i = 0; i < adev->usec_timeout; i++) {
1354                 sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1355                 sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1356                 sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG));
1357                 sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG));
1358
1359                 if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK)
1360                         return 0;
1361                 udelay(1);
1362         }
1363         return -ETIMEDOUT;
1364 }
1365
1366 static int sdma_v5_2_soft_reset(void *handle)
1367 {
1368         /* todo */
1369
1370         return 0;
1371 }
1372
1373 static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring)
1374 {
1375         int i, r = 0;
1376         struct amdgpu_device *adev = ring->adev;
1377         u32 index = 0;
1378         u64 sdma_gfx_preempt;
1379
1380         amdgpu_sdma_get_index_from_ring(ring, &index);
1381         sdma_gfx_preempt =
1382                 sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT);
1383
1384         /* assert preemption condition */
1385         amdgpu_ring_set_preempt_cond_exec(ring, false);
1386
1387         /* emit the trailing fence */
1388         ring->trail_seq += 1;
1389         amdgpu_ring_alloc(ring, 10);
1390         sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1391                                   ring->trail_seq, 0);
1392         amdgpu_ring_commit(ring);
1393
1394         /* assert IB preemption */
1395         WREG32(sdma_gfx_preempt, 1);
1396
1397         /* poll the trailing fence */
1398         for (i = 0; i < adev->usec_timeout; i++) {
1399                 if (ring->trail_seq ==
1400                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1401                         break;
1402                 udelay(1);
1403         }
1404
1405         if (i >= adev->usec_timeout) {
1406                 r = -EINVAL;
1407                 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1408         }
1409
1410         /* deassert IB preemption */
1411         WREG32(sdma_gfx_preempt, 0);
1412
1413         /* deassert the preemption condition */
1414         amdgpu_ring_set_preempt_cond_exec(ring, true);
1415         return r;
1416 }
1417
1418 static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev,
1419                                         struct amdgpu_irq_src *source,
1420                                         unsigned type,
1421                                         enum amdgpu_interrupt_state state)
1422 {
1423         u32 sdma_cntl;
1424
1425         u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL);
1426
1427         sdma_cntl = RREG32(reg_offset);
1428         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1429                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1430         WREG32(reg_offset, sdma_cntl);
1431
1432         return 0;
1433 }
1434
1435 static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev,
1436                                       struct amdgpu_irq_src *source,
1437                                       struct amdgpu_iv_entry *entry)
1438 {
1439         DRM_DEBUG("IH: SDMA trap\n");
1440         switch (entry->client_id) {
1441         case SOC15_IH_CLIENTID_SDMA0:
1442                 switch (entry->ring_id) {
1443                 case 0:
1444                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1445                         break;
1446                 case 1:
1447                         /* XXX compute */
1448                         break;
1449                 case 2:
1450                         /* XXX compute */
1451                         break;
1452                 case 3:
1453                         /* XXX page queue*/
1454                         break;
1455                 }
1456                 break;
1457         case SOC15_IH_CLIENTID_SDMA1:
1458                 switch (entry->ring_id) {
1459                 case 0:
1460                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1461                         break;
1462                 case 1:
1463                         /* XXX compute */
1464                         break;
1465                 case 2:
1466                         /* XXX compute */
1467                         break;
1468                 case 3:
1469                         /* XXX page queue*/
1470                         break;
1471                 }
1472                 break;
1473         case SOC15_IH_CLIENTID_SDMA2:
1474                 switch (entry->ring_id) {
1475                 case 0:
1476                         amdgpu_fence_process(&adev->sdma.instance[2].ring);
1477                         break;
1478                 case 1:
1479                         /* XXX compute */
1480                         break;
1481                 case 2:
1482                         /* XXX compute */
1483                         break;
1484                 case 3:
1485                         /* XXX page queue*/
1486                         break;
1487                 }
1488                 break;
1489         case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid:
1490                 switch (entry->ring_id) {
1491                 case 0:
1492                         amdgpu_fence_process(&adev->sdma.instance[3].ring);
1493                         break;
1494                 case 1:
1495                         /* XXX compute */
1496                         break;
1497                 case 2:
1498                         /* XXX compute */
1499                         break;
1500                 case 3:
1501                         /* XXX page queue*/
1502                         break;
1503                 }
1504                 break;
1505         }
1506         return 0;
1507 }
1508
1509 static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev,
1510                                               struct amdgpu_irq_src *source,
1511                                               struct amdgpu_iv_entry *entry)
1512 {
1513         return 0;
1514 }
1515
1516 static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1517                                                        bool enable)
1518 {
1519         uint32_t data, def;
1520         int i;
1521
1522         for (i = 0; i < adev->sdma.num_instances; i++) {
1523                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1524                         /* Enable sdma clock gating */
1525                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1526                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1527                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1528                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1529                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1530                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1531                                   SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1532                         if (def != data)
1533                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1534                 } else {
1535                         /* Disable sdma clock gating */
1536                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1537                         data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1538                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1539                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1540                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1541                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1542                                  SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1543                         if (def != data)
1544                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1545                 }
1546         }
1547 }
1548
1549 static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1550                                                       bool enable)
1551 {
1552         uint32_t data, def;
1553         int i;
1554
1555         for (i = 0; i < adev->sdma.num_instances; i++) {
1556                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1557                         /* Enable sdma mem light sleep */
1558                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1559                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1560                         if (def != data)
1561                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1562
1563                 } else {
1564                         /* Disable sdma mem light sleep */
1565                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1566                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1567                         if (def != data)
1568                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1569
1570                 }
1571         }
1572 }
1573
1574 static int sdma_v5_2_set_clockgating_state(void *handle,
1575                                            enum amd_clockgating_state state)
1576 {
1577         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1578
1579         if (amdgpu_sriov_vf(adev))
1580                 return 0;
1581
1582         switch (adev->asic_type) {
1583         case CHIP_SIENNA_CICHLID:
1584         case CHIP_NAVY_FLOUNDER:
1585         case CHIP_VANGOGH:
1586         case CHIP_DIMGREY_CAVEFISH:
1587                 sdma_v5_2_update_medium_grain_clock_gating(adev,
1588                                 state == AMD_CG_STATE_GATE ? true : false);
1589                 sdma_v5_2_update_medium_grain_light_sleep(adev,
1590                                 state == AMD_CG_STATE_GATE ? true : false);
1591                 break;
1592         default:
1593                 break;
1594         }
1595
1596         return 0;
1597 }
1598
1599 static int sdma_v5_2_set_powergating_state(void *handle,
1600                                           enum amd_powergating_state state)
1601 {
1602         return 0;
1603 }
1604
1605 static void sdma_v5_2_get_clockgating_state(void *handle, u32 *flags)
1606 {
1607         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1608         int data;
1609
1610         if (amdgpu_sriov_vf(adev))
1611                 *flags = 0;
1612
1613         /* AMD_CG_SUPPORT_SDMA_LS */
1614         data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1615         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1616                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1617 }
1618
1619 const struct amd_ip_funcs sdma_v5_2_ip_funcs = {
1620         .name = "sdma_v5_2",
1621         .early_init = sdma_v5_2_early_init,
1622         .late_init = NULL,
1623         .sw_init = sdma_v5_2_sw_init,
1624         .sw_fini = sdma_v5_2_sw_fini,
1625         .hw_init = sdma_v5_2_hw_init,
1626         .hw_fini = sdma_v5_2_hw_fini,
1627         .suspend = sdma_v5_2_suspend,
1628         .resume = sdma_v5_2_resume,
1629         .is_idle = sdma_v5_2_is_idle,
1630         .wait_for_idle = sdma_v5_2_wait_for_idle,
1631         .soft_reset = sdma_v5_2_soft_reset,
1632         .set_clockgating_state = sdma_v5_2_set_clockgating_state,
1633         .set_powergating_state = sdma_v5_2_set_powergating_state,
1634         .get_clockgating_state = sdma_v5_2_get_clockgating_state,
1635 };
1636
1637 static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {
1638         .type = AMDGPU_RING_TYPE_SDMA,
1639         .align_mask = 0xf,
1640         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1641         .support_64bit_ptrs = true,
1642         .vmhub = AMDGPU_GFXHUB_0,
1643         .get_rptr = sdma_v5_2_ring_get_rptr,
1644         .get_wptr = sdma_v5_2_ring_get_wptr,
1645         .set_wptr = sdma_v5_2_ring_set_wptr,
1646         .emit_frame_size =
1647                 5 + /* sdma_v5_2_ring_init_cond_exec */
1648                 6 + /* sdma_v5_2_ring_emit_hdp_flush */
1649                 3 + /* hdp_invalidate */
1650                 6 + /* sdma_v5_2_ring_emit_pipeline_sync */
1651                 /* sdma_v5_2_ring_emit_vm_flush */
1652                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1653                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1654                 10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */
1655         .emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */
1656         .emit_ib = sdma_v5_2_ring_emit_ib,
1657         .emit_fence = sdma_v5_2_ring_emit_fence,
1658         .emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync,
1659         .emit_vm_flush = sdma_v5_2_ring_emit_vm_flush,
1660         .emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush,
1661         .test_ring = sdma_v5_2_ring_test_ring,
1662         .test_ib = sdma_v5_2_ring_test_ib,
1663         .insert_nop = sdma_v5_2_ring_insert_nop,
1664         .pad_ib = sdma_v5_2_ring_pad_ib,
1665         .emit_wreg = sdma_v5_2_ring_emit_wreg,
1666         .emit_reg_wait = sdma_v5_2_ring_emit_reg_wait,
1667         .emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait,
1668         .init_cond_exec = sdma_v5_2_ring_init_cond_exec,
1669         .patch_cond_exec = sdma_v5_2_ring_patch_cond_exec,
1670         .preempt_ib = sdma_v5_2_ring_preempt_ib,
1671 };
1672
1673 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev)
1674 {
1675         int i;
1676
1677         for (i = 0; i < adev->sdma.num_instances; i++) {
1678                 adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs;
1679                 adev->sdma.instance[i].ring.me = i;
1680         }
1681 }
1682
1683 static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = {
1684         .set = sdma_v5_2_set_trap_irq_state,
1685         .process = sdma_v5_2_process_trap_irq,
1686 };
1687
1688 static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = {
1689         .process = sdma_v5_2_process_illegal_inst_irq,
1690 };
1691
1692 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev)
1693 {
1694         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1695                                         adev->sdma.num_instances;
1696         adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs;
1697         adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs;
1698 }
1699
1700 /**
1701  * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine
1702  *
1703  * @ring: amdgpu_ring structure holding ring information
1704  * @src_offset: src GPU address
1705  * @dst_offset: dst GPU address
1706  * @byte_count: number of bytes to xfer
1707  *
1708  * Copy GPU buffers using the DMA engine.
1709  * Used by the amdgpu ttm implementation to move pages if
1710  * registered as the asic copy callback.
1711  */
1712 static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib,
1713                                        uint64_t src_offset,
1714                                        uint64_t dst_offset,
1715                                        uint32_t byte_count,
1716                                        bool tmz)
1717 {
1718         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1719                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1720                 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1721         ib->ptr[ib->length_dw++] = byte_count - 1;
1722         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1723         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1724         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1725         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1726         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1727 }
1728
1729 /**
1730  * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine
1731  *
1732  * @ring: amdgpu_ring structure holding ring information
1733  * @src_data: value to write to buffer
1734  * @dst_offset: dst GPU address
1735  * @byte_count: number of bytes to xfer
1736  *
1737  * Fill GPU buffers using the DMA engine.
1738  */
1739 static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
1740                                        uint32_t src_data,
1741                                        uint64_t dst_offset,
1742                                        uint32_t byte_count)
1743 {
1744         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1745         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1746         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1747         ib->ptr[ib->length_dw++] = src_data;
1748         ib->ptr[ib->length_dw++] = byte_count - 1;
1749 }
1750
1751 static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = {
1752         .copy_max_bytes = 0x400000,
1753         .copy_num_dw = 7,
1754         .emit_copy_buffer = sdma_v5_2_emit_copy_buffer,
1755
1756         .fill_max_bytes = 0x400000,
1757         .fill_num_dw = 5,
1758         .emit_fill_buffer = sdma_v5_2_emit_fill_buffer,
1759 };
1760
1761 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev)
1762 {
1763         if (adev->mman.buffer_funcs == NULL) {
1764                 adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs;
1765                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1766         }
1767 }
1768
1769 static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = {
1770         .copy_pte_num_dw = 7,
1771         .copy_pte = sdma_v5_2_vm_copy_pte,
1772         .write_pte = sdma_v5_2_vm_write_pte,
1773         .set_pte_pde = sdma_v5_2_vm_set_pte_pde,
1774 };
1775
1776 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev)
1777 {
1778         unsigned i;
1779
1780         if (adev->vm_manager.vm_pte_funcs == NULL) {
1781                 adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs;
1782                 for (i = 0; i < adev->sdma.num_instances; i++) {
1783                         adev->vm_manager.vm_pte_scheds[i] =
1784                                 &adev->sdma.instance[i].ring.sched;
1785                 }
1786                 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1787         }
1788 }
1789
1790 const struct amdgpu_ip_block_version sdma_v5_2_ip_block = {
1791         .type = AMD_IP_BLOCK_TYPE_SDMA,
1792         .major = 5,
1793         .minor = 2,
1794         .rev = 0,
1795         .funcs = &sdma_v5_2_ip_funcs,
1796 };