drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_ucode.h"
  31 #include "amdgpu_trace.h"
  32
  33 #include "gc/gc_10_3_0_offset.h"
  34 #include "gc/gc_10_3_0_sh_mask.h"
  35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
  36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
  37 #include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h"
  38 #include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h"
  39
  40 #include "soc15_common.h"
  41 #include "soc15.h"
  42 #include "navi10_sdma_pkt_open.h"
  43 #include "nbio_v2_3.h"
  44 #include "sdma_common.h"
  45 #include "sdma_v5_2.h"
  46
  47 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin");
  48 MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin");
  49 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin");
  50
  51 MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin");
  52
  53 #define SDMA1_REG_OFFSET 0x600
  54 #define SDMA3_REG_OFFSET 0x400
  55 #define SDMA0_HYP_DEC_REG_START 0x5880
  56 #define SDMA0_HYP_DEC_REG_END 0x5893
  57 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
  58
  59 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev);
  60 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev);
  61 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev);
  62 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev);
  63
  64 static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
  65 {
  66         u32 base;
  67
  68         if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
  69             internal_offset <= SDMA0_HYP_DEC_REG_END) {
  70                 base = adev->reg_offset[GC_HWIP][0][1];
  71                 if (instance != 0)
  72                         internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
  73         } else {
  74                 if (instance < 2) {
  75                         base = adev->reg_offset[GC_HWIP][0][0];
  76                         if (instance == 1)
  77                                 internal_offset += SDMA1_REG_OFFSET;
  78                 } else {
  79                         base = adev->reg_offset[GC_HWIP][0][2];
  80                         if (instance == 3)
  81                                 internal_offset += SDMA3_REG_OFFSET;
  82                 }
  83         }
  84
  85         return base + internal_offset;
  86 }
  87
  88 static void sdma_v5_2_init_golden_registers(struct amdgpu_device *adev)
  89 {
  90         switch (adev->asic_type) {
  91         case CHIP_SIENNA_CICHLID:
  92         case CHIP_NAVY_FLOUNDER:
  93         case CHIP_VANGOGH:
  94         case CHIP_DIMGREY_CAVEFISH:
  95                 break;
  96         default:
  97                 break;
  98         }
  99 }
 100
 101 static int sdma_v5_2_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
 102 {
 103         int err = 0;
 104         const struct sdma_firmware_header_v1_0 *hdr;
 105
 106         err = amdgpu_ucode_validate(sdma_inst->fw);
 107         if (err)
 108                 return err;
 109
 110         hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
 111         sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
 112         sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
 113
 114         if (sdma_inst->feature_version >= 20)
 115                 sdma_inst->burst_nop = true;
 116
 117         return 0;
 118 }
 119
 120 static void sdma_v5_2_destroy_inst_ctx(struct amdgpu_device *adev)
 121 {
 122         release_firmware(adev->sdma.instance[0].fw);
 123
 124         memset((void *)adev->sdma.instance, 0,
 125                sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
 126 }
 127
 128 /**
 129  * sdma_v5_2_init_microcode - load ucode images from disk
 130  *
 131  * @adev: amdgpu_device pointer
 132  *
 133  * Use the firmware interface to load the ucode images into
 134  * the driver (not loaded into hw).
 135  * Returns 0 on success, error on failure.
 136  */
 137
 138 // emulation only, won't work on real chip
 139 // navi10 real chip need to use PSP to load firmware
 140 static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
 141 {
 142         const char *chip_name;
 143         char fw_name[40];
 144         int err = 0, i;
 145         struct amdgpu_firmware_info *info = NULL;
 146         const struct common_firmware_header *header = NULL;
 147
 148         if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_SIENNA_CICHLID))
 149                 return 0;
 150
 151         DRM_DEBUG("\n");
 152
 153         switch (adev->asic_type) {
 154         case CHIP_SIENNA_CICHLID:
 155                 chip_name = "sienna_cichlid";
 156                 break;
 157         case CHIP_NAVY_FLOUNDER:
 158                 chip_name = "navy_flounder";
 159                 break;
 160         case CHIP_VANGOGH:
 161                 chip_name = "vangogh";
 162                 break;
 163         case CHIP_DIMGREY_CAVEFISH:
 164                 chip_name = "dimgrey_cavefish";
 165                 break;
 166         default:
 167                 BUG();
 168         }
 169
 170         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 171
 172         err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);
 173         if (err)
 174                 goto out;
 175
 176         err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]);
 177         if (err)
 178                 goto out;
 179
 180         for (i = 1; i < adev->sdma.num_instances; i++)
 181                 memcpy((void *)&adev->sdma.instance[i],
 182                        (void *)&adev->sdma.instance[0],
 183                        sizeof(struct amdgpu_sdma_instance));
 184
 185         DRM_DEBUG("psp_load == '%s'\n",
 186                   adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
 187
 188         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 189                 for (i = 0; i < adev->sdma.num_instances; i++) {
 190                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 191                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 192                         info->fw = adev->sdma.instance[i].fw;
 193                         header = (const struct common_firmware_header *)info->fw->data;
 194                         adev->firmware.fw_size +=
 195                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 196                 }
 197         }
 198
 199 out:
 200         if (err) {
 201                 DRM_ERROR("sdma_v5_2: Failed to load firmware \"%s\"\n", fw_name);
 202                 sdma_v5_2_destroy_inst_ctx(adev);
 203         }
 204         return err;
 205 }
 206
 207 static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring)
 208 {
 209         unsigned ret;
 210
 211         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
 212         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
 213         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
 214         amdgpu_ring_write(ring, 1);
 215         ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
 216         amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
 217
 218         return ret;
 219 }
 220
 221 static void sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring *ring,
 222                                            unsigned offset)
 223 {
 224         unsigned cur;
 225
 226         BUG_ON(offset > ring->buf_mask);
 227         BUG_ON(ring->ring[offset] != 0x55aa55aa);
 228
 229         cur = (ring->wptr - 1) & ring->buf_mask;
 230         if (cur > offset)
 231                 ring->ring[offset] = cur - offset;
 232         else
 233                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
 234 }
 235
 236 /**
 237  * sdma_v5_2_ring_get_rptr - get the current read pointer
 238  *
 239  * @ring: amdgpu ring pointer
 240  *
 241  * Get the current rptr from the hardware (NAVI10+).
 242  */
 243 static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring)
 244 {
 245         u64 *rptr;
 246
 247         /* XXX check if swapping is necessary on BE */
 248         rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
 249
 250         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 251         return ((*rptr) >> 2);
 252 }
 253
 254 /**
 255  * sdma_v5_2_ring_get_wptr - get the current write pointer
 256  *
 257  * @ring: amdgpu ring pointer
 258  *
 259  * Get the current wptr from the hardware (NAVI10+).
 260  */
 261 static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring)
 262 {
 263         struct amdgpu_device *adev = ring->adev;
 264         u64 wptr;
 265
 266         if (ring->use_doorbell) {
 267                 /* XXX check if swapping is necessary on BE */
 268                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 269                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 270         } else {
 271                 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
 272                 wptr = wptr << 32;
 273                 wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
 274                 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
 275         }
 276
 277         return wptr >> 2;
 278 }
 279
 280 /**
 281  * sdma_v5_2_ring_set_wptr - commit the write pointer
 282  *
 283  * @ring: amdgpu ring pointer
 284  *
 285  * Write the wptr back to the hardware (NAVI10+).
 286  */
 287 static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring)
 288 {
 289         struct amdgpu_device *adev = ring->adev;
 290
 291         DRM_DEBUG("Setting write pointer\n");
 292         if (ring->use_doorbell) {
 293                 DRM_DEBUG("Using doorbell -- "
 294                                 "wptr_offs == 0x%08x "
 295                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 296                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 297                                 ring->wptr_offs,
 298                                 lower_32_bits(ring->wptr << 2),
 299                                 upper_32_bits(ring->wptr << 2));
 300                 /* XXX check if swapping is necessary on BE */
 301                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
 302                 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
 303                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 304                                 ring->doorbell_index, ring->wptr << 2);
 305                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 306         } else {
 307                 DRM_DEBUG("Not using doorbell -- "
 308                                 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 309                                 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 310                                 ring->me,
 311                                 lower_32_bits(ring->wptr << 2),
 312                                 ring->me,
 313                                 upper_32_bits(ring->wptr << 2));
 314                 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
 315                         lower_32_bits(ring->wptr << 2));
 316                 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
 317                         upper_32_bits(ring->wptr << 2));
 318         }
 319 }
 320
 321 static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 322 {
 323         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 324         int i;
 325
 326         for (i = 0; i < count; i++)
 327                 if (sdma && sdma->burst_nop && (i == 0))
 328                         amdgpu_ring_write(ring, ring->funcs->nop |
 329                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 330                 else
 331                         amdgpu_ring_write(ring, ring->funcs->nop);
 332 }
 333
 334 /**
 335  * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine
 336  *
 337  * @ring: amdgpu ring pointer
 338  * @job: job to retrieve vmid from
 339  * @ib: IB object to schedule
 340  * @flags: unused
 341  *
 342  * Schedule an IB in the DMA ring.
 343  */
 344 static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring,
 345                                    struct amdgpu_job *job,
 346                                    struct amdgpu_ib *ib,
 347                                    uint32_t flags)
 348 {
 349         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 350         uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
 351
 352         /* An IB packet must end on a 8 DW boundary--the next dword
 353          * must be on a 8-dword boundary. Our IB packet below is 6
 354          * dwords long, thus add x number of NOPs, such that, in
 355          * modular arithmetic,
 356          * wptr + 6 + x = 8k, k >= 0, which in C is,
 357          * (wptr + 6 + x) % 8 = 0.
 358          * The expression below, is a solution of x.
 359          */
 360         sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 361
 362         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 363                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 364         /* base must be 32 byte aligned */
 365         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 366         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 367         amdgpu_ring_write(ring, ib->length_dw);
 368         amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
 369         amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
 370 }
 371
 372 /**
 373  * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 374  *
 375  * @ring: amdgpu ring pointer
 376  *
 377  * Emit an hdp flush packet on the requested DMA ring.
 378  */
 379 static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 380 {
 381         struct amdgpu_device *adev = ring->adev;
 382         u32 ref_and_mask = 0;
 383         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 384
 385         ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
 386
 387         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 388                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 389                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 390         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
 391         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
 392         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 393         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 394         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 395                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 396 }
 397
 398 /**
 399  * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring
 400  *
 401  * @ring: amdgpu ring pointer
 402  * @addr: address
 403  * @seq: sequence number
 404  * @flags: fence related flags
 405  *
 406  * Add a DMA fence packet to the ring to write
 407  * the fence seq number and DMA trap packet to generate
 408  * an interrupt if needed.
 409  */
 410 static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 411                                       unsigned flags)
 412 {
 413         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 414         /* write the fence */
 415         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 416                           SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
 417         /* zero in first two bits */
 418         BUG_ON(addr & 0x3);
 419         amdgpu_ring_write(ring, lower_32_bits(addr));
 420         amdgpu_ring_write(ring, upper_32_bits(addr));
 421         amdgpu_ring_write(ring, lower_32_bits(seq));
 422
 423         /* optionally write high bits as well */
 424         if (write64bit) {
 425                 addr += 4;
 426                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 427                                   SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
 428                 /* zero in first two bits */
 429                 BUG_ON(addr & 0x3);
 430                 amdgpu_ring_write(ring, lower_32_bits(addr));
 431                 amdgpu_ring_write(ring, upper_32_bits(addr));
 432                 amdgpu_ring_write(ring, upper_32_bits(seq));
 433         }
 434
 435         if (flags & AMDGPU_FENCE_FLAG_INT) {
 436                 /* generate an interrupt */
 437                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 438                 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 439         }
 440 }
 441
 442
 443 /**
 444  * sdma_v5_2_gfx_stop - stop the gfx async dma engines
 445  *
 446  * @adev: amdgpu_device pointer
 447  *
 448  * Stop the gfx async dma ring buffers.
 449  */
 450 static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev)
 451 {
 452         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 453         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 454         struct amdgpu_ring *sdma2 = &adev->sdma.instance[2].ring;
 455         struct amdgpu_ring *sdma3 = &adev->sdma.instance[3].ring;
 456         u32 rb_cntl, ib_cntl;
 457         int i;
 458
 459         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 460             (adev->mman.buffer_funcs_ring == sdma1) ||
 461             (adev->mman.buffer_funcs_ring == sdma2) ||
 462             (adev->mman.buffer_funcs_ring == sdma3))
 463                 amdgpu_ttm_set_buffer_funcs_status(adev, false);
 464
 465         for (i = 0; i < adev->sdma.num_instances; i++) {
 466                 rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 467                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 468                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 469                 ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 470                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 471                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 472         }
 473
 474         sdma0->sched.ready = false;
 475         sdma1->sched.ready = false;
 476         sdma2->sched.ready = false;
 477         sdma3->sched.ready = false;
 478 }
 479
 480 /**
 481  * sdma_v5_2_rlc_stop - stop the compute async dma engines
 482  *
 483  * @adev: amdgpu_device pointer
 484  *
 485  * Stop the compute async dma queues.
 486  */
 487 static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev)
 488 {
 489         /* XXX todo */
 490 }
 491
 492 /**
 493  * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
 494  *
 495  * @adev: amdgpu_device pointer
 496  * @enable: enable/disable the DMA MEs context switch.
 497  *
 498  * Halt or unhalt the async dma engines context switch.
 499  */
 500 static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 501 {
 502         u32 f32_cntl, phase_quantum = 0;
 503         int i;
 504
 505         if (amdgpu_sdma_phase_quantum) {
 506                 unsigned value = amdgpu_sdma_phase_quantum;
 507                 unsigned unit = 0;
 508
 509                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 510                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 511                         value = (value + 1) >> 1;
 512                         unit++;
 513                 }
 514                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 515                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 516                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 517                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 518                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 519                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 520                         WARN_ONCE(1,
 521                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 522                                   value << unit);
 523                 }
 524                 phase_quantum =
 525                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 526                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 527         }
 528
 529         for (i = 0; i < adev->sdma.num_instances; i++) {
 530                 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
 531                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 532                                 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 533                 if (enable && amdgpu_sdma_phase_quantum) {
 534                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
 535                                phase_quantum);
 536                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
 537                                phase_quantum);
 538                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
 539                                phase_quantum);
 540                 }
 541                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
 542         }
 543
 544 }
 545
 546 /**
 547  * sdma_v5_2_enable - stop the async dma engines
 548  *
 549  * @adev: amdgpu_device pointer
 550  * @enable: enable/disable the DMA MEs.
 551  *
 552  * Halt or unhalt the async dma engines.
 553  */
 554 static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable)
 555 {
 556         u32 f32_cntl;
 557         int i;
 558
 559         if (!enable) {
 560                 sdma_v5_2_gfx_stop(adev);
 561                 sdma_v5_2_rlc_stop(adev);
 562         }
 563
 564         for (i = 0; i < adev->sdma.num_instances; i++) {
 565                 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 566                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 567                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
 568         }
 569 }
 570
 571 /**
 572  * sdma_v5_2_gfx_resume - setup and start the async dma engines
 573  *
 574  * @adev: amdgpu_device pointer
 575  *
 576  * Set up the gfx DMA ring buffers and enable them.
 577  * Returns 0 for success, error for failure.
 578  */
 579 static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
 580 {
 581         struct amdgpu_ring *ring;
 582         u32 rb_cntl, ib_cntl;
 583         u32 rb_bufsz;
 584         u32 wb_offset;
 585         u32 doorbell;
 586         u32 doorbell_offset;
 587         u32 temp;
 588         u32 wptr_poll_cntl;
 589         u64 wptr_gpu_addr;
 590         int i, r;
 591
 592         for (i = 0; i < adev->sdma.num_instances; i++) {
 593                 ring = &adev->sdma.instance[i].ring;
 594                 wb_offset = (ring->rptr_offs * 4);
 595
 596                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 597
 598                 /* Set ring buffer size in dwords */
 599                 rb_bufsz = order_base_2(ring->ring_size / 4);
 600                 rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 601                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 602 #ifdef __BIG_ENDIAN
 603                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 604                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 605                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 606 #endif
 607                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 608
 609                 /* Initialize the ring buffer's read and write pointers */
 610                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
 611                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
 612                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
 613                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 614
 615                 /* setup the wptr shadow polling */
 616                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 617                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
 618                        lower_32_bits(wptr_gpu_addr));
 619                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
 620                        upper_32_bits(wptr_gpu_addr));
 621                 wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i,
 622                                                          mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 623                 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 624                                                SDMA0_GFX_RB_WPTR_POLL_CNTL,
 625                                                F32_POLL_ENABLE, 1);
 626                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
 627                        wptr_poll_cntl);
 628
 629                 /* set the wb address whether it's enabled or not */
 630                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
 631                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 632                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
 633                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 634
 635                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 636
 637                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
 638                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
 639
 640                 ring->wptr = 0;
 641
 642                 /* before programing wptr to a less value, need set minor_ptr_update first */
 643                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
 644
 645                 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 646                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
 647                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
 648                 }
 649
 650                 doorbell = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
 651                 doorbell_offset = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
 652
 653                 if (ring->use_doorbell) {
 654                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 655                         doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
 656                                         OFFSET, ring->doorbell_index);
 657                 } else {
 658                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 659                 }
 660                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
 661                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
 662
 663                 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 664                                                       ring->doorbell_index,
 665                                                       adev->doorbell_index.sdma_doorbell_range);
 666
 667                 if (amdgpu_sriov_vf(adev))
 668                         sdma_v5_2_ring_set_wptr(ring);
 669
 670                 /* set minor_ptr_update to 0 after wptr programed */
 671                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
 672
 673                 /* set utc l1 enable flag always to 1 */
 674                 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
 675                 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
 676
 677                 /* enable MCBP */
 678                 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
 679                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
 680
 681                 /* Set up RESP_MODE to non-copy addresses */
 682                 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
 683                 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
 684                 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
 685                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
 686
 687                 /* program default cache read and write policy */
 688                 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
 689                 /* clean read policy and write policy bits */
 690                 temp &= 0xFF0FFF;
 691                 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
 692                          (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
 693                          SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
 694                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
 695
 696                 if (!amdgpu_sriov_vf(adev)) {
 697                         /* unhalt engine */
 698                         temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 699                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 700                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
 701                 }
 702
 703                 /* enable DMA RB */
 704                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 705                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 706
 707                 ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 708                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 709 #ifdef __BIG_ENDIAN
 710                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 711 #endif
 712                 /* enable DMA IBs */
 713                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 714
 715                 ring->sched.ready = true;
 716
 717                 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
 718                         sdma_v5_2_ctx_switch_enable(adev, true);
 719                         sdma_v5_2_enable(adev, true);
 720                 }
 721
 722                 r = amdgpu_ring_test_ring(ring);
 723                 if (r) {
 724                         ring->sched.ready = false;
 725                         return r;
 726                 }
 727
 728                 if (adev->mman.buffer_funcs_ring == ring)
 729                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 730         }
 731
 732         return 0;
 733 }
 734
 735 /**
 736  * sdma_v5_2_rlc_resume - setup and start the async dma engines
 737  *
 738  * @adev: amdgpu_device pointer
 739  *
 740  * Set up the compute DMA queues and enable them.
 741  * Returns 0 for success, error for failure.
 742  */
 743 static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev)
 744 {
 745         return 0;
 746 }
 747
 748 /**
 749  * sdma_v5_2_load_microcode - load the sDMA ME ucode
 750  *
 751  * @adev: amdgpu_device pointer
 752  *
 753  * Loads the sDMA0/1/2/3 ucode.
 754  * Returns 0 for success, -EINVAL if the ucode is not available.
 755  */
 756 static int sdma_v5_2_load_microcode(struct amdgpu_device *adev)
 757 {
 758         const struct sdma_firmware_header_v1_0 *hdr;
 759         const __le32 *fw_data;
 760         u32 fw_size;
 761         int i, j;
 762
 763         /* halt the MEs */
 764         sdma_v5_2_enable(adev, false);
 765
 766         for (i = 0; i < adev->sdma.num_instances; i++) {
 767                 if (!adev->sdma.instance[i].fw)
 768                         return -EINVAL;
 769
 770                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 771                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 772                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 773
 774                 fw_data = (const __le32 *)
 775                         (adev->sdma.instance[i].fw->data +
 776                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 777
 778                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
 779
 780                 for (j = 0; j < fw_size; j++) {
 781                         if (amdgpu_emu_mode == 1 && j % 500 == 0)
 782                                 msleep(1);
 783                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 784                 }
 785
 786                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
 787         }
 788
 789         return 0;
 790 }
 791
 792 static int sdma_v5_2_soft_reset(void *handle)
 793 {
 794         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 795         u32 grbm_soft_reset;
 796         u32 tmp;
 797         int i;
 798
 799         for (i = 0; i < adev->sdma.num_instances; i++) {
 800                 grbm_soft_reset = REG_SET_FIELD(0,
 801                                                 GRBM_SOFT_RESET, SOFT_RESET_SDMA0,
 802                                                 1);
 803                 grbm_soft_reset <<= i;
 804
 805                 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
 806                 tmp |= grbm_soft_reset;
 807                 DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp);
 808                 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
 809                 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
 810
 811                 udelay(50);
 812
 813                 tmp &= ~grbm_soft_reset;
 814                 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
 815                 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
 816
 817                 udelay(50);
 818         }
 819
 820         return 0;
 821 }
 822
 823 /**
 824  * sdma_v5_2_start - setup and start the async dma engines
 825  *
 826  * @adev: amdgpu_device pointer
 827  *
 828  * Set up the DMA engines and enable them.
 829  * Returns 0 for success, error for failure.
 830  */
 831 static int sdma_v5_2_start(struct amdgpu_device *adev)
 832 {
 833         int r = 0;
 834
 835         if (amdgpu_sriov_vf(adev)) {
 836                 sdma_v5_2_ctx_switch_enable(adev, false);
 837                 sdma_v5_2_enable(adev, false);
 838
 839                 /* set RB registers */
 840                 r = sdma_v5_2_gfx_resume(adev);
 841                 return r;
 842         }
 843
 844         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 845                 r = sdma_v5_2_load_microcode(adev);
 846                 if (r)
 847                         return r;
 848
 849                 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */
 850                 if (amdgpu_emu_mode == 1)
 851                         msleep(1000);
 852         }
 853
 854         sdma_v5_2_soft_reset(adev);
 855         /* unhalt the MEs */
 856         sdma_v5_2_enable(adev, true);
 857         /* enable sdma ring preemption */
 858         sdma_v5_2_ctx_switch_enable(adev, true);
 859
 860         /* start the gfx rings and rlc compute queues */
 861         r = sdma_v5_2_gfx_resume(adev);
 862         if (r)
 863                 return r;
 864         r = sdma_v5_2_rlc_resume(adev);
 865
 866         return r;
 867 }
 868
 869 /**
 870  * sdma_v5_2_ring_test_ring - simple async dma engine test
 871  *
 872  * @ring: amdgpu_ring structure holding ring information
 873  *
 874  * Test the DMA engine by writing using it to write an
 875  * value to memory.
 876  * Returns 0 for success, error for failure.
 877  */
 878 static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring)
 879 {
 880         struct amdgpu_device *adev = ring->adev;
 881         unsigned i;
 882         unsigned index;
 883         int r;
 884         u32 tmp;
 885         u64 gpu_addr;
 886
 887         r = amdgpu_device_wb_get(adev, &index);
 888         if (r) {
 889                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 890                 return r;
 891         }
 892
 893         gpu_addr = adev->wb.gpu_addr + (index * 4);
 894         tmp = 0xCAFEDEAD;
 895         adev->wb.wb[index] = cpu_to_le32(tmp);
 896
 897         r = amdgpu_ring_alloc(ring, 5);
 898         if (r) {
 899                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 900                 amdgpu_device_wb_free(adev, index);
 901                 return r;
 902         }
 903
 904         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 905                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 906         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 907         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 908         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 909         amdgpu_ring_write(ring, 0xDEADBEEF);
 910         amdgpu_ring_commit(ring);
 911
 912         for (i = 0; i < adev->usec_timeout; i++) {
 913                 tmp = le32_to_cpu(adev->wb.wb[index]);
 914                 if (tmp == 0xDEADBEEF)
 915                         break;
 916                 if (amdgpu_emu_mode == 1)
 917                         msleep(1);
 918                 else
 919                         udelay(1);
 920         }
 921
 922         if (i >= adev->usec_timeout)
 923                 r = -ETIMEDOUT;
 924
 925         amdgpu_device_wb_free(adev, index);
 926
 927         return r;
 928 }
 929
 930 /**
 931  * sdma_v5_2_ring_test_ib - test an IB on the DMA engine
 932  *
 933  * @ring: amdgpu_ring structure holding ring information
 934  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
 935  *
 936  * Test a simple IB in the DMA ring.
 937  * Returns 0 on success, error on failure.
 938  */
 939 static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 940 {
 941         struct amdgpu_device *adev = ring->adev;
 942         struct amdgpu_ib ib;
 943         struct dma_fence *f = NULL;
 944         unsigned index;
 945         long r;
 946         u32 tmp = 0;
 947         u64 gpu_addr;
 948
 949         r = amdgpu_device_wb_get(adev, &index);
 950         if (r) {
 951                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 952                 return r;
 953         }
 954
 955         gpu_addr = adev->wb.gpu_addr + (index * 4);
 956         tmp = 0xCAFEDEAD;
 957         adev->wb.wb[index] = cpu_to_le32(tmp);
 958         memset(&ib, 0, sizeof(ib));
 959         r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
 960         if (r) {
 961                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 962                 goto err0;
 963         }
 964
 965         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 966                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 967         ib.ptr[1] = lower_32_bits(gpu_addr);
 968         ib.ptr[2] = upper_32_bits(gpu_addr);
 969         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
 970         ib.ptr[4] = 0xDEADBEEF;
 971         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 972         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 973         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 974         ib.length_dw = 8;
 975
 976         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 977         if (r)
 978                 goto err1;
 979
 980         r = dma_fence_wait_timeout(f, false, timeout);
 981         if (r == 0) {
 982                 DRM_ERROR("amdgpu: IB test timed out\n");
 983                 r = -ETIMEDOUT;
 984                 goto err1;
 985         } else if (r < 0) {
 986                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 987                 goto err1;
 988         }
 989         tmp = le32_to_cpu(adev->wb.wb[index]);
 990         if (tmp == 0xDEADBEEF)
 991                 r = 0;
 992         else
 993                 r = -EINVAL;
 994
 995 err1:
 996         amdgpu_ib_free(adev, &ib, NULL);
 997         dma_fence_put(f);
 998 err0:
 999         amdgpu_device_wb_free(adev, index);
1000         return r;
1001 }
1002
1003
1004 /**
1005  * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART
1006  *
1007  * @ib: indirect buffer to fill with commands
1008  * @pe: addr of the page entry
1009  * @src: src addr to copy from
1010  * @count: number of page entries to update
1011  *
1012  * Update PTEs by copying them from the GART using sDMA.
1013  */
1014 static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib,
1015                                   uint64_t pe, uint64_t src,
1016                                   unsigned count)
1017 {
1018         unsigned bytes = count * 8;
1019
1020         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1021                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1022         ib->ptr[ib->length_dw++] = bytes - 1;
1023         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1024         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1025         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1026         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1027         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1028
1029 }
1030
1031 /**
1032  * sdma_v5_2_vm_write_pte - update PTEs by writing them manually
1033  *
1034  * @ib: indirect buffer to fill with commands
1035  * @pe: addr of the page entry
1036  * @value: dst addr to write into pe
1037  * @count: number of page entries to update
1038  * @incr: increase next addr by incr bytes
1039  *
1040  * Update PTEs by writing them manually using sDMA.
1041  */
1042 static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1043                                    uint64_t value, unsigned count,
1044                                    uint32_t incr)
1045 {
1046         unsigned ndw = count * 2;
1047
1048         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1049                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1050         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1051         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1052         ib->ptr[ib->length_dw++] = ndw - 1;
1053         for (; ndw > 0; ndw -= 2) {
1054                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1055                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1056                 value += incr;
1057         }
1058 }
1059
1060 /**
1061  * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA
1062  *
1063  * @ib: indirect buffer to fill with commands
1064  * @pe: addr of the page entry
1065  * @addr: dst addr to write into pe
1066  * @count: number of page entries to update
1067  * @incr: increase next addr by incr bytes
1068  * @flags: access flags
1069  *
1070  * Update the page tables using sDMA.
1071  */
1072 static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib,
1073                                      uint64_t pe,
1074                                      uint64_t addr, unsigned count,
1075                                      uint32_t incr, uint64_t flags)
1076 {
1077         /* for physically contiguous pages (vram) */
1078         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1079         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1080         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1081         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1082         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1083         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1084         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1085         ib->ptr[ib->length_dw++] = incr; /* increment size */
1086         ib->ptr[ib->length_dw++] = 0;
1087         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1088 }
1089
1090 /**
1091  * sdma_v5_2_ring_pad_ib - pad the IB
1092  *
1093  * @ib: indirect buffer to fill with padding
1094  * @ring: amdgpu_ring structure holding ring information
1095  *
1096  * Pad the IB with NOPs to a boundary multiple of 8.
1097  */
1098 static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1099 {
1100         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1101         u32 pad_count;
1102         int i;
1103
1104         pad_count = (-ib->length_dw) & 0x7;
1105         for (i = 0; i < pad_count; i++)
1106                 if (sdma && sdma->burst_nop && (i == 0))
1107                         ib->ptr[ib->length_dw++] =
1108                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1109                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1110                 else
1111                         ib->ptr[ib->length_dw++] =
1112                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1113 }
1114
1115
1116 /**
1117  * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline
1118  *
1119  * @ring: amdgpu_ring pointer
1120  *
1121  * Make sure all previous operations are completed (CIK).
1122  */
1123 static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1124 {
1125         uint32_t seq = ring->fence_drv.sync_seq;
1126         uint64_t addr = ring->fence_drv.gpu_addr;
1127
1128         /* wait for idle */
1129         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1130                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1131                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1132                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1133         amdgpu_ring_write(ring, addr & 0xfffffffc);
1134         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1135         amdgpu_ring_write(ring, seq); /* reference */
1136         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1137         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1138                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1139 }
1140
1141
1142 /**
1143  * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA
1144  *
1145  * @ring: amdgpu_ring pointer
1146  * @vmid: vmid number to use
1147  * @pd_addr: address
1148  *
1149  * Update the page table base and flush the VM TLB
1150  * using sDMA.
1151  */
1152 static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
1153                                          unsigned vmid, uint64_t pd_addr)
1154 {
1155         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1156 }
1157
1158 static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring,
1159                                      uint32_t reg, uint32_t val)
1160 {
1161         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1162                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1163         amdgpu_ring_write(ring, reg);
1164         amdgpu_ring_write(ring, val);
1165 }
1166
1167 static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1168                                          uint32_t val, uint32_t mask)
1169 {
1170         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1171                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1172                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1173         amdgpu_ring_write(ring, reg << 2);
1174         amdgpu_ring_write(ring, 0);
1175         amdgpu_ring_write(ring, val); /* reference */
1176         amdgpu_ring_write(ring, mask); /* mask */
1177         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1178                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1179 }
1180
1181 static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1182                                                    uint32_t reg0, uint32_t reg1,
1183                                                    uint32_t ref, uint32_t mask)
1184 {
1185         amdgpu_ring_emit_wreg(ring, reg0, ref);
1186         /* wait for a cycle to reset vm_inv_eng*_ack */
1187         amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1188         amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1189 }
1190
1191 static int sdma_v5_2_early_init(void *handle)
1192 {
1193         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1194
1195         switch (adev->asic_type) {
1196         case CHIP_SIENNA_CICHLID:
1197                 adev->sdma.num_instances = 4;
1198                 break;
1199         case CHIP_NAVY_FLOUNDER:
1200         case CHIP_DIMGREY_CAVEFISH:
1201                 adev->sdma.num_instances = 2;
1202                 break;
1203         case CHIP_VANGOGH:
1204                 adev->sdma.num_instances = 1;
1205                 break;
1206         default:
1207                 break;
1208         }
1209
1210         sdma_v5_2_set_ring_funcs(adev);
1211         sdma_v5_2_set_buffer_funcs(adev);
1212         sdma_v5_2_set_vm_pte_funcs(adev);
1213         sdma_v5_2_set_irq_funcs(adev);
1214
1215         return 0;
1216 }
1217
1218 static unsigned sdma_v5_2_seq_to_irq_id(int seq_num)
1219 {
1220         switch (seq_num) {
1221         case 0:
1222                 return SOC15_IH_CLIENTID_SDMA0;
1223         case 1:
1224                 return SOC15_IH_CLIENTID_SDMA1;
1225         case 2:
1226                 return SOC15_IH_CLIENTID_SDMA2;
1227         case 3:
1228                 return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid;
1229         default:
1230                 break;
1231         }
1232         return -EINVAL;
1233 }
1234
1235 static unsigned sdma_v5_2_seq_to_trap_id(int seq_num)
1236 {
1237         switch (seq_num) {
1238         case 0:
1239                 return SDMA0_5_0__SRCID__SDMA_TRAP;
1240         case 1:
1241                 return SDMA1_5_0__SRCID__SDMA_TRAP;
1242         case 2:
1243                 return SDMA2_5_0__SRCID__SDMA_TRAP;
1244         case 3:
1245                 return SDMA3_5_0__SRCID__SDMA_TRAP;
1246         default:
1247                 break;
1248         }
1249         return -EINVAL;
1250 }
1251
1252 static int sdma_v5_2_sw_init(void *handle)
1253 {
1254         struct amdgpu_ring *ring;
1255         int r, i;
1256         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1257
1258         /* SDMA trap event */
1259         for (i = 0; i < adev->sdma.num_instances; i++) {
1260                 r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i),
1261                                       sdma_v5_2_seq_to_trap_id(i),
1262                                       &adev->sdma.trap_irq);
1263                 if (r)
1264                         return r;
1265         }
1266
1267         r = sdma_v5_2_init_microcode(adev);
1268         if (r) {
1269                 DRM_ERROR("Failed to load sdma firmware!\n");
1270                 return r;
1271         }
1272
1273         for (i = 0; i < adev->sdma.num_instances; i++) {
1274                 ring = &adev->sdma.instance[i].ring;
1275                 ring->ring_obj = NULL;
1276                 ring->use_doorbell = true;
1277                 ring->me = i;
1278
1279                 DRM_INFO("use_doorbell being set to: [%s]\n",
1280                                 ring->use_doorbell?"true":"false");
1281
1282                 ring->doorbell_index =
1283                         (adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset
1284
1285                 sprintf(ring->name, "sdma%d", i);
1286                 r = amdgpu_ring_init(adev, ring, 1024,
1287                                      &adev->sdma.trap_irq,
1288                                      AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1289                                      AMDGPU_RING_PRIO_DEFAULT);
1290                 if (r)
1291                         return r;
1292         }
1293
1294         return r;
1295 }
1296
1297 static int sdma_v5_2_sw_fini(void *handle)
1298 {
1299         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1300         int i;
1301
1302         for (i = 0; i < adev->sdma.num_instances; i++)
1303                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1304
1305         sdma_v5_2_destroy_inst_ctx(adev);
1306
1307         return 0;
1308 }
1309
1310 static int sdma_v5_2_hw_init(void *handle)
1311 {
1312         int r;
1313         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1314
1315         sdma_v5_2_init_golden_registers(adev);
1316
1317         r = sdma_v5_2_start(adev);
1318
1319         return r;
1320 }
1321
1322 static int sdma_v5_2_hw_fini(void *handle)
1323 {
1324         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1325
1326         if (amdgpu_sriov_vf(adev))
1327                 return 0;
1328
1329         sdma_v5_2_ctx_switch_enable(adev, false);
1330         sdma_v5_2_enable(adev, false);
1331
1332         return 0;
1333 }
1334
1335 static int sdma_v5_2_suspend(void *handle)
1336 {
1337         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1338
1339         return sdma_v5_2_hw_fini(adev);
1340 }
1341
1342 static int sdma_v5_2_resume(void *handle)
1343 {
1344         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1345
1346         return sdma_v5_2_hw_init(adev);
1347 }
1348
1349 static bool sdma_v5_2_is_idle(void *handle)
1350 {
1351         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1352         u32 i;
1353
1354         for (i = 0; i < adev->sdma.num_instances; i++) {
1355                 u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1356
1357                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1358                         return false;
1359         }
1360
1361         return true;
1362 }
1363
1364 static int sdma_v5_2_wait_for_idle(void *handle)
1365 {
1366         unsigned i;
1367         u32 sdma0, sdma1, sdma2, sdma3;
1368         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1369
1370         for (i = 0; i < adev->usec_timeout; i++) {
1371                 sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1372                 sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1373                 sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG));
1374                 sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG));
1375
1376                 if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK)
1377                         return 0;
1378                 udelay(1);
1379         }
1380         return -ETIMEDOUT;
1381 }
1382
1383 static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring)
1384 {
1385         int i, r = 0;
1386         struct amdgpu_device *adev = ring->adev;
1387         u32 index = 0;
1388         u64 sdma_gfx_preempt;
1389
1390         amdgpu_sdma_get_index_from_ring(ring, &index);
1391         sdma_gfx_preempt =
1392                 sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT);
1393
1394         /* assert preemption condition */
1395         amdgpu_ring_set_preempt_cond_exec(ring, false);
1396
1397         /* emit the trailing fence */
1398         ring->trail_seq += 1;
1399         amdgpu_ring_alloc(ring, 10);
1400         sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1401                                   ring->trail_seq, 0);
1402         amdgpu_ring_commit(ring);
1403
1404         /* assert IB preemption */
1405         WREG32(sdma_gfx_preempt, 1);
1406
1407         /* poll the trailing fence */
1408         for (i = 0; i < adev->usec_timeout; i++) {
1409                 if (ring->trail_seq ==
1410                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1411                         break;
1412                 udelay(1);
1413         }
1414
1415         if (i >= adev->usec_timeout) {
1416                 r = -EINVAL;
1417                 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1418         }
1419
1420         /* deassert IB preemption */
1421         WREG32(sdma_gfx_preempt, 0);
1422
1423         /* deassert the preemption condition */
1424         amdgpu_ring_set_preempt_cond_exec(ring, true);
1425         return r;
1426 }
1427
1428 static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev,
1429                                         struct amdgpu_irq_src *source,
1430                                         unsigned type,
1431                                         enum amdgpu_interrupt_state state)
1432 {
1433         u32 sdma_cntl;
1434
1435         u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL);
1436
1437         sdma_cntl = RREG32(reg_offset);
1438         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1439                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1440         WREG32(reg_offset, sdma_cntl);
1441
1442         return 0;
1443 }
1444
1445 static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev,
1446                                       struct amdgpu_irq_src *source,
1447                                       struct amdgpu_iv_entry *entry)
1448 {
1449         DRM_DEBUG("IH: SDMA trap\n");
1450         switch (entry->client_id) {
1451         case SOC15_IH_CLIENTID_SDMA0:
1452                 switch (entry->ring_id) {
1453                 case 0:
1454                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1455                         break;
1456                 case 1:
1457                         /* XXX compute */
1458                         break;
1459                 case 2:
1460                         /* XXX compute */
1461                         break;
1462                 case 3:
1463                         /* XXX page queue*/
1464                         break;
1465                 }
1466                 break;
1467         case SOC15_IH_CLIENTID_SDMA1:
1468                 switch (entry->ring_id) {
1469                 case 0:
1470                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1471                         break;
1472                 case 1:
1473                         /* XXX compute */
1474                         break;
1475                 case 2:
1476                         /* XXX compute */
1477                         break;
1478                 case 3:
1479                         /* XXX page queue*/
1480                         break;
1481                 }
1482                 break;
1483         case SOC15_IH_CLIENTID_SDMA2:
1484                 switch (entry->ring_id) {
1485                 case 0:
1486                         amdgpu_fence_process(&adev->sdma.instance[2].ring);
1487                         break;
1488                 case 1:
1489                         /* XXX compute */
1490                         break;
1491                 case 2:
1492                         /* XXX compute */
1493                         break;
1494                 case 3:
1495                         /* XXX page queue*/
1496                         break;
1497                 }
1498                 break;
1499         case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid:
1500                 switch (entry->ring_id) {
1501                 case 0:
1502                         amdgpu_fence_process(&adev->sdma.instance[3].ring);
1503                         break;
1504                 case 1:
1505                         /* XXX compute */
1506                         break;
1507                 case 2:
1508                         /* XXX compute */
1509                         break;
1510                 case 3:
1511                         /* XXX page queue*/
1512                         break;
1513                 }
1514                 break;
1515         }
1516         return 0;
1517 }
1518
1519 static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev,
1520                                               struct amdgpu_irq_src *source,
1521                                               struct amdgpu_iv_entry *entry)
1522 {
1523         return 0;
1524 }
1525
1526 static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1527                                                        bool enable)
1528 {
1529         uint32_t data, def;
1530         int i;
1531
1532         for (i = 0; i < adev->sdma.num_instances; i++) {
1533                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1534                         /* Enable sdma clock gating */
1535                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1536                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1537                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1538                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1539                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1540                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1541                                   SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1542                         if (def != data)
1543                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1544                 } else {
1545                         /* Disable sdma clock gating */
1546                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1547                         data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1548                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1549                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1550                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1551                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1552                                  SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1553                         if (def != data)
1554                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1555                 }
1556         }
1557 }
1558
1559 static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1560                                                       bool enable)
1561 {
1562         uint32_t data, def;
1563         int i;
1564
1565         for (i = 0; i < adev->sdma.num_instances; i++) {
1566                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1567                         /* Enable sdma mem light sleep */
1568                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1569                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1570                         if (def != data)
1571                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1572
1573                 } else {
1574                         /* Disable sdma mem light sleep */
1575                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1576                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1577                         if (def != data)
1578                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1579
1580                 }
1581         }
1582 }
1583
1584 static int sdma_v5_2_set_clockgating_state(void *handle,
1585                                            enum amd_clockgating_state state)
1586 {
1587         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1588
1589         if (amdgpu_sriov_vf(adev))
1590                 return 0;
1591
1592         switch (adev->asic_type) {
1593         case CHIP_SIENNA_CICHLID:
1594         case CHIP_NAVY_FLOUNDER:
1595         case CHIP_VANGOGH:
1596         case CHIP_DIMGREY_CAVEFISH:
1597                 sdma_v5_2_update_medium_grain_clock_gating(adev,
1598                                 state == AMD_CG_STATE_GATE ? true : false);
1599                 sdma_v5_2_update_medium_grain_light_sleep(adev,
1600                                 state == AMD_CG_STATE_GATE ? true : false);
1601                 break;
1602         default:
1603                 break;
1604         }
1605
1606         return 0;
1607 }
1608
1609 static int sdma_v5_2_set_powergating_state(void *handle,
1610                                           enum amd_powergating_state state)
1611 {
1612         return 0;
1613 }
1614
1615 static void sdma_v5_2_get_clockgating_state(void *handle, u32 *flags)
1616 {
1617         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1618         int data;
1619
1620         if (amdgpu_sriov_vf(adev))
1621                 *flags = 0;
1622
1623         /* AMD_CG_SUPPORT_SDMA_LS */
1624         data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1625         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1626                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1627 }
1628
1629 const struct amd_ip_funcs sdma_v5_2_ip_funcs = {
1630         .name = "sdma_v5_2",
1631         .early_init = sdma_v5_2_early_init,
1632         .late_init = NULL,
1633         .sw_init = sdma_v5_2_sw_init,
1634         .sw_fini = sdma_v5_2_sw_fini,
1635         .hw_init = sdma_v5_2_hw_init,
1636         .hw_fini = sdma_v5_2_hw_fini,
1637         .suspend = sdma_v5_2_suspend,
1638         .resume = sdma_v5_2_resume,
1639         .is_idle = sdma_v5_2_is_idle,
1640         .wait_for_idle = sdma_v5_2_wait_for_idle,
1641         .soft_reset = sdma_v5_2_soft_reset,
1642         .set_clockgating_state = sdma_v5_2_set_clockgating_state,
1643         .set_powergating_state = sdma_v5_2_set_powergating_state,
1644         .get_clockgating_state = sdma_v5_2_get_clockgating_state,
1645 };
1646
1647 static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {
1648         .type = AMDGPU_RING_TYPE_SDMA,
1649         .align_mask = 0xf,
1650         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1651         .support_64bit_ptrs = true,
1652         .vmhub = AMDGPU_GFXHUB_0,
1653         .get_rptr = sdma_v5_2_ring_get_rptr,
1654         .get_wptr = sdma_v5_2_ring_get_wptr,
1655         .set_wptr = sdma_v5_2_ring_set_wptr,
1656         .emit_frame_size =
1657                 5 + /* sdma_v5_2_ring_init_cond_exec */
1658                 6 + /* sdma_v5_2_ring_emit_hdp_flush */
1659                 3 + /* hdp_invalidate */
1660                 6 + /* sdma_v5_2_ring_emit_pipeline_sync */
1661                 /* sdma_v5_2_ring_emit_vm_flush */
1662                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1663                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1664                 10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */
1665         .emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */
1666         .emit_ib = sdma_v5_2_ring_emit_ib,
1667         .emit_fence = sdma_v5_2_ring_emit_fence,
1668         .emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync,
1669         .emit_vm_flush = sdma_v5_2_ring_emit_vm_flush,
1670         .emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush,
1671         .test_ring = sdma_v5_2_ring_test_ring,
1672         .test_ib = sdma_v5_2_ring_test_ib,
1673         .insert_nop = sdma_v5_2_ring_insert_nop,
1674         .pad_ib = sdma_v5_2_ring_pad_ib,
1675         .emit_wreg = sdma_v5_2_ring_emit_wreg,
1676         .emit_reg_wait = sdma_v5_2_ring_emit_reg_wait,
1677         .emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait,
1678         .init_cond_exec = sdma_v5_2_ring_init_cond_exec,
1679         .patch_cond_exec = sdma_v5_2_ring_patch_cond_exec,
1680         .preempt_ib = sdma_v5_2_ring_preempt_ib,
1681 };
1682
1683 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev)
1684 {
1685         int i;
1686
1687         for (i = 0; i < adev->sdma.num_instances; i++) {
1688                 adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs;
1689                 adev->sdma.instance[i].ring.me = i;
1690         }
1691 }
1692
1693 static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = {
1694         .set = sdma_v5_2_set_trap_irq_state,
1695         .process = sdma_v5_2_process_trap_irq,
1696 };
1697
1698 static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = {
1699         .process = sdma_v5_2_process_illegal_inst_irq,
1700 };
1701
1702 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev)
1703 {
1704         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1705                                         adev->sdma.num_instances;
1706         adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs;
1707         adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs;
1708 }
1709
1710 /**
1711  * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine
1712  *
1713  * @ib: indirect buffer to copy to
1714  * @src_offset: src GPU address
1715  * @dst_offset: dst GPU address
1716  * @byte_count: number of bytes to xfer
1717  * @tmz: if a secure copy should be used
1718  *
1719  * Copy GPU buffers using the DMA engine.
1720  * Used by the amdgpu ttm implementation to move pages if
1721  * registered as the asic copy callback.
1722  */
1723 static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib,
1724                                        uint64_t src_offset,
1725                                        uint64_t dst_offset,
1726                                        uint32_t byte_count,
1727                                        bool tmz)
1728 {
1729         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1730                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1731                 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1732         ib->ptr[ib->length_dw++] = byte_count - 1;
1733         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1734         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1735         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1736         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1737         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1738 }
1739
1740 /**
1741  * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine
1742  *
1743  * @ib: indirect buffer to fill
1744  * @src_data: value to write to buffer
1745  * @dst_offset: dst GPU address
1746  * @byte_count: number of bytes to xfer
1747  *
1748  * Fill GPU buffers using the DMA engine.
1749  */
1750 static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
1751                                        uint32_t src_data,
1752                                        uint64_t dst_offset,
1753                                        uint32_t byte_count)
1754 {
1755         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1756         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1757         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1758         ib->ptr[ib->length_dw++] = src_data;
1759         ib->ptr[ib->length_dw++] = byte_count - 1;
1760 }
1761
1762 static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = {
1763         .copy_max_bytes = 0x400000,
1764         .copy_num_dw = 7,
1765         .emit_copy_buffer = sdma_v5_2_emit_copy_buffer,
1766
1767         .fill_max_bytes = 0x400000,
1768         .fill_num_dw = 5,
1769         .emit_fill_buffer = sdma_v5_2_emit_fill_buffer,
1770 };
1771
1772 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev)
1773 {
1774         if (adev->mman.buffer_funcs == NULL) {
1775                 adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs;
1776                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1777         }
1778 }
1779
1780 static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = {
1781         .copy_pte_num_dw = 7,
1782         .copy_pte = sdma_v5_2_vm_copy_pte,
1783         .write_pte = sdma_v5_2_vm_write_pte,
1784         .set_pte_pde = sdma_v5_2_vm_set_pte_pde,
1785 };
1786
1787 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev)
1788 {
1789         unsigned i;
1790
1791         if (adev->vm_manager.vm_pte_funcs == NULL) {
1792                 adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs;
1793                 for (i = 0; i < adev->sdma.num_instances; i++) {
1794                         adev->vm_manager.vm_pte_scheds[i] =
1795                                 &adev->sdma.instance[i].ring.sched;
1796                 }
1797                 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1798         }
1799 }
1800
1801 const struct amdgpu_ip_block_version sdma_v5_2_ip_block = {
1802         .type = AMD_IP_BLOCK_TYPE_SDMA,
1803         .major = 5,
1804         .minor = 2,
1805         .rev = 0,
1806         .funcs = &sdma_v5_2_ip_funcs,
1807 };