drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_ucode.h"
  31 #include "amdgpu_trace.h"
  32
  33 #include "gc/gc_10_3_0_offset.h"
  34 #include "gc/gc_10_3_0_sh_mask.h"
  35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
  36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
  37 #include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h"
  38 #include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h"
  39
  40 #include "soc15_common.h"
  41 #include "soc15.h"
  42 #include "navi10_sdma_pkt_open.h"
  43 #include "nbio_v2_3.h"
  44 #include "sdma_common.h"
  45 #include "sdma_v5_2.h"
  46
  47 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin");
  48 MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin");
  49 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin");
  50
  51 MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin");
  52
  53 #define SDMA1_REG_OFFSET 0x600
  54 #define SDMA3_REG_OFFSET 0x400
  55 #define SDMA0_HYP_DEC_REG_START 0x5880
  56 #define SDMA0_HYP_DEC_REG_END 0x5893
  57 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
  58
  59 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev);
  60 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev);
  61 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev);
  62 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev);
  63
  64 static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
  65 {
  66         u32 base;
  67
  68         if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
  69             internal_offset <= SDMA0_HYP_DEC_REG_END) {
  70                 base = adev->reg_offset[GC_HWIP][0][1];
  71                 if (instance != 0)
  72                         internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
  73         } else {
  74                 if (instance < 2) {
  75                         base = adev->reg_offset[GC_HWIP][0][0];
  76                         if (instance == 1)
  77                                 internal_offset += SDMA1_REG_OFFSET;
  78                 } else {
  79                         base = adev->reg_offset[GC_HWIP][0][2];
  80                         if (instance == 3)
  81                                 internal_offset += SDMA3_REG_OFFSET;
  82                 }
  83         }
  84
  85         return base + internal_offset;
  86 }
  87
  88 static void sdma_v5_2_init_golden_registers(struct amdgpu_device *adev)
  89 {
  90         switch (adev->asic_type) {
  91         case CHIP_SIENNA_CICHLID:
  92         case CHIP_NAVY_FLOUNDER:
  93         case CHIP_VANGOGH:
  94         case CHIP_DIMGREY_CAVEFISH:
  95                 break;
  96         default:
  97                 break;
  98         }
  99 }
 100
 101 static int sdma_v5_2_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
 102 {
 103         int err = 0;
 104         const struct sdma_firmware_header_v1_0 *hdr;
 105
 106         err = amdgpu_ucode_validate(sdma_inst->fw);
 107         if (err)
 108                 return err;
 109
 110         hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
 111         sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
 112         sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
 113
 114         if (sdma_inst->feature_version >= 20)
 115                 sdma_inst->burst_nop = true;
 116
 117         return 0;
 118 }
 119
 120 static void sdma_v5_2_destroy_inst_ctx(struct amdgpu_device *adev)
 121 {
 122         int i;
 123
 124         for (i = 0; i < adev->sdma.num_instances; i++) {
 125                 release_firmware(adev->sdma.instance[i].fw);
 126                 adev->sdma.instance[i].fw = NULL;
 127
 128                 if (adev->asic_type == CHIP_SIENNA_CICHLID)
 129                         break;
 130         }
 131
 132         memset((void *)adev->sdma.instance, 0,
 133                sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
 134 }
 135
 136 /**
 137  * sdma_v5_2_init_microcode - load ucode images from disk
 138  *
 139  * @adev: amdgpu_device pointer
 140  *
 141  * Use the firmware interface to load the ucode images into
 142  * the driver (not loaded into hw).
 143  * Returns 0 on success, error on failure.
 144  */
 145
 146 // emulation only, won't work on real chip
 147 // navi10 real chip need to use PSP to load firmware
 148 static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
 149 {
 150         const char *chip_name;
 151         char fw_name[40];
 152         int err = 0, i;
 153         struct amdgpu_firmware_info *info = NULL;
 154         const struct common_firmware_header *header = NULL;
 155
 156         DRM_DEBUG("\n");
 157
 158         switch (adev->asic_type) {
 159         case CHIP_SIENNA_CICHLID:
 160                 chip_name = "sienna_cichlid";
 161                 break;
 162         case CHIP_NAVY_FLOUNDER:
 163                 chip_name = "navy_flounder";
 164                 break;
 165         case CHIP_VANGOGH:
 166                 chip_name = "vangogh";
 167                 break;
 168         case CHIP_DIMGREY_CAVEFISH:
 169                 chip_name = "dimgrey_cavefish";
 170                 break;
 171         default:
 172                 BUG();
 173         }
 174
 175         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 176
 177         err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);
 178         if (err)
 179                 goto out;
 180
 181         err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]);
 182         if (err)
 183                 goto out;
 184
 185         for (i = 1; i < adev->sdma.num_instances; i++) {
 186                 if (adev->asic_type >= CHIP_SIENNA_CICHLID &&
 187                     adev->asic_type <= CHIP_DIMGREY_CAVEFISH) {
 188                         memcpy((void *)&adev->sdma.instance[i],
 189                                (void *)&adev->sdma.instance[0],
 190                                sizeof(struct amdgpu_sdma_instance));
 191                 } else {
 192                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i);
 193                         err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 194                         if (err)
 195                                 goto out;
 196
 197                         err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[i]);
 198                         if (err)
 199                                 goto out;
 200                 }
 201         }
 202
 203         DRM_DEBUG("psp_load == '%s'\n",
 204                   adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
 205
 206         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 207                 for (i = 0; i < adev->sdma.num_instances; i++) {
 208                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 209                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 210                         info->fw = adev->sdma.instance[i].fw;
 211                         header = (const struct common_firmware_header *)info->fw->data;
 212                         adev->firmware.fw_size +=
 213                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 214                 }
 215         }
 216
 217 out:
 218         if (err) {
 219                 DRM_ERROR("sdma_v5_2: Failed to load firmware \"%s\"\n", fw_name);
 220                 sdma_v5_2_destroy_inst_ctx(adev);
 221         }
 222         return err;
 223 }
 224
 225 static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring)
 226 {
 227         unsigned ret;
 228
 229         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
 230         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
 231         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
 232         amdgpu_ring_write(ring, 1);
 233         ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
 234         amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
 235
 236         return ret;
 237 }
 238
 239 static void sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring *ring,
 240                                            unsigned offset)
 241 {
 242         unsigned cur;
 243
 244         BUG_ON(offset > ring->buf_mask);
 245         BUG_ON(ring->ring[offset] != 0x55aa55aa);
 246
 247         cur = (ring->wptr - 1) & ring->buf_mask;
 248         if (cur > offset)
 249                 ring->ring[offset] = cur - offset;
 250         else
 251                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
 252 }
 253
 254 /**
 255  * sdma_v5_2_ring_get_rptr - get the current read pointer
 256  *
 257  * @ring: amdgpu ring pointer
 258  *
 259  * Get the current rptr from the hardware (NAVI10+).
 260  */
 261 static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring)
 262 {
 263         u64 *rptr;
 264
 265         /* XXX check if swapping is necessary on BE */
 266         rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
 267
 268         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 269         return ((*rptr) >> 2);
 270 }
 271
 272 /**
 273  * sdma_v5_2_ring_get_wptr - get the current write pointer
 274  *
 275  * @ring: amdgpu ring pointer
 276  *
 277  * Get the current wptr from the hardware (NAVI10+).
 278  */
 279 static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring)
 280 {
 281         struct amdgpu_device *adev = ring->adev;
 282         u64 wptr;
 283
 284         if (ring->use_doorbell) {
 285                 /* XXX check if swapping is necessary on BE */
 286                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 287                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 288         } else {
 289                 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
 290                 wptr = wptr << 32;
 291                 wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
 292                 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
 293         }
 294
 295         return wptr >> 2;
 296 }
 297
 298 /**
 299  * sdma_v5_2_ring_set_wptr - commit the write pointer
 300  *
 301  * @ring: amdgpu ring pointer
 302  *
 303  * Write the wptr back to the hardware (NAVI10+).
 304  */
 305 static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring)
 306 {
 307         struct amdgpu_device *adev = ring->adev;
 308
 309         DRM_DEBUG("Setting write pointer\n");
 310         if (ring->use_doorbell) {
 311                 DRM_DEBUG("Using doorbell -- "
 312                                 "wptr_offs == 0x%08x "
 313                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 314                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 315                                 ring->wptr_offs,
 316                                 lower_32_bits(ring->wptr << 2),
 317                                 upper_32_bits(ring->wptr << 2));
 318                 /* XXX check if swapping is necessary on BE */
 319                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
 320                 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
 321                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 322                                 ring->doorbell_index, ring->wptr << 2);
 323                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 324         } else {
 325                 DRM_DEBUG("Not using doorbell -- "
 326                                 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 327                                 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 328                                 ring->me,
 329                                 lower_32_bits(ring->wptr << 2),
 330                                 ring->me,
 331                                 upper_32_bits(ring->wptr << 2));
 332                 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
 333                         lower_32_bits(ring->wptr << 2));
 334                 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
 335                         upper_32_bits(ring->wptr << 2));
 336         }
 337 }
 338
 339 static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 340 {
 341         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 342         int i;
 343
 344         for (i = 0; i < count; i++)
 345                 if (sdma && sdma->burst_nop && (i == 0))
 346                         amdgpu_ring_write(ring, ring->funcs->nop |
 347                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 348                 else
 349                         amdgpu_ring_write(ring, ring->funcs->nop);
 350 }
 351
 352 /**
 353  * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine
 354  *
 355  * @ring: amdgpu ring pointer
 356  * @job: job to retrieve vmid from
 357  * @ib: IB object to schedule
 358  * @flags: unused
 359  *
 360  * Schedule an IB in the DMA ring.
 361  */
 362 static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring,
 363                                    struct amdgpu_job *job,
 364                                    struct amdgpu_ib *ib,
 365                                    uint32_t flags)
 366 {
 367         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 368         uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
 369
 370         /* An IB packet must end on a 8 DW boundary--the next dword
 371          * must be on a 8-dword boundary. Our IB packet below is 6
 372          * dwords long, thus add x number of NOPs, such that, in
 373          * modular arithmetic,
 374          * wptr + 6 + x = 8k, k >= 0, which in C is,
 375          * (wptr + 6 + x) % 8 = 0.
 376          * The expression below, is a solution of x.
 377          */
 378         sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 379
 380         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 381                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 382         /* base must be 32 byte aligned */
 383         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 384         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 385         amdgpu_ring_write(ring, ib->length_dw);
 386         amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
 387         amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
 388 }
 389
 390 /**
 391  * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 392  *
 393  * @ring: amdgpu ring pointer
 394  *
 395  * Emit an hdp flush packet on the requested DMA ring.
 396  */
 397 static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 398 {
 399         struct amdgpu_device *adev = ring->adev;
 400         u32 ref_and_mask = 0;
 401         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 402
 403         ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
 404
 405         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 406                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 407                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 408         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
 409         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
 410         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 411         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 412         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 413                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 414 }
 415
 416 /**
 417  * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring
 418  *
 419  * @ring: amdgpu ring pointer
 420  * @addr: address
 421  * @seq: sequence number
 422  * @flags: fence related flags
 423  *
 424  * Add a DMA fence packet to the ring to write
 425  * the fence seq number and DMA trap packet to generate
 426  * an interrupt if needed.
 427  */
 428 static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 429                                       unsigned flags)
 430 {
 431         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 432         /* write the fence */
 433         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 434                           SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
 435         /* zero in first two bits */
 436         BUG_ON(addr & 0x3);
 437         amdgpu_ring_write(ring, lower_32_bits(addr));
 438         amdgpu_ring_write(ring, upper_32_bits(addr));
 439         amdgpu_ring_write(ring, lower_32_bits(seq));
 440
 441         /* optionally write high bits as well */
 442         if (write64bit) {
 443                 addr += 4;
 444                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 445                                   SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
 446                 /* zero in first two bits */
 447                 BUG_ON(addr & 0x3);
 448                 amdgpu_ring_write(ring, lower_32_bits(addr));
 449                 amdgpu_ring_write(ring, upper_32_bits(addr));
 450                 amdgpu_ring_write(ring, upper_32_bits(seq));
 451         }
 452
 453         if (flags & AMDGPU_FENCE_FLAG_INT) {
 454                 /* generate an interrupt */
 455                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 456                 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 457         }
 458 }
 459
 460
 461 /**
 462  * sdma_v5_2_gfx_stop - stop the gfx async dma engines
 463  *
 464  * @adev: amdgpu_device pointer
 465  *
 466  * Stop the gfx async dma ring buffers.
 467  */
 468 static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev)
 469 {
 470         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 471         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 472         struct amdgpu_ring *sdma2 = &adev->sdma.instance[2].ring;
 473         struct amdgpu_ring *sdma3 = &adev->sdma.instance[3].ring;
 474         u32 rb_cntl, ib_cntl;
 475         int i;
 476
 477         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 478             (adev->mman.buffer_funcs_ring == sdma1) ||
 479             (adev->mman.buffer_funcs_ring == sdma2) ||
 480             (adev->mman.buffer_funcs_ring == sdma3))
 481                 amdgpu_ttm_set_buffer_funcs_status(adev, false);
 482
 483         for (i = 0; i < adev->sdma.num_instances; i++) {
 484                 rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 485                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 486                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 487                 ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 488                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 489                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 490         }
 491
 492         sdma0->sched.ready = false;
 493         sdma1->sched.ready = false;
 494         sdma2->sched.ready = false;
 495         sdma3->sched.ready = false;
 496 }
 497
 498 /**
 499  * sdma_v5_2_rlc_stop - stop the compute async dma engines
 500  *
 501  * @adev: amdgpu_device pointer
 502  *
 503  * Stop the compute async dma queues.
 504  */
 505 static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev)
 506 {
 507         /* XXX todo */
 508 }
 509
 510 /**
 511  * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
 512  *
 513  * @adev: amdgpu_device pointer
 514  * @enable: enable/disable the DMA MEs context switch.
 515  *
 516  * Halt or unhalt the async dma engines context switch.
 517  */
 518 static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 519 {
 520         u32 f32_cntl, phase_quantum = 0;
 521         int i;
 522
 523         if (amdgpu_sdma_phase_quantum) {
 524                 unsigned value = amdgpu_sdma_phase_quantum;
 525                 unsigned unit = 0;
 526
 527                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 528                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 529                         value = (value + 1) >> 1;
 530                         unit++;
 531                 }
 532                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 533                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 534                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 535                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 536                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 537                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 538                         WARN_ONCE(1,
 539                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 540                                   value << unit);
 541                 }
 542                 phase_quantum =
 543                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 544                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 545         }
 546
 547         for (i = 0; i < adev->sdma.num_instances; i++) {
 548                 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
 549                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 550                                 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 551                 if (enable && amdgpu_sdma_phase_quantum) {
 552                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
 553                                phase_quantum);
 554                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
 555                                phase_quantum);
 556                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
 557                                phase_quantum);
 558                 }
 559                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
 560         }
 561
 562 }
 563
 564 /**
 565  * sdma_v5_2_enable - stop the async dma engines
 566  *
 567  * @adev: amdgpu_device pointer
 568  * @enable: enable/disable the DMA MEs.
 569  *
 570  * Halt or unhalt the async dma engines.
 571  */
 572 static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable)
 573 {
 574         u32 f32_cntl;
 575         int i;
 576
 577         if (!enable) {
 578                 sdma_v5_2_gfx_stop(adev);
 579                 sdma_v5_2_rlc_stop(adev);
 580         }
 581
 582         for (i = 0; i < adev->sdma.num_instances; i++) {
 583                 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 584                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 585                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
 586         }
 587 }
 588
 589 /**
 590  * sdma_v5_2_gfx_resume - setup and start the async dma engines
 591  *
 592  * @adev: amdgpu_device pointer
 593  *
 594  * Set up the gfx DMA ring buffers and enable them.
 595  * Returns 0 for success, error for failure.
 596  */
 597 static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
 598 {
 599         struct amdgpu_ring *ring;
 600         u32 rb_cntl, ib_cntl;
 601         u32 rb_bufsz;
 602         u32 wb_offset;
 603         u32 doorbell;
 604         u32 doorbell_offset;
 605         u32 temp;
 606         u32 wptr_poll_cntl;
 607         u64 wptr_gpu_addr;
 608         int i, r;
 609
 610         for (i = 0; i < adev->sdma.num_instances; i++) {
 611                 ring = &adev->sdma.instance[i].ring;
 612                 wb_offset = (ring->rptr_offs * 4);
 613
 614                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 615
 616                 /* Set ring buffer size in dwords */
 617                 rb_bufsz = order_base_2(ring->ring_size / 4);
 618                 rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 619                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 620 #ifdef __BIG_ENDIAN
 621                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 622                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 623                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 624 #endif
 625                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 626
 627                 /* Initialize the ring buffer's read and write pointers */
 628                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
 629                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
 630                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
 631                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 632
 633                 /* setup the wptr shadow polling */
 634                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 635                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
 636                        lower_32_bits(wptr_gpu_addr));
 637                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
 638                        upper_32_bits(wptr_gpu_addr));
 639                 wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i,
 640                                                          mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 641                 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 642                                                SDMA0_GFX_RB_WPTR_POLL_CNTL,
 643                                                F32_POLL_ENABLE, 1);
 644                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
 645                        wptr_poll_cntl);
 646
 647                 /* set the wb address whether it's enabled or not */
 648                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
 649                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 650                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
 651                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 652
 653                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 654
 655                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
 656                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
 657
 658                 ring->wptr = 0;
 659
 660                 /* before programing wptr to a less value, need set minor_ptr_update first */
 661                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
 662
 663                 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 664                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
 665                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
 666                 }
 667
 668                 doorbell = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
 669                 doorbell_offset = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
 670
 671                 if (ring->use_doorbell) {
 672                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 673                         doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
 674                                         OFFSET, ring->doorbell_index);
 675                 } else {
 676                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 677                 }
 678                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
 679                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
 680
 681                 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 682                                                       ring->doorbell_index,
 683                                                       adev->doorbell_index.sdma_doorbell_range);
 684
 685                 if (amdgpu_sriov_vf(adev))
 686                         sdma_v5_2_ring_set_wptr(ring);
 687
 688                 /* set minor_ptr_update to 0 after wptr programed */
 689                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
 690
 691                 /* set utc l1 enable flag always to 1 */
 692                 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
 693                 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
 694
 695                 /* enable MCBP */
 696                 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
 697                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
 698
 699                 /* Set up RESP_MODE to non-copy addresses */
 700                 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
 701                 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
 702                 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
 703                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
 704
 705                 /* program default cache read and write policy */
 706                 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
 707                 /* clean read policy and write policy bits */
 708                 temp &= 0xFF0FFF;
 709                 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
 710                          (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
 711                          SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
 712                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
 713
 714                 if (!amdgpu_sriov_vf(adev)) {
 715                         /* unhalt engine */
 716                         temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 717                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 718                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
 719                 }
 720
 721                 /* enable DMA RB */
 722                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 723                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 724
 725                 ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 726                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 727 #ifdef __BIG_ENDIAN
 728                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 729 #endif
 730                 /* enable DMA IBs */
 731                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 732
 733                 ring->sched.ready = true;
 734
 735                 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
 736                         sdma_v5_2_ctx_switch_enable(adev, true);
 737                         sdma_v5_2_enable(adev, true);
 738                 }
 739
 740                 r = amdgpu_ring_test_ring(ring);
 741                 if (r) {
 742                         ring->sched.ready = false;
 743                         return r;
 744                 }
 745
 746                 if (adev->mman.buffer_funcs_ring == ring)
 747                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 748         }
 749
 750         return 0;
 751 }
 752
 753 /**
 754  * sdma_v5_2_rlc_resume - setup and start the async dma engines
 755  *
 756  * @adev: amdgpu_device pointer
 757  *
 758  * Set up the compute DMA queues and enable them.
 759  * Returns 0 for success, error for failure.
 760  */
 761 static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev)
 762 {
 763         return 0;
 764 }
 765
 766 /**
 767  * sdma_v5_2_load_microcode - load the sDMA ME ucode
 768  *
 769  * @adev: amdgpu_device pointer
 770  *
 771  * Loads the sDMA0/1/2/3 ucode.
 772  * Returns 0 for success, -EINVAL if the ucode is not available.
 773  */
 774 static int sdma_v5_2_load_microcode(struct amdgpu_device *adev)
 775 {
 776         const struct sdma_firmware_header_v1_0 *hdr;
 777         const __le32 *fw_data;
 778         u32 fw_size;
 779         int i, j;
 780
 781         /* halt the MEs */
 782         sdma_v5_2_enable(adev, false);
 783
 784         for (i = 0; i < adev->sdma.num_instances; i++) {
 785                 if (!adev->sdma.instance[i].fw)
 786                         return -EINVAL;
 787
 788                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 789                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 790                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 791
 792                 fw_data = (const __le32 *)
 793                         (adev->sdma.instance[i].fw->data +
 794                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 795
 796                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
 797
 798                 for (j = 0; j < fw_size; j++) {
 799                         if (amdgpu_emu_mode == 1 && j % 500 == 0)
 800                                 msleep(1);
 801                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 802                 }
 803
 804                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
 805         }
 806
 807         return 0;
 808 }
 809
 810 /**
 811  * sdma_v5_2_start - setup and start the async dma engines
 812  *
 813  * @adev: amdgpu_device pointer
 814  *
 815  * Set up the DMA engines and enable them.
 816  * Returns 0 for success, error for failure.
 817  */
 818 static int sdma_v5_2_start(struct amdgpu_device *adev)
 819 {
 820         int r = 0;
 821
 822         if (amdgpu_sriov_vf(adev)) {
 823                 sdma_v5_2_ctx_switch_enable(adev, false);
 824                 sdma_v5_2_enable(adev, false);
 825
 826                 /* set RB registers */
 827                 r = sdma_v5_2_gfx_resume(adev);
 828                 return r;
 829         }
 830
 831         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 832                 r = sdma_v5_2_load_microcode(adev);
 833                 if (r)
 834                         return r;
 835
 836                 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */
 837                 if (amdgpu_emu_mode == 1)
 838                         msleep(1000);
 839         }
 840
 841         /* unhalt the MEs */
 842         sdma_v5_2_enable(adev, true);
 843         /* enable sdma ring preemption */
 844         sdma_v5_2_ctx_switch_enable(adev, true);
 845
 846         /* start the gfx rings and rlc compute queues */
 847         r = sdma_v5_2_gfx_resume(adev);
 848         if (r)
 849                 return r;
 850         r = sdma_v5_2_rlc_resume(adev);
 851
 852         return r;
 853 }
 854
 855 /**
 856  * sdma_v5_2_ring_test_ring - simple async dma engine test
 857  *
 858  * @ring: amdgpu_ring structure holding ring information
 859  *
 860  * Test the DMA engine by writing using it to write an
 861  * value to memory.
 862  * Returns 0 for success, error for failure.
 863  */
 864 static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring)
 865 {
 866         struct amdgpu_device *adev = ring->adev;
 867         unsigned i;
 868         unsigned index;
 869         int r;
 870         u32 tmp;
 871         u64 gpu_addr;
 872
 873         r = amdgpu_device_wb_get(adev, &index);
 874         if (r) {
 875                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 876                 return r;
 877         }
 878
 879         gpu_addr = adev->wb.gpu_addr + (index * 4);
 880         tmp = 0xCAFEDEAD;
 881         adev->wb.wb[index] = cpu_to_le32(tmp);
 882
 883         r = amdgpu_ring_alloc(ring, 5);
 884         if (r) {
 885                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 886                 amdgpu_device_wb_free(adev, index);
 887                 return r;
 888         }
 889
 890         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 891                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 892         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 893         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 894         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 895         amdgpu_ring_write(ring, 0xDEADBEEF);
 896         amdgpu_ring_commit(ring);
 897
 898         for (i = 0; i < adev->usec_timeout; i++) {
 899                 tmp = le32_to_cpu(adev->wb.wb[index]);
 900                 if (tmp == 0xDEADBEEF)
 901                         break;
 902                 if (amdgpu_emu_mode == 1)
 903                         msleep(1);
 904                 else
 905                         udelay(1);
 906         }
 907
 908         if (i >= adev->usec_timeout)
 909                 r = -ETIMEDOUT;
 910
 911         amdgpu_device_wb_free(adev, index);
 912
 913         return r;
 914 }
 915
 916 /**
 917  * sdma_v5_2_ring_test_ib - test an IB on the DMA engine
 918  *
 919  * @ring: amdgpu_ring structure holding ring information
 920  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
 921  *
 922  * Test a simple IB in the DMA ring.
 923  * Returns 0 on success, error on failure.
 924  */
 925 static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 926 {
 927         struct amdgpu_device *adev = ring->adev;
 928         struct amdgpu_ib ib;
 929         struct dma_fence *f = NULL;
 930         unsigned index;
 931         long r;
 932         u32 tmp = 0;
 933         u64 gpu_addr;
 934
 935         r = amdgpu_device_wb_get(adev, &index);
 936         if (r) {
 937                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 938                 return r;
 939         }
 940
 941         gpu_addr = adev->wb.gpu_addr + (index * 4);
 942         tmp = 0xCAFEDEAD;
 943         adev->wb.wb[index] = cpu_to_le32(tmp);
 944         memset(&ib, 0, sizeof(ib));
 945         r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
 946         if (r) {
 947                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 948                 goto err0;
 949         }
 950
 951         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 952                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 953         ib.ptr[1] = lower_32_bits(gpu_addr);
 954         ib.ptr[2] = upper_32_bits(gpu_addr);
 955         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
 956         ib.ptr[4] = 0xDEADBEEF;
 957         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 958         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 959         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 960         ib.length_dw = 8;
 961
 962         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 963         if (r)
 964                 goto err1;
 965
 966         r = dma_fence_wait_timeout(f, false, timeout);
 967         if (r == 0) {
 968                 DRM_ERROR("amdgpu: IB test timed out\n");
 969                 r = -ETIMEDOUT;
 970                 goto err1;
 971         } else if (r < 0) {
 972                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 973                 goto err1;
 974         }
 975         tmp = le32_to_cpu(adev->wb.wb[index]);
 976         if (tmp == 0xDEADBEEF)
 977                 r = 0;
 978         else
 979                 r = -EINVAL;
 980
 981 err1:
 982         amdgpu_ib_free(adev, &ib, NULL);
 983         dma_fence_put(f);
 984 err0:
 985         amdgpu_device_wb_free(adev, index);
 986         return r;
 987 }
 988
 989
 990 /**
 991  * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART
 992  *
 993  * @ib: indirect buffer to fill with commands
 994  * @pe: addr of the page entry
 995  * @src: src addr to copy from
 996  * @count: number of page entries to update
 997  *
 998  * Update PTEs by copying them from the GART using sDMA.
 999  */
1000 static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib,
1001                                   uint64_t pe, uint64_t src,
1002                                   unsigned count)
1003 {
1004         unsigned bytes = count * 8;
1005
1006         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1007                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1008         ib->ptr[ib->length_dw++] = bytes - 1;
1009         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1010         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1011         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1012         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1013         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1014
1015 }
1016
1017 /**
1018  * sdma_v5_2_vm_write_pte - update PTEs by writing them manually
1019  *
1020  * @ib: indirect buffer to fill with commands
1021  * @pe: addr of the page entry
1022  * @value: dst addr to write into pe
1023  * @count: number of page entries to update
1024  * @incr: increase next addr by incr bytes
1025  *
1026  * Update PTEs by writing them manually using sDMA.
1027  */
1028 static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1029                                    uint64_t value, unsigned count,
1030                                    uint32_t incr)
1031 {
1032         unsigned ndw = count * 2;
1033
1034         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1035                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1036         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1037         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1038         ib->ptr[ib->length_dw++] = ndw - 1;
1039         for (; ndw > 0; ndw -= 2) {
1040                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1041                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1042                 value += incr;
1043         }
1044 }
1045
1046 /**
1047  * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA
1048  *
1049  * @ib: indirect buffer to fill with commands
1050  * @pe: addr of the page entry
1051  * @addr: dst addr to write into pe
1052  * @count: number of page entries to update
1053  * @incr: increase next addr by incr bytes
1054  * @flags: access flags
1055  *
1056  * Update the page tables using sDMA.
1057  */
1058 static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib,
1059                                      uint64_t pe,
1060                                      uint64_t addr, unsigned count,
1061                                      uint32_t incr, uint64_t flags)
1062 {
1063         /* for physically contiguous pages (vram) */
1064         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1065         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1066         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1067         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1068         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1069         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1070         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1071         ib->ptr[ib->length_dw++] = incr; /* increment size */
1072         ib->ptr[ib->length_dw++] = 0;
1073         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1074 }
1075
1076 /**
1077  * sdma_v5_2_ring_pad_ib - pad the IB
1078  *
1079  * @ib: indirect buffer to fill with padding
1080  * @ring: amdgpu_ring structure holding ring information
1081  *
1082  * Pad the IB with NOPs to a boundary multiple of 8.
1083  */
1084 static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1085 {
1086         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1087         u32 pad_count;
1088         int i;
1089
1090         pad_count = (-ib->length_dw) & 0x7;
1091         for (i = 0; i < pad_count; i++)
1092                 if (sdma && sdma->burst_nop && (i == 0))
1093                         ib->ptr[ib->length_dw++] =
1094                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1095                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1096                 else
1097                         ib->ptr[ib->length_dw++] =
1098                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1099 }
1100
1101
1102 /**
1103  * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline
1104  *
1105  * @ring: amdgpu_ring pointer
1106  *
1107  * Make sure all previous operations are completed (CIK).
1108  */
1109 static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1110 {
1111         uint32_t seq = ring->fence_drv.sync_seq;
1112         uint64_t addr = ring->fence_drv.gpu_addr;
1113
1114         /* wait for idle */
1115         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1116                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1117                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1118                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1119         amdgpu_ring_write(ring, addr & 0xfffffffc);
1120         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1121         amdgpu_ring_write(ring, seq); /* reference */
1122         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1123         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1124                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1125 }
1126
1127
1128 /**
1129  * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA
1130  *
1131  * @ring: amdgpu_ring pointer
1132  * @vmid: vmid number to use
1133  * @pd_addr: address
1134  *
1135  * Update the page table base and flush the VM TLB
1136  * using sDMA.
1137  */
1138 static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
1139                                          unsigned vmid, uint64_t pd_addr)
1140 {
1141         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1142 }
1143
1144 static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring,
1145                                      uint32_t reg, uint32_t val)
1146 {
1147         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1148                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1149         amdgpu_ring_write(ring, reg);
1150         amdgpu_ring_write(ring, val);
1151 }
1152
1153 static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1154                                          uint32_t val, uint32_t mask)
1155 {
1156         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1157                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1158                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1159         amdgpu_ring_write(ring, reg << 2);
1160         amdgpu_ring_write(ring, 0);
1161         amdgpu_ring_write(ring, val); /* reference */
1162         amdgpu_ring_write(ring, mask); /* mask */
1163         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1164                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1165 }
1166
1167 static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1168                                                    uint32_t reg0, uint32_t reg1,
1169                                                    uint32_t ref, uint32_t mask)
1170 {
1171         amdgpu_ring_emit_wreg(ring, reg0, ref);
1172         /* wait for a cycle to reset vm_inv_eng*_ack */
1173         amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1174         amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1175 }
1176
1177 static int sdma_v5_2_early_init(void *handle)
1178 {
1179         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1180
1181         switch (adev->asic_type) {
1182         case CHIP_SIENNA_CICHLID:
1183                 adev->sdma.num_instances = 4;
1184                 break;
1185         case CHIP_NAVY_FLOUNDER:
1186         case CHIP_DIMGREY_CAVEFISH:
1187                 adev->sdma.num_instances = 2;
1188                 break;
1189         case CHIP_VANGOGH:
1190                 adev->sdma.num_instances = 1;
1191                 break;
1192         default:
1193                 break;
1194         }
1195
1196         sdma_v5_2_set_ring_funcs(adev);
1197         sdma_v5_2_set_buffer_funcs(adev);
1198         sdma_v5_2_set_vm_pte_funcs(adev);
1199         sdma_v5_2_set_irq_funcs(adev);
1200
1201         return 0;
1202 }
1203
1204 static unsigned sdma_v5_2_seq_to_irq_id(int seq_num)
1205 {
1206         switch (seq_num) {
1207         case 0:
1208                 return SOC15_IH_CLIENTID_SDMA0;
1209         case 1:
1210                 return SOC15_IH_CLIENTID_SDMA1;
1211         case 2:
1212                 return SOC15_IH_CLIENTID_SDMA2;
1213         case 3:
1214                 return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid;
1215         default:
1216                 break;
1217         }
1218         return -EINVAL;
1219 }
1220
1221 static unsigned sdma_v5_2_seq_to_trap_id(int seq_num)
1222 {
1223         switch (seq_num) {
1224         case 0:
1225                 return SDMA0_5_0__SRCID__SDMA_TRAP;
1226         case 1:
1227                 return SDMA1_5_0__SRCID__SDMA_TRAP;
1228         case 2:
1229                 return SDMA2_5_0__SRCID__SDMA_TRAP;
1230         case 3:
1231                 return SDMA3_5_0__SRCID__SDMA_TRAP;
1232         default:
1233                 break;
1234         }
1235         return -EINVAL;
1236 }
1237
1238 static int sdma_v5_2_sw_init(void *handle)
1239 {
1240         struct amdgpu_ring *ring;
1241         int r, i;
1242         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1243
1244         /* SDMA trap event */
1245         for (i = 0; i < adev->sdma.num_instances; i++) {
1246                 r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i),
1247                                       sdma_v5_2_seq_to_trap_id(i),
1248                                       &adev->sdma.trap_irq);
1249                 if (r)
1250                         return r;
1251         }
1252
1253         r = sdma_v5_2_init_microcode(adev);
1254         if (r) {
1255                 DRM_ERROR("Failed to load sdma firmware!\n");
1256                 return r;
1257         }
1258
1259         for (i = 0; i < adev->sdma.num_instances; i++) {
1260                 ring = &adev->sdma.instance[i].ring;
1261                 ring->ring_obj = NULL;
1262                 ring->use_doorbell = true;
1263                 ring->me = i;
1264
1265                 DRM_INFO("use_doorbell being set to: [%s]\n",
1266                                 ring->use_doorbell?"true":"false");
1267
1268                 ring->doorbell_index =
1269                         (adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset
1270
1271                 sprintf(ring->name, "sdma%d", i);
1272                 r = amdgpu_ring_init(adev, ring, 1024,
1273                                      &adev->sdma.trap_irq,
1274                                      AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1275                                      AMDGPU_RING_PRIO_DEFAULT);
1276                 if (r)
1277                         return r;
1278         }
1279
1280         return r;
1281 }
1282
1283 static int sdma_v5_2_sw_fini(void *handle)
1284 {
1285         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1286         int i;
1287
1288         for (i = 0; i < adev->sdma.num_instances; i++)
1289                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1290
1291         sdma_v5_2_destroy_inst_ctx(adev);
1292
1293         return 0;
1294 }
1295
1296 static int sdma_v5_2_hw_init(void *handle)
1297 {
1298         int r;
1299         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1300
1301         sdma_v5_2_init_golden_registers(adev);
1302
1303         r = sdma_v5_2_start(adev);
1304
1305         return r;
1306 }
1307
1308 static int sdma_v5_2_hw_fini(void *handle)
1309 {
1310         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1311
1312         if (amdgpu_sriov_vf(adev))
1313                 return 0;
1314
1315         sdma_v5_2_ctx_switch_enable(adev, false);
1316         sdma_v5_2_enable(adev, false);
1317
1318         return 0;
1319 }
1320
1321 static int sdma_v5_2_suspend(void *handle)
1322 {
1323         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1324
1325         return sdma_v5_2_hw_fini(adev);
1326 }
1327
1328 static int sdma_v5_2_resume(void *handle)
1329 {
1330         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1331
1332         return sdma_v5_2_hw_init(adev);
1333 }
1334
1335 static bool sdma_v5_2_is_idle(void *handle)
1336 {
1337         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1338         u32 i;
1339
1340         for (i = 0; i < adev->sdma.num_instances; i++) {
1341                 u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1342
1343                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1344                         return false;
1345         }
1346
1347         return true;
1348 }
1349
1350 static int sdma_v5_2_wait_for_idle(void *handle)
1351 {
1352         unsigned i;
1353         u32 sdma0, sdma1, sdma2, sdma3;
1354         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1355
1356         for (i = 0; i < adev->usec_timeout; i++) {
1357                 sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1358                 sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1359                 sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG));
1360                 sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG));
1361
1362                 if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK)
1363                         return 0;
1364                 udelay(1);
1365         }
1366         return -ETIMEDOUT;
1367 }
1368
1369 static int sdma_v5_2_soft_reset(void *handle)
1370 {
1371         /* todo */
1372
1373         return 0;
1374 }
1375
1376 static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring)
1377 {
1378         int i, r = 0;
1379         struct amdgpu_device *adev = ring->adev;
1380         u32 index = 0;
1381         u64 sdma_gfx_preempt;
1382
1383         amdgpu_sdma_get_index_from_ring(ring, &index);
1384         sdma_gfx_preempt =
1385                 sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT);
1386
1387         /* assert preemption condition */
1388         amdgpu_ring_set_preempt_cond_exec(ring, false);
1389
1390         /* emit the trailing fence */
1391         ring->trail_seq += 1;
1392         amdgpu_ring_alloc(ring, 10);
1393         sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1394                                   ring->trail_seq, 0);
1395         amdgpu_ring_commit(ring);
1396
1397         /* assert IB preemption */
1398         WREG32(sdma_gfx_preempt, 1);
1399
1400         /* poll the trailing fence */
1401         for (i = 0; i < adev->usec_timeout; i++) {
1402                 if (ring->trail_seq ==
1403                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1404                         break;
1405                 udelay(1);
1406         }
1407
1408         if (i >= adev->usec_timeout) {
1409                 r = -EINVAL;
1410                 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1411         }
1412
1413         /* deassert IB preemption */
1414         WREG32(sdma_gfx_preempt, 0);
1415
1416         /* deassert the preemption condition */
1417         amdgpu_ring_set_preempt_cond_exec(ring, true);
1418         return r;
1419 }
1420
1421 static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev,
1422                                         struct amdgpu_irq_src *source,
1423                                         unsigned type,
1424                                         enum amdgpu_interrupt_state state)
1425 {
1426         u32 sdma_cntl;
1427
1428         u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL);
1429
1430         sdma_cntl = RREG32(reg_offset);
1431         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1432                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1433         WREG32(reg_offset, sdma_cntl);
1434
1435         return 0;
1436 }
1437
1438 static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev,
1439                                       struct amdgpu_irq_src *source,
1440                                       struct amdgpu_iv_entry *entry)
1441 {
1442         DRM_DEBUG("IH: SDMA trap\n");
1443         switch (entry->client_id) {
1444         case SOC15_IH_CLIENTID_SDMA0:
1445                 switch (entry->ring_id) {
1446                 case 0:
1447                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1448                         break;
1449                 case 1:
1450                         /* XXX compute */
1451                         break;
1452                 case 2:
1453                         /* XXX compute */
1454                         break;
1455                 case 3:
1456                         /* XXX page queue*/
1457                         break;
1458                 }
1459                 break;
1460         case SOC15_IH_CLIENTID_SDMA1:
1461                 switch (entry->ring_id) {
1462                 case 0:
1463                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1464                         break;
1465                 case 1:
1466                         /* XXX compute */
1467                         break;
1468                 case 2:
1469                         /* XXX compute */
1470                         break;
1471                 case 3:
1472                         /* XXX page queue*/
1473                         break;
1474                 }
1475                 break;
1476         case SOC15_IH_CLIENTID_SDMA2:
1477                 switch (entry->ring_id) {
1478                 case 0:
1479                         amdgpu_fence_process(&adev->sdma.instance[2].ring);
1480                         break;
1481                 case 1:
1482                         /* XXX compute */
1483                         break;
1484                 case 2:
1485                         /* XXX compute */
1486                         break;
1487                 case 3:
1488                         /* XXX page queue*/
1489                         break;
1490                 }
1491                 break;
1492         case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid:
1493                 switch (entry->ring_id) {
1494                 case 0:
1495                         amdgpu_fence_process(&adev->sdma.instance[3].ring);
1496                         break;
1497                 case 1:
1498                         /* XXX compute */
1499                         break;
1500                 case 2:
1501                         /* XXX compute */
1502                         break;
1503                 case 3:
1504                         /* XXX page queue*/
1505                         break;
1506                 }
1507                 break;
1508         }
1509         return 0;
1510 }
1511
1512 static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev,
1513                                               struct amdgpu_irq_src *source,
1514                                               struct amdgpu_iv_entry *entry)
1515 {
1516         return 0;
1517 }
1518
1519 static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1520                                                        bool enable)
1521 {
1522         uint32_t data, def;
1523         int i;
1524
1525         for (i = 0; i < adev->sdma.num_instances; i++) {
1526                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1527                         /* Enable sdma clock gating */
1528                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1529                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1530                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1531                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1532                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1533                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1534                                   SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1535                         if (def != data)
1536                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1537                 } else {
1538                         /* Disable sdma clock gating */
1539                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1540                         data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1541                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1542                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1543                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1544                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1545                                  SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1546                         if (def != data)
1547                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1548                 }
1549         }
1550 }
1551
1552 static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1553                                                       bool enable)
1554 {
1555         uint32_t data, def;
1556         int i;
1557
1558         for (i = 0; i < adev->sdma.num_instances; i++) {
1559                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1560                         /* Enable sdma mem light sleep */
1561                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1562                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1563                         if (def != data)
1564                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1565
1566                 } else {
1567                         /* Disable sdma mem light sleep */
1568                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1569                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1570                         if (def != data)
1571                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1572
1573                 }
1574         }
1575 }
1576
1577 static int sdma_v5_2_set_clockgating_state(void *handle,
1578                                            enum amd_clockgating_state state)
1579 {
1580         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1581
1582         if (amdgpu_sriov_vf(adev))
1583                 return 0;
1584
1585         switch (adev->asic_type) {
1586         case CHIP_SIENNA_CICHLID:
1587         case CHIP_NAVY_FLOUNDER:
1588         case CHIP_VANGOGH:
1589         case CHIP_DIMGREY_CAVEFISH:
1590                 sdma_v5_2_update_medium_grain_clock_gating(adev,
1591                                 state == AMD_CG_STATE_GATE ? true : false);
1592                 sdma_v5_2_update_medium_grain_light_sleep(adev,
1593                                 state == AMD_CG_STATE_GATE ? true : false);
1594                 break;
1595         default:
1596                 break;
1597         }
1598
1599         return 0;
1600 }
1601
1602 static int sdma_v5_2_set_powergating_state(void *handle,
1603                                           enum amd_powergating_state state)
1604 {
1605         return 0;
1606 }
1607
1608 static void sdma_v5_2_get_clockgating_state(void *handle, u32 *flags)
1609 {
1610         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1611         int data;
1612
1613         if (amdgpu_sriov_vf(adev))
1614                 *flags = 0;
1615
1616         /* AMD_CG_SUPPORT_SDMA_LS */
1617         data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1618         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1619                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1620 }
1621
1622 const struct amd_ip_funcs sdma_v5_2_ip_funcs = {
1623         .name = "sdma_v5_2",
1624         .early_init = sdma_v5_2_early_init,
1625         .late_init = NULL,
1626         .sw_init = sdma_v5_2_sw_init,
1627         .sw_fini = sdma_v5_2_sw_fini,
1628         .hw_init = sdma_v5_2_hw_init,
1629         .hw_fini = sdma_v5_2_hw_fini,
1630         .suspend = sdma_v5_2_suspend,
1631         .resume = sdma_v5_2_resume,
1632         .is_idle = sdma_v5_2_is_idle,
1633         .wait_for_idle = sdma_v5_2_wait_for_idle,
1634         .soft_reset = sdma_v5_2_soft_reset,
1635         .set_clockgating_state = sdma_v5_2_set_clockgating_state,
1636         .set_powergating_state = sdma_v5_2_set_powergating_state,
1637         .get_clockgating_state = sdma_v5_2_get_clockgating_state,
1638 };
1639
1640 static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {
1641         .type = AMDGPU_RING_TYPE_SDMA,
1642         .align_mask = 0xf,
1643         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1644         .support_64bit_ptrs = true,
1645         .vmhub = AMDGPU_GFXHUB_0,
1646         .get_rptr = sdma_v5_2_ring_get_rptr,
1647         .get_wptr = sdma_v5_2_ring_get_wptr,
1648         .set_wptr = sdma_v5_2_ring_set_wptr,
1649         .emit_frame_size =
1650                 5 + /* sdma_v5_2_ring_init_cond_exec */
1651                 6 + /* sdma_v5_2_ring_emit_hdp_flush */
1652                 3 + /* hdp_invalidate */
1653                 6 + /* sdma_v5_2_ring_emit_pipeline_sync */
1654                 /* sdma_v5_2_ring_emit_vm_flush */
1655                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1656                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1657                 10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */
1658         .emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */
1659         .emit_ib = sdma_v5_2_ring_emit_ib,
1660         .emit_fence = sdma_v5_2_ring_emit_fence,
1661         .emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync,
1662         .emit_vm_flush = sdma_v5_2_ring_emit_vm_flush,
1663         .emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush,
1664         .test_ring = sdma_v5_2_ring_test_ring,
1665         .test_ib = sdma_v5_2_ring_test_ib,
1666         .insert_nop = sdma_v5_2_ring_insert_nop,
1667         .pad_ib = sdma_v5_2_ring_pad_ib,
1668         .emit_wreg = sdma_v5_2_ring_emit_wreg,
1669         .emit_reg_wait = sdma_v5_2_ring_emit_reg_wait,
1670         .emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait,
1671         .init_cond_exec = sdma_v5_2_ring_init_cond_exec,
1672         .patch_cond_exec = sdma_v5_2_ring_patch_cond_exec,
1673         .preempt_ib = sdma_v5_2_ring_preempt_ib,
1674 };
1675
1676 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev)
1677 {
1678         int i;
1679
1680         for (i = 0; i < adev->sdma.num_instances; i++) {
1681                 adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs;
1682                 adev->sdma.instance[i].ring.me = i;
1683         }
1684 }
1685
1686 static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = {
1687         .set = sdma_v5_2_set_trap_irq_state,
1688         .process = sdma_v5_2_process_trap_irq,
1689 };
1690
1691 static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = {
1692         .process = sdma_v5_2_process_illegal_inst_irq,
1693 };
1694
1695 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev)
1696 {
1697         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1698                                         adev->sdma.num_instances;
1699         adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs;
1700         adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs;
1701 }
1702
1703 /**
1704  * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine
1705  *
1706  * @ib: indirect buffer to copy to
1707  * @src_offset: src GPU address
1708  * @dst_offset: dst GPU address
1709  * @byte_count: number of bytes to xfer
1710  * @tmz: if a secure copy should be used
1711  *
1712  * Copy GPU buffers using the DMA engine.
1713  * Used by the amdgpu ttm implementation to move pages if
1714  * registered as the asic copy callback.
1715  */
1716 static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib,
1717                                        uint64_t src_offset,
1718                                        uint64_t dst_offset,
1719                                        uint32_t byte_count,
1720                                        bool tmz)
1721 {
1722         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1723                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1724                 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1725         ib->ptr[ib->length_dw++] = byte_count - 1;
1726         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1727         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1728         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1729         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1730         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1731 }
1732
1733 /**
1734  * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine
1735  *
1736  * @ib: indirect buffer to fill
1737  * @src_data: value to write to buffer
1738  * @dst_offset: dst GPU address
1739  * @byte_count: number of bytes to xfer
1740  *
1741  * Fill GPU buffers using the DMA engine.
1742  */
1743 static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
1744                                        uint32_t src_data,
1745                                        uint64_t dst_offset,
1746                                        uint32_t byte_count)
1747 {
1748         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1749         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1750         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1751         ib->ptr[ib->length_dw++] = src_data;
1752         ib->ptr[ib->length_dw++] = byte_count - 1;
1753 }
1754
1755 static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = {
1756         .copy_max_bytes = 0x400000,
1757         .copy_num_dw = 7,
1758         .emit_copy_buffer = sdma_v5_2_emit_copy_buffer,
1759
1760         .fill_max_bytes = 0x400000,
1761         .fill_num_dw = 5,
1762         .emit_fill_buffer = sdma_v5_2_emit_fill_buffer,
1763 };
1764
1765 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev)
1766 {
1767         if (adev->mman.buffer_funcs == NULL) {
1768                 adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs;
1769                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1770         }
1771 }
1772
1773 static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = {
1774         .copy_pte_num_dw = 7,
1775         .copy_pte = sdma_v5_2_vm_copy_pte,
1776         .write_pte = sdma_v5_2_vm_write_pte,
1777         .set_pte_pde = sdma_v5_2_vm_set_pte_pde,
1778 };
1779
1780 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev)
1781 {
1782         unsigned i;
1783
1784         if (adev->vm_manager.vm_pte_funcs == NULL) {
1785                 adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs;
1786                 for (i = 0; i < adev->sdma.num_instances; i++) {
1787                         adev->vm_manager.vm_pte_scheds[i] =
1788                                 &adev->sdma.instance[i].ring.sched;
1789                 }
1790                 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1791         }
1792 }
1793
1794 const struct amdgpu_ip_block_version sdma_v5_2_ip_block = {
1795         .type = AMD_IP_BLOCK_TYPE_SDMA,
1796         .major = 5,
1797         .minor = 2,
1798         .rev = 0,
1799         .funcs = &sdma_v5_2_ip_funcs,
1800 };