drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_ucode.h"
  31 #include "amdgpu_trace.h"
  32
  33 #include "gc/gc_10_1_0_offset.h"
  34 #include "gc/gc_10_1_0_sh_mask.h"
  35 #include "hdp/hdp_5_0_0_offset.h"
  36 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
  37 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
  38
  39 #include "soc15_common.h"
  40 #include "soc15.h"
  41 #include "navi10_sdma_pkt_open.h"
  42 #include "nbio_v2_3.h"
  43 #include "sdma_common.h"
  44 #include "sdma_v5_0.h"
  45
  46 MODULE_FIRMWARE("amdgpu/navi10_sdma.bin");
  47 MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin");
  48
  49 MODULE_FIRMWARE("amdgpu/navi14_sdma.bin");
  50 MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin");
  51
  52 MODULE_FIRMWARE("amdgpu/navi12_sdma.bin");
  53 MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin");
  54
  55 #define SDMA1_REG_OFFSET 0x600
  56 #define SDMA0_HYP_DEC_REG_START 0x5880
  57 #define SDMA0_HYP_DEC_REG_END 0x5893
  58 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
  59
  60 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev);
  61 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev);
  62 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  63 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev);
  64
  65 static const struct soc15_reg_golden golden_settings_sdma_5[] = {
  66         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
  67         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  68         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  69         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  70         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  71         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  72         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  73         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  74         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  75         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  76         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  77         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00),
  78         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
  79         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  80         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  81         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  82         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  83         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  84         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  85         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  86         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  87         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  88         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  89         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00)
  90 };
  91
  92 static const struct soc15_reg_golden golden_settings_sdma_5_sriov[] = {
  93         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  94         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  95         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  96         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  97         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  98         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  99         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 113 };
 114
 115 static const struct soc15_reg_golden golden_settings_sdma_nv10[] = {
 116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 118 };
 119
 120 static const struct soc15_reg_golden golden_settings_sdma_nv14[] = {
 121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 123 };
 124
 125 static const struct soc15_reg_golden golden_settings_sdma_nv12[] = {
 126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 128 };
 129
 130 static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
 131 {
 132         u32 base;
 133
 134         if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
 135             internal_offset <= SDMA0_HYP_DEC_REG_END) {
 136                 base = adev->reg_offset[GC_HWIP][0][1];
 137                 if (instance == 1)
 138                         internal_offset += SDMA1_HYP_DEC_REG_OFFSET;
 139         } else {
 140                 base = adev->reg_offset[GC_HWIP][0][0];
 141                 if (instance == 1)
 142                         internal_offset += SDMA1_REG_OFFSET;
 143         }
 144
 145         return base + internal_offset;
 146 }
 147
 148 static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
 149 {
 150         switch (adev->asic_type) {
 151         case CHIP_NAVI10:
 152                 soc15_program_register_sequence(adev,
 153                                                 golden_settings_sdma_5,
 154                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
 155                 soc15_program_register_sequence(adev,
 156                                                 golden_settings_sdma_nv10,
 157                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_nv10));
 158                 break;
 159         case CHIP_NAVI14:
 160                 soc15_program_register_sequence(adev,
 161                                                 golden_settings_sdma_5,
 162                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
 163                 soc15_program_register_sequence(adev,
 164                                                 golden_settings_sdma_nv14,
 165                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_nv14));
 166                 break;
 167         case CHIP_NAVI12:
 168                 if (amdgpu_sriov_vf(adev))
 169                         soc15_program_register_sequence(adev,
 170                                                         golden_settings_sdma_5_sriov,
 171                                                         (const u32)ARRAY_SIZE(golden_settings_sdma_5_sriov));
 172                 else
 173                         soc15_program_register_sequence(adev,
 174                                                         golden_settings_sdma_5,
 175                                                         (const u32)ARRAY_SIZE(golden_settings_sdma_5));
 176                 soc15_program_register_sequence(adev,
 177                                                 golden_settings_sdma_nv12,
 178                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_nv12));
 179                 break;
 180         default:
 181                 break;
 182         }
 183 }
 184
 185 /**
 186  * sdma_v5_0_init_microcode - load ucode images from disk
 187  *
 188  * @adev: amdgpu_device pointer
 189  *
 190  * Use the firmware interface to load the ucode images into
 191  * the driver (not loaded into hw).
 192  * Returns 0 on success, error on failure.
 193  */
 194
 195 // emulation only, won't work on real chip
 196 // navi10 real chip need to use PSP to load firmware
 197 static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
 198 {
 199         const char *chip_name;
 200         char fw_name[30];
 201         int err = 0, i;
 202         struct amdgpu_firmware_info *info = NULL;
 203         const struct common_firmware_header *header = NULL;
 204         const struct sdma_firmware_header_v1_0 *hdr;
 205
 206         if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_NAVI12))
 207                 return 0;
 208
 209         DRM_DEBUG("\n");
 210
 211         switch (adev->asic_type) {
 212         case CHIP_NAVI10:
 213                 chip_name = "navi10";
 214                 break;
 215         case CHIP_NAVI14:
 216                 chip_name = "navi14";
 217                 break;
 218         case CHIP_NAVI12:
 219                 chip_name = "navi12";
 220                 break;
 221         default:
 222                 BUG();
 223         }
 224
 225         for (i = 0; i < adev->sdma.num_instances; i++) {
 226                 if (i == 0)
 227                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 228                 else
 229                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 230                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 231                 if (err)
 232                         goto out;
 233                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 234                 if (err)
 235                         goto out;
 236                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 237                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 238                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 239                 if (adev->sdma.instance[i].feature_version >= 20)
 240                         adev->sdma.instance[i].burst_nop = true;
 241                 DRM_DEBUG("psp_load == '%s'\n",
 242                                 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
 243
 244                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 245                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 246                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 247                         info->fw = adev->sdma.instance[i].fw;
 248                         header = (const struct common_firmware_header *)info->fw->data;
 249                         adev->firmware.fw_size +=
 250                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 251                 }
 252         }
 253 out:
 254         if (err) {
 255                 DRM_ERROR("sdma_v5_0: Failed to load firmware \"%s\"\n", fw_name);
 256                 for (i = 0; i < adev->sdma.num_instances; i++) {
 257                         release_firmware(adev->sdma.instance[i].fw);
 258                         adev->sdma.instance[i].fw = NULL;
 259                 }
 260         }
 261         return err;
 262 }
 263
 264 static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring)
 265 {
 266         unsigned ret;
 267
 268         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
 269         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
 270         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
 271         amdgpu_ring_write(ring, 1);
 272         ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
 273         amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
 274
 275         return ret;
 276 }
 277
 278 static void sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring *ring,
 279                                            unsigned offset)
 280 {
 281         unsigned cur;
 282
 283         BUG_ON(offset > ring->buf_mask);
 284         BUG_ON(ring->ring[offset] != 0x55aa55aa);
 285
 286         cur = (ring->wptr - 1) & ring->buf_mask;
 287         if (cur > offset)
 288                 ring->ring[offset] = cur - offset;
 289         else
 290                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
 291 }
 292
 293 /**
 294  * sdma_v5_0_ring_get_rptr - get the current read pointer
 295  *
 296  * @ring: amdgpu ring pointer
 297  *
 298  * Get the current rptr from the hardware (NAVI10+).
 299  */
 300 static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
 301 {
 302         u64 *rptr;
 303
 304         /* XXX check if swapping is necessary on BE */
 305         rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
 306
 307         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 308         return ((*rptr) >> 2);
 309 }
 310
 311 /**
 312  * sdma_v5_0_ring_get_wptr - get the current write pointer
 313  *
 314  * @ring: amdgpu ring pointer
 315  *
 316  * Get the current wptr from the hardware (NAVI10+).
 317  */
 318 static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
 319 {
 320         struct amdgpu_device *adev = ring->adev;
 321         u64 wptr;
 322
 323         if (ring->use_doorbell) {
 324                 /* XXX check if swapping is necessary on BE */
 325                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 326                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 327         } else {
 328                 wptr = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
 329                 wptr = wptr << 32;
 330                 wptr |= RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
 331                 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
 332         }
 333
 334         return wptr >> 2;
 335 }
 336
 337 /**
 338  * sdma_v5_0_ring_set_wptr - commit the write pointer
 339  *
 340  * @ring: amdgpu ring pointer
 341  *
 342  * Write the wptr back to the hardware (NAVI10+).
 343  */
 344 static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
 345 {
 346         struct amdgpu_device *adev = ring->adev;
 347
 348         DRM_DEBUG("Setting write pointer\n");
 349         if (ring->use_doorbell) {
 350                 DRM_DEBUG("Using doorbell -- "
 351                                 "wptr_offs == 0x%08x "
 352                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 353                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 354                                 ring->wptr_offs,
 355                                 lower_32_bits(ring->wptr << 2),
 356                                 upper_32_bits(ring->wptr << 2));
 357                 /* XXX check if swapping is necessary on BE */
 358                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
 359                 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
 360                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 361                                 ring->doorbell_index, ring->wptr << 2);
 362                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 363         } else {
 364                 DRM_DEBUG("Not using doorbell -- "
 365                                 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 366                                 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 367                                 ring->me,
 368                                 lower_32_bits(ring->wptr << 2),
 369                                 ring->me,
 370                                 upper_32_bits(ring->wptr << 2));
 371                 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
 372                         lower_32_bits(ring->wptr << 2));
 373                 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
 374                         upper_32_bits(ring->wptr << 2));
 375         }
 376 }
 377
 378 static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 379 {
 380         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 381         int i;
 382
 383         for (i = 0; i < count; i++)
 384                 if (sdma && sdma->burst_nop && (i == 0))
 385                         amdgpu_ring_write(ring, ring->funcs->nop |
 386                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 387                 else
 388                         amdgpu_ring_write(ring, ring->funcs->nop);
 389 }
 390
 391 /**
 392  * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine
 393  *
 394  * @ring: amdgpu ring pointer
 395  * @job: job to retrieve vmid from
 396  * @ib: IB object to schedule
 397  * @flags: unused
 398  *
 399  * Schedule an IB in the DMA ring (NAVI10).
 400  */
 401 static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
 402                                    struct amdgpu_job *job,
 403                                    struct amdgpu_ib *ib,
 404                                    uint32_t flags)
 405 {
 406         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 407         uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
 408
 409         /* Invalidate L2, because if we don't do it, we might get stale cache
 410          * lines from previous IBs.
 411          */
 412         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
 413         amdgpu_ring_write(ring, 0);
 414         amdgpu_ring_write(ring, (SDMA_GCR_GL2_INV |
 415                                  SDMA_GCR_GL2_WB |
 416                                  SDMA_GCR_GLM_INV |
 417                                  SDMA_GCR_GLM_WB) << 16);
 418         amdgpu_ring_write(ring, 0xffffff80);
 419         amdgpu_ring_write(ring, 0xffff);
 420
 421         /* An IB packet must end on a 8 DW boundary--the next dword
 422          * must be on a 8-dword boundary. Our IB packet below is 6
 423          * dwords long, thus add x number of NOPs, such that, in
 424          * modular arithmetic,
 425          * wptr + 6 + x = 8k, k >= 0, which in C is,
 426          * (wptr + 6 + x) % 8 = 0.
 427          * The expression below, is a solution of x.
 428          */
 429         sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 430
 431         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 432                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 433         /* base must be 32 byte aligned */
 434         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 435         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 436         amdgpu_ring_write(ring, ib->length_dw);
 437         amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
 438         amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
 439 }
 440
 441 /**
 442  * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 443  *
 444  * @ring: amdgpu ring pointer
 445  *
 446  * Emit an hdp flush packet on the requested DMA ring.
 447  */
 448 static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 449 {
 450         struct amdgpu_device *adev = ring->adev;
 451         u32 ref_and_mask = 0;
 452         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 453
 454         if (ring->me == 0)
 455                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
 456         else
 457                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
 458
 459         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 460                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 461                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 462         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
 463         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
 464         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 465         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 466         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 467                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 468 }
 469
 470 /**
 471  * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring
 472  *
 473  * @ring: amdgpu ring pointer
 474  * @addr: address
 475  * @seq: sequence number
 476  * @flags: fence related flags
 477  *
 478  * Add a DMA fence packet to the ring to write
 479  * the fence seq number and DMA trap packet to generate
 480  * an interrupt if needed (NAVI10).
 481  */
 482 static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 483                                       unsigned flags)
 484 {
 485         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 486         /* write the fence */
 487         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 488                           SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
 489         /* zero in first two bits */
 490         BUG_ON(addr & 0x3);
 491         amdgpu_ring_write(ring, lower_32_bits(addr));
 492         amdgpu_ring_write(ring, upper_32_bits(addr));
 493         amdgpu_ring_write(ring, lower_32_bits(seq));
 494
 495         /* optionally write high bits as well */
 496         if (write64bit) {
 497                 addr += 4;
 498                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 499                                   SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
 500                 /* zero in first two bits */
 501                 BUG_ON(addr & 0x3);
 502                 amdgpu_ring_write(ring, lower_32_bits(addr));
 503                 amdgpu_ring_write(ring, upper_32_bits(addr));
 504                 amdgpu_ring_write(ring, upper_32_bits(seq));
 505         }
 506
 507         if (flags & AMDGPU_FENCE_FLAG_INT) {
 508                 /* generate an interrupt */
 509                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 510                 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 511         }
 512 }
 513
 514
 515 /**
 516  * sdma_v5_0_gfx_stop - stop the gfx async dma engines
 517  *
 518  * @adev: amdgpu_device pointer
 519  *
 520  * Stop the gfx async dma ring buffers (NAVI10).
 521  */
 522 static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev)
 523 {
 524         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 525         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 526         u32 rb_cntl, ib_cntl;
 527         int i;
 528
 529         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 530             (adev->mman.buffer_funcs_ring == sdma1))
 531                 amdgpu_ttm_set_buffer_funcs_status(adev, false);
 532
 533         for (i = 0; i < adev->sdma.num_instances; i++) {
 534                 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 535                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 536                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 537                 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 538                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 539                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 540         }
 541 }
 542
 543 /**
 544  * sdma_v5_0_rlc_stop - stop the compute async dma engines
 545  *
 546  * @adev: amdgpu_device pointer
 547  *
 548  * Stop the compute async dma queues (NAVI10).
 549  */
 550 static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev)
 551 {
 552         /* XXX todo */
 553 }
 554
 555 /**
 556  * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
 557  *
 558  * @adev: amdgpu_device pointer
 559  * @enable: enable/disable the DMA MEs context switch.
 560  *
 561  * Halt or unhalt the async dma engines context switch (NAVI10).
 562  */
 563 static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 564 {
 565         u32 f32_cntl = 0, phase_quantum = 0;
 566         int i;
 567
 568         if (amdgpu_sdma_phase_quantum) {
 569                 unsigned value = amdgpu_sdma_phase_quantum;
 570                 unsigned unit = 0;
 571
 572                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 573                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 574                         value = (value + 1) >> 1;
 575                         unit++;
 576                 }
 577                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 578                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 579                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 580                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 581                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 582                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 583                         WARN_ONCE(1,
 584                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 585                                   value << unit);
 586                 }
 587                 phase_quantum =
 588                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 589                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 590         }
 591
 592         for (i = 0; i < adev->sdma.num_instances; i++) {
 593                 if (!amdgpu_sriov_vf(adev)) {
 594                         f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
 595                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 596                                                  AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 597                 }
 598
 599                 if (enable && amdgpu_sdma_phase_quantum) {
 600                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
 601                                phase_quantum);
 602                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
 603                                phase_quantum);
 604                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
 605                                phase_quantum);
 606                 }
 607                 if (!amdgpu_sriov_vf(adev))
 608                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
 609         }
 610
 611 }
 612
 613 /**
 614  * sdma_v5_0_enable - stop the async dma engines
 615  *
 616  * @adev: amdgpu_device pointer
 617  * @enable: enable/disable the DMA MEs.
 618  *
 619  * Halt or unhalt the async dma engines (NAVI10).
 620  */
 621 static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable)
 622 {
 623         u32 f32_cntl;
 624         int i;
 625
 626         if (!enable) {
 627                 sdma_v5_0_gfx_stop(adev);
 628                 sdma_v5_0_rlc_stop(adev);
 629         }
 630
 631         if (amdgpu_sriov_vf(adev))
 632                 return;
 633
 634         for (i = 0; i < adev->sdma.num_instances; i++) {
 635                 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 636                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 637                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
 638         }
 639 }
 640
 641 /**
 642  * sdma_v5_0_gfx_resume - setup and start the async dma engines
 643  *
 644  * @adev: amdgpu_device pointer
 645  *
 646  * Set up the gfx DMA ring buffers and enable them (NAVI10).
 647  * Returns 0 for success, error for failure.
 648  */
 649 static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
 650 {
 651         struct amdgpu_ring *ring;
 652         u32 rb_cntl, ib_cntl;
 653         u32 rb_bufsz;
 654         u32 wb_offset;
 655         u32 doorbell;
 656         u32 doorbell_offset;
 657         u32 temp;
 658         u32 wptr_poll_cntl;
 659         u64 wptr_gpu_addr;
 660         int i, r;
 661
 662         for (i = 0; i < adev->sdma.num_instances; i++) {
 663                 ring = &adev->sdma.instance[i].ring;
 664                 wb_offset = (ring->rptr_offs * 4);
 665
 666                 if (!amdgpu_sriov_vf(adev))
 667                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 668
 669                 /* Set ring buffer size in dwords */
 670                 rb_bufsz = order_base_2(ring->ring_size / 4);
 671                 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 672                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 673 #ifdef __BIG_ENDIAN
 674                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 675                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 676                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 677 #endif
 678                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 679
 680                 /* Initialize the ring buffer's read and write pointers */
 681                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
 682                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
 683                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
 684                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 685
 686                 /* setup the wptr shadow polling */
 687                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 688                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
 689                        lower_32_bits(wptr_gpu_addr));
 690                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
 691                        upper_32_bits(wptr_gpu_addr));
 692                 wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i,
 693                                                          mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 694                 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 695                                                SDMA0_GFX_RB_WPTR_POLL_CNTL,
 696                                                F32_POLL_ENABLE, 1);
 697                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
 698                        wptr_poll_cntl);
 699
 700                 /* set the wb address whether it's enabled or not */
 701                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
 702                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 703                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
 704                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 705
 706                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 707
 708                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
 709                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
 710
 711                 ring->wptr = 0;
 712
 713                 /* before programing wptr to a less value, need set minor_ptr_update first */
 714                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
 715
 716                 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 717                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
 718                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
 719                 }
 720
 721                 doorbell = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
 722                 doorbell_offset = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
 723
 724                 if (ring->use_doorbell) {
 725                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 726                         doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
 727                                         OFFSET, ring->doorbell_index);
 728                 } else {
 729                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 730                 }
 731                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
 732                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
 733
 734                 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 735                                                       ring->doorbell_index, 20);
 736
 737                 if (amdgpu_sriov_vf(adev))
 738                         sdma_v5_0_ring_set_wptr(ring);
 739
 740                 /* set minor_ptr_update to 0 after wptr programed */
 741                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
 742
 743                 if (!amdgpu_sriov_vf(adev)) {
 744                         /* set utc l1 enable flag always to 1 */
 745                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
 746                         temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
 747
 748                         /* enable MCBP */
 749                         temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
 750                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
 751
 752                         /* Set up RESP_MODE to non-copy addresses */
 753                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
 754                         temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
 755                         temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
 756                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
 757
 758                         /* program default cache read and write policy */
 759                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
 760                         /* clean read policy and write policy bits */
 761                         temp &= 0xFF0FFF;
 762                         temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14));
 763                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
 764                 }
 765
 766                 if (!amdgpu_sriov_vf(adev)) {
 767                         /* unhalt engine */
 768                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 769                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 770                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
 771                 }
 772
 773                 /* enable DMA RB */
 774                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 775                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 776
 777                 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 778                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 779 #ifdef __BIG_ENDIAN
 780                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 781 #endif
 782                 /* enable DMA IBs */
 783                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 784
 785                 ring->sched.ready = true;
 786
 787                 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
 788                         sdma_v5_0_ctx_switch_enable(adev, true);
 789                         sdma_v5_0_enable(adev, true);
 790                 }
 791
 792                 r = amdgpu_ring_test_helper(ring);
 793                 if (r)
 794                         return r;
 795
 796                 if (adev->mman.buffer_funcs_ring == ring)
 797                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 798         }
 799
 800         return 0;
 801 }
 802
 803 /**
 804  * sdma_v5_0_rlc_resume - setup and start the async dma engines
 805  *
 806  * @adev: amdgpu_device pointer
 807  *
 808  * Set up the compute DMA queues and enable them (NAVI10).
 809  * Returns 0 for success, error for failure.
 810  */
 811 static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev)
 812 {
 813         return 0;
 814 }
 815
 816 /**
 817  * sdma_v5_0_load_microcode - load the sDMA ME ucode
 818  *
 819  * @adev: amdgpu_device pointer
 820  *
 821  * Loads the sDMA0/1 ucode.
 822  * Returns 0 for success, -EINVAL if the ucode is not available.
 823  */
 824 static int sdma_v5_0_load_microcode(struct amdgpu_device *adev)
 825 {
 826         const struct sdma_firmware_header_v1_0 *hdr;
 827         const __le32 *fw_data;
 828         u32 fw_size;
 829         int i, j;
 830
 831         /* halt the MEs */
 832         sdma_v5_0_enable(adev, false);
 833
 834         for (i = 0; i < adev->sdma.num_instances; i++) {
 835                 if (!adev->sdma.instance[i].fw)
 836                         return -EINVAL;
 837
 838                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 839                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 840                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 841
 842                 fw_data = (const __le32 *)
 843                         (adev->sdma.instance[i].fw->data +
 844                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 845
 846                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
 847
 848                 for (j = 0; j < fw_size; j++) {
 849                         if (amdgpu_emu_mode == 1 && j % 500 == 0)
 850                                 msleep(1);
 851                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 852                 }
 853
 854                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
 855         }
 856
 857         return 0;
 858 }
 859
 860 /**
 861  * sdma_v5_0_start - setup and start the async dma engines
 862  *
 863  * @adev: amdgpu_device pointer
 864  *
 865  * Set up the DMA engines and enable them (NAVI10).
 866  * Returns 0 for success, error for failure.
 867  */
 868 static int sdma_v5_0_start(struct amdgpu_device *adev)
 869 {
 870         int r = 0;
 871
 872         if (amdgpu_sriov_vf(adev)) {
 873                 sdma_v5_0_ctx_switch_enable(adev, false);
 874                 sdma_v5_0_enable(adev, false);
 875
 876                 /* set RB registers */
 877                 r = sdma_v5_0_gfx_resume(adev);
 878                 return r;
 879         }
 880
 881         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 882                 r = sdma_v5_0_load_microcode(adev);
 883                 if (r)
 884                         return r;
 885         }
 886
 887         /* unhalt the MEs */
 888         sdma_v5_0_enable(adev, true);
 889         /* enable sdma ring preemption */
 890         sdma_v5_0_ctx_switch_enable(adev, true);
 891
 892         /* start the gfx rings and rlc compute queues */
 893         r = sdma_v5_0_gfx_resume(adev);
 894         if (r)
 895                 return r;
 896         r = sdma_v5_0_rlc_resume(adev);
 897
 898         return r;
 899 }
 900
 901 /**
 902  * sdma_v5_0_ring_test_ring - simple async dma engine test
 903  *
 904  * @ring: amdgpu_ring structure holding ring information
 905  *
 906  * Test the DMA engine by writing using it to write an
 907  * value to memory. (NAVI10).
 908  * Returns 0 for success, error for failure.
 909  */
 910 static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring)
 911 {
 912         struct amdgpu_device *adev = ring->adev;
 913         unsigned i;
 914         unsigned index;
 915         int r;
 916         u32 tmp;
 917         u64 gpu_addr;
 918
 919         r = amdgpu_device_wb_get(adev, &index);
 920         if (r) {
 921                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 922                 return r;
 923         }
 924
 925         gpu_addr = adev->wb.gpu_addr + (index * 4);
 926         tmp = 0xCAFEDEAD;
 927         adev->wb.wb[index] = cpu_to_le32(tmp);
 928
 929         r = amdgpu_ring_alloc(ring, 5);
 930         if (r) {
 931                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 932                 amdgpu_device_wb_free(adev, index);
 933                 return r;
 934         }
 935
 936         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 937                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 938         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 939         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 940         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 941         amdgpu_ring_write(ring, 0xDEADBEEF);
 942         amdgpu_ring_commit(ring);
 943
 944         for (i = 0; i < adev->usec_timeout; i++) {
 945                 tmp = le32_to_cpu(adev->wb.wb[index]);
 946                 if (tmp == 0xDEADBEEF)
 947                         break;
 948                 if (amdgpu_emu_mode == 1)
 949                         msleep(1);
 950                 else
 951                         udelay(1);
 952         }
 953
 954         if (i >= adev->usec_timeout)
 955                 r = -ETIMEDOUT;
 956
 957         amdgpu_device_wb_free(adev, index);
 958
 959         return r;
 960 }
 961
 962 /**
 963  * sdma_v5_0_ring_test_ib - test an IB on the DMA engine
 964  *
 965  * @ring: amdgpu_ring structure holding ring information
 966  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
 967  *
 968  * Test a simple IB in the DMA ring (NAVI10).
 969  * Returns 0 on success, error on failure.
 970  */
 971 static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 972 {
 973         struct amdgpu_device *adev = ring->adev;
 974         struct amdgpu_ib ib;
 975         struct dma_fence *f = NULL;
 976         unsigned index;
 977         long r;
 978         u32 tmp = 0;
 979         u64 gpu_addr;
 980
 981         r = amdgpu_device_wb_get(adev, &index);
 982         if (r) {
 983                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 984                 return r;
 985         }
 986
 987         gpu_addr = adev->wb.gpu_addr + (index * 4);
 988         tmp = 0xCAFEDEAD;
 989         adev->wb.wb[index] = cpu_to_le32(tmp);
 990         memset(&ib, 0, sizeof(ib));
 991         r = amdgpu_ib_get(adev, NULL, 256,
 992                                         AMDGPU_IB_POOL_DIRECT, &ib);
 993         if (r) {
 994                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 995                 goto err0;
 996         }
 997
 998         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 999                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1000         ib.ptr[1] = lower_32_bits(gpu_addr);
1001         ib.ptr[2] = upper_32_bits(gpu_addr);
1002         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1003         ib.ptr[4] = 0xDEADBEEF;
1004         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1005         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1006         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1007         ib.length_dw = 8;
1008
1009         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1010         if (r)
1011                 goto err1;
1012
1013         r = dma_fence_wait_timeout(f, false, timeout);
1014         if (r == 0) {
1015                 DRM_ERROR("amdgpu: IB test timed out\n");
1016                 r = -ETIMEDOUT;
1017                 goto err1;
1018         } else if (r < 0) {
1019                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1020                 goto err1;
1021         }
1022         tmp = le32_to_cpu(adev->wb.wb[index]);
1023         if (tmp == 0xDEADBEEF)
1024                 r = 0;
1025         else
1026                 r = -EINVAL;
1027
1028 err1:
1029         amdgpu_ib_free(adev, &ib, NULL);
1030         dma_fence_put(f);
1031 err0:
1032         amdgpu_device_wb_free(adev, index);
1033         return r;
1034 }
1035
1036
1037 /**
1038  * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART
1039  *
1040  * @ib: indirect buffer to fill with commands
1041  * @pe: addr of the page entry
1042  * @src: src addr to copy from
1043  * @count: number of page entries to update
1044  *
1045  * Update PTEs by copying them from the GART using sDMA (NAVI10).
1046  */
1047 static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib,
1048                                   uint64_t pe, uint64_t src,
1049                                   unsigned count)
1050 {
1051         unsigned bytes = count * 8;
1052
1053         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1054                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1055         ib->ptr[ib->length_dw++] = bytes - 1;
1056         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1057         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1058         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1059         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1060         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1061
1062 }
1063
1064 /**
1065  * sdma_v5_0_vm_write_pte - update PTEs by writing them manually
1066  *
1067  * @ib: indirect buffer to fill with commands
1068  * @pe: addr of the page entry
1069  * @value: dst addr to write into pe
1070  * @count: number of page entries to update
1071  * @incr: increase next addr by incr bytes
1072  *
1073  * Update PTEs by writing them manually using sDMA (NAVI10).
1074  */
1075 static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1076                                    uint64_t value, unsigned count,
1077                                    uint32_t incr)
1078 {
1079         unsigned ndw = count * 2;
1080
1081         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1082                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1083         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1084         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1085         ib->ptr[ib->length_dw++] = ndw - 1;
1086         for (; ndw > 0; ndw -= 2) {
1087                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1088                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1089                 value += incr;
1090         }
1091 }
1092
1093 /**
1094  * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA
1095  *
1096  * @ib: indirect buffer to fill with commands
1097  * @pe: addr of the page entry
1098  * @addr: dst addr to write into pe
1099  * @count: number of page entries to update
1100  * @incr: increase next addr by incr bytes
1101  * @flags: access flags
1102  *
1103  * Update the page tables using sDMA (NAVI10).
1104  */
1105 static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1106                                      uint64_t pe,
1107                                      uint64_t addr, unsigned count,
1108                                      uint32_t incr, uint64_t flags)
1109 {
1110         /* for physically contiguous pages (vram) */
1111         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1112         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1113         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1114         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1115         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1116         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1117         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1118         ib->ptr[ib->length_dw++] = incr; /* increment size */
1119         ib->ptr[ib->length_dw++] = 0;
1120         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1121 }
1122
1123 /**
1124  * sdma_v5_0_ring_pad_ib - pad the IB
1125  * @ring: amdgpu_ring structure holding ring information
1126  * @ib: indirect buffer to fill with padding
1127  *
1128  * Pad the IB with NOPs to a boundary multiple of 8.
1129  */
1130 static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1131 {
1132         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1133         u32 pad_count;
1134         int i;
1135
1136         pad_count = (-ib->length_dw) & 0x7;
1137         for (i = 0; i < pad_count; i++)
1138                 if (sdma && sdma->burst_nop && (i == 0))
1139                         ib->ptr[ib->length_dw++] =
1140                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1141                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1142                 else
1143                         ib->ptr[ib->length_dw++] =
1144                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1145 }
1146
1147
1148 /**
1149  * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline
1150  *
1151  * @ring: amdgpu_ring pointer
1152  *
1153  * Make sure all previous operations are completed (CIK).
1154  */
1155 static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1156 {
1157         uint32_t seq = ring->fence_drv.sync_seq;
1158         uint64_t addr = ring->fence_drv.gpu_addr;
1159
1160         /* wait for idle */
1161         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1162                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1163                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1164                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1165         amdgpu_ring_write(ring, addr & 0xfffffffc);
1166         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1167         amdgpu_ring_write(ring, seq); /* reference */
1168         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1169         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1170                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1171 }
1172
1173
1174 /**
1175  * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA
1176  *
1177  * @ring: amdgpu_ring pointer
1178  * @vmid: vmid number to use
1179  * @pd_addr: address
1180  *
1181  * Update the page table base and flush the VM TLB
1182  * using sDMA (NAVI10).
1183  */
1184 static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1185                                          unsigned vmid, uint64_t pd_addr)
1186 {
1187         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1188 }
1189
1190 static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring *ring,
1191                                      uint32_t reg, uint32_t val)
1192 {
1193         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1194                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1195         amdgpu_ring_write(ring, reg);
1196         amdgpu_ring_write(ring, val);
1197 }
1198
1199 static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1200                                          uint32_t val, uint32_t mask)
1201 {
1202         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1203                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1204                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1205         amdgpu_ring_write(ring, reg << 2);
1206         amdgpu_ring_write(ring, 0);
1207         amdgpu_ring_write(ring, val); /* reference */
1208         amdgpu_ring_write(ring, mask); /* mask */
1209         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1210                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1211 }
1212
1213 static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1214                                                    uint32_t reg0, uint32_t reg1,
1215                                                    uint32_t ref, uint32_t mask)
1216 {
1217         amdgpu_ring_emit_wreg(ring, reg0, ref);
1218         /* wait for a cycle to reset vm_inv_eng*_ack */
1219         amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1220         amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1221 }
1222
1223 static int sdma_v5_0_early_init(void *handle)
1224 {
1225         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1226
1227         adev->sdma.num_instances = 2;
1228
1229         sdma_v5_0_set_ring_funcs(adev);
1230         sdma_v5_0_set_buffer_funcs(adev);
1231         sdma_v5_0_set_vm_pte_funcs(adev);
1232         sdma_v5_0_set_irq_funcs(adev);
1233
1234         return 0;
1235 }
1236
1237
1238 static int sdma_v5_0_sw_init(void *handle)
1239 {
1240         struct amdgpu_ring *ring;
1241         int r, i;
1242         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1243
1244         /* SDMA trap event */
1245         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0,
1246                               SDMA0_5_0__SRCID__SDMA_TRAP,
1247                               &adev->sdma.trap_irq);
1248         if (r)
1249                 return r;
1250
1251         /* SDMA trap event */
1252         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1,
1253                               SDMA1_5_0__SRCID__SDMA_TRAP,
1254                               &adev->sdma.trap_irq);
1255         if (r)
1256                 return r;
1257
1258         r = sdma_v5_0_init_microcode(adev);
1259         if (r) {
1260                 DRM_ERROR("Failed to load sdma firmware!\n");
1261                 return r;
1262         }
1263
1264         for (i = 0; i < adev->sdma.num_instances; i++) {
1265                 ring = &adev->sdma.instance[i].ring;
1266                 ring->ring_obj = NULL;
1267                 ring->use_doorbell = true;
1268
1269                 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1270                                 ring->use_doorbell?"true":"false");
1271
1272                 ring->doorbell_index = (i == 0) ?
1273                         (adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset
1274                         : (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset
1275
1276                 sprintf(ring->name, "sdma%d", i);
1277                 r = amdgpu_ring_init(adev, ring, 1024,
1278                                      &adev->sdma.trap_irq,
1279                                      (i == 0) ?
1280                                      AMDGPU_SDMA_IRQ_INSTANCE0 :
1281                                      AMDGPU_SDMA_IRQ_INSTANCE1,
1282                                      AMDGPU_RING_PRIO_DEFAULT);
1283                 if (r)
1284                         return r;
1285         }
1286
1287         return r;
1288 }
1289
1290 static int sdma_v5_0_sw_fini(void *handle)
1291 {
1292         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1293         int i;
1294
1295         for (i = 0; i < adev->sdma.num_instances; i++) {
1296                 release_firmware(adev->sdma.instance[i].fw);
1297                 adev->sdma.instance[i].fw = NULL;
1298
1299                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1300         }
1301
1302         return 0;
1303 }
1304
1305 static int sdma_v5_0_hw_init(void *handle)
1306 {
1307         int r;
1308         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1309
1310         sdma_v5_0_init_golden_registers(adev);
1311
1312         r = sdma_v5_0_start(adev);
1313
1314         return r;
1315 }
1316
1317 static int sdma_v5_0_hw_fini(void *handle)
1318 {
1319         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1320
1321         if (amdgpu_sriov_vf(adev))
1322                 return 0;
1323
1324         sdma_v5_0_ctx_switch_enable(adev, false);
1325         sdma_v5_0_enable(adev, false);
1326
1327         return 0;
1328 }
1329
1330 static int sdma_v5_0_suspend(void *handle)
1331 {
1332         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1333
1334         return sdma_v5_0_hw_fini(adev);
1335 }
1336
1337 static int sdma_v5_0_resume(void *handle)
1338 {
1339         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1340
1341         return sdma_v5_0_hw_init(adev);
1342 }
1343
1344 static bool sdma_v5_0_is_idle(void *handle)
1345 {
1346         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1347         u32 i;
1348
1349         for (i = 0; i < adev->sdma.num_instances; i++) {
1350                 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1351
1352                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1353                         return false;
1354         }
1355
1356         return true;
1357 }
1358
1359 static int sdma_v5_0_wait_for_idle(void *handle)
1360 {
1361         unsigned i;
1362         u32 sdma0, sdma1;
1363         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1364
1365         for (i = 0; i < adev->usec_timeout; i++) {
1366                 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1367                 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1368
1369                 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1370                         return 0;
1371                 udelay(1);
1372         }
1373         return -ETIMEDOUT;
1374 }
1375
1376 static int sdma_v5_0_soft_reset(void *handle)
1377 {
1378         /* todo */
1379
1380         return 0;
1381 }
1382
1383 static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring)
1384 {
1385         int i, r = 0;
1386         struct amdgpu_device *adev = ring->adev;
1387         u32 index = 0;
1388         u64 sdma_gfx_preempt;
1389
1390         amdgpu_sdma_get_index_from_ring(ring, &index);
1391         if (index == 0)
1392                 sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT;
1393         else
1394                 sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT;
1395
1396         /* assert preemption condition */
1397         amdgpu_ring_set_preempt_cond_exec(ring, false);
1398
1399         /* emit the trailing fence */
1400         ring->trail_seq += 1;
1401         amdgpu_ring_alloc(ring, 10);
1402         sdma_v5_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1403                                   ring->trail_seq, 0);
1404         amdgpu_ring_commit(ring);
1405
1406         /* assert IB preemption */
1407         WREG32(sdma_gfx_preempt, 1);
1408
1409         /* poll the trailing fence */
1410         for (i = 0; i < adev->usec_timeout; i++) {
1411                 if (ring->trail_seq ==
1412                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1413                         break;
1414                 udelay(1);
1415         }
1416
1417         if (i >= adev->usec_timeout) {
1418                 r = -EINVAL;
1419                 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1420         }
1421
1422         /* deassert IB preemption */
1423         WREG32(sdma_gfx_preempt, 0);
1424
1425         /* deassert the preemption condition */
1426         amdgpu_ring_set_preempt_cond_exec(ring, true);
1427         return r;
1428 }
1429
1430 static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev,
1431                                         struct amdgpu_irq_src *source,
1432                                         unsigned type,
1433                                         enum amdgpu_interrupt_state state)
1434 {
1435         u32 sdma_cntl;
1436
1437         if (!amdgpu_sriov_vf(adev)) {
1438                 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ?
1439                         sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :
1440                         sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);
1441
1442                 sdma_cntl = RREG32(reg_offset);
1443                 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1444                                           state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1445                 WREG32(reg_offset, sdma_cntl);
1446         }
1447
1448         return 0;
1449 }
1450
1451 static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev,
1452                                       struct amdgpu_irq_src *source,
1453                                       struct amdgpu_iv_entry *entry)
1454 {
1455         DRM_DEBUG("IH: SDMA trap\n");
1456         switch (entry->client_id) {
1457         case SOC15_IH_CLIENTID_SDMA0:
1458                 switch (entry->ring_id) {
1459                 case 0:
1460                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1461                         break;
1462                 case 1:
1463                         /* XXX compute */
1464                         break;
1465                 case 2:
1466                         /* XXX compute */
1467                         break;
1468                 case 3:
1469                         /* XXX page queue*/
1470                         break;
1471                 }
1472                 break;
1473         case SOC15_IH_CLIENTID_SDMA1:
1474                 switch (entry->ring_id) {
1475                 case 0:
1476                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1477                         break;
1478                 case 1:
1479                         /* XXX compute */
1480                         break;
1481                 case 2:
1482                         /* XXX compute */
1483                         break;
1484                 case 3:
1485                         /* XXX page queue*/
1486                         break;
1487                 }
1488                 break;
1489         }
1490         return 0;
1491 }
1492
1493 static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1494                                               struct amdgpu_irq_src *source,
1495                                               struct amdgpu_iv_entry *entry)
1496 {
1497         return 0;
1498 }
1499
1500 static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1501                                                        bool enable)
1502 {
1503         uint32_t data, def;
1504         int i;
1505
1506         for (i = 0; i < adev->sdma.num_instances; i++) {
1507                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1508                         /* Enable sdma clock gating */
1509                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1510                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1511                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1512                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1513                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1514                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1515                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1516                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1517                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1518                         if (def != data)
1519                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1520                 } else {
1521                         /* Disable sdma clock gating */
1522                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1523                         data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1524                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1525                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1526                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1527                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1528                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1529                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1530                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1531                         if (def != data)
1532                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1533                 }
1534         }
1535 }
1536
1537 static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1538                                                       bool enable)
1539 {
1540         uint32_t data, def;
1541         int i;
1542
1543         for (i = 0; i < adev->sdma.num_instances; i++) {
1544                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1545                         /* Enable sdma mem light sleep */
1546                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1547                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1548                         if (def != data)
1549                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1550
1551                 } else {
1552                         /* Disable sdma mem light sleep */
1553                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1554                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1555                         if (def != data)
1556                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1557
1558                 }
1559         }
1560 }
1561
1562 static int sdma_v5_0_set_clockgating_state(void *handle,
1563                                            enum amd_clockgating_state state)
1564 {
1565         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1566
1567         if (amdgpu_sriov_vf(adev))
1568                 return 0;
1569
1570         switch (adev->asic_type) {
1571         case CHIP_NAVI10:
1572         case CHIP_NAVI14:
1573         case CHIP_NAVI12:
1574                 sdma_v5_0_update_medium_grain_clock_gating(adev,
1575                                 state == AMD_CG_STATE_GATE);
1576                 sdma_v5_0_update_medium_grain_light_sleep(adev,
1577                                 state == AMD_CG_STATE_GATE);
1578                 break;
1579         default:
1580                 break;
1581         }
1582
1583         return 0;
1584 }
1585
1586 static int sdma_v5_0_set_powergating_state(void *handle,
1587                                           enum amd_powergating_state state)
1588 {
1589         return 0;
1590 }
1591
1592 static void sdma_v5_0_get_clockgating_state(void *handle, u32 *flags)
1593 {
1594         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1595         int data;
1596
1597         if (amdgpu_sriov_vf(adev))
1598                 *flags = 0;
1599
1600         /* AMD_CG_SUPPORT_SDMA_MGCG */
1601         data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
1602         if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
1603                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1604
1605         /* AMD_CG_SUPPORT_SDMA_LS */
1606         data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1607         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1608                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1609 }
1610
1611 const struct amd_ip_funcs sdma_v5_0_ip_funcs = {
1612         .name = "sdma_v5_0",
1613         .early_init = sdma_v5_0_early_init,
1614         .late_init = NULL,
1615         .sw_init = sdma_v5_0_sw_init,
1616         .sw_fini = sdma_v5_0_sw_fini,
1617         .hw_init = sdma_v5_0_hw_init,
1618         .hw_fini = sdma_v5_0_hw_fini,
1619         .suspend = sdma_v5_0_suspend,
1620         .resume = sdma_v5_0_resume,
1621         .is_idle = sdma_v5_0_is_idle,
1622         .wait_for_idle = sdma_v5_0_wait_for_idle,
1623         .soft_reset = sdma_v5_0_soft_reset,
1624         .set_clockgating_state = sdma_v5_0_set_clockgating_state,
1625         .set_powergating_state = sdma_v5_0_set_powergating_state,
1626         .get_clockgating_state = sdma_v5_0_get_clockgating_state,
1627 };
1628
1629 static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
1630         .type = AMDGPU_RING_TYPE_SDMA,
1631         .align_mask = 0xf,
1632         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1633         .support_64bit_ptrs = true,
1634         .vmhub = AMDGPU_GFXHUB_0,
1635         .get_rptr = sdma_v5_0_ring_get_rptr,
1636         .get_wptr = sdma_v5_0_ring_get_wptr,
1637         .set_wptr = sdma_v5_0_ring_set_wptr,
1638         .emit_frame_size =
1639                 5 + /* sdma_v5_0_ring_init_cond_exec */
1640                 6 + /* sdma_v5_0_ring_emit_hdp_flush */
1641                 3 + /* hdp_invalidate */
1642                 6 + /* sdma_v5_0_ring_emit_pipeline_sync */
1643                 /* sdma_v5_0_ring_emit_vm_flush */
1644                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1645                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 +
1646                 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */
1647         .emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */
1648         .emit_ib = sdma_v5_0_ring_emit_ib,
1649         .emit_fence = sdma_v5_0_ring_emit_fence,
1650         .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync,
1651         .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush,
1652         .emit_hdp_flush = sdma_v5_0_ring_emit_hdp_flush,
1653         .test_ring = sdma_v5_0_ring_test_ring,
1654         .test_ib = sdma_v5_0_ring_test_ib,
1655         .insert_nop = sdma_v5_0_ring_insert_nop,
1656         .pad_ib = sdma_v5_0_ring_pad_ib,
1657         .emit_wreg = sdma_v5_0_ring_emit_wreg,
1658         .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait,
1659         .emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait,
1660         .init_cond_exec = sdma_v5_0_ring_init_cond_exec,
1661         .patch_cond_exec = sdma_v5_0_ring_patch_cond_exec,
1662         .preempt_ib = sdma_v5_0_ring_preempt_ib,
1663 };
1664
1665 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev)
1666 {
1667         int i;
1668
1669         for (i = 0; i < adev->sdma.num_instances; i++) {
1670                 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs;
1671                 adev->sdma.instance[i].ring.me = i;
1672         }
1673 }
1674
1675 static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs = {
1676         .set = sdma_v5_0_set_trap_irq_state,
1677         .process = sdma_v5_0_process_trap_irq,
1678 };
1679
1680 static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = {
1681         .process = sdma_v5_0_process_illegal_inst_irq,
1682 };
1683
1684 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev)
1685 {
1686         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1687                                         adev->sdma.num_instances;
1688         adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs;
1689         adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs;
1690 }
1691
1692 /**
1693  * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine
1694  *
1695  * @ib: indirect buffer to copy to
1696  * @src_offset: src GPU address
1697  * @dst_offset: dst GPU address
1698  * @byte_count: number of bytes to xfer
1699  * @tmz: if a secure copy should be used
1700  *
1701  * Copy GPU buffers using the DMA engine (NAVI10).
1702  * Used by the amdgpu ttm implementation to move pages if
1703  * registered as the asic copy callback.
1704  */
1705 static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib,
1706                                        uint64_t src_offset,
1707                                        uint64_t dst_offset,
1708                                        uint32_t byte_count,
1709                                        bool tmz)
1710 {
1711         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1712                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1713                 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1714         ib->ptr[ib->length_dw++] = byte_count - 1;
1715         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1716         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1717         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1718         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1719         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1720 }
1721
1722 /**
1723  * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine
1724  *
1725  * @ib: indirect buffer to fill
1726  * @src_data: value to write to buffer
1727  * @dst_offset: dst GPU address
1728  * @byte_count: number of bytes to xfer
1729  *
1730  * Fill GPU buffers using the DMA engine (NAVI10).
1731  */
1732 static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib,
1733                                        uint32_t src_data,
1734                                        uint64_t dst_offset,
1735                                        uint32_t byte_count)
1736 {
1737         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1738         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1739         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1740         ib->ptr[ib->length_dw++] = src_data;
1741         ib->ptr[ib->length_dw++] = byte_count - 1;
1742 }
1743
1744 static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = {
1745         .copy_max_bytes = 0x400000,
1746         .copy_num_dw = 7,
1747         .emit_copy_buffer = sdma_v5_0_emit_copy_buffer,
1748
1749         .fill_max_bytes = 0x400000,
1750         .fill_num_dw = 5,
1751         .emit_fill_buffer = sdma_v5_0_emit_fill_buffer,
1752 };
1753
1754 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev)
1755 {
1756         if (adev->mman.buffer_funcs == NULL) {
1757                 adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs;
1758                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1759         }
1760 }
1761
1762 static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = {
1763         .copy_pte_num_dw = 7,
1764         .copy_pte = sdma_v5_0_vm_copy_pte,
1765         .write_pte = sdma_v5_0_vm_write_pte,
1766         .set_pte_pde = sdma_v5_0_vm_set_pte_pde,
1767 };
1768
1769 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1770 {
1771         unsigned i;
1772
1773         if (adev->vm_manager.vm_pte_funcs == NULL) {
1774                 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs;
1775                 for (i = 0; i < adev->sdma.num_instances; i++) {
1776                         adev->vm_manager.vm_pte_scheds[i] =
1777                                 &adev->sdma.instance[i].ring.sched;
1778                 }
1779                 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1780         }
1781 }
1782
1783 const struct amdgpu_ip_block_version sdma_v5_0_ip_block = {
1784         .type = AMD_IP_BLOCK_TYPE_SDMA,
1785         .major = 5,
1786         .minor = 0,
1787         .rev = 0,
1788         .funcs = &sdma_v5_0_ip_funcs,
1789 };