2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
25 #include <linux/firmware.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
30 #include "amdgpu_ucode.h"
31 #include "amdgpu_trace.h"
33 #include "gc/gc_10_1_0_offset.h"
34 #include "gc/gc_10_1_0_sh_mask.h"
35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
38 #include "soc15_common.h"
40 #include "navi10_sdma_pkt_open.h"
41 #include "nbio_v2_3.h"
42 #include "sdma_common.h"
43 #include "sdma_v5_0.h"
45 MODULE_FIRMWARE("amdgpu/navi10_sdma.bin");
46 MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin");
48 MODULE_FIRMWARE("amdgpu/navi14_sdma.bin");
49 MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin");
51 MODULE_FIRMWARE("amdgpu/navi12_sdma.bin");
52 MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin");
54 #define SDMA1_REG_OFFSET 0x600
55 #define SDMA0_HYP_DEC_REG_START 0x5880
56 #define SDMA0_HYP_DEC_REG_END 0x5893
57 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
59 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev);
60 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev);
61 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev);
62 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev);
64 static const struct soc15_reg_golden golden_settings_sdma_5[] = {
65 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
66 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
67 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
68 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
69 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
70 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
71 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
72 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
73 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
74 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
75 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
76 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00),
77 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
78 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
79 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
80 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
81 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
82 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
83 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
84 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
85 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
86 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
87 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
88 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00)
91 static const struct soc15_reg_golden golden_settings_sdma_5_sriov[] = {
92 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
93 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
94 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
95 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
96 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
97 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
98 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
99 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
114 static const struct soc15_reg_golden golden_settings_sdma_nv10[] = {
115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
119 static const struct soc15_reg_golden golden_settings_sdma_nv14[] = {
120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
124 static const struct soc15_reg_golden golden_settings_sdma_nv12[] = {
125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
133 static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
137 if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
138 internal_offset <= SDMA0_HYP_DEC_REG_END) {
139 base = adev->reg_offset[GC_HWIP][0][1];
141 internal_offset += SDMA1_HYP_DEC_REG_OFFSET;
143 base = adev->reg_offset[GC_HWIP][0][0];
145 internal_offset += SDMA1_REG_OFFSET;
148 return base + internal_offset;
151 static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
153 switch (adev->asic_type) {
155 soc15_program_register_sequence(adev,
156 golden_settings_sdma_5,
157 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
158 soc15_program_register_sequence(adev,
159 golden_settings_sdma_nv10,
160 (const u32)ARRAY_SIZE(golden_settings_sdma_nv10));
163 soc15_program_register_sequence(adev,
164 golden_settings_sdma_5,
165 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
166 soc15_program_register_sequence(adev,
167 golden_settings_sdma_nv14,
168 (const u32)ARRAY_SIZE(golden_settings_sdma_nv14));
171 if (amdgpu_sriov_vf(adev))
172 soc15_program_register_sequence(adev,
173 golden_settings_sdma_5_sriov,
174 (const u32)ARRAY_SIZE(golden_settings_sdma_5_sriov));
176 soc15_program_register_sequence(adev,
177 golden_settings_sdma_5,
178 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
179 soc15_program_register_sequence(adev,
180 golden_settings_sdma_nv12,
181 (const u32)ARRAY_SIZE(golden_settings_sdma_nv12));
189 * sdma_v5_0_init_microcode - load ucode images from disk
191 * @adev: amdgpu_device pointer
193 * Use the firmware interface to load the ucode images into
194 * the driver (not loaded into hw).
195 * Returns 0 on success, error on failure.
198 // emulation only, won't work on real chip
199 // navi10 real chip need to use PSP to load firmware
200 static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
202 const char *chip_name;
205 struct amdgpu_firmware_info *info = NULL;
206 const struct common_firmware_header *header = NULL;
207 const struct sdma_firmware_header_v1_0 *hdr;
209 if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_NAVI12))
214 switch (adev->asic_type) {
216 chip_name = "navi10";
219 chip_name = "navi14";
222 chip_name = "navi12";
228 for (i = 0; i < adev->sdma.num_instances; i++) {
230 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
232 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
233 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
236 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
239 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
240 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
241 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
242 if (adev->sdma.instance[i].feature_version >= 20)
243 adev->sdma.instance[i].burst_nop = true;
244 DRM_DEBUG("psp_load == '%s'\n",
245 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
247 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
248 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
249 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
250 info->fw = adev->sdma.instance[i].fw;
251 header = (const struct common_firmware_header *)info->fw->data;
252 adev->firmware.fw_size +=
253 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
258 DRM_ERROR("sdma_v5_0: Failed to load firmware \"%s\"\n", fw_name);
259 for (i = 0; i < adev->sdma.num_instances; i++) {
260 release_firmware(adev->sdma.instance[i].fw);
261 adev->sdma.instance[i].fw = NULL;
267 static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring)
271 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
272 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
273 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
274 amdgpu_ring_write(ring, 1);
275 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
276 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
281 static void sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring *ring,
286 BUG_ON(offset > ring->buf_mask);
287 BUG_ON(ring->ring[offset] != 0x55aa55aa);
289 cur = (ring->wptr - 1) & ring->buf_mask;
291 ring->ring[offset] = cur - offset;
293 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
297 * sdma_v5_0_ring_get_rptr - get the current read pointer
299 * @ring: amdgpu ring pointer
301 * Get the current rptr from the hardware (NAVI10+).
303 static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
307 /* XXX check if swapping is necessary on BE */
308 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
310 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
311 return ((*rptr) >> 2);
315 * sdma_v5_0_ring_get_wptr - get the current write pointer
317 * @ring: amdgpu ring pointer
319 * Get the current wptr from the hardware (NAVI10+).
321 static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
323 struct amdgpu_device *adev = ring->adev;
326 if (ring->use_doorbell) {
327 /* XXX check if swapping is necessary on BE */
328 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
329 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
331 wptr = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
333 wptr |= RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
334 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
341 * sdma_v5_0_ring_set_wptr - commit the write pointer
343 * @ring: amdgpu ring pointer
345 * Write the wptr back to the hardware (NAVI10+).
347 static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
349 struct amdgpu_device *adev = ring->adev;
351 DRM_DEBUG("Setting write pointer\n");
352 if (ring->use_doorbell) {
353 DRM_DEBUG("Using doorbell -- "
354 "wptr_offs == 0x%08x "
355 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
356 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
358 lower_32_bits(ring->wptr << 2),
359 upper_32_bits(ring->wptr << 2));
360 /* XXX check if swapping is necessary on BE */
361 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
362 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
363 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
364 ring->doorbell_index, ring->wptr << 2);
365 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
367 DRM_DEBUG("Not using doorbell -- "
368 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
369 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
371 lower_32_bits(ring->wptr << 2),
373 upper_32_bits(ring->wptr << 2));
374 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
375 lower_32_bits(ring->wptr << 2));
376 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
377 upper_32_bits(ring->wptr << 2));
381 static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
383 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
386 for (i = 0; i < count; i++)
387 if (sdma && sdma->burst_nop && (i == 0))
388 amdgpu_ring_write(ring, ring->funcs->nop |
389 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
391 amdgpu_ring_write(ring, ring->funcs->nop);
395 * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine
397 * @ring: amdgpu ring pointer
398 * @job: job to retrieve vmid from
399 * @ib: IB object to schedule
402 * Schedule an IB in the DMA ring (NAVI10).
404 static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
405 struct amdgpu_job *job,
406 struct amdgpu_ib *ib,
409 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
410 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
412 /* Invalidate L2, because if we don't do it, we might get stale cache
413 * lines from previous IBs.
415 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
416 amdgpu_ring_write(ring, 0);
417 amdgpu_ring_write(ring, (SDMA_GCR_GL2_INV |
420 SDMA_GCR_GLM_WB) << 16);
421 amdgpu_ring_write(ring, 0xffffff80);
422 amdgpu_ring_write(ring, 0xffff);
424 /* An IB packet must end on a 8 DW boundary--the next dword
425 * must be on a 8-dword boundary. Our IB packet below is 6
426 * dwords long, thus add x number of NOPs, such that, in
427 * modular arithmetic,
428 * wptr + 6 + x = 8k, k >= 0, which in C is,
429 * (wptr + 6 + x) % 8 = 0.
430 * The expression below, is a solution of x.
432 sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
434 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
435 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
436 /* base must be 32 byte aligned */
437 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
438 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
439 amdgpu_ring_write(ring, ib->length_dw);
440 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
441 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
445 * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
447 * @ring: amdgpu ring pointer
449 * Emit an hdp flush packet on the requested DMA ring.
451 static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
453 struct amdgpu_device *adev = ring->adev;
454 u32 ref_and_mask = 0;
455 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
458 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
460 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
462 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
463 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
464 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
465 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
466 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
467 amdgpu_ring_write(ring, ref_and_mask); /* reference */
468 amdgpu_ring_write(ring, ref_and_mask); /* mask */
469 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
470 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
474 * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring
476 * @ring: amdgpu ring pointer
478 * @seq: sequence number
479 * @flags: fence related flags
481 * Add a DMA fence packet to the ring to write
482 * the fence seq number and DMA trap packet to generate
483 * an interrupt if needed (NAVI10).
485 static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
488 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
489 /* write the fence */
490 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
491 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
492 /* zero in first two bits */
494 amdgpu_ring_write(ring, lower_32_bits(addr));
495 amdgpu_ring_write(ring, upper_32_bits(addr));
496 amdgpu_ring_write(ring, lower_32_bits(seq));
498 /* optionally write high bits as well */
501 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
502 SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
503 /* zero in first two bits */
505 amdgpu_ring_write(ring, lower_32_bits(addr));
506 amdgpu_ring_write(ring, upper_32_bits(addr));
507 amdgpu_ring_write(ring, upper_32_bits(seq));
510 if (flags & AMDGPU_FENCE_FLAG_INT) {
511 /* generate an interrupt */
512 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
513 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
519 * sdma_v5_0_gfx_stop - stop the gfx async dma engines
521 * @adev: amdgpu_device pointer
523 * Stop the gfx async dma ring buffers (NAVI10).
525 static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev)
527 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
528 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
529 u32 rb_cntl, ib_cntl;
532 if ((adev->mman.buffer_funcs_ring == sdma0) ||
533 (adev->mman.buffer_funcs_ring == sdma1))
534 amdgpu_ttm_set_buffer_funcs_status(adev, false);
536 for (i = 0; i < adev->sdma.num_instances; i++) {
537 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
538 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
539 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
540 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
541 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
542 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
547 * sdma_v5_0_rlc_stop - stop the compute async dma engines
549 * @adev: amdgpu_device pointer
551 * Stop the compute async dma queues (NAVI10).
553 static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev)
559 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
561 * @adev: amdgpu_device pointer
562 * @enable: enable/disable the DMA MEs context switch.
564 * Halt or unhalt the async dma engines context switch (NAVI10).
566 static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
568 u32 f32_cntl = 0, phase_quantum = 0;
571 if (amdgpu_sdma_phase_quantum) {
572 unsigned value = amdgpu_sdma_phase_quantum;
575 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
576 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
577 value = (value + 1) >> 1;
580 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
581 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
582 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
583 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
584 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
585 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
587 "clamping sdma_phase_quantum to %uK clock cycles\n",
591 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
592 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
595 for (i = 0; i < adev->sdma.num_instances; i++) {
596 if (!amdgpu_sriov_vf(adev)) {
597 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
598 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
599 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
602 if (enable && amdgpu_sdma_phase_quantum) {
603 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
605 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
607 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
610 if (!amdgpu_sriov_vf(adev))
611 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
617 * sdma_v5_0_enable - stop the async dma engines
619 * @adev: amdgpu_device pointer
620 * @enable: enable/disable the DMA MEs.
622 * Halt or unhalt the async dma engines (NAVI10).
624 static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable)
630 sdma_v5_0_gfx_stop(adev);
631 sdma_v5_0_rlc_stop(adev);
634 if (amdgpu_sriov_vf(adev))
637 for (i = 0; i < adev->sdma.num_instances; i++) {
638 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
639 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
640 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
645 * sdma_v5_0_gfx_resume - setup and start the async dma engines
647 * @adev: amdgpu_device pointer
649 * Set up the gfx DMA ring buffers and enable them (NAVI10).
650 * Returns 0 for success, error for failure.
652 static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
654 struct amdgpu_ring *ring;
655 u32 rb_cntl, ib_cntl;
665 for (i = 0; i < adev->sdma.num_instances; i++) {
666 ring = &adev->sdma.instance[i].ring;
667 wb_offset = (ring->rptr_offs * 4);
669 if (!amdgpu_sriov_vf(adev))
670 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
672 /* Set ring buffer size in dwords */
673 rb_bufsz = order_base_2(ring->ring_size / 4);
674 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
675 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
677 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
678 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
679 RPTR_WRITEBACK_SWAP_ENABLE, 1);
681 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
683 /* Initialize the ring buffer's read and write pointers */
684 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
685 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
686 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
687 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
689 /* setup the wptr shadow polling */
690 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
691 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
692 lower_32_bits(wptr_gpu_addr));
693 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
694 upper_32_bits(wptr_gpu_addr));
695 wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i,
696 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
697 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
698 SDMA0_GFX_RB_WPTR_POLL_CNTL,
700 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
703 /* set the wb address whether it's enabled or not */
704 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
705 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
706 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
707 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
709 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
711 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
712 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
716 /* before programing wptr to a less value, need set minor_ptr_update first */
717 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
719 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
720 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
721 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
724 doorbell = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
725 doorbell_offset = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
727 if (ring->use_doorbell) {
728 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
729 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
730 OFFSET, ring->doorbell_index);
732 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
734 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
735 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
737 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
738 ring->doorbell_index, 20);
740 if (amdgpu_sriov_vf(adev))
741 sdma_v5_0_ring_set_wptr(ring);
743 /* set minor_ptr_update to 0 after wptr programed */
744 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
746 if (!amdgpu_sriov_vf(adev)) {
747 /* set utc l1 enable flag always to 1 */
748 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
749 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
752 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
753 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
755 /* Set up RESP_MODE to non-copy addresses */
756 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
757 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
758 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
759 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
761 /* program default cache read and write policy */
762 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
763 /* clean read policy and write policy bits */
765 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14));
766 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
769 if (!amdgpu_sriov_vf(adev)) {
771 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
772 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
773 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
777 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
778 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
780 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
781 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
783 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
786 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
788 ring->sched.ready = true;
790 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
791 sdma_v5_0_ctx_switch_enable(adev, true);
792 sdma_v5_0_enable(adev, true);
795 r = amdgpu_ring_test_helper(ring);
799 if (adev->mman.buffer_funcs_ring == ring)
800 amdgpu_ttm_set_buffer_funcs_status(adev, true);
807 * sdma_v5_0_rlc_resume - setup and start the async dma engines
809 * @adev: amdgpu_device pointer
811 * Set up the compute DMA queues and enable them (NAVI10).
812 * Returns 0 for success, error for failure.
814 static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev)
820 * sdma_v5_0_load_microcode - load the sDMA ME ucode
822 * @adev: amdgpu_device pointer
824 * Loads the sDMA0/1 ucode.
825 * Returns 0 for success, -EINVAL if the ucode is not available.
827 static int sdma_v5_0_load_microcode(struct amdgpu_device *adev)
829 const struct sdma_firmware_header_v1_0 *hdr;
830 const __le32 *fw_data;
835 sdma_v5_0_enable(adev, false);
837 for (i = 0; i < adev->sdma.num_instances; i++) {
838 if (!adev->sdma.instance[i].fw)
841 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
842 amdgpu_ucode_print_sdma_hdr(&hdr->header);
843 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
845 fw_data = (const __le32 *)
846 (adev->sdma.instance[i].fw->data +
847 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
849 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
851 for (j = 0; j < fw_size; j++) {
852 if (amdgpu_emu_mode == 1 && j % 500 == 0)
854 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
857 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
864 * sdma_v5_0_start - setup and start the async dma engines
866 * @adev: amdgpu_device pointer
868 * Set up the DMA engines and enable them (NAVI10).
869 * Returns 0 for success, error for failure.
871 static int sdma_v5_0_start(struct amdgpu_device *adev)
875 if (amdgpu_sriov_vf(adev)) {
876 sdma_v5_0_ctx_switch_enable(adev, false);
877 sdma_v5_0_enable(adev, false);
879 /* set RB registers */
880 r = sdma_v5_0_gfx_resume(adev);
884 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
885 r = sdma_v5_0_load_microcode(adev);
891 sdma_v5_0_enable(adev, true);
892 /* enable sdma ring preemption */
893 sdma_v5_0_ctx_switch_enable(adev, true);
895 /* start the gfx rings and rlc compute queues */
896 r = sdma_v5_0_gfx_resume(adev);
899 r = sdma_v5_0_rlc_resume(adev);
905 * sdma_v5_0_ring_test_ring - simple async dma engine test
907 * @ring: amdgpu_ring structure holding ring information
909 * Test the DMA engine by writing using it to write an
910 * value to memory. (NAVI10).
911 * Returns 0 for success, error for failure.
913 static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring)
915 struct amdgpu_device *adev = ring->adev;
922 r = amdgpu_device_wb_get(adev, &index);
924 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
928 gpu_addr = adev->wb.gpu_addr + (index * 4);
930 adev->wb.wb[index] = cpu_to_le32(tmp);
932 r = amdgpu_ring_alloc(ring, 5);
934 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
935 amdgpu_device_wb_free(adev, index);
939 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
940 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
941 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
942 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
943 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
944 amdgpu_ring_write(ring, 0xDEADBEEF);
945 amdgpu_ring_commit(ring);
947 for (i = 0; i < adev->usec_timeout; i++) {
948 tmp = le32_to_cpu(adev->wb.wb[index]);
949 if (tmp == 0xDEADBEEF)
951 if (amdgpu_emu_mode == 1)
957 if (i >= adev->usec_timeout)
960 amdgpu_device_wb_free(adev, index);
966 * sdma_v5_0_ring_test_ib - test an IB on the DMA engine
968 * @ring: amdgpu_ring structure holding ring information
969 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
971 * Test a simple IB in the DMA ring (NAVI10).
972 * Returns 0 on success, error on failure.
974 static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
976 struct amdgpu_device *adev = ring->adev;
978 struct dma_fence *f = NULL;
984 r = amdgpu_device_wb_get(adev, &index);
986 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
990 gpu_addr = adev->wb.gpu_addr + (index * 4);
992 adev->wb.wb[index] = cpu_to_le32(tmp);
993 memset(&ib, 0, sizeof(ib));
994 r = amdgpu_ib_get(adev, NULL, 256,
995 AMDGPU_IB_POOL_DIRECT, &ib);
997 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1001 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1002 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1003 ib.ptr[1] = lower_32_bits(gpu_addr);
1004 ib.ptr[2] = upper_32_bits(gpu_addr);
1005 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1006 ib.ptr[4] = 0xDEADBEEF;
1007 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1008 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1009 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1012 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1016 r = dma_fence_wait_timeout(f, false, timeout);
1018 DRM_ERROR("amdgpu: IB test timed out\n");
1022 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1025 tmp = le32_to_cpu(adev->wb.wb[index]);
1026 if (tmp == 0xDEADBEEF)
1032 amdgpu_ib_free(adev, &ib, NULL);
1035 amdgpu_device_wb_free(adev, index);
1041 * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART
1043 * @ib: indirect buffer to fill with commands
1044 * @pe: addr of the page entry
1045 * @src: src addr to copy from
1046 * @count: number of page entries to update
1048 * Update PTEs by copying them from the GART using sDMA (NAVI10).
1050 static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib,
1051 uint64_t pe, uint64_t src,
1054 unsigned bytes = count * 8;
1056 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1057 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1058 ib->ptr[ib->length_dw++] = bytes - 1;
1059 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1060 ib->ptr[ib->length_dw++] = lower_32_bits(src);
1061 ib->ptr[ib->length_dw++] = upper_32_bits(src);
1062 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1063 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1068 * sdma_v5_0_vm_write_pte - update PTEs by writing them manually
1070 * @ib: indirect buffer to fill with commands
1071 * @pe: addr of the page entry
1072 * @value: dst addr to write into pe
1073 * @count: number of page entries to update
1074 * @incr: increase next addr by incr bytes
1076 * Update PTEs by writing them manually using sDMA (NAVI10).
1078 static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1079 uint64_t value, unsigned count,
1082 unsigned ndw = count * 2;
1084 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1085 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1086 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1087 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1088 ib->ptr[ib->length_dw++] = ndw - 1;
1089 for (; ndw > 0; ndw -= 2) {
1090 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1091 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1097 * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA
1099 * @ib: indirect buffer to fill with commands
1100 * @pe: addr of the page entry
1101 * @addr: dst addr to write into pe
1102 * @count: number of page entries to update
1103 * @incr: increase next addr by incr bytes
1104 * @flags: access flags
1106 * Update the page tables using sDMA (NAVI10).
1108 static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1110 uint64_t addr, unsigned count,
1111 uint32_t incr, uint64_t flags)
1113 /* for physically contiguous pages (vram) */
1114 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1115 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1116 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1117 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1118 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1119 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1120 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1121 ib->ptr[ib->length_dw++] = incr; /* increment size */
1122 ib->ptr[ib->length_dw++] = 0;
1123 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1127 * sdma_v5_0_ring_pad_ib - pad the IB
1128 * @ring: amdgpu_ring structure holding ring information
1129 * @ib: indirect buffer to fill with padding
1131 * Pad the IB with NOPs to a boundary multiple of 8.
1133 static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1135 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1139 pad_count = (-ib->length_dw) & 0x7;
1140 for (i = 0; i < pad_count; i++)
1141 if (sdma && sdma->burst_nop && (i == 0))
1142 ib->ptr[ib->length_dw++] =
1143 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1144 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1146 ib->ptr[ib->length_dw++] =
1147 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1152 * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline
1154 * @ring: amdgpu_ring pointer
1156 * Make sure all previous operations are completed (CIK).
1158 static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1160 uint32_t seq = ring->fence_drv.sync_seq;
1161 uint64_t addr = ring->fence_drv.gpu_addr;
1164 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1165 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1166 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1167 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1168 amdgpu_ring_write(ring, addr & 0xfffffffc);
1169 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1170 amdgpu_ring_write(ring, seq); /* reference */
1171 amdgpu_ring_write(ring, 0xffffffff); /* mask */
1172 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1173 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1178 * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA
1180 * @ring: amdgpu_ring pointer
1181 * @vmid: vmid number to use
1184 * Update the page table base and flush the VM TLB
1185 * using sDMA (NAVI10).
1187 static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1188 unsigned vmid, uint64_t pd_addr)
1190 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1193 static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring *ring,
1194 uint32_t reg, uint32_t val)
1196 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1197 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1198 amdgpu_ring_write(ring, reg);
1199 amdgpu_ring_write(ring, val);
1202 static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1203 uint32_t val, uint32_t mask)
1205 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1206 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1207 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1208 amdgpu_ring_write(ring, reg << 2);
1209 amdgpu_ring_write(ring, 0);
1210 amdgpu_ring_write(ring, val); /* reference */
1211 amdgpu_ring_write(ring, mask); /* mask */
1212 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1213 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1216 static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1217 uint32_t reg0, uint32_t reg1,
1218 uint32_t ref, uint32_t mask)
1220 amdgpu_ring_emit_wreg(ring, reg0, ref);
1221 /* wait for a cycle to reset vm_inv_eng*_ack */
1222 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1223 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1226 static int sdma_v5_0_early_init(void *handle)
1228 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1230 adev->sdma.num_instances = 2;
1232 sdma_v5_0_set_ring_funcs(adev);
1233 sdma_v5_0_set_buffer_funcs(adev);
1234 sdma_v5_0_set_vm_pte_funcs(adev);
1235 sdma_v5_0_set_irq_funcs(adev);
1241 static int sdma_v5_0_sw_init(void *handle)
1243 struct amdgpu_ring *ring;
1245 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1247 /* SDMA trap event */
1248 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0,
1249 SDMA0_5_0__SRCID__SDMA_TRAP,
1250 &adev->sdma.trap_irq);
1254 /* SDMA trap event */
1255 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1,
1256 SDMA1_5_0__SRCID__SDMA_TRAP,
1257 &adev->sdma.trap_irq);
1261 r = sdma_v5_0_init_microcode(adev);
1263 DRM_ERROR("Failed to load sdma firmware!\n");
1267 for (i = 0; i < adev->sdma.num_instances; i++) {
1268 ring = &adev->sdma.instance[i].ring;
1269 ring->ring_obj = NULL;
1270 ring->use_doorbell = true;
1272 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1273 ring->use_doorbell?"true":"false");
1275 ring->doorbell_index = (i == 0) ?
1276 (adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset
1277 : (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset
1279 sprintf(ring->name, "sdma%d", i);
1280 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1281 (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 :
1282 AMDGPU_SDMA_IRQ_INSTANCE1,
1283 AMDGPU_RING_PRIO_DEFAULT, NULL);
1291 static int sdma_v5_0_sw_fini(void *handle)
1293 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1296 for (i = 0; i < adev->sdma.num_instances; i++) {
1297 release_firmware(adev->sdma.instance[i].fw);
1298 adev->sdma.instance[i].fw = NULL;
1300 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1306 static int sdma_v5_0_hw_init(void *handle)
1309 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1311 sdma_v5_0_init_golden_registers(adev);
1313 r = sdma_v5_0_start(adev);
1318 static int sdma_v5_0_hw_fini(void *handle)
1320 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1322 if (amdgpu_sriov_vf(adev))
1325 sdma_v5_0_ctx_switch_enable(adev, false);
1326 sdma_v5_0_enable(adev, false);
1331 static int sdma_v5_0_suspend(void *handle)
1333 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1335 return sdma_v5_0_hw_fini(adev);
1338 static int sdma_v5_0_resume(void *handle)
1340 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1342 return sdma_v5_0_hw_init(adev);
1345 static bool sdma_v5_0_is_idle(void *handle)
1347 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1350 for (i = 0; i < adev->sdma.num_instances; i++) {
1351 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1353 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1360 static int sdma_v5_0_wait_for_idle(void *handle)
1364 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1366 for (i = 0; i < adev->usec_timeout; i++) {
1367 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1368 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1370 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1377 static int sdma_v5_0_soft_reset(void *handle)
1384 static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring)
1387 struct amdgpu_device *adev = ring->adev;
1389 u64 sdma_gfx_preempt;
1391 amdgpu_sdma_get_index_from_ring(ring, &index);
1393 sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT;
1395 sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT;
1397 /* assert preemption condition */
1398 amdgpu_ring_set_preempt_cond_exec(ring, false);
1400 /* emit the trailing fence */
1401 ring->trail_seq += 1;
1402 amdgpu_ring_alloc(ring, 10);
1403 sdma_v5_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1404 ring->trail_seq, 0);
1405 amdgpu_ring_commit(ring);
1407 /* assert IB preemption */
1408 WREG32(sdma_gfx_preempt, 1);
1410 /* poll the trailing fence */
1411 for (i = 0; i < adev->usec_timeout; i++) {
1412 if (ring->trail_seq ==
1413 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1418 if (i >= adev->usec_timeout) {
1420 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1423 /* deassert IB preemption */
1424 WREG32(sdma_gfx_preempt, 0);
1426 /* deassert the preemption condition */
1427 amdgpu_ring_set_preempt_cond_exec(ring, true);
1431 static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev,
1432 struct amdgpu_irq_src *source,
1434 enum amdgpu_interrupt_state state)
1438 if (!amdgpu_sriov_vf(adev)) {
1439 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ?
1440 sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :
1441 sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);
1443 sdma_cntl = RREG32(reg_offset);
1444 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1445 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1446 WREG32(reg_offset, sdma_cntl);
1452 static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev,
1453 struct amdgpu_irq_src *source,
1454 struct amdgpu_iv_entry *entry)
1456 DRM_DEBUG("IH: SDMA trap\n");
1457 switch (entry->client_id) {
1458 case SOC15_IH_CLIENTID_SDMA0:
1459 switch (entry->ring_id) {
1461 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1474 case SOC15_IH_CLIENTID_SDMA1:
1475 switch (entry->ring_id) {
1477 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1494 static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1495 struct amdgpu_irq_src *source,
1496 struct amdgpu_iv_entry *entry)
1501 static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1507 for (i = 0; i < adev->sdma.num_instances; i++) {
1508 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1509 /* Enable sdma clock gating */
1510 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1511 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1512 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1513 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1514 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1515 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1516 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1517 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1518 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1520 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1522 /* Disable sdma clock gating */
1523 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1524 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1525 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1526 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1527 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1528 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1529 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1530 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1531 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1533 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1538 static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1544 for (i = 0; i < adev->sdma.num_instances; i++) {
1545 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1546 /* Enable sdma mem light sleep */
1547 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1548 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1550 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1553 /* Disable sdma mem light sleep */
1554 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1555 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1557 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1563 static int sdma_v5_0_set_clockgating_state(void *handle,
1564 enum amd_clockgating_state state)
1566 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1568 if (amdgpu_sriov_vf(adev))
1571 switch (adev->asic_type) {
1575 sdma_v5_0_update_medium_grain_clock_gating(adev,
1576 state == AMD_CG_STATE_GATE);
1577 sdma_v5_0_update_medium_grain_light_sleep(adev,
1578 state == AMD_CG_STATE_GATE);
1587 static int sdma_v5_0_set_powergating_state(void *handle,
1588 enum amd_powergating_state state)
1593 static void sdma_v5_0_get_clockgating_state(void *handle, u32 *flags)
1595 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1598 if (amdgpu_sriov_vf(adev))
1601 /* AMD_CG_SUPPORT_SDMA_MGCG */
1602 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
1603 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
1604 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1606 /* AMD_CG_SUPPORT_SDMA_LS */
1607 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1608 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1609 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1612 const struct amd_ip_funcs sdma_v5_0_ip_funcs = {
1613 .name = "sdma_v5_0",
1614 .early_init = sdma_v5_0_early_init,
1616 .sw_init = sdma_v5_0_sw_init,
1617 .sw_fini = sdma_v5_0_sw_fini,
1618 .hw_init = sdma_v5_0_hw_init,
1619 .hw_fini = sdma_v5_0_hw_fini,
1620 .suspend = sdma_v5_0_suspend,
1621 .resume = sdma_v5_0_resume,
1622 .is_idle = sdma_v5_0_is_idle,
1623 .wait_for_idle = sdma_v5_0_wait_for_idle,
1624 .soft_reset = sdma_v5_0_soft_reset,
1625 .set_clockgating_state = sdma_v5_0_set_clockgating_state,
1626 .set_powergating_state = sdma_v5_0_set_powergating_state,
1627 .get_clockgating_state = sdma_v5_0_get_clockgating_state,
1630 static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
1631 .type = AMDGPU_RING_TYPE_SDMA,
1633 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1634 .support_64bit_ptrs = true,
1635 .vmhub = AMDGPU_GFXHUB_0,
1636 .get_rptr = sdma_v5_0_ring_get_rptr,
1637 .get_wptr = sdma_v5_0_ring_get_wptr,
1638 .set_wptr = sdma_v5_0_ring_set_wptr,
1640 5 + /* sdma_v5_0_ring_init_cond_exec */
1641 6 + /* sdma_v5_0_ring_emit_hdp_flush */
1642 3 + /* hdp_invalidate */
1643 6 + /* sdma_v5_0_ring_emit_pipeline_sync */
1644 /* sdma_v5_0_ring_emit_vm_flush */
1645 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1646 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 +
1647 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */
1648 .emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */
1649 .emit_ib = sdma_v5_0_ring_emit_ib,
1650 .emit_fence = sdma_v5_0_ring_emit_fence,
1651 .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync,
1652 .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush,
1653 .emit_hdp_flush = sdma_v5_0_ring_emit_hdp_flush,
1654 .test_ring = sdma_v5_0_ring_test_ring,
1655 .test_ib = sdma_v5_0_ring_test_ib,
1656 .insert_nop = sdma_v5_0_ring_insert_nop,
1657 .pad_ib = sdma_v5_0_ring_pad_ib,
1658 .emit_wreg = sdma_v5_0_ring_emit_wreg,
1659 .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait,
1660 .emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait,
1661 .init_cond_exec = sdma_v5_0_ring_init_cond_exec,
1662 .patch_cond_exec = sdma_v5_0_ring_patch_cond_exec,
1663 .preempt_ib = sdma_v5_0_ring_preempt_ib,
1666 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev)
1670 for (i = 0; i < adev->sdma.num_instances; i++) {
1671 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs;
1672 adev->sdma.instance[i].ring.me = i;
1676 static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs = {
1677 .set = sdma_v5_0_set_trap_irq_state,
1678 .process = sdma_v5_0_process_trap_irq,
1681 static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = {
1682 .process = sdma_v5_0_process_illegal_inst_irq,
1685 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev)
1687 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1688 adev->sdma.num_instances;
1689 adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs;
1690 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs;
1694 * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine
1696 * @ib: indirect buffer to copy to
1697 * @src_offset: src GPU address
1698 * @dst_offset: dst GPU address
1699 * @byte_count: number of bytes to xfer
1700 * @tmz: if a secure copy should be used
1702 * Copy GPU buffers using the DMA engine (NAVI10).
1703 * Used by the amdgpu ttm implementation to move pages if
1704 * registered as the asic copy callback.
1706 static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib,
1707 uint64_t src_offset,
1708 uint64_t dst_offset,
1709 uint32_t byte_count,
1712 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1713 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1714 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1715 ib->ptr[ib->length_dw++] = byte_count - 1;
1716 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1717 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1718 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1719 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1720 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1724 * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine
1726 * @ib: indirect buffer to fill
1727 * @src_data: value to write to buffer
1728 * @dst_offset: dst GPU address
1729 * @byte_count: number of bytes to xfer
1731 * Fill GPU buffers using the DMA engine (NAVI10).
1733 static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib,
1735 uint64_t dst_offset,
1736 uint32_t byte_count)
1738 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1739 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1740 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1741 ib->ptr[ib->length_dw++] = src_data;
1742 ib->ptr[ib->length_dw++] = byte_count - 1;
1745 static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = {
1746 .copy_max_bytes = 0x400000,
1748 .emit_copy_buffer = sdma_v5_0_emit_copy_buffer,
1750 .fill_max_bytes = 0x400000,
1752 .emit_fill_buffer = sdma_v5_0_emit_fill_buffer,
1755 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev)
1757 if (adev->mman.buffer_funcs == NULL) {
1758 adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs;
1759 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1763 static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = {
1764 .copy_pte_num_dw = 7,
1765 .copy_pte = sdma_v5_0_vm_copy_pte,
1766 .write_pte = sdma_v5_0_vm_write_pte,
1767 .set_pte_pde = sdma_v5_0_vm_set_pte_pde,
1770 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1774 if (adev->vm_manager.vm_pte_funcs == NULL) {
1775 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs;
1776 for (i = 0; i < adev->sdma.num_instances; i++) {
1777 adev->vm_manager.vm_pte_scheds[i] =
1778 &adev->sdma.instance[i].ring.sched;
1780 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1784 const struct amdgpu_ip_block_version sdma_v5_0_ip_block = {
1785 .type = AMD_IP_BLOCK_TYPE_SDMA,
1789 .funcs = &sdma_v5_0_ip_funcs,