drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_ucode.h"
  31 #include "amdgpu_trace.h"
  32
  33 #include "gc/gc_10_1_0_offset.h"
  34 #include "gc/gc_10_1_0_sh_mask.h"
  35 #include "hdp/hdp_5_0_0_offset.h"
  36 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
  37 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
  38
  39 #include "soc15_common.h"
  40 #include "soc15.h"
  41 #include "navi10_sdma_pkt_open.h"
  42 #include "nbio_v2_3.h"
  43 #include "sdma_v5_0.h"
  44
  45 MODULE_FIRMWARE("amdgpu/navi10_sdma.bin");
  46 MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin");
  47
  48 MODULE_FIRMWARE("amdgpu/navi14_sdma.bin");
  49 MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin");
  50
  51 MODULE_FIRMWARE("amdgpu/navi12_sdma.bin");
  52 MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin");
  53
  54 #define SDMA1_REG_OFFSET 0x600
  55 #define SDMA0_HYP_DEC_REG_START 0x5880
  56 #define SDMA0_HYP_DEC_REG_END 0x5893
  57 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
  58
  59 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev);
  60 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev);
  61 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  62 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev);
  63
  64 static const struct soc15_reg_golden golden_settings_sdma_5[] = {
  65         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
  66         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  67         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  68         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  69         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  70         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  71         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  72         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  73         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  74         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  75         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  76         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00),
  77         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
  78         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  79         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  80         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  81         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  82         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  83         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  84         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  85         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  86         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  87         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  88         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00)
  89 };
  90
  91 static const struct soc15_reg_golden golden_settings_sdma_5_sriov[] = {
  92         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  93         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  94         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  95         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  96         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  97         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  98         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  99         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 112 };
 113
 114 static const struct soc15_reg_golden golden_settings_sdma_nv10[] = {
 115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 117 };
 118
 119 static const struct soc15_reg_golden golden_settings_sdma_nv14[] = {
 120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 122 };
 123
 124 static const struct soc15_reg_golden golden_settings_sdma_nv12[] = {
 125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 127 };
 128
 129 static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
 130 {
 131         u32 base;
 132
 133         if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
 134             internal_offset <= SDMA0_HYP_DEC_REG_END) {
 135                 base = adev->reg_offset[GC_HWIP][0][1];
 136                 if (instance == 1)
 137                         internal_offset += SDMA1_HYP_DEC_REG_OFFSET;
 138         } else {
 139                 base = adev->reg_offset[GC_HWIP][0][0];
 140                 if (instance == 1)
 141                         internal_offset += SDMA1_REG_OFFSET;
 142         }
 143
 144         return base + internal_offset;
 145 }
 146
 147 static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
 148 {
 149         switch (adev->asic_type) {
 150         case CHIP_NAVI10:
 151                 soc15_program_register_sequence(adev,
 152                                                 golden_settings_sdma_5,
 153                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
 154                 soc15_program_register_sequence(adev,
 155                                                 golden_settings_sdma_nv10,
 156                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_nv10));
 157                 break;
 158         case CHIP_NAVI14:
 159                 soc15_program_register_sequence(adev,
 160                                                 golden_settings_sdma_5,
 161                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
 162                 soc15_program_register_sequence(adev,
 163                                                 golden_settings_sdma_nv14,
 164                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_nv14));
 165                 break;
 166         case CHIP_NAVI12:
 167                 if (amdgpu_sriov_vf(adev))
 168                         soc15_program_register_sequence(adev,
 169                                                         golden_settings_sdma_5_sriov,
 170                                                         (const u32)ARRAY_SIZE(golden_settings_sdma_5_sriov));
 171                 else
 172                         soc15_program_register_sequence(adev,
 173                                                         golden_settings_sdma_5,
 174                                                         (const u32)ARRAY_SIZE(golden_settings_sdma_5));
 175                 soc15_program_register_sequence(adev,
 176                                                 golden_settings_sdma_nv12,
 177                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_nv12));
 178                 break;
 179         default:
 180                 break;
 181         }
 182 }
 183
 184 /**
 185  * sdma_v5_0_init_microcode - load ucode images from disk
 186  *
 187  * @adev: amdgpu_device pointer
 188  *
 189  * Use the firmware interface to load the ucode images into
 190  * the driver (not loaded into hw).
 191  * Returns 0 on success, error on failure.
 192  */
 193
 194 // emulation only, won't work on real chip
 195 // navi10 real chip need to use PSP to load firmware
 196 static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
 197 {
 198         const char *chip_name;
 199         char fw_name[30];
 200         int err = 0, i;
 201         struct amdgpu_firmware_info *info = NULL;
 202         const struct common_firmware_header *header = NULL;
 203         const struct sdma_firmware_header_v1_0 *hdr;
 204
 205         DRM_DEBUG("\n");
 206
 207         switch (adev->asic_type) {
 208         case CHIP_NAVI10:
 209                 chip_name = "navi10";
 210                 break;
 211         case CHIP_NAVI14:
 212                 chip_name = "navi14";
 213                 break;
 214         case CHIP_NAVI12:
 215                 chip_name = "navi12";
 216                 break;
 217         default:
 218                 BUG();
 219         }
 220
 221         for (i = 0; i < adev->sdma.num_instances; i++) {
 222                 if (i == 0)
 223                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 224                 else
 225                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 226                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 227                 if (err)
 228                         goto out;
 229                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 230                 if (err)
 231                         goto out;
 232                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 233                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 234                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 235                 if (adev->sdma.instance[i].feature_version >= 20)
 236                         adev->sdma.instance[i].burst_nop = true;
 237                 DRM_DEBUG("psp_load == '%s'\n",
 238                                 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
 239
 240                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 241                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 242                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 243                         info->fw = adev->sdma.instance[i].fw;
 244                         header = (const struct common_firmware_header *)info->fw->data;
 245                         adev->firmware.fw_size +=
 246                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 247                 }
 248         }
 249 out:
 250         if (err) {
 251                 DRM_ERROR("sdma_v5_0: Failed to load firmware \"%s\"\n", fw_name);
 252                 for (i = 0; i < adev->sdma.num_instances; i++) {
 253                         release_firmware(adev->sdma.instance[i].fw);
 254                         adev->sdma.instance[i].fw = NULL;
 255                 }
 256         }
 257         return err;
 258 }
 259
 260 static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring)
 261 {
 262         unsigned ret;
 263
 264         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
 265         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
 266         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
 267         amdgpu_ring_write(ring, 1);
 268         ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
 269         amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
 270
 271         return ret;
 272 }
 273
 274 static void sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring *ring,
 275                                            unsigned offset)
 276 {
 277         unsigned cur;
 278
 279         BUG_ON(offset > ring->buf_mask);
 280         BUG_ON(ring->ring[offset] != 0x55aa55aa);
 281
 282         cur = (ring->wptr - 1) & ring->buf_mask;
 283         if (cur > offset)
 284                 ring->ring[offset] = cur - offset;
 285         else
 286                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
 287 }
 288
 289 /**
 290  * sdma_v5_0_ring_get_rptr - get the current read pointer
 291  *
 292  * @ring: amdgpu ring pointer
 293  *
 294  * Get the current rptr from the hardware (NAVI10+).
 295  */
 296 static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
 297 {
 298         u64 *rptr;
 299
 300         /* XXX check if swapping is necessary on BE */
 301         rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
 302
 303         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 304         return ((*rptr) >> 2);
 305 }
 306
 307 /**
 308  * sdma_v5_0_ring_get_wptr - get the current write pointer
 309  *
 310  * @ring: amdgpu ring pointer
 311  *
 312  * Get the current wptr from the hardware (NAVI10+).
 313  */
 314 static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
 315 {
 316         struct amdgpu_device *adev = ring->adev;
 317         u64 *wptr = NULL;
 318         uint64_t local_wptr = 0;
 319
 320         if (ring->use_doorbell) {
 321                 /* XXX check if swapping is necessary on BE */
 322                 wptr = ((u64 *)&adev->wb.wb[ring->wptr_offs]);
 323                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", *wptr);
 324                 *wptr = (*wptr) >> 2;
 325                 DRM_DEBUG("wptr/doorbell after shift == 0x%016llx\n", *wptr);
 326         } else {
 327                 u32 lowbit, highbit;
 328
 329                 wptr = &local_wptr;
 330                 lowbit = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)) >> 2;
 331                 highbit = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
 332
 333                 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",
 334                                 ring->me, highbit, lowbit);
 335                 *wptr = highbit;
 336                 *wptr = (*wptr) << 32;
 337                 *wptr |= lowbit;
 338         }
 339
 340         return *wptr;
 341 }
 342
 343 /**
 344  * sdma_v5_0_ring_set_wptr - commit the write pointer
 345  *
 346  * @ring: amdgpu ring pointer
 347  *
 348  * Write the wptr back to the hardware (NAVI10+).
 349  */
 350 static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
 351 {
 352         struct amdgpu_device *adev = ring->adev;
 353
 354         DRM_DEBUG("Setting write pointer\n");
 355         if (ring->use_doorbell) {
 356                 DRM_DEBUG("Using doorbell -- "
 357                                 "wptr_offs == 0x%08x "
 358                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 359                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 360                                 ring->wptr_offs,
 361                                 lower_32_bits(ring->wptr << 2),
 362                                 upper_32_bits(ring->wptr << 2));
 363                 /* XXX check if swapping is necessary on BE */
 364                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
 365                 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
 366                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 367                                 ring->doorbell_index, ring->wptr << 2);
 368                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 369         } else {
 370                 DRM_DEBUG("Not using doorbell -- "
 371                                 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 372                                 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 373                                 ring->me,
 374                                 lower_32_bits(ring->wptr << 2),
 375                                 ring->me,
 376                                 upper_32_bits(ring->wptr << 2));
 377                 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
 378                         lower_32_bits(ring->wptr << 2));
 379                 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
 380                         upper_32_bits(ring->wptr << 2));
 381         }
 382 }
 383
 384 static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 385 {
 386         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 387         int i;
 388
 389         for (i = 0; i < count; i++)
 390                 if (sdma && sdma->burst_nop && (i == 0))
 391                         amdgpu_ring_write(ring, ring->funcs->nop |
 392                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 393                 else
 394                         amdgpu_ring_write(ring, ring->funcs->nop);
 395 }
 396
 397 /**
 398  * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine
 399  *
 400  * @ring: amdgpu ring pointer
 401  * @ib: IB object to schedule
 402  *
 403  * Schedule an IB in the DMA ring (NAVI10).
 404  */
 405 static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
 406                                    struct amdgpu_job *job,
 407                                    struct amdgpu_ib *ib,
 408                                    uint32_t flags)
 409 {
 410         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 411         uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
 412
 413         /* Invalidate L2, because if we don't do it, we might get stale cache
 414          * lines from previous IBs.
 415          */
 416         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
 417         amdgpu_ring_write(ring, 0);
 418         amdgpu_ring_write(ring, (SDMA_GCR_GL2_INV |
 419                                  SDMA_GCR_GL2_WB |
 420                                  SDMA_GCR_GLM_INV |
 421                                  SDMA_GCR_GLM_WB) << 16);
 422         amdgpu_ring_write(ring, 0xffffff80);
 423         amdgpu_ring_write(ring, 0xffff);
 424
 425         /* An IB packet must end on a 8 DW boundary--the next dword
 426          * must be on a 8-dword boundary. Our IB packet below is 6
 427          * dwords long, thus add x number of NOPs, such that, in
 428          * modular arithmetic,
 429          * wptr + 6 + x = 8k, k >= 0, which in C is,
 430          * (wptr + 6 + x) % 8 = 0.
 431          * The expression below, is a solution of x.
 432          */
 433         sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 434
 435         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 436                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 437         /* base must be 32 byte aligned */
 438         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 439         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 440         amdgpu_ring_write(ring, ib->length_dw);
 441         amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
 442         amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
 443 }
 444
 445 /**
 446  * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 447  *
 448  * @ring: amdgpu ring pointer
 449  *
 450  * Emit an hdp flush packet on the requested DMA ring.
 451  */
 452 static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 453 {
 454         struct amdgpu_device *adev = ring->adev;
 455         u32 ref_and_mask = 0;
 456         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 457
 458         if (ring->me == 0)
 459                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
 460         else
 461                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
 462
 463         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 464                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 465                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 466         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
 467         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
 468         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 469         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 470         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 471                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 472 }
 473
 474 /**
 475  * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring
 476  *
 477  * @ring: amdgpu ring pointer
 478  * @fence: amdgpu fence object
 479  *
 480  * Add a DMA fence packet to the ring to write
 481  * the fence seq number and DMA trap packet to generate
 482  * an interrupt if needed (NAVI10).
 483  */
 484 static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 485                                       unsigned flags)
 486 {
 487         struct amdgpu_device *adev = ring->adev;
 488         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 489         /* write the fence */
 490         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 491                           SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
 492         /* zero in first two bits */
 493         BUG_ON(addr & 0x3);
 494         amdgpu_ring_write(ring, lower_32_bits(addr));
 495         amdgpu_ring_write(ring, upper_32_bits(addr));
 496         amdgpu_ring_write(ring, lower_32_bits(seq));
 497
 498         /* optionally write high bits as well */
 499         if (write64bit) {
 500                 addr += 4;
 501                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 502                                   SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
 503                 /* zero in first two bits */
 504                 BUG_ON(addr & 0x3);
 505                 amdgpu_ring_write(ring, lower_32_bits(addr));
 506                 amdgpu_ring_write(ring, upper_32_bits(addr));
 507                 amdgpu_ring_write(ring, upper_32_bits(seq));
 508         }
 509
 510         /* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */
 511         if ((flags & AMDGPU_FENCE_FLAG_INT) && adev->pdev->device != 0x50) {
 512                 /* generate an interrupt */
 513                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 514                 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 515         }
 516 }
 517
 518
 519 /**
 520  * sdma_v5_0_gfx_stop - stop the gfx async dma engines
 521  *
 522  * @adev: amdgpu_device pointer
 523  *
 524  * Stop the gfx async dma ring buffers (NAVI10).
 525  */
 526 static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev)
 527 {
 528         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 529         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 530         u32 rb_cntl, ib_cntl;
 531         int i;
 532
 533         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 534             (adev->mman.buffer_funcs_ring == sdma1))
 535                 amdgpu_ttm_set_buffer_funcs_status(adev, false);
 536
 537         for (i = 0; i < adev->sdma.num_instances; i++) {
 538                 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 539                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 540                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 541                 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 542                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 543                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 544         }
 545 }
 546
 547 /**
 548  * sdma_v5_0_rlc_stop - stop the compute async dma engines
 549  *
 550  * @adev: amdgpu_device pointer
 551  *
 552  * Stop the compute async dma queues (NAVI10).
 553  */
 554 static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev)
 555 {
 556         /* XXX todo */
 557 }
 558
 559 /**
 560  * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
 561  *
 562  * @adev: amdgpu_device pointer
 563  * @enable: enable/disable the DMA MEs context switch.
 564  *
 565  * Halt or unhalt the async dma engines context switch (NAVI10).
 566  */
 567 static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 568 {
 569         u32 f32_cntl = 0, phase_quantum = 0;
 570         int i;
 571
 572         if (amdgpu_sdma_phase_quantum) {
 573                 unsigned value = amdgpu_sdma_phase_quantum;
 574                 unsigned unit = 0;
 575
 576                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 577                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 578                         value = (value + 1) >> 1;
 579                         unit++;
 580                 }
 581                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 582                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 583                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 584                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 585                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 586                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 587                         WARN_ONCE(1,
 588                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 589                                   value << unit);
 590                 }
 591                 phase_quantum =
 592                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 593                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 594         }
 595
 596         for (i = 0; i < adev->sdma.num_instances; i++) {
 597                 if (!amdgpu_sriov_vf(adev)) {
 598                         f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
 599                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 600                                                  AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 601                 }
 602
 603                 if (enable && amdgpu_sdma_phase_quantum) {
 604                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
 605                                phase_quantum);
 606                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
 607                                phase_quantum);
 608                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
 609                                phase_quantum);
 610                 }
 611                 if (!amdgpu_sriov_vf(adev))
 612                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
 613         }
 614
 615 }
 616
 617 /**
 618  * sdma_v5_0_enable - stop the async dma engines
 619  *
 620  * @adev: amdgpu_device pointer
 621  * @enable: enable/disable the DMA MEs.
 622  *
 623  * Halt or unhalt the async dma engines (NAVI10).
 624  */
 625 static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable)
 626 {
 627         u32 f32_cntl;
 628         int i;
 629
 630         if (enable == false) {
 631                 sdma_v5_0_gfx_stop(adev);
 632                 sdma_v5_0_rlc_stop(adev);
 633         }
 634
 635         if (amdgpu_sriov_vf(adev))
 636                 return;
 637
 638         for (i = 0; i < adev->sdma.num_instances; i++) {
 639                 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 640                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 641                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
 642         }
 643 }
 644
 645 /**
 646  * sdma_v5_0_gfx_resume - setup and start the async dma engines
 647  *
 648  * @adev: amdgpu_device pointer
 649  *
 650  * Set up the gfx DMA ring buffers and enable them (NAVI10).
 651  * Returns 0 for success, error for failure.
 652  */
 653 static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
 654 {
 655         struct amdgpu_ring *ring;
 656         u32 rb_cntl, ib_cntl;
 657         u32 rb_bufsz;
 658         u32 wb_offset;
 659         u32 doorbell;
 660         u32 doorbell_offset;
 661         u32 temp;
 662         u32 wptr_poll_cntl;
 663         u64 wptr_gpu_addr;
 664         int i, r;
 665
 666         for (i = 0; i < adev->sdma.num_instances; i++) {
 667                 ring = &adev->sdma.instance[i].ring;
 668                 wb_offset = (ring->rptr_offs * 4);
 669
 670                 if (!amdgpu_sriov_vf(adev))
 671                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 672
 673                 /* Set ring buffer size in dwords */
 674                 rb_bufsz = order_base_2(ring->ring_size / 4);
 675                 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 676                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 677 #ifdef __BIG_ENDIAN
 678                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 679                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 680                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 681 #endif
 682                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 683
 684                 /* Initialize the ring buffer's read and write pointers */
 685                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
 686                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
 687                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
 688                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 689
 690                 /* setup the wptr shadow polling */
 691                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 692                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
 693                        lower_32_bits(wptr_gpu_addr));
 694                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
 695                        upper_32_bits(wptr_gpu_addr));
 696                 wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i,
 697                                                          mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 698                 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 699                                                SDMA0_GFX_RB_WPTR_POLL_CNTL,
 700                                                F32_POLL_ENABLE, 1);
 701                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
 702                        wptr_poll_cntl);
 703
 704                 /* set the wb address whether it's enabled or not */
 705                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
 706                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 707                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
 708                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 709
 710                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 711
 712                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
 713                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
 714
 715                 ring->wptr = 0;
 716
 717                 /* before programing wptr to a less value, need set minor_ptr_update first */
 718                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
 719
 720                 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 721                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
 722                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
 723                 }
 724
 725                 doorbell = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
 726                 doorbell_offset = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
 727
 728                 if (ring->use_doorbell) {
 729                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 730                         doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
 731                                         OFFSET, ring->doorbell_index);
 732                 } else {
 733                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 734                 }
 735                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
 736                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
 737
 738                 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 739                                                       ring->doorbell_index, 20);
 740
 741                 if (amdgpu_sriov_vf(adev))
 742                         sdma_v5_0_ring_set_wptr(ring);
 743
 744                 /* set minor_ptr_update to 0 after wptr programed */
 745                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
 746
 747                 if (!amdgpu_sriov_vf(adev)) {
 748                         /* set utc l1 enable flag always to 1 */
 749                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
 750                         temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
 751
 752                         /* enable MCBP */
 753                         temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
 754                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
 755
 756                         /* Set up RESP_MODE to non-copy addresses */
 757                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
 758                         temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
 759                         temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
 760                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
 761
 762                         /* program default cache read and write policy */
 763                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
 764                         /* clean read policy and write policy bits */
 765                         temp &= 0xFF0FFF;
 766                         temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14));
 767                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
 768                 }
 769
 770                 if (!amdgpu_sriov_vf(adev)) {
 771                         /* unhalt engine */
 772                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 773                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 774                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
 775                 }
 776
 777                 /* enable DMA RB */
 778                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 779                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 780
 781                 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 782                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 783 #ifdef __BIG_ENDIAN
 784                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 785 #endif
 786                 /* enable DMA IBs */
 787                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 788
 789                 ring->sched.ready = true;
 790
 791                 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
 792                         sdma_v5_0_ctx_switch_enable(adev, true);
 793                         sdma_v5_0_enable(adev, true);
 794                 }
 795
 796                 r = amdgpu_ring_test_helper(ring);
 797                 if (r)
 798                         return r;
 799
 800                 if (adev->mman.buffer_funcs_ring == ring)
 801                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 802         }
 803
 804         return 0;
 805 }
 806
 807 /**
 808  * sdma_v5_0_rlc_resume - setup and start the async dma engines
 809  *
 810  * @adev: amdgpu_device pointer
 811  *
 812  * Set up the compute DMA queues and enable them (NAVI10).
 813  * Returns 0 for success, error for failure.
 814  */
 815 static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev)
 816 {
 817         return 0;
 818 }
 819
 820 /**
 821  * sdma_v5_0_load_microcode - load the sDMA ME ucode
 822  *
 823  * @adev: amdgpu_device pointer
 824  *
 825  * Loads the sDMA0/1 ucode.
 826  * Returns 0 for success, -EINVAL if the ucode is not available.
 827  */
 828 static int sdma_v5_0_load_microcode(struct amdgpu_device *adev)
 829 {
 830         const struct sdma_firmware_header_v1_0 *hdr;
 831         const __le32 *fw_data;
 832         u32 fw_size;
 833         int i, j;
 834
 835         /* halt the MEs */
 836         sdma_v5_0_enable(adev, false);
 837
 838         for (i = 0; i < adev->sdma.num_instances; i++) {
 839                 if (!adev->sdma.instance[i].fw)
 840                         return -EINVAL;
 841
 842                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 843                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 844                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 845
 846                 fw_data = (const __le32 *)
 847                         (adev->sdma.instance[i].fw->data +
 848                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 849
 850                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
 851
 852                 for (j = 0; j < fw_size; j++) {
 853                         if (amdgpu_emu_mode == 1 && j % 500 == 0)
 854                                 msleep(1);
 855                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 856                 }
 857
 858                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
 859         }
 860
 861         return 0;
 862 }
 863
 864 /**
 865  * sdma_v5_0_start - setup and start the async dma engines
 866  *
 867  * @adev: amdgpu_device pointer
 868  *
 869  * Set up the DMA engines and enable them (NAVI10).
 870  * Returns 0 for success, error for failure.
 871  */
 872 static int sdma_v5_0_start(struct amdgpu_device *adev)
 873 {
 874         int r = 0;
 875
 876         if (amdgpu_sriov_vf(adev)) {
 877                 sdma_v5_0_ctx_switch_enable(adev, false);
 878                 sdma_v5_0_enable(adev, false);
 879
 880                 /* set RB registers */
 881                 r = sdma_v5_0_gfx_resume(adev);
 882                 return r;
 883         }
 884
 885         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 886                 r = sdma_v5_0_load_microcode(adev);
 887                 if (r)
 888                         return r;
 889
 890                 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */
 891                 if (amdgpu_emu_mode == 1 && adev->pdev->device == 0x4d)
 892                         msleep(1000);
 893         }
 894
 895         /* unhalt the MEs */
 896         sdma_v5_0_enable(adev, true);
 897         /* enable sdma ring preemption */
 898         sdma_v5_0_ctx_switch_enable(adev, true);
 899
 900         /* start the gfx rings and rlc compute queues */
 901         r = sdma_v5_0_gfx_resume(adev);
 902         if (r)
 903                 return r;
 904         r = sdma_v5_0_rlc_resume(adev);
 905
 906         return r;
 907 }
 908
 909 /**
 910  * sdma_v5_0_ring_test_ring - simple async dma engine test
 911  *
 912  * @ring: amdgpu_ring structure holding ring information
 913  *
 914  * Test the DMA engine by writing using it to write an
 915  * value to memory. (NAVI10).
 916  * Returns 0 for success, error for failure.
 917  */
 918 static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring)
 919 {
 920         struct amdgpu_device *adev = ring->adev;
 921         unsigned i;
 922         unsigned index;
 923         int r;
 924         u32 tmp;
 925         u64 gpu_addr;
 926
 927         r = amdgpu_device_wb_get(adev, &index);
 928         if (r) {
 929                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 930                 return r;
 931         }
 932
 933         gpu_addr = adev->wb.gpu_addr + (index * 4);
 934         tmp = 0xCAFEDEAD;
 935         adev->wb.wb[index] = cpu_to_le32(tmp);
 936
 937         r = amdgpu_ring_alloc(ring, 5);
 938         if (r) {
 939                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 940                 amdgpu_device_wb_free(adev, index);
 941                 return r;
 942         }
 943
 944         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 945                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 946         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 947         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 948         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 949         amdgpu_ring_write(ring, 0xDEADBEEF);
 950         amdgpu_ring_commit(ring);
 951
 952         for (i = 0; i < adev->usec_timeout; i++) {
 953                 tmp = le32_to_cpu(adev->wb.wb[index]);
 954                 if (tmp == 0xDEADBEEF)
 955                         break;
 956                 if (amdgpu_emu_mode == 1)
 957                         msleep(1);
 958                 else
 959                         udelay(1);
 960         }
 961
 962         if (i >= adev->usec_timeout)
 963                 r = -ETIMEDOUT;
 964
 965         amdgpu_device_wb_free(adev, index);
 966
 967         return r;
 968 }
 969
 970 /**
 971  * sdma_v5_0_ring_test_ib - test an IB on the DMA engine
 972  *
 973  * @ring: amdgpu_ring structure holding ring information
 974  *
 975  * Test a simple IB in the DMA ring (NAVI10).
 976  * Returns 0 on success, error on failure.
 977  */
 978 static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 979 {
 980         struct amdgpu_device *adev = ring->adev;
 981         struct amdgpu_ib ib;
 982         struct dma_fence *f = NULL;
 983         unsigned index;
 984         long r;
 985         u32 tmp = 0;
 986         u64 gpu_addr;
 987
 988         r = amdgpu_device_wb_get(adev, &index);
 989         if (r) {
 990                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 991                 return r;
 992         }
 993
 994         gpu_addr = adev->wb.gpu_addr + (index * 4);
 995         tmp = 0xCAFEDEAD;
 996         adev->wb.wb[index] = cpu_to_le32(tmp);
 997         memset(&ib, 0, sizeof(ib));
 998         r = amdgpu_ib_get(adev, NULL, 256,
 999                                         AMDGPU_IB_POOL_DIRECT, &ib);
1000         if (r) {
1001                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1002                 goto err0;
1003         }
1004
1005         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1006                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1007         ib.ptr[1] = lower_32_bits(gpu_addr);
1008         ib.ptr[2] = upper_32_bits(gpu_addr);
1009         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1010         ib.ptr[4] = 0xDEADBEEF;
1011         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1012         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1013         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1014         ib.length_dw = 8;
1015
1016         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1017         if (r)
1018                 goto err1;
1019
1020         r = dma_fence_wait_timeout(f, false, timeout);
1021         if (r == 0) {
1022                 DRM_ERROR("amdgpu: IB test timed out\n");
1023                 r = -ETIMEDOUT;
1024                 goto err1;
1025         } else if (r < 0) {
1026                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1027                 goto err1;
1028         }
1029         tmp = le32_to_cpu(adev->wb.wb[index]);
1030         if (tmp == 0xDEADBEEF)
1031                 r = 0;
1032         else
1033                 r = -EINVAL;
1034
1035 err1:
1036         amdgpu_ib_free(adev, &ib, NULL);
1037         dma_fence_put(f);
1038 err0:
1039         amdgpu_device_wb_free(adev, index);
1040         return r;
1041 }
1042
1043
1044 /**
1045  * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART
1046  *
1047  * @ib: indirect buffer to fill with commands
1048  * @pe: addr of the page entry
1049  * @src: src addr to copy from
1050  * @count: number of page entries to update
1051  *
1052  * Update PTEs by copying them from the GART using sDMA (NAVI10).
1053  */
1054 static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib,
1055                                   uint64_t pe, uint64_t src,
1056                                   unsigned count)
1057 {
1058         unsigned bytes = count * 8;
1059
1060         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1061                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1062         ib->ptr[ib->length_dw++] = bytes - 1;
1063         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1064         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1065         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1066         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1067         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1068
1069 }
1070
1071 /**
1072  * sdma_v5_0_vm_write_pte - update PTEs by writing them manually
1073  *
1074  * @ib: indirect buffer to fill with commands
1075  * @pe: addr of the page entry
1076  * @addr: dst addr to write into pe
1077  * @count: number of page entries to update
1078  * @incr: increase next addr by incr bytes
1079  * @flags: access flags
1080  *
1081  * Update PTEs by writing them manually using sDMA (NAVI10).
1082  */
1083 static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1084                                    uint64_t value, unsigned count,
1085                                    uint32_t incr)
1086 {
1087         unsigned ndw = count * 2;
1088
1089         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1090                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1091         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1092         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1093         ib->ptr[ib->length_dw++] = ndw - 1;
1094         for (; ndw > 0; ndw -= 2) {
1095                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1096                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1097                 value += incr;
1098         }
1099 }
1100
1101 /**
1102  * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA
1103  *
1104  * @ib: indirect buffer to fill with commands
1105  * @pe: addr of the page entry
1106  * @addr: dst addr to write into pe
1107  * @count: number of page entries to update
1108  * @incr: increase next addr by incr bytes
1109  * @flags: access flags
1110  *
1111  * Update the page tables using sDMA (NAVI10).
1112  */
1113 static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1114                                      uint64_t pe,
1115                                      uint64_t addr, unsigned count,
1116                                      uint32_t incr, uint64_t flags)
1117 {
1118         /* for physically contiguous pages (vram) */
1119         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1120         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1121         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1122         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1123         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1124         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1125         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1126         ib->ptr[ib->length_dw++] = incr; /* increment size */
1127         ib->ptr[ib->length_dw++] = 0;
1128         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1129 }
1130
1131 /**
1132  * sdma_v5_0_ring_pad_ib - pad the IB
1133  * @ib: indirect buffer to fill with padding
1134  *
1135  * Pad the IB with NOPs to a boundary multiple of 8.
1136  */
1137 static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1138 {
1139         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1140         u32 pad_count;
1141         int i;
1142
1143         pad_count = (-ib->length_dw) & 0x7;
1144         for (i = 0; i < pad_count; i++)
1145                 if (sdma && sdma->burst_nop && (i == 0))
1146                         ib->ptr[ib->length_dw++] =
1147                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1148                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1149                 else
1150                         ib->ptr[ib->length_dw++] =
1151                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1152 }
1153
1154
1155 /**
1156  * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline
1157  *
1158  * @ring: amdgpu_ring pointer
1159  *
1160  * Make sure all previous operations are completed (CIK).
1161  */
1162 static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1163 {
1164         uint32_t seq = ring->fence_drv.sync_seq;
1165         uint64_t addr = ring->fence_drv.gpu_addr;
1166
1167         /* wait for idle */
1168         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1169                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1170                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1171                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1172         amdgpu_ring_write(ring, addr & 0xfffffffc);
1173         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1174         amdgpu_ring_write(ring, seq); /* reference */
1175         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1176         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1177                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1178 }
1179
1180
1181 /**
1182  * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA
1183  *
1184  * @ring: amdgpu_ring pointer
1185  * @vm: amdgpu_vm pointer
1186  *
1187  * Update the page table base and flush the VM TLB
1188  * using sDMA (NAVI10).
1189  */
1190 static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1191                                          unsigned vmid, uint64_t pd_addr)
1192 {
1193         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1194 }
1195
1196 static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring *ring,
1197                                      uint32_t reg, uint32_t val)
1198 {
1199         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1200                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1201         amdgpu_ring_write(ring, reg);
1202         amdgpu_ring_write(ring, val);
1203 }
1204
1205 static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1206                                          uint32_t val, uint32_t mask)
1207 {
1208         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1209                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1210                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1211         amdgpu_ring_write(ring, reg << 2);
1212         amdgpu_ring_write(ring, 0);
1213         amdgpu_ring_write(ring, val); /* reference */
1214         amdgpu_ring_write(ring, mask); /* mask */
1215         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1216                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1217 }
1218
1219 static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1220                                                    uint32_t reg0, uint32_t reg1,
1221                                                    uint32_t ref, uint32_t mask)
1222 {
1223         amdgpu_ring_emit_wreg(ring, reg0, ref);
1224         /* wait for a cycle to reset vm_inv_eng*_ack */
1225         amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1226         amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1227 }
1228
1229 static int sdma_v5_0_early_init(void *handle)
1230 {
1231         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1232
1233         adev->sdma.num_instances = 2;
1234
1235         sdma_v5_0_set_ring_funcs(adev);
1236         sdma_v5_0_set_buffer_funcs(adev);
1237         sdma_v5_0_set_vm_pte_funcs(adev);
1238         sdma_v5_0_set_irq_funcs(adev);
1239
1240         return 0;
1241 }
1242
1243
1244 static int sdma_v5_0_sw_init(void *handle)
1245 {
1246         struct amdgpu_ring *ring;
1247         int r, i;
1248         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1249
1250         /* SDMA trap event */
1251         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0,
1252                               SDMA0_5_0__SRCID__SDMA_TRAP,
1253                               &adev->sdma.trap_irq);
1254         if (r)
1255                 return r;
1256
1257         /* SDMA trap event */
1258         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1,
1259                               SDMA1_5_0__SRCID__SDMA_TRAP,
1260                               &adev->sdma.trap_irq);
1261         if (r)
1262                 return r;
1263
1264         r = sdma_v5_0_init_microcode(adev);
1265         if (r) {
1266                 DRM_ERROR("Failed to load sdma firmware!\n");
1267                 return r;
1268         }
1269
1270         for (i = 0; i < adev->sdma.num_instances; i++) {
1271                 ring = &adev->sdma.instance[i].ring;
1272                 ring->ring_obj = NULL;
1273                 ring->use_doorbell = true;
1274
1275                 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1276                                 ring->use_doorbell?"true":"false");
1277
1278                 ring->doorbell_index = (i == 0) ?
1279                         (adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset
1280                         : (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset
1281
1282                 sprintf(ring->name, "sdma%d", i);
1283                 r = amdgpu_ring_init(adev, ring, 1024,
1284                                      &adev->sdma.trap_irq,
1285                                      (i == 0) ?
1286                                      AMDGPU_SDMA_IRQ_INSTANCE0 :
1287                                      AMDGPU_SDMA_IRQ_INSTANCE1,
1288                                      AMDGPU_RING_PRIO_DEFAULT);
1289                 if (r)
1290                         return r;
1291         }
1292
1293         return r;
1294 }
1295
1296 static int sdma_v5_0_sw_fini(void *handle)
1297 {
1298         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1299         int i;
1300
1301         for (i = 0; i < adev->sdma.num_instances; i++) {
1302                 if (adev->sdma.instance[i].fw != NULL)
1303                         release_firmware(adev->sdma.instance[i].fw);
1304
1305                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1306         }
1307
1308         return 0;
1309 }
1310
1311 static int sdma_v5_0_hw_init(void *handle)
1312 {
1313         int r;
1314         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1315
1316         sdma_v5_0_init_golden_registers(adev);
1317
1318         r = sdma_v5_0_start(adev);
1319
1320         return r;
1321 }
1322
1323 static int sdma_v5_0_hw_fini(void *handle)
1324 {
1325         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1326
1327         if (amdgpu_sriov_vf(adev))
1328                 return 0;
1329
1330         sdma_v5_0_ctx_switch_enable(adev, false);
1331         sdma_v5_0_enable(adev, false);
1332
1333         return 0;
1334 }
1335
1336 static int sdma_v5_0_suspend(void *handle)
1337 {
1338         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1339
1340         return sdma_v5_0_hw_fini(adev);
1341 }
1342
1343 static int sdma_v5_0_resume(void *handle)
1344 {
1345         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1346
1347         return sdma_v5_0_hw_init(adev);
1348 }
1349
1350 static bool sdma_v5_0_is_idle(void *handle)
1351 {
1352         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1353         u32 i;
1354
1355         for (i = 0; i < adev->sdma.num_instances; i++) {
1356                 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1357
1358                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1359                         return false;
1360         }
1361
1362         return true;
1363 }
1364
1365 static int sdma_v5_0_wait_for_idle(void *handle)
1366 {
1367         unsigned i;
1368         u32 sdma0, sdma1;
1369         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1370
1371         for (i = 0; i < adev->usec_timeout; i++) {
1372                 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1373                 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1374
1375                 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1376                         return 0;
1377                 udelay(1);
1378         }
1379         return -ETIMEDOUT;
1380 }
1381
1382 static int sdma_v5_0_soft_reset(void *handle)
1383 {
1384         /* todo */
1385
1386         return 0;
1387 }
1388
1389 static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring)
1390 {
1391         int i, r = 0;
1392         struct amdgpu_device *adev = ring->adev;
1393         u32 index = 0;
1394         u64 sdma_gfx_preempt;
1395
1396         amdgpu_sdma_get_index_from_ring(ring, &index);
1397         if (index == 0)
1398                 sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT;
1399         else
1400                 sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT;
1401
1402         /* assert preemption condition */
1403         amdgpu_ring_set_preempt_cond_exec(ring, false);
1404
1405         /* emit the trailing fence */
1406         ring->trail_seq += 1;
1407         amdgpu_ring_alloc(ring, 10);
1408         sdma_v5_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1409                                   ring->trail_seq, 0);
1410         amdgpu_ring_commit(ring);
1411
1412         /* assert IB preemption */
1413         WREG32(sdma_gfx_preempt, 1);
1414
1415         /* poll the trailing fence */
1416         for (i = 0; i < adev->usec_timeout; i++) {
1417                 if (ring->trail_seq ==
1418                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1419                         break;
1420                 udelay(1);
1421         }
1422
1423         if (i >= adev->usec_timeout) {
1424                 r = -EINVAL;
1425                 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1426         }
1427
1428         /* deassert IB preemption */
1429         WREG32(sdma_gfx_preempt, 0);
1430
1431         /* deassert the preemption condition */
1432         amdgpu_ring_set_preempt_cond_exec(ring, true);
1433         return r;
1434 }
1435
1436 static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev,
1437                                         struct amdgpu_irq_src *source,
1438                                         unsigned type,
1439                                         enum amdgpu_interrupt_state state)
1440 {
1441         u32 sdma_cntl;
1442
1443         if (!amdgpu_sriov_vf(adev)) {
1444                 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ?
1445                         sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :
1446                         sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);
1447
1448                 sdma_cntl = RREG32(reg_offset);
1449                 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1450                                           state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1451                 WREG32(reg_offset, sdma_cntl);
1452         }
1453
1454         return 0;
1455 }
1456
1457 static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev,
1458                                       struct amdgpu_irq_src *source,
1459                                       struct amdgpu_iv_entry *entry)
1460 {
1461         DRM_DEBUG("IH: SDMA trap\n");
1462         switch (entry->client_id) {
1463         case SOC15_IH_CLIENTID_SDMA0:
1464                 switch (entry->ring_id) {
1465                 case 0:
1466                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1467                         break;
1468                 case 1:
1469                         /* XXX compute */
1470                         break;
1471                 case 2:
1472                         /* XXX compute */
1473                         break;
1474                 case 3:
1475                         /* XXX page queue*/
1476                         break;
1477                 }
1478                 break;
1479         case SOC15_IH_CLIENTID_SDMA1:
1480                 switch (entry->ring_id) {
1481                 case 0:
1482                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1483                         break;
1484                 case 1:
1485                         /* XXX compute */
1486                         break;
1487                 case 2:
1488                         /* XXX compute */
1489                         break;
1490                 case 3:
1491                         /* XXX page queue*/
1492                         break;
1493                 }
1494                 break;
1495         }
1496         return 0;
1497 }
1498
1499 static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1500                                               struct amdgpu_irq_src *source,
1501                                               struct amdgpu_iv_entry *entry)
1502 {
1503         return 0;
1504 }
1505
1506 static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1507                                                        bool enable)
1508 {
1509         uint32_t data, def;
1510         int i;
1511
1512         for (i = 0; i < adev->sdma.num_instances; i++) {
1513                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1514                         /* Enable sdma clock gating */
1515                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1516                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1517                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1518                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1519                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1520                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1521                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1522                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1523                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1524                         if (def != data)
1525                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1526                 } else {
1527                         /* Disable sdma clock gating */
1528                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1529                         data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1530                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1531                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1532                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1533                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1534                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1535                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1536                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1537                         if (def != data)
1538                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1539                 }
1540         }
1541 }
1542
1543 static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1544                                                       bool enable)
1545 {
1546         uint32_t data, def;
1547         int i;
1548
1549         for (i = 0; i < adev->sdma.num_instances; i++) {
1550                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1551                         /* Enable sdma mem light sleep */
1552                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1553                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1554                         if (def != data)
1555                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1556
1557                 } else {
1558                         /* Disable sdma mem light sleep */
1559                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1560                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1561                         if (def != data)
1562                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1563
1564                 }
1565         }
1566 }
1567
1568 static int sdma_v5_0_set_clockgating_state(void *handle,
1569                                            enum amd_clockgating_state state)
1570 {
1571         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1572
1573         if (amdgpu_sriov_vf(adev))
1574                 return 0;
1575
1576         switch (adev->asic_type) {
1577         case CHIP_NAVI10:
1578         case CHIP_NAVI14:
1579         case CHIP_NAVI12:
1580                 sdma_v5_0_update_medium_grain_clock_gating(adev,
1581                                 state == AMD_CG_STATE_GATE);
1582                 sdma_v5_0_update_medium_grain_light_sleep(adev,
1583                                 state == AMD_CG_STATE_GATE);
1584                 break;
1585         default:
1586                 break;
1587         }
1588
1589         return 0;
1590 }
1591
1592 static int sdma_v5_0_set_powergating_state(void *handle,
1593                                           enum amd_powergating_state state)
1594 {
1595         return 0;
1596 }
1597
1598 static void sdma_v5_0_get_clockgating_state(void *handle, u32 *flags)
1599 {
1600         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1601         int data;
1602
1603         if (amdgpu_sriov_vf(adev))
1604                 *flags = 0;
1605
1606         /* AMD_CG_SUPPORT_SDMA_MGCG */
1607         data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
1608         if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
1609                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1610
1611         /* AMD_CG_SUPPORT_SDMA_LS */
1612         data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1613         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1614                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1615 }
1616
1617 const struct amd_ip_funcs sdma_v5_0_ip_funcs = {
1618         .name = "sdma_v5_0",
1619         .early_init = sdma_v5_0_early_init,
1620         .late_init = NULL,
1621         .sw_init = sdma_v5_0_sw_init,
1622         .sw_fini = sdma_v5_0_sw_fini,
1623         .hw_init = sdma_v5_0_hw_init,
1624         .hw_fini = sdma_v5_0_hw_fini,
1625         .suspend = sdma_v5_0_suspend,
1626         .resume = sdma_v5_0_resume,
1627         .is_idle = sdma_v5_0_is_idle,
1628         .wait_for_idle = sdma_v5_0_wait_for_idle,
1629         .soft_reset = sdma_v5_0_soft_reset,
1630         .set_clockgating_state = sdma_v5_0_set_clockgating_state,
1631         .set_powergating_state = sdma_v5_0_set_powergating_state,
1632         .get_clockgating_state = sdma_v5_0_get_clockgating_state,
1633 };
1634
1635 static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
1636         .type = AMDGPU_RING_TYPE_SDMA,
1637         .align_mask = 0xf,
1638         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1639         .support_64bit_ptrs = true,
1640         .vmhub = AMDGPU_GFXHUB_0,
1641         .get_rptr = sdma_v5_0_ring_get_rptr,
1642         .get_wptr = sdma_v5_0_ring_get_wptr,
1643         .set_wptr = sdma_v5_0_ring_set_wptr,
1644         .emit_frame_size =
1645                 5 + /* sdma_v5_0_ring_init_cond_exec */
1646                 6 + /* sdma_v5_0_ring_emit_hdp_flush */
1647                 3 + /* hdp_invalidate */
1648                 6 + /* sdma_v5_0_ring_emit_pipeline_sync */
1649                 /* sdma_v5_0_ring_emit_vm_flush */
1650                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1651                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 +
1652                 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */
1653         .emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */
1654         .emit_ib = sdma_v5_0_ring_emit_ib,
1655         .emit_fence = sdma_v5_0_ring_emit_fence,
1656         .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync,
1657         .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush,
1658         .emit_hdp_flush = sdma_v5_0_ring_emit_hdp_flush,
1659         .test_ring = sdma_v5_0_ring_test_ring,
1660         .test_ib = sdma_v5_0_ring_test_ib,
1661         .insert_nop = sdma_v5_0_ring_insert_nop,
1662         .pad_ib = sdma_v5_0_ring_pad_ib,
1663         .emit_wreg = sdma_v5_0_ring_emit_wreg,
1664         .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait,
1665         .emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait,
1666         .init_cond_exec = sdma_v5_0_ring_init_cond_exec,
1667         .patch_cond_exec = sdma_v5_0_ring_patch_cond_exec,
1668         .preempt_ib = sdma_v5_0_ring_preempt_ib,
1669 };
1670
1671 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev)
1672 {
1673         int i;
1674
1675         for (i = 0; i < adev->sdma.num_instances; i++) {
1676                 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs;
1677                 adev->sdma.instance[i].ring.me = i;
1678         }
1679 }
1680
1681 static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs = {
1682         .set = sdma_v5_0_set_trap_irq_state,
1683         .process = sdma_v5_0_process_trap_irq,
1684 };
1685
1686 static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = {
1687         .process = sdma_v5_0_process_illegal_inst_irq,
1688 };
1689
1690 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev)
1691 {
1692         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1693                                         adev->sdma.num_instances;
1694         adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs;
1695         adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs;
1696 }
1697
1698 /**
1699  * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine
1700  *
1701  * @ring: amdgpu_ring structure holding ring information
1702  * @src_offset: src GPU address
1703  * @dst_offset: dst GPU address
1704  * @byte_count: number of bytes to xfer
1705  *
1706  * Copy GPU buffers using the DMA engine (NAVI10).
1707  * Used by the amdgpu ttm implementation to move pages if
1708  * registered as the asic copy callback.
1709  */
1710 static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib,
1711                                        uint64_t src_offset,
1712                                        uint64_t dst_offset,
1713                                        uint32_t byte_count,
1714                                        bool tmz)
1715 {
1716         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1717                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1718                 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1719         ib->ptr[ib->length_dw++] = byte_count - 1;
1720         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1721         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1722         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1723         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1724         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1725 }
1726
1727 /**
1728  * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine
1729  *
1730  * @ring: amdgpu_ring structure holding ring information
1731  * @src_data: value to write to buffer
1732  * @dst_offset: dst GPU address
1733  * @byte_count: number of bytes to xfer
1734  *
1735  * Fill GPU buffers using the DMA engine (NAVI10).
1736  */
1737 static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib,
1738                                        uint32_t src_data,
1739                                        uint64_t dst_offset,
1740                                        uint32_t byte_count)
1741 {
1742         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1743         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1744         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1745         ib->ptr[ib->length_dw++] = src_data;
1746         ib->ptr[ib->length_dw++] = byte_count - 1;
1747 }
1748
1749 static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = {
1750         .copy_max_bytes = 0x400000,
1751         .copy_num_dw = 7,
1752         .emit_copy_buffer = sdma_v5_0_emit_copy_buffer,
1753
1754         .fill_max_bytes = 0x400000,
1755         .fill_num_dw = 5,
1756         .emit_fill_buffer = sdma_v5_0_emit_fill_buffer,
1757 };
1758
1759 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev)
1760 {
1761         if (adev->mman.buffer_funcs == NULL) {
1762                 adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs;
1763                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1764         }
1765 }
1766
1767 static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = {
1768         .copy_pte_num_dw = 7,
1769         .copy_pte = sdma_v5_0_vm_copy_pte,
1770         .write_pte = sdma_v5_0_vm_write_pte,
1771         .set_pte_pde = sdma_v5_0_vm_set_pte_pde,
1772 };
1773
1774 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1775 {
1776         unsigned i;
1777
1778         if (adev->vm_manager.vm_pte_funcs == NULL) {
1779                 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs;
1780                 for (i = 0; i < adev->sdma.num_instances; i++) {
1781                         adev->vm_manager.vm_pte_scheds[i] =
1782                                 &adev->sdma.instance[i].ring.sched;
1783                 }
1784                 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1785         }
1786 }
1787
1788 const struct amdgpu_ip_block_version sdma_v5_0_ip_block = {
1789         .type = AMD_IP_BLOCK_TYPE_SDMA,
1790         .major = 5,
1791         .minor = 0,
1792         .rev = 0,
1793         .funcs = &sdma_v5_0_ip_funcs,
1794 };