2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
25 #include <linux/firmware.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
30 #include "amdgpu_ucode.h"
31 #include "amdgpu_trace.h"
33 #include "gc/gc_10_1_0_offset.h"
34 #include "gc/gc_10_1_0_sh_mask.h"
35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
38 #include "soc15_common.h"
40 #include "navi10_sdma_pkt_open.h"
41 #include "nbio_v2_3.h"
42 #include "sdma_common.h"
43 #include "sdma_v5_0.h"
45 MODULE_FIRMWARE("amdgpu/navi10_sdma.bin");
46 MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin");
48 MODULE_FIRMWARE("amdgpu/navi14_sdma.bin");
49 MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin");
51 MODULE_FIRMWARE("amdgpu/navi12_sdma.bin");
52 MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin");
54 MODULE_FIRMWARE("amdgpu/cyan_skillfish_sdma.bin");
55 MODULE_FIRMWARE("amdgpu/cyan_skillfish_sdma1.bin");
57 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma.bin");
58 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma1.bin");
60 #define SDMA1_REG_OFFSET 0x600
61 #define SDMA0_HYP_DEC_REG_START 0x5880
62 #define SDMA0_HYP_DEC_REG_END 0x5893
63 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
65 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev);
66 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev);
67 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev);
68 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev);
70 static const struct soc15_reg_golden golden_settings_sdma_5[] = {
71 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
72 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
73 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
74 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
75 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
76 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
77 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
78 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
79 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
80 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
81 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
82 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00),
83 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
84 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
85 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
86 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
87 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
88 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
89 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
90 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
91 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
92 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
93 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
94 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00)
97 static const struct soc15_reg_golden golden_settings_sdma_5_sriov[] = {
98 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
99 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
120 static const struct soc15_reg_golden golden_settings_sdma_nv10[] = {
121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
125 static const struct soc15_reg_golden golden_settings_sdma_nv14[] = {
126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
130 static const struct soc15_reg_golden golden_settings_sdma_nv12[] = {
131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
139 static const struct soc15_reg_golden golden_settings_sdma_cyan_skillfish[] = {
140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x007fffff, 0x004c5c00),
154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x007fffff, 0x004c5c00)
170 static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
174 if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
175 internal_offset <= SDMA0_HYP_DEC_REG_END) {
176 base = adev->reg_offset[GC_HWIP][0][1];
178 internal_offset += SDMA1_HYP_DEC_REG_OFFSET;
180 base = adev->reg_offset[GC_HWIP][0][0];
182 internal_offset += SDMA1_REG_OFFSET;
185 return base + internal_offset;
188 static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
190 switch (adev->asic_type) {
192 soc15_program_register_sequence(adev,
193 golden_settings_sdma_5,
194 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
195 soc15_program_register_sequence(adev,
196 golden_settings_sdma_nv10,
197 (const u32)ARRAY_SIZE(golden_settings_sdma_nv10));
200 soc15_program_register_sequence(adev,
201 golden_settings_sdma_5,
202 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
203 soc15_program_register_sequence(adev,
204 golden_settings_sdma_nv14,
205 (const u32)ARRAY_SIZE(golden_settings_sdma_nv14));
208 if (amdgpu_sriov_vf(adev))
209 soc15_program_register_sequence(adev,
210 golden_settings_sdma_5_sriov,
211 (const u32)ARRAY_SIZE(golden_settings_sdma_5_sriov));
213 soc15_program_register_sequence(adev,
214 golden_settings_sdma_5,
215 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
216 soc15_program_register_sequence(adev,
217 golden_settings_sdma_nv12,
218 (const u32)ARRAY_SIZE(golden_settings_sdma_nv12));
220 case CHIP_CYAN_SKILLFISH:
221 soc15_program_register_sequence(adev,
222 golden_settings_sdma_cyan_skillfish,
223 (const u32)ARRAY_SIZE(golden_settings_sdma_cyan_skillfish));
231 * sdma_v5_0_init_microcode - load ucode images from disk
233 * @adev: amdgpu_device pointer
235 * Use the firmware interface to load the ucode images into
236 * the driver (not loaded into hw).
237 * Returns 0 on success, error on failure.
240 // emulation only, won't work on real chip
241 // navi10 real chip need to use PSP to load firmware
242 static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
244 const char *chip_name;
247 struct amdgpu_firmware_info *info = NULL;
248 const struct common_firmware_header *header = NULL;
249 const struct sdma_firmware_header_v1_0 *hdr;
251 if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_NAVI12))
256 switch (adev->asic_type) {
258 chip_name = "navi10";
261 chip_name = "navi14";
264 chip_name = "navi12";
266 case CHIP_CYAN_SKILLFISH:
267 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2)
268 chip_name = "cyan_skillfish2";
270 chip_name = "cyan_skillfish";
276 for (i = 0; i < adev->sdma.num_instances; i++) {
278 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
280 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
281 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
284 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
287 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
288 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
289 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
290 if (adev->sdma.instance[i].feature_version >= 20)
291 adev->sdma.instance[i].burst_nop = true;
292 DRM_DEBUG("psp_load == '%s'\n",
293 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
295 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
296 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
297 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
298 info->fw = adev->sdma.instance[i].fw;
299 header = (const struct common_firmware_header *)info->fw->data;
300 adev->firmware.fw_size +=
301 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
306 DRM_ERROR("sdma_v5_0: Failed to load firmware \"%s\"\n", fw_name);
307 for (i = 0; i < adev->sdma.num_instances; i++) {
308 release_firmware(adev->sdma.instance[i].fw);
309 adev->sdma.instance[i].fw = NULL;
315 static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring)
319 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
320 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
321 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
322 amdgpu_ring_write(ring, 1);
323 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
324 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
329 static void sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring *ring,
334 BUG_ON(offset > ring->buf_mask);
335 BUG_ON(ring->ring[offset] != 0x55aa55aa);
337 cur = (ring->wptr - 1) & ring->buf_mask;
339 ring->ring[offset] = cur - offset;
341 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
345 * sdma_v5_0_ring_get_rptr - get the current read pointer
347 * @ring: amdgpu ring pointer
349 * Get the current rptr from the hardware (NAVI10+).
351 static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
355 /* XXX check if swapping is necessary on BE */
356 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
358 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
359 return ((*rptr) >> 2);
363 * sdma_v5_0_ring_get_wptr - get the current write pointer
365 * @ring: amdgpu ring pointer
367 * Get the current wptr from the hardware (NAVI10+).
369 static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
371 struct amdgpu_device *adev = ring->adev;
374 if (ring->use_doorbell) {
375 /* XXX check if swapping is necessary on BE */
376 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
377 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
379 wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
381 wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
382 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
389 * sdma_v5_0_ring_set_wptr - commit the write pointer
391 * @ring: amdgpu ring pointer
393 * Write the wptr back to the hardware (NAVI10+).
395 static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
397 struct amdgpu_device *adev = ring->adev;
399 DRM_DEBUG("Setting write pointer\n");
400 if (ring->use_doorbell) {
401 DRM_DEBUG("Using doorbell -- "
402 "wptr_offs == 0x%08x "
403 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
404 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
406 lower_32_bits(ring->wptr << 2),
407 upper_32_bits(ring->wptr << 2));
408 /* XXX check if swapping is necessary on BE */
409 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
410 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
411 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
412 ring->doorbell_index, ring->wptr << 2);
413 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
415 DRM_DEBUG("Not using doorbell -- "
416 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
417 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
419 lower_32_bits(ring->wptr << 2),
421 upper_32_bits(ring->wptr << 2));
422 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
423 lower_32_bits(ring->wptr << 2));
424 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
425 upper_32_bits(ring->wptr << 2));
429 static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
431 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
434 for (i = 0; i < count; i++)
435 if (sdma && sdma->burst_nop && (i == 0))
436 amdgpu_ring_write(ring, ring->funcs->nop |
437 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
439 amdgpu_ring_write(ring, ring->funcs->nop);
443 * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine
445 * @ring: amdgpu ring pointer
446 * @job: job to retrieve vmid from
447 * @ib: IB object to schedule
450 * Schedule an IB in the DMA ring (NAVI10).
452 static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
453 struct amdgpu_job *job,
454 struct amdgpu_ib *ib,
457 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
458 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
460 /* An IB packet must end on a 8 DW boundary--the next dword
461 * must be on a 8-dword boundary. Our IB packet below is 6
462 * dwords long, thus add x number of NOPs, such that, in
463 * modular arithmetic,
464 * wptr + 6 + x = 8k, k >= 0, which in C is,
465 * (wptr + 6 + x) % 8 = 0.
466 * The expression below, is a solution of x.
468 sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
470 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
471 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
472 /* base must be 32 byte aligned */
473 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
474 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
475 amdgpu_ring_write(ring, ib->length_dw);
476 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
477 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
481 * sdma_v5_0_ring_emit_mem_sync - flush the IB by graphics cache rinse
483 * @ring: amdgpu ring pointer
484 * @job: job to retrieve vmid from
485 * @ib: IB object to schedule
487 * flush the IB by graphics cache rinse.
489 static void sdma_v5_0_ring_emit_mem_sync(struct amdgpu_ring *ring)
491 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
492 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
495 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
496 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
497 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
498 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
499 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
500 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
501 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
502 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
503 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
507 * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
509 * @ring: amdgpu ring pointer
511 * Emit an hdp flush packet on the requested DMA ring.
513 static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
515 struct amdgpu_device *adev = ring->adev;
516 u32 ref_and_mask = 0;
517 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
520 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
522 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
524 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
525 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
526 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
527 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
528 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
529 amdgpu_ring_write(ring, ref_and_mask); /* reference */
530 amdgpu_ring_write(ring, ref_and_mask); /* mask */
531 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
532 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
536 * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring
538 * @ring: amdgpu ring pointer
540 * @seq: sequence number
541 * @flags: fence related flags
543 * Add a DMA fence packet to the ring to write
544 * the fence seq number and DMA trap packet to generate
545 * an interrupt if needed (NAVI10).
547 static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
550 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
551 /* write the fence */
552 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
553 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
554 /* zero in first two bits */
556 amdgpu_ring_write(ring, lower_32_bits(addr));
557 amdgpu_ring_write(ring, upper_32_bits(addr));
558 amdgpu_ring_write(ring, lower_32_bits(seq));
560 /* optionally write high bits as well */
563 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
564 SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
565 /* zero in first two bits */
567 amdgpu_ring_write(ring, lower_32_bits(addr));
568 amdgpu_ring_write(ring, upper_32_bits(addr));
569 amdgpu_ring_write(ring, upper_32_bits(seq));
572 if (flags & AMDGPU_FENCE_FLAG_INT) {
573 /* generate an interrupt */
574 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
575 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
581 * sdma_v5_0_gfx_stop - stop the gfx async dma engines
583 * @adev: amdgpu_device pointer
585 * Stop the gfx async dma ring buffers (NAVI10).
587 static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev)
589 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
590 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
591 u32 rb_cntl, ib_cntl;
594 if ((adev->mman.buffer_funcs_ring == sdma0) ||
595 (adev->mman.buffer_funcs_ring == sdma1))
596 amdgpu_ttm_set_buffer_funcs_status(adev, false);
598 for (i = 0; i < adev->sdma.num_instances; i++) {
599 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
600 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
601 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
602 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
603 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
604 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
609 * sdma_v5_0_rlc_stop - stop the compute async dma engines
611 * @adev: amdgpu_device pointer
613 * Stop the compute async dma queues (NAVI10).
615 static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev)
621 * sdma_v5_0_ctx_switch_enable - stop the async dma engines context switch
623 * @adev: amdgpu_device pointer
624 * @enable: enable/disable the DMA MEs context switch.
626 * Halt or unhalt the async dma engines context switch (NAVI10).
628 static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
630 u32 f32_cntl = 0, phase_quantum = 0;
633 if (amdgpu_sdma_phase_quantum) {
634 unsigned value = amdgpu_sdma_phase_quantum;
637 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
638 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
639 value = (value + 1) >> 1;
642 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
643 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
644 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
645 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
646 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
647 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
649 "clamping sdma_phase_quantum to %uK clock cycles\n",
653 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
654 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
657 for (i = 0; i < adev->sdma.num_instances; i++) {
658 if (!amdgpu_sriov_vf(adev)) {
659 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
660 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
661 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
664 if (enable && amdgpu_sdma_phase_quantum) {
665 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
667 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
669 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
672 if (!amdgpu_sriov_vf(adev))
673 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
679 * sdma_v5_0_enable - stop the async dma engines
681 * @adev: amdgpu_device pointer
682 * @enable: enable/disable the DMA MEs.
684 * Halt or unhalt the async dma engines (NAVI10).
686 static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable)
692 sdma_v5_0_gfx_stop(adev);
693 sdma_v5_0_rlc_stop(adev);
696 if (amdgpu_sriov_vf(adev))
699 for (i = 0; i < adev->sdma.num_instances; i++) {
700 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
701 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
702 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
707 * sdma_v5_0_gfx_resume - setup and start the async dma engines
709 * @adev: amdgpu_device pointer
711 * Set up the gfx DMA ring buffers and enable them (NAVI10).
712 * Returns 0 for success, error for failure.
714 static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
716 struct amdgpu_ring *ring;
717 u32 rb_cntl, ib_cntl;
727 for (i = 0; i < adev->sdma.num_instances; i++) {
728 ring = &adev->sdma.instance[i].ring;
729 wb_offset = (ring->rptr_offs * 4);
731 if (!amdgpu_sriov_vf(adev))
732 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
734 /* Set ring buffer size in dwords */
735 rb_bufsz = order_base_2(ring->ring_size / 4);
736 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
737 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
739 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
740 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
741 RPTR_WRITEBACK_SWAP_ENABLE, 1);
743 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
745 /* Initialize the ring buffer's read and write pointers */
746 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
747 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
748 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
749 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
751 /* setup the wptr shadow polling */
752 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
753 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
754 lower_32_bits(wptr_gpu_addr));
755 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
756 upper_32_bits(wptr_gpu_addr));
757 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,
758 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
759 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
760 SDMA0_GFX_RB_WPTR_POLL_CNTL,
762 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
765 /* set the wb address whether it's enabled or not */
766 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
767 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
768 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
769 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
771 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
773 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE),
774 ring->gpu_addr >> 8);
775 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI),
776 ring->gpu_addr >> 40);
780 /* before programing wptr to a less value, need set minor_ptr_update first */
781 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
783 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
784 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR),
785 lower_32_bits(ring->wptr) << 2);
786 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI),
787 upper_32_bits(ring->wptr) << 2);
790 doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
791 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,
792 mmSDMA0_GFX_DOORBELL_OFFSET));
794 if (ring->use_doorbell) {
795 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
796 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
797 OFFSET, ring->doorbell_index);
799 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
801 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
802 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET),
805 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
806 ring->doorbell_index, 20);
808 if (amdgpu_sriov_vf(adev))
809 sdma_v5_0_ring_set_wptr(ring);
811 /* set minor_ptr_update to 0 after wptr programed */
812 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
814 if (!amdgpu_sriov_vf(adev)) {
815 /* set utc l1 enable flag always to 1 */
816 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
817 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
820 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
821 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
823 /* Set up RESP_MODE to non-copy addresses */
824 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
825 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
826 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
827 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
829 /* program default cache read and write policy */
830 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
831 /* clean read policy and write policy bits */
833 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14));
834 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
837 if (!amdgpu_sriov_vf(adev)) {
839 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
840 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
841 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
845 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
846 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
848 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
849 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
851 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
854 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
856 ring->sched.ready = true;
858 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
859 sdma_v5_0_ctx_switch_enable(adev, true);
860 sdma_v5_0_enable(adev, true);
863 r = amdgpu_ring_test_helper(ring);
867 if (adev->mman.buffer_funcs_ring == ring)
868 amdgpu_ttm_set_buffer_funcs_status(adev, true);
875 * sdma_v5_0_rlc_resume - setup and start the async dma engines
877 * @adev: amdgpu_device pointer
879 * Set up the compute DMA queues and enable them (NAVI10).
880 * Returns 0 for success, error for failure.
882 static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev)
888 * sdma_v5_0_load_microcode - load the sDMA ME ucode
890 * @adev: amdgpu_device pointer
892 * Loads the sDMA0/1 ucode.
893 * Returns 0 for success, -EINVAL if the ucode is not available.
895 static int sdma_v5_0_load_microcode(struct amdgpu_device *adev)
897 const struct sdma_firmware_header_v1_0 *hdr;
898 const __le32 *fw_data;
903 sdma_v5_0_enable(adev, false);
905 for (i = 0; i < adev->sdma.num_instances; i++) {
906 if (!adev->sdma.instance[i].fw)
909 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
910 amdgpu_ucode_print_sdma_hdr(&hdr->header);
911 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
913 fw_data = (const __le32 *)
914 (adev->sdma.instance[i].fw->data +
915 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
917 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
919 for (j = 0; j < fw_size; j++) {
920 if (amdgpu_emu_mode == 1 && j % 500 == 0)
922 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
925 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
932 * sdma_v5_0_start - setup and start the async dma engines
934 * @adev: amdgpu_device pointer
936 * Set up the DMA engines and enable them (NAVI10).
937 * Returns 0 for success, error for failure.
939 static int sdma_v5_0_start(struct amdgpu_device *adev)
943 if (amdgpu_sriov_vf(adev)) {
944 sdma_v5_0_ctx_switch_enable(adev, false);
945 sdma_v5_0_enable(adev, false);
947 /* set RB registers */
948 r = sdma_v5_0_gfx_resume(adev);
952 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
953 r = sdma_v5_0_load_microcode(adev);
959 sdma_v5_0_enable(adev, true);
960 /* enable sdma ring preemption */
961 sdma_v5_0_ctx_switch_enable(adev, true);
963 /* start the gfx rings and rlc compute queues */
964 r = sdma_v5_0_gfx_resume(adev);
967 r = sdma_v5_0_rlc_resume(adev);
973 * sdma_v5_0_ring_test_ring - simple async dma engine test
975 * @ring: amdgpu_ring structure holding ring information
977 * Test the DMA engine by writing using it to write an
978 * value to memory. (NAVI10).
979 * Returns 0 for success, error for failure.
981 static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring)
983 struct amdgpu_device *adev = ring->adev;
990 r = amdgpu_device_wb_get(adev, &index);
992 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
996 gpu_addr = adev->wb.gpu_addr + (index * 4);
998 adev->wb.wb[index] = cpu_to_le32(tmp);
1000 r = amdgpu_ring_alloc(ring, 5);
1002 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
1003 amdgpu_device_wb_free(adev, index);
1007 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1008 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
1009 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
1010 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
1011 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
1012 amdgpu_ring_write(ring, 0xDEADBEEF);
1013 amdgpu_ring_commit(ring);
1015 for (i = 0; i < adev->usec_timeout; i++) {
1016 tmp = le32_to_cpu(adev->wb.wb[index]);
1017 if (tmp == 0xDEADBEEF)
1019 if (amdgpu_emu_mode == 1)
1025 if (i >= adev->usec_timeout)
1028 amdgpu_device_wb_free(adev, index);
1034 * sdma_v5_0_ring_test_ib - test an IB on the DMA engine
1036 * @ring: amdgpu_ring structure holding ring information
1037 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1039 * Test a simple IB in the DMA ring (NAVI10).
1040 * Returns 0 on success, error on failure.
1042 static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1044 struct amdgpu_device *adev = ring->adev;
1045 struct amdgpu_ib ib;
1046 struct dma_fence *f = NULL;
1052 r = amdgpu_device_wb_get(adev, &index);
1054 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
1058 gpu_addr = adev->wb.gpu_addr + (index * 4);
1060 adev->wb.wb[index] = cpu_to_le32(tmp);
1061 memset(&ib, 0, sizeof(ib));
1062 r = amdgpu_ib_get(adev, NULL, 256,
1063 AMDGPU_IB_POOL_DIRECT, &ib);
1065 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1069 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1070 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1071 ib.ptr[1] = lower_32_bits(gpu_addr);
1072 ib.ptr[2] = upper_32_bits(gpu_addr);
1073 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1074 ib.ptr[4] = 0xDEADBEEF;
1075 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1076 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1077 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1080 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1084 r = dma_fence_wait_timeout(f, false, timeout);
1086 DRM_ERROR("amdgpu: IB test timed out\n");
1090 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1093 tmp = le32_to_cpu(adev->wb.wb[index]);
1094 if (tmp == 0xDEADBEEF)
1100 amdgpu_ib_free(adev, &ib, NULL);
1103 amdgpu_device_wb_free(adev, index);
1109 * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART
1111 * @ib: indirect buffer to fill with commands
1112 * @pe: addr of the page entry
1113 * @src: src addr to copy from
1114 * @count: number of page entries to update
1116 * Update PTEs by copying them from the GART using sDMA (NAVI10).
1118 static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib,
1119 uint64_t pe, uint64_t src,
1122 unsigned bytes = count * 8;
1124 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1125 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1126 ib->ptr[ib->length_dw++] = bytes - 1;
1127 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1128 ib->ptr[ib->length_dw++] = lower_32_bits(src);
1129 ib->ptr[ib->length_dw++] = upper_32_bits(src);
1130 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1131 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1136 * sdma_v5_0_vm_write_pte - update PTEs by writing them manually
1138 * @ib: indirect buffer to fill with commands
1139 * @pe: addr of the page entry
1140 * @value: dst addr to write into pe
1141 * @count: number of page entries to update
1142 * @incr: increase next addr by incr bytes
1144 * Update PTEs by writing them manually using sDMA (NAVI10).
1146 static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1147 uint64_t value, unsigned count,
1150 unsigned ndw = count * 2;
1152 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1153 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1154 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1155 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1156 ib->ptr[ib->length_dw++] = ndw - 1;
1157 for (; ndw > 0; ndw -= 2) {
1158 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1159 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1165 * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA
1167 * @ib: indirect buffer to fill with commands
1168 * @pe: addr of the page entry
1169 * @addr: dst addr to write into pe
1170 * @count: number of page entries to update
1171 * @incr: increase next addr by incr bytes
1172 * @flags: access flags
1174 * Update the page tables using sDMA (NAVI10).
1176 static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1178 uint64_t addr, unsigned count,
1179 uint32_t incr, uint64_t flags)
1181 /* for physically contiguous pages (vram) */
1182 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1183 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1184 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1185 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1186 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1187 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1188 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1189 ib->ptr[ib->length_dw++] = incr; /* increment size */
1190 ib->ptr[ib->length_dw++] = 0;
1191 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1195 * sdma_v5_0_ring_pad_ib - pad the IB
1196 * @ring: amdgpu_ring structure holding ring information
1197 * @ib: indirect buffer to fill with padding
1199 * Pad the IB with NOPs to a boundary multiple of 8.
1201 static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1203 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1207 pad_count = (-ib->length_dw) & 0x7;
1208 for (i = 0; i < pad_count; i++)
1209 if (sdma && sdma->burst_nop && (i == 0))
1210 ib->ptr[ib->length_dw++] =
1211 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1212 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1214 ib->ptr[ib->length_dw++] =
1215 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1220 * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline
1222 * @ring: amdgpu_ring pointer
1224 * Make sure all previous operations are completed (CIK).
1226 static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1228 uint32_t seq = ring->fence_drv.sync_seq;
1229 uint64_t addr = ring->fence_drv.gpu_addr;
1232 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1233 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1234 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1235 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1236 amdgpu_ring_write(ring, addr & 0xfffffffc);
1237 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1238 amdgpu_ring_write(ring, seq); /* reference */
1239 amdgpu_ring_write(ring, 0xffffffff); /* mask */
1240 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1241 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1246 * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA
1248 * @ring: amdgpu_ring pointer
1249 * @vmid: vmid number to use
1252 * Update the page table base and flush the VM TLB
1253 * using sDMA (NAVI10).
1255 static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1256 unsigned vmid, uint64_t pd_addr)
1258 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1261 static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring *ring,
1262 uint32_t reg, uint32_t val)
1264 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1265 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1266 amdgpu_ring_write(ring, reg);
1267 amdgpu_ring_write(ring, val);
1270 static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1271 uint32_t val, uint32_t mask)
1273 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1274 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1275 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1276 amdgpu_ring_write(ring, reg << 2);
1277 amdgpu_ring_write(ring, 0);
1278 amdgpu_ring_write(ring, val); /* reference */
1279 amdgpu_ring_write(ring, mask); /* mask */
1280 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1281 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1284 static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1285 uint32_t reg0, uint32_t reg1,
1286 uint32_t ref, uint32_t mask)
1288 amdgpu_ring_emit_wreg(ring, reg0, ref);
1289 /* wait for a cycle to reset vm_inv_eng*_ack */
1290 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1291 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1294 static int sdma_v5_0_early_init(void *handle)
1296 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1298 adev->sdma.num_instances = 2;
1300 sdma_v5_0_set_ring_funcs(adev);
1301 sdma_v5_0_set_buffer_funcs(adev);
1302 sdma_v5_0_set_vm_pte_funcs(adev);
1303 sdma_v5_0_set_irq_funcs(adev);
1309 static int sdma_v5_0_sw_init(void *handle)
1311 struct amdgpu_ring *ring;
1313 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1315 /* SDMA trap event */
1316 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0,
1317 SDMA0_5_0__SRCID__SDMA_TRAP,
1318 &adev->sdma.trap_irq);
1322 /* SDMA trap event */
1323 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1,
1324 SDMA1_5_0__SRCID__SDMA_TRAP,
1325 &adev->sdma.trap_irq);
1329 r = sdma_v5_0_init_microcode(adev);
1331 DRM_ERROR("Failed to load sdma firmware!\n");
1335 for (i = 0; i < adev->sdma.num_instances; i++) {
1336 ring = &adev->sdma.instance[i].ring;
1337 ring->ring_obj = NULL;
1338 ring->use_doorbell = true;
1340 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1341 ring->use_doorbell?"true":"false");
1343 ring->doorbell_index = (i == 0) ?
1344 (adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset
1345 : (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset
1347 sprintf(ring->name, "sdma%d", i);
1348 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1349 (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 :
1350 AMDGPU_SDMA_IRQ_INSTANCE1,
1351 AMDGPU_RING_PRIO_DEFAULT, NULL);
1359 static int sdma_v5_0_sw_fini(void *handle)
1361 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1364 for (i = 0; i < adev->sdma.num_instances; i++) {
1365 release_firmware(adev->sdma.instance[i].fw);
1366 adev->sdma.instance[i].fw = NULL;
1368 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1374 static int sdma_v5_0_hw_init(void *handle)
1377 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1379 sdma_v5_0_init_golden_registers(adev);
1381 r = sdma_v5_0_start(adev);
1386 static int sdma_v5_0_hw_fini(void *handle)
1388 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1390 if (amdgpu_sriov_vf(adev))
1393 sdma_v5_0_ctx_switch_enable(adev, false);
1394 sdma_v5_0_enable(adev, false);
1399 static int sdma_v5_0_suspend(void *handle)
1401 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1403 return sdma_v5_0_hw_fini(adev);
1406 static int sdma_v5_0_resume(void *handle)
1408 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1410 return sdma_v5_0_hw_init(adev);
1413 static bool sdma_v5_0_is_idle(void *handle)
1415 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1418 for (i = 0; i < adev->sdma.num_instances; i++) {
1419 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1421 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1428 static int sdma_v5_0_wait_for_idle(void *handle)
1432 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1434 for (i = 0; i < adev->usec_timeout; i++) {
1435 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1436 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1438 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1445 static int sdma_v5_0_soft_reset(void *handle)
1452 static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring)
1455 struct amdgpu_device *adev = ring->adev;
1457 u64 sdma_gfx_preempt;
1459 amdgpu_sdma_get_index_from_ring(ring, &index);
1461 sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT;
1463 sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT;
1465 /* assert preemption condition */
1466 amdgpu_ring_set_preempt_cond_exec(ring, false);
1468 /* emit the trailing fence */
1469 ring->trail_seq += 1;
1470 amdgpu_ring_alloc(ring, 10);
1471 sdma_v5_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1472 ring->trail_seq, 0);
1473 amdgpu_ring_commit(ring);
1475 /* assert IB preemption */
1476 WREG32(sdma_gfx_preempt, 1);
1478 /* poll the trailing fence */
1479 for (i = 0; i < adev->usec_timeout; i++) {
1480 if (ring->trail_seq ==
1481 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1486 if (i >= adev->usec_timeout) {
1488 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1491 /* deassert IB preemption */
1492 WREG32(sdma_gfx_preempt, 0);
1494 /* deassert the preemption condition */
1495 amdgpu_ring_set_preempt_cond_exec(ring, true);
1499 static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev,
1500 struct amdgpu_irq_src *source,
1502 enum amdgpu_interrupt_state state)
1506 if (!amdgpu_sriov_vf(adev)) {
1507 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ?
1508 sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :
1509 sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);
1511 sdma_cntl = RREG32(reg_offset);
1512 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1513 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1514 WREG32(reg_offset, sdma_cntl);
1520 static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev,
1521 struct amdgpu_irq_src *source,
1522 struct amdgpu_iv_entry *entry)
1524 DRM_DEBUG("IH: SDMA trap\n");
1525 switch (entry->client_id) {
1526 case SOC15_IH_CLIENTID_SDMA0:
1527 switch (entry->ring_id) {
1529 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1542 case SOC15_IH_CLIENTID_SDMA1:
1543 switch (entry->ring_id) {
1545 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1562 static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1563 struct amdgpu_irq_src *source,
1564 struct amdgpu_iv_entry *entry)
1569 static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1575 for (i = 0; i < adev->sdma.num_instances; i++) {
1576 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1577 /* Enable sdma clock gating */
1578 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1579 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1580 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1581 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1582 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1583 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1584 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1585 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1586 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1588 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1590 /* Disable sdma clock gating */
1591 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1592 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1593 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1594 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1595 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1596 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1597 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1598 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1599 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1601 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1606 static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1612 for (i = 0; i < adev->sdma.num_instances; i++) {
1613 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1614 /* Enable sdma mem light sleep */
1615 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1616 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1618 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1621 /* Disable sdma mem light sleep */
1622 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1623 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1625 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1631 static int sdma_v5_0_set_clockgating_state(void *handle,
1632 enum amd_clockgating_state state)
1634 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1636 if (amdgpu_sriov_vf(adev))
1639 switch (adev->asic_type) {
1643 sdma_v5_0_update_medium_grain_clock_gating(adev,
1644 state == AMD_CG_STATE_GATE);
1645 sdma_v5_0_update_medium_grain_light_sleep(adev,
1646 state == AMD_CG_STATE_GATE);
1655 static int sdma_v5_0_set_powergating_state(void *handle,
1656 enum amd_powergating_state state)
1661 static void sdma_v5_0_get_clockgating_state(void *handle, u32 *flags)
1663 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1666 if (amdgpu_sriov_vf(adev))
1669 /* AMD_CG_SUPPORT_SDMA_MGCG */
1670 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
1671 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
1672 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1674 /* AMD_CG_SUPPORT_SDMA_LS */
1675 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1676 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1677 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1680 const struct amd_ip_funcs sdma_v5_0_ip_funcs = {
1681 .name = "sdma_v5_0",
1682 .early_init = sdma_v5_0_early_init,
1684 .sw_init = sdma_v5_0_sw_init,
1685 .sw_fini = sdma_v5_0_sw_fini,
1686 .hw_init = sdma_v5_0_hw_init,
1687 .hw_fini = sdma_v5_0_hw_fini,
1688 .suspend = sdma_v5_0_suspend,
1689 .resume = sdma_v5_0_resume,
1690 .is_idle = sdma_v5_0_is_idle,
1691 .wait_for_idle = sdma_v5_0_wait_for_idle,
1692 .soft_reset = sdma_v5_0_soft_reset,
1693 .set_clockgating_state = sdma_v5_0_set_clockgating_state,
1694 .set_powergating_state = sdma_v5_0_set_powergating_state,
1695 .get_clockgating_state = sdma_v5_0_get_clockgating_state,
1698 static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
1699 .type = AMDGPU_RING_TYPE_SDMA,
1701 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1702 .support_64bit_ptrs = true,
1703 .vmhub = AMDGPU_GFXHUB_0,
1704 .get_rptr = sdma_v5_0_ring_get_rptr,
1705 .get_wptr = sdma_v5_0_ring_get_wptr,
1706 .set_wptr = sdma_v5_0_ring_set_wptr,
1708 5 + /* sdma_v5_0_ring_init_cond_exec */
1709 6 + /* sdma_v5_0_ring_emit_hdp_flush */
1710 3 + /* hdp_invalidate */
1711 6 + /* sdma_v5_0_ring_emit_pipeline_sync */
1712 /* sdma_v5_0_ring_emit_vm_flush */
1713 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1714 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 +
1715 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */
1716 .emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */
1717 .emit_ib = sdma_v5_0_ring_emit_ib,
1718 .emit_mem_sync = sdma_v5_0_ring_emit_mem_sync,
1719 .emit_fence = sdma_v5_0_ring_emit_fence,
1720 .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync,
1721 .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush,
1722 .emit_hdp_flush = sdma_v5_0_ring_emit_hdp_flush,
1723 .test_ring = sdma_v5_0_ring_test_ring,
1724 .test_ib = sdma_v5_0_ring_test_ib,
1725 .insert_nop = sdma_v5_0_ring_insert_nop,
1726 .pad_ib = sdma_v5_0_ring_pad_ib,
1727 .emit_wreg = sdma_v5_0_ring_emit_wreg,
1728 .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait,
1729 .emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait,
1730 .init_cond_exec = sdma_v5_0_ring_init_cond_exec,
1731 .patch_cond_exec = sdma_v5_0_ring_patch_cond_exec,
1732 .preempt_ib = sdma_v5_0_ring_preempt_ib,
1735 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev)
1739 for (i = 0; i < adev->sdma.num_instances; i++) {
1740 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs;
1741 adev->sdma.instance[i].ring.me = i;
1745 static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs = {
1746 .set = sdma_v5_0_set_trap_irq_state,
1747 .process = sdma_v5_0_process_trap_irq,
1750 static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = {
1751 .process = sdma_v5_0_process_illegal_inst_irq,
1754 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev)
1756 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1757 adev->sdma.num_instances;
1758 adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs;
1759 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs;
1763 * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine
1765 * @ib: indirect buffer to copy to
1766 * @src_offset: src GPU address
1767 * @dst_offset: dst GPU address
1768 * @byte_count: number of bytes to xfer
1769 * @tmz: if a secure copy should be used
1771 * Copy GPU buffers using the DMA engine (NAVI10).
1772 * Used by the amdgpu ttm implementation to move pages if
1773 * registered as the asic copy callback.
1775 static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib,
1776 uint64_t src_offset,
1777 uint64_t dst_offset,
1778 uint32_t byte_count,
1781 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1782 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1783 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1784 ib->ptr[ib->length_dw++] = byte_count - 1;
1785 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1786 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1787 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1788 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1789 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1793 * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine
1795 * @ib: indirect buffer to fill
1796 * @src_data: value to write to buffer
1797 * @dst_offset: dst GPU address
1798 * @byte_count: number of bytes to xfer
1800 * Fill GPU buffers using the DMA engine (NAVI10).
1802 static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib,
1804 uint64_t dst_offset,
1805 uint32_t byte_count)
1807 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1808 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1809 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1810 ib->ptr[ib->length_dw++] = src_data;
1811 ib->ptr[ib->length_dw++] = byte_count - 1;
1814 static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = {
1815 .copy_max_bytes = 0x400000,
1817 .emit_copy_buffer = sdma_v5_0_emit_copy_buffer,
1819 .fill_max_bytes = 0x400000,
1821 .emit_fill_buffer = sdma_v5_0_emit_fill_buffer,
1824 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev)
1826 if (adev->mman.buffer_funcs == NULL) {
1827 adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs;
1828 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1832 static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = {
1833 .copy_pte_num_dw = 7,
1834 .copy_pte = sdma_v5_0_vm_copy_pte,
1835 .write_pte = sdma_v5_0_vm_write_pte,
1836 .set_pte_pde = sdma_v5_0_vm_set_pte_pde,
1839 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1843 if (adev->vm_manager.vm_pte_funcs == NULL) {
1844 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs;
1845 for (i = 0; i < adev->sdma.num_instances; i++) {
1846 adev->vm_manager.vm_pte_scheds[i] =
1847 &adev->sdma.instance[i].ring.sched;
1849 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1853 const struct amdgpu_ip_block_version sdma_v5_0_ip_block = {
1854 .type = AMD_IP_BLOCK_TYPE_SDMA,
1858 .funcs = &sdma_v5_0_ip_funcs,