drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_ucode.h"
  31 #include "amdgpu_trace.h"
  32
  33 #include "sdma0/sdma0_4_2_offset.h"
  34 #include "sdma0/sdma0_4_2_sh_mask.h"
  35 #include "sdma1/sdma1_4_2_offset.h"
  36 #include "sdma1/sdma1_4_2_sh_mask.h"
  37 #include "sdma2/sdma2_4_2_2_offset.h"
  38 #include "sdma2/sdma2_4_2_2_sh_mask.h"
  39 #include "sdma3/sdma3_4_2_2_offset.h"
  40 #include "sdma3/sdma3_4_2_2_sh_mask.h"
  41 #include "sdma4/sdma4_4_2_2_offset.h"
  42 #include "sdma4/sdma4_4_2_2_sh_mask.h"
  43 #include "sdma5/sdma5_4_2_2_offset.h"
  44 #include "sdma5/sdma5_4_2_2_sh_mask.h"
  45 #include "sdma6/sdma6_4_2_2_offset.h"
  46 #include "sdma6/sdma6_4_2_2_sh_mask.h"
  47 #include "sdma7/sdma7_4_2_2_offset.h"
  48 #include "sdma7/sdma7_4_2_2_sh_mask.h"
  49 #include "hdp/hdp_4_0_offset.h"
  50 #include "sdma0/sdma0_4_1_default.h"
  51
  52 #include "soc15_common.h"
  53 #include "soc15.h"
  54 #include "vega10_sdma_pkt_open.h"
  55
  56 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h"
  57 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h"
  58
  59 #include "amdgpu_ras.h"
  60
  61 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin");
  62 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin");
  63 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin");
  64 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin");
  65 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin");
  66 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin");
  67 MODULE_FIRMWARE("amdgpu/raven_sdma.bin");
  68 MODULE_FIRMWARE("amdgpu/picasso_sdma.bin");
  69 MODULE_FIRMWARE("amdgpu/raven2_sdma.bin");
  70 MODULE_FIRMWARE("amdgpu/arcturus_sdma.bin");
  71 MODULE_FIRMWARE("amdgpu/renoir_sdma.bin");
  72
  73 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK  0x000000F8L
  74 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
  75
  76 #define WREG32_SDMA(instance, offset, value) \
  77         WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value)
  78 #define RREG32_SDMA(instance, offset) \
  79         RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)))
  80
  81 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev);
  82 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev);
  83 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  84 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev);
  85 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev);
  86
  87 static const struct soc15_reg_golden golden_settings_sdma_4[] = {
  88         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
  89         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
  90         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),
  91         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  92         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
  93         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  94         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000),
  95         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
  96         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  97         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
  98         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  99         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
 100         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000),
 101         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
 102         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100),
 103         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 104         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
 105         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 106         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000),
 107         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
 108         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 109         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
 110         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 111         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
 112         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000)
 113 };
 114
 115 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = {
 116         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
 117         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
 118         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
 119         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
 120         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002)
 121 };
 122
 123 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = {
 124         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
 125         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001),
 126         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
 127         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
 128         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001)
 129 };
 130
 131 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = {
 132         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
 133         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
 134         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100),
 135         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 136         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051),
 137         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100),
 138         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 139         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100),
 140         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 141         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
 142         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000)
 143 };
 144
 145 static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = {
 146         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
 147 };
 148
 149 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] =
 150 {
 151         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 152         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
 153         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 154         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 155         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 156         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 157         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 158         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 159         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003),
 160         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 161         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
 162         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 163         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 164         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 165         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 166         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 167         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 168         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 169         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 170         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 171         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 172         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 173         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 174         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 175         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 176         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
 177 };
 178
 179 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = {
 180         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 181         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
 182         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 183         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 184         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 185         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 186         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 187         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 188         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003),
 189         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 190         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
 191         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 192         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 193         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 194         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 195         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 196         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 197         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 198         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 199         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 200         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 201         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 202         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 203         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 204         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 205         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
 206 };
 207
 208 static const struct soc15_reg_golden golden_settings_sdma_rv1[] =
 209 {
 210         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
 211         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002)
 212 };
 213
 214 static const struct soc15_reg_golden golden_settings_sdma_rv2[] =
 215 {
 216         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001),
 217         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001)
 218 };
 219
 220 static const struct soc15_reg_golden golden_settings_sdma_arct[] =
 221 {
 222         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 223         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 224         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 225         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 226         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 227         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 228         SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 229         SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 230         SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 231         SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 232         SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 233         SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 234         SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 235         SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 236         SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 237         SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 238         SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 239         SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 240         SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 241         SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 242         SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 243         SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 244         SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 245         SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002)
 246 };
 247
 248 static const struct soc15_reg_golden golden_settings_sdma_4_3[] = {
 249         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 250         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
 251         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
 252         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002),
 253         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 254         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051),
 255         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 256         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 257         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
 258         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x03fbe1fe)
 259 };
 260
 261 static const struct soc15_ras_field_entry sdma_v4_0_ras_fields[] = {
 262         { "SDMA_UCODE_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 263         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UCODE_BUF_SED),
 264         0, 0,
 265         },
 266         { "SDMA_RB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 267         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_RB_CMD_BUF_SED),
 268         0, 0,
 269         },
 270         { "SDMA_IB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 271         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_IB_CMD_BUF_SED),
 272         0, 0,
 273         },
 274         { "SDMA_UTCL1_RD_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 275         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RD_FIFO_SED),
 276         0, 0,
 277         },
 278         { "SDMA_UTCL1_RDBST_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 279         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RDBST_FIFO_SED),
 280         0, 0,
 281         },
 282         { "SDMA_DATA_LUT_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 283         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_DATA_LUT_FIFO_SED),
 284         0, 0,
 285         },
 286         { "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 287         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF0_SED),
 288         0, 0,
 289         },
 290         { "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 291         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF1_SED),
 292         0, 0,
 293         },
 294         { "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 295         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF2_SED),
 296         0, 0,
 297         },
 298         { "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 299         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF3_SED),
 300         0, 0,
 301         },
 302         { "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 303         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF4_SED),
 304         0, 0,
 305         },
 306         { "SDMA_MBANK_DATA_BUF5_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 307         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF5_SED),
 308         0, 0,
 309         },
 310         { "SDMA_MBANK_DATA_BUF6_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 311         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF6_SED),
 312         0, 0,
 313         },
 314         { "SDMA_MBANK_DATA_BUF7_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 315         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF7_SED),
 316         0, 0,
 317         },
 318         { "SDMA_MBANK_DATA_BUF8_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 319         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF8_SED),
 320         0, 0,
 321         },
 322         { "SDMA_MBANK_DATA_BUF9_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 323         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF9_SED),
 324         0, 0,
 325         },
 326         { "SDMA_MBANK_DATA_BUF10_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 327         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF10_SED),
 328         0, 0,
 329         },
 330         { "SDMA_MBANK_DATA_BUF11_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 331         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF11_SED),
 332         0, 0,
 333         },
 334         { "SDMA_MBANK_DATA_BUF12_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 335         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF12_SED),
 336         0, 0,
 337         },
 338         { "SDMA_MBANK_DATA_BUF13_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 339         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF13_SED),
 340         0, 0,
 341         },
 342         { "SDMA_MBANK_DATA_BUF14_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 343         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF14_SED),
 344         0, 0,
 345         },
 346         { "SDMA_MBANK_DATA_BUF15_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 347         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF15_SED),
 348         0, 0,
 349         },
 350         { "SDMA_SPLIT_DAT_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 351         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_SPLIT_DAT_BUF_SED),
 352         0, 0,
 353         },
 354         { "SDMA_MC_WR_ADDR_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 355         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MC_WR_ADDR_FIFO_SED),
 356         0, 0,
 357         },
 358 };
 359
 360 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
 361                 u32 instance, u32 offset)
 362 {
 363         switch (instance) {
 364         case 0:
 365                 return (adev->reg_offset[SDMA0_HWIP][0][0] + offset);
 366         case 1:
 367                 return (adev->reg_offset[SDMA1_HWIP][0][0] + offset);
 368         case 2:
 369                 return (adev->reg_offset[SDMA2_HWIP][0][1] + offset);
 370         case 3:
 371                 return (adev->reg_offset[SDMA3_HWIP][0][1] + offset);
 372         case 4:
 373                 return (adev->reg_offset[SDMA4_HWIP][0][1] + offset);
 374         case 5:
 375                 return (adev->reg_offset[SDMA5_HWIP][0][1] + offset);
 376         case 6:
 377                 return (adev->reg_offset[SDMA6_HWIP][0][1] + offset);
 378         case 7:
 379                 return (adev->reg_offset[SDMA7_HWIP][0][1] + offset);
 380         default:
 381                 break;
 382         }
 383         return 0;
 384 }
 385
 386 static unsigned sdma_v4_0_seq_to_irq_id(int seq_num)
 387 {
 388         switch (seq_num) {
 389         case 0:
 390                 return SOC15_IH_CLIENTID_SDMA0;
 391         case 1:
 392                 return SOC15_IH_CLIENTID_SDMA1;
 393         case 2:
 394                 return SOC15_IH_CLIENTID_SDMA2;
 395         case 3:
 396                 return SOC15_IH_CLIENTID_SDMA3;
 397         case 4:
 398                 return SOC15_IH_CLIENTID_SDMA4;
 399         case 5:
 400                 return SOC15_IH_CLIENTID_SDMA5;
 401         case 6:
 402                 return SOC15_IH_CLIENTID_SDMA6;
 403         case 7:
 404                 return SOC15_IH_CLIENTID_SDMA7;
 405         default:
 406                 break;
 407         }
 408         return -EINVAL;
 409 }
 410
 411 static int sdma_v4_0_irq_id_to_seq(unsigned client_id)
 412 {
 413         switch (client_id) {
 414         case SOC15_IH_CLIENTID_SDMA0:
 415                 return 0;
 416         case SOC15_IH_CLIENTID_SDMA1:
 417                 return 1;
 418         case SOC15_IH_CLIENTID_SDMA2:
 419                 return 2;
 420         case SOC15_IH_CLIENTID_SDMA3:
 421                 return 3;
 422         case SOC15_IH_CLIENTID_SDMA4:
 423                 return 4;
 424         case SOC15_IH_CLIENTID_SDMA5:
 425                 return 5;
 426         case SOC15_IH_CLIENTID_SDMA6:
 427                 return 6;
 428         case SOC15_IH_CLIENTID_SDMA7:
 429                 return 7;
 430         default:
 431                 break;
 432         }
 433         return -EINVAL;
 434 }
 435
 436 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
 437 {
 438         switch (adev->asic_type) {
 439         case CHIP_VEGA10:
 440                 soc15_program_register_sequence(adev,
 441                                                 golden_settings_sdma_4,
 442                                                 ARRAY_SIZE(golden_settings_sdma_4));
 443                 soc15_program_register_sequence(adev,
 444                                                 golden_settings_sdma_vg10,
 445                                                 ARRAY_SIZE(golden_settings_sdma_vg10));
 446                 break;
 447         case CHIP_VEGA12:
 448                 soc15_program_register_sequence(adev,
 449                                                 golden_settings_sdma_4,
 450                                                 ARRAY_SIZE(golden_settings_sdma_4));
 451                 soc15_program_register_sequence(adev,
 452                                                 golden_settings_sdma_vg12,
 453                                                 ARRAY_SIZE(golden_settings_sdma_vg12));
 454                 break;
 455         case CHIP_VEGA20:
 456                 soc15_program_register_sequence(adev,
 457                                                 golden_settings_sdma0_4_2_init,
 458                                                 ARRAY_SIZE(golden_settings_sdma0_4_2_init));
 459                 soc15_program_register_sequence(adev,
 460                                                 golden_settings_sdma0_4_2,
 461                                                 ARRAY_SIZE(golden_settings_sdma0_4_2));
 462                 soc15_program_register_sequence(adev,
 463                                                 golden_settings_sdma1_4_2,
 464                                                 ARRAY_SIZE(golden_settings_sdma1_4_2));
 465                 break;
 466         case CHIP_ARCTURUS:
 467                 soc15_program_register_sequence(adev,
 468                                                 golden_settings_sdma_arct,
 469                                                 ARRAY_SIZE(golden_settings_sdma_arct));
 470                 break;
 471         case CHIP_RAVEN:
 472                 soc15_program_register_sequence(adev,
 473                                                 golden_settings_sdma_4_1,
 474                                                 ARRAY_SIZE(golden_settings_sdma_4_1));
 475                 if (adev->rev_id >= 8)
 476                         soc15_program_register_sequence(adev,
 477                                                         golden_settings_sdma_rv2,
 478                                                         ARRAY_SIZE(golden_settings_sdma_rv2));
 479                 else
 480                         soc15_program_register_sequence(adev,
 481                                                         golden_settings_sdma_rv1,
 482                                                         ARRAY_SIZE(golden_settings_sdma_rv1));
 483                 break;
 484         case CHIP_RENOIR:
 485                 soc15_program_register_sequence(adev,
 486                                                 golden_settings_sdma_4_3,
 487                                                 ARRAY_SIZE(golden_settings_sdma_4_3));
 488                 break;
 489         default:
 490                 break;
 491         }
 492 }
 493
 494 static int sdma_v4_0_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
 495 {
 496         int err = 0;
 497         const struct sdma_firmware_header_v1_0 *hdr;
 498
 499         err = amdgpu_ucode_validate(sdma_inst->fw);
 500         if (err)
 501                 return err;
 502
 503         hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
 504         sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
 505         sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
 506
 507         if (sdma_inst->feature_version >= 20)
 508                 sdma_inst->burst_nop = true;
 509
 510         return 0;
 511 }
 512
 513 static void sdma_v4_0_destroy_inst_ctx(struct amdgpu_device *adev)
 514 {
 515         int i;
 516
 517         for (i = 0; i < adev->sdma.num_instances; i++) {
 518                 if (adev->sdma.instance[i].fw != NULL)
 519                         release_firmware(adev->sdma.instance[i].fw);
 520
 521                 /* arcturus shares the same FW memory across
 522                    all SDMA isntances */
 523                 if (adev->asic_type == CHIP_ARCTURUS)
 524                         break;
 525         }
 526
 527         memset((void*)adev->sdma.instance, 0,
 528                 sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
 529 }
 530
 531 /**
 532  * sdma_v4_0_init_microcode - load ucode images from disk
 533  *
 534  * @adev: amdgpu_device pointer
 535  *
 536  * Use the firmware interface to load the ucode images into
 537  * the driver (not loaded into hw).
 538  * Returns 0 on success, error on failure.
 539  */
 540
 541 // emulation only, won't work on real chip
 542 // vega10 real chip need to use PSP to load firmware
 543 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
 544 {
 545         const char *chip_name;
 546         char fw_name[30];
 547         int err = 0, i;
 548         struct amdgpu_firmware_info *info = NULL;
 549         const struct common_firmware_header *header = NULL;
 550
 551         DRM_DEBUG("\n");
 552
 553         switch (adev->asic_type) {
 554         case CHIP_VEGA10:
 555                 chip_name = "vega10";
 556                 break;
 557         case CHIP_VEGA12:
 558                 chip_name = "vega12";
 559                 break;
 560         case CHIP_VEGA20:
 561                 chip_name = "vega20";
 562                 break;
 563         case CHIP_RAVEN:
 564                 if (adev->rev_id >= 8)
 565                         chip_name = "raven2";
 566                 else if (adev->pdev->device == 0x15d8)
 567                         chip_name = "picasso";
 568                 else
 569                         chip_name = "raven";
 570                 break;
 571         case CHIP_ARCTURUS:
 572                 chip_name = "arcturus";
 573                 break;
 574         case CHIP_RENOIR:
 575                 chip_name = "renoir";
 576                 break;
 577         default:
 578                 BUG();
 579         }
 580
 581         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 582
 583         err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);
 584         if (err)
 585                 goto out;
 586
 587         err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[0]);
 588         if (err)
 589                 goto out;
 590
 591         for (i = 1; i < adev->sdma.num_instances; i++) {
 592                 if (adev->asic_type == CHIP_ARCTURUS) {
 593                         /* Acturus will leverage the same FW memory
 594                            for every SDMA instance */
 595                         memcpy((void*)&adev->sdma.instance[i],
 596                                (void*)&adev->sdma.instance[0],
 597                                sizeof(struct amdgpu_sdma_instance));
 598                 }
 599                 else {
 600                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i);
 601
 602                         err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 603                         if (err)
 604                                 goto out;
 605
 606                         err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[i]);
 607                         if (err)
 608                                 goto out;
 609                 }
 610         }
 611
 612         DRM_DEBUG("psp_load == '%s'\n",
 613                 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
 614
 615         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 616                 for (i = 0; i < adev->sdma.num_instances; i++) {
 617                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 618                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 619                         info->fw = adev->sdma.instance[i].fw;
 620                         header = (const struct common_firmware_header *)info->fw->data;
 621                         adev->firmware.fw_size +=
 622                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 623                 }
 624         }
 625
 626 out:
 627         if (err) {
 628                 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name);
 629                 sdma_v4_0_destroy_inst_ctx(adev);
 630         }
 631         return err;
 632 }
 633
 634 /**
 635  * sdma_v4_0_ring_get_rptr - get the current read pointer
 636  *
 637  * @ring: amdgpu ring pointer
 638  *
 639  * Get the current rptr from the hardware (VEGA10+).
 640  */
 641 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring)
 642 {
 643         u64 *rptr;
 644
 645         /* XXX check if swapping is necessary on BE */
 646         rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
 647
 648         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 649         return ((*rptr) >> 2);
 650 }
 651
 652 /**
 653  * sdma_v4_0_ring_get_wptr - get the current write pointer
 654  *
 655  * @ring: amdgpu ring pointer
 656  *
 657  * Get the current wptr from the hardware (VEGA10+).
 658  */
 659 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
 660 {
 661         struct amdgpu_device *adev = ring->adev;
 662         u64 wptr;
 663
 664         if (ring->use_doorbell) {
 665                 /* XXX check if swapping is necessary on BE */
 666                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 667                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 668         } else {
 669                 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI);
 670                 wptr = wptr << 32;
 671                 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR);
 672                 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n",
 673                                 ring->me, wptr);
 674         }
 675
 676         return wptr >> 2;
 677 }
 678
 679 /**
 680  * sdma_v4_0_page_ring_set_wptr - commit the write pointer
 681  *
 682  * @ring: amdgpu ring pointer
 683  *
 684  * Write the wptr back to the hardware (VEGA10+).
 685  */
 686 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
 687 {
 688         struct amdgpu_device *adev = ring->adev;
 689
 690         DRM_DEBUG("Setting write pointer\n");
 691         if (ring->use_doorbell) {
 692                 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
 693
 694                 DRM_DEBUG("Using doorbell -- "
 695                                 "wptr_offs == 0x%08x "
 696                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 697                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 698                                 ring->wptr_offs,
 699                                 lower_32_bits(ring->wptr << 2),
 700                                 upper_32_bits(ring->wptr << 2));
 701                 /* XXX check if swapping is necessary on BE */
 702                 WRITE_ONCE(*wb, (ring->wptr << 2));
 703                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 704                                 ring->doorbell_index, ring->wptr << 2);
 705                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 706         } else {
 707                 DRM_DEBUG("Not using doorbell -- "
 708                                 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 709                                 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 710                                 ring->me,
 711                                 lower_32_bits(ring->wptr << 2),
 712                                 ring->me,
 713                                 upper_32_bits(ring->wptr << 2));
 714                 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR,
 715                             lower_32_bits(ring->wptr << 2));
 716                 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI,
 717                             upper_32_bits(ring->wptr << 2));
 718         }
 719 }
 720
 721 /**
 722  * sdma_v4_0_page_ring_get_wptr - get the current write pointer
 723  *
 724  * @ring: amdgpu ring pointer
 725  *
 726  * Get the current wptr from the hardware (VEGA10+).
 727  */
 728 static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring)
 729 {
 730         struct amdgpu_device *adev = ring->adev;
 731         u64 wptr;
 732
 733         if (ring->use_doorbell) {
 734                 /* XXX check if swapping is necessary on BE */
 735                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 736         } else {
 737                 wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI);
 738                 wptr = wptr << 32;
 739                 wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR);
 740         }
 741
 742         return wptr >> 2;
 743 }
 744
 745 /**
 746  * sdma_v4_0_ring_set_wptr - commit the write pointer
 747  *
 748  * @ring: amdgpu ring pointer
 749  *
 750  * Write the wptr back to the hardware (VEGA10+).
 751  */
 752 static void sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring *ring)
 753 {
 754         struct amdgpu_device *adev = ring->adev;
 755
 756         if (ring->use_doorbell) {
 757                 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
 758
 759                 /* XXX check if swapping is necessary on BE */
 760                 WRITE_ONCE(*wb, (ring->wptr << 2));
 761                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 762         } else {
 763                 uint64_t wptr = ring->wptr << 2;
 764
 765                 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR,
 766                             lower_32_bits(wptr));
 767                 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI,
 768                             upper_32_bits(wptr));
 769         }
 770 }
 771
 772 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 773 {
 774         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 775         int i;
 776
 777         for (i = 0; i < count; i++)
 778                 if (sdma && sdma->burst_nop && (i == 0))
 779                         amdgpu_ring_write(ring, ring->funcs->nop |
 780                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 781                 else
 782                         amdgpu_ring_write(ring, ring->funcs->nop);
 783 }
 784
 785 /**
 786  * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine
 787  *
 788  * @ring: amdgpu ring pointer
 789  * @ib: IB object to schedule
 790  *
 791  * Schedule an IB in the DMA ring (VEGA10).
 792  */
 793 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
 794                                    struct amdgpu_job *job,
 795                                    struct amdgpu_ib *ib,
 796                                    uint32_t flags)
 797 {
 798         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 799
 800         /* IB packet must end on a 8 DW boundary */
 801         sdma_v4_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 802
 803         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 804                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 805         /* base must be 32 byte aligned */
 806         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 807         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 808         amdgpu_ring_write(ring, ib->length_dw);
 809         amdgpu_ring_write(ring, 0);
 810         amdgpu_ring_write(ring, 0);
 811
 812 }
 813
 814 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring,
 815                                    int mem_space, int hdp,
 816                                    uint32_t addr0, uint32_t addr1,
 817                                    uint32_t ref, uint32_t mask,
 818                                    uint32_t inv)
 819 {
 820         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 821                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) |
 822                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) |
 823                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 824         if (mem_space) {
 825                 /* memory */
 826                 amdgpu_ring_write(ring, addr0);
 827                 amdgpu_ring_write(ring, addr1);
 828         } else {
 829                 /* registers */
 830                 amdgpu_ring_write(ring, addr0 << 2);
 831                 amdgpu_ring_write(ring, addr1 << 2);
 832         }
 833         amdgpu_ring_write(ring, ref); /* reference */
 834         amdgpu_ring_write(ring, mask); /* mask */
 835         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 836                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */
 837 }
 838
 839 /**
 840  * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 841  *
 842  * @ring: amdgpu ring pointer
 843  *
 844  * Emit an hdp flush packet on the requested DMA ring.
 845  */
 846 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 847 {
 848         struct amdgpu_device *adev = ring->adev;
 849         u32 ref_and_mask = 0;
 850         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 851
 852         ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
 853
 854         sdma_v4_0_wait_reg_mem(ring, 0, 1,
 855                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
 856                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
 857                                ref_and_mask, ref_and_mask, 10);
 858 }
 859
 860 /**
 861  * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring
 862  *
 863  * @ring: amdgpu ring pointer
 864  * @fence: amdgpu fence object
 865  *
 866  * Add a DMA fence packet to the ring to write
 867  * the fence seq number and DMA trap packet to generate
 868  * an interrupt if needed (VEGA10).
 869  */
 870 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 871                                       unsigned flags)
 872 {
 873         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 874         /* write the fence */
 875         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 876         /* zero in first two bits */
 877         BUG_ON(addr & 0x3);
 878         amdgpu_ring_write(ring, lower_32_bits(addr));
 879         amdgpu_ring_write(ring, upper_32_bits(addr));
 880         amdgpu_ring_write(ring, lower_32_bits(seq));
 881
 882         /* optionally write high bits as well */
 883         if (write64bit) {
 884                 addr += 4;
 885                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 886                 /* zero in first two bits */
 887                 BUG_ON(addr & 0x3);
 888                 amdgpu_ring_write(ring, lower_32_bits(addr));
 889                 amdgpu_ring_write(ring, upper_32_bits(addr));
 890                 amdgpu_ring_write(ring, upper_32_bits(seq));
 891         }
 892
 893         /* generate an interrupt */
 894         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 895         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 896 }
 897
 898
 899 /**
 900  * sdma_v4_0_gfx_stop - stop the gfx async dma engines
 901  *
 902  * @adev: amdgpu_device pointer
 903  *
 904  * Stop the gfx async dma ring buffers (VEGA10).
 905  */
 906 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev)
 907 {
 908         struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
 909         u32 rb_cntl, ib_cntl;
 910         int i, unset = 0;
 911
 912         for (i = 0; i < adev->sdma.num_instances; i++) {
 913                 sdma[i] = &adev->sdma.instance[i].ring;
 914
 915                 if ((adev->mman.buffer_funcs_ring == sdma[i]) && unset != 1) {
 916                         amdgpu_ttm_set_buffer_funcs_status(adev, false);
 917                         unset = 1;
 918                 }
 919
 920                 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
 921                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 922                 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
 923                 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
 924                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 925                 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
 926
 927                 sdma[i]->sched.ready = false;
 928         }
 929 }
 930
 931 /**
 932  * sdma_v4_0_rlc_stop - stop the compute async dma engines
 933  *
 934  * @adev: amdgpu_device pointer
 935  *
 936  * Stop the compute async dma queues (VEGA10).
 937  */
 938 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev)
 939 {
 940         /* XXX todo */
 941 }
 942
 943 /**
 944  * sdma_v4_0_page_stop - stop the page async dma engines
 945  *
 946  * @adev: amdgpu_device pointer
 947  *
 948  * Stop the page async dma ring buffers (VEGA10).
 949  */
 950 static void sdma_v4_0_page_stop(struct amdgpu_device *adev)
 951 {
 952         struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
 953         u32 rb_cntl, ib_cntl;
 954         int i;
 955         bool unset = false;
 956
 957         for (i = 0; i < adev->sdma.num_instances; i++) {
 958                 sdma[i] = &adev->sdma.instance[i].page;
 959
 960                 if ((adev->mman.buffer_funcs_ring == sdma[i]) &&
 961                         (unset == false)) {
 962                         amdgpu_ttm_set_buffer_funcs_status(adev, false);
 963                         unset = true;
 964                 }
 965
 966                 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);
 967                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
 968                                         RB_ENABLE, 0);
 969                 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
 970                 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL);
 971                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL,
 972                                         IB_ENABLE, 0);
 973                 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
 974
 975                 sdma[i]->sched.ready = false;
 976         }
 977 }
 978
 979 /**
 980  * sdma_v4_0_ctx_switch_enable - stop the async dma engines context switch
 981  *
 982  * @adev: amdgpu_device pointer
 983  * @enable: enable/disable the DMA MEs context switch.
 984  *
 985  * Halt or unhalt the async dma engines context switch (VEGA10).
 986  */
 987 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 988 {
 989         u32 f32_cntl, phase_quantum = 0;
 990         int i;
 991
 992         if (amdgpu_sdma_phase_quantum) {
 993                 unsigned value = amdgpu_sdma_phase_quantum;
 994                 unsigned unit = 0;
 995
 996                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 997                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 998                         value = (value + 1) >> 1;
 999                         unit++;
1000                 }
1001                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
1002                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
1003                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
1004                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
1005                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
1006                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
1007                         WARN_ONCE(1,
1008                         "clamping sdma_phase_quantum to %uK clock cycles\n",
1009                                   value << unit);
1010                 }
1011                 phase_quantum =
1012                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
1013                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
1014         }
1015
1016         for (i = 0; i < adev->sdma.num_instances; i++) {
1017                 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL);
1018                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
1019                                 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
1020                 if (enable && amdgpu_sdma_phase_quantum) {
1021                         WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum);
1022                         WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum);
1023                         WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum);
1024                 }
1025                 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl);
1026         }
1027
1028 }
1029
1030 /**
1031  * sdma_v4_0_enable - stop the async dma engines
1032  *
1033  * @adev: amdgpu_device pointer
1034  * @enable: enable/disable the DMA MEs.
1035  *
1036  * Halt or unhalt the async dma engines (VEGA10).
1037  */
1038 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable)
1039 {
1040         u32 f32_cntl;
1041         int i;
1042
1043         if (enable == false) {
1044                 sdma_v4_0_gfx_stop(adev);
1045                 sdma_v4_0_rlc_stop(adev);
1046                 if (adev->sdma.has_page_queue)
1047                         sdma_v4_0_page_stop(adev);
1048         }
1049
1050         for (i = 0; i < adev->sdma.num_instances; i++) {
1051                 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
1052                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
1053                 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl);
1054         }
1055 }
1056
1057 /**
1058  * sdma_v4_0_rb_cntl - get parameters for rb_cntl
1059  */
1060 static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl)
1061 {
1062         /* Set ring buffer size in dwords */
1063         uint32_t rb_bufsz = order_base_2(ring->ring_size / 4);
1064
1065         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
1066 #ifdef __BIG_ENDIAN
1067         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
1068         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
1069                                 RPTR_WRITEBACK_SWAP_ENABLE, 1);
1070 #endif
1071         return rb_cntl;
1072 }
1073
1074 /**
1075  * sdma_v4_0_gfx_resume - setup and start the async dma engines
1076  *
1077  * @adev: amdgpu_device pointer
1078  * @i: instance to resume
1079  *
1080  * Set up the gfx DMA ring buffers and enable them (VEGA10).
1081  * Returns 0 for success, error for failure.
1082  */
1083 static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i)
1084 {
1085         struct amdgpu_ring *ring = &adev->sdma.instance[i].ring;
1086         u32 rb_cntl, ib_cntl, wptr_poll_cntl;
1087         u32 wb_offset;
1088         u32 doorbell;
1089         u32 doorbell_offset;
1090         u64 wptr_gpu_addr;
1091
1092         wb_offset = (ring->rptr_offs * 4);
1093
1094         rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
1095         rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl);
1096         WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
1097
1098         /* Initialize the ring buffer's read and write pointers */
1099         WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0);
1100         WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0);
1101         WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0);
1102         WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0);
1103
1104         /* set the wb address whether it's enabled or not */
1105         WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI,
1106                upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
1107         WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO,
1108                lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
1109
1110         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
1111                                 RPTR_WRITEBACK_ENABLE, 1);
1112
1113         WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8);
1114         WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40);
1115
1116         ring->wptr = 0;
1117
1118         /* before programing wptr to a less value, need set minor_ptr_update first */
1119         WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1);
1120
1121         doorbell = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL);
1122         doorbell_offset = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET);
1123
1124         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE,
1125                                  ring->use_doorbell);
1126         doorbell_offset = REG_SET_FIELD(doorbell_offset,
1127                                         SDMA0_GFX_DOORBELL_OFFSET,
1128                                         OFFSET, ring->doorbell_index);
1129         WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell);
1130         WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset);
1131
1132         sdma_v4_0_ring_set_wptr(ring);
1133
1134         /* set minor_ptr_update to 0 after wptr programed */
1135         WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0);
1136
1137         /* setup the wptr shadow polling */
1138         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1139         WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO,
1140                     lower_32_bits(wptr_gpu_addr));
1141         WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI,
1142                     upper_32_bits(wptr_gpu_addr));
1143         wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL);
1144         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
1145                                        SDMA0_GFX_RB_WPTR_POLL_CNTL,
1146                                        F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
1147         WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
1148
1149         /* enable DMA RB */
1150         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
1151         WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
1152
1153         ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
1154         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
1155 #ifdef __BIG_ENDIAN
1156         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
1157 #endif
1158         /* enable DMA IBs */
1159         WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
1160
1161         ring->sched.ready = true;
1162 }
1163
1164 /**
1165  * sdma_v4_0_page_resume - setup and start the async dma engines
1166  *
1167  * @adev: amdgpu_device pointer
1168  * @i: instance to resume
1169  *
1170  * Set up the page DMA ring buffers and enable them (VEGA10).
1171  * Returns 0 for success, error for failure.
1172  */
1173 static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i)
1174 {
1175         struct amdgpu_ring *ring = &adev->sdma.instance[i].page;
1176         u32 rb_cntl, ib_cntl, wptr_poll_cntl;
1177         u32 wb_offset;
1178         u32 doorbell;
1179         u32 doorbell_offset;
1180         u64 wptr_gpu_addr;
1181
1182         wb_offset = (ring->rptr_offs * 4);
1183
1184         rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);
1185         rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl);
1186         WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
1187
1188         /* Initialize the ring buffer's read and write pointers */
1189         WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR, 0);
1190         WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_HI, 0);
1191         WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR, 0);
1192         WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_HI, 0);
1193
1194         /* set the wb address whether it's enabled or not */
1195         WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_HI,
1196                upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
1197         WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_LO,
1198                lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
1199
1200         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
1201                                 RPTR_WRITEBACK_ENABLE, 1);
1202
1203         WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE, ring->gpu_addr >> 8);
1204         WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE_HI, ring->gpu_addr >> 40);
1205
1206         ring->wptr = 0;
1207
1208         /* before programing wptr to a less value, need set minor_ptr_update first */
1209         WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 1);
1210
1211         doorbell = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL);
1212         doorbell_offset = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET);
1213
1214         doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE,
1215                                  ring->use_doorbell);
1216         doorbell_offset = REG_SET_FIELD(doorbell_offset,
1217                                         SDMA0_PAGE_DOORBELL_OFFSET,
1218                                         OFFSET, ring->doorbell_index);
1219         WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell);
1220         WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset);
1221
1222         /* paging queue doorbell range is setup at sdma_v4_0_gfx_resume */
1223         sdma_v4_0_page_ring_set_wptr(ring);
1224
1225         /* set minor_ptr_update to 0 after wptr programed */
1226         WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0);
1227
1228         /* setup the wptr shadow polling */
1229         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1230         WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO,
1231                     lower_32_bits(wptr_gpu_addr));
1232         WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI,
1233                     upper_32_bits(wptr_gpu_addr));
1234         wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL);
1235         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
1236                                        SDMA0_PAGE_RB_WPTR_POLL_CNTL,
1237                                        F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
1238         WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
1239
1240         /* enable DMA RB */
1241         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1);
1242         WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
1243
1244         ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL);
1245         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_ENABLE, 1);
1246 #ifdef __BIG_ENDIAN
1247         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1);
1248 #endif
1249         /* enable DMA IBs */
1250         WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
1251
1252         ring->sched.ready = true;
1253 }
1254
1255 static void
1256 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable)
1257 {
1258         uint32_t def, data;
1259
1260         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) {
1261                 /* enable idle interrupt */
1262                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1263                 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1264
1265                 if (data != def)
1266                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1267         } else {
1268                 /* disable idle interrupt */
1269                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1270                 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1271                 if (data != def)
1272                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1273         }
1274 }
1275
1276 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev)
1277 {
1278         uint32_t def, data;
1279
1280         /* Enable HW based PG. */
1281         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1282         data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK;
1283         if (data != def)
1284                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1285
1286         /* enable interrupt */
1287         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1288         data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1289         if (data != def)
1290                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1291
1292         /* Configure hold time to filter in-valid power on/off request. Use default right now */
1293         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1294         data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK;
1295         data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK);
1296         /* Configure switch time for hysteresis purpose. Use default right now */
1297         data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK;
1298         data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK);
1299         if(data != def)
1300                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1301 }
1302
1303 static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
1304 {
1305         if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA))
1306                 return;
1307
1308         switch (adev->asic_type) {
1309         case CHIP_RAVEN:
1310         case CHIP_RENOIR:
1311                 sdma_v4_1_init_power_gating(adev);
1312                 sdma_v4_1_update_power_gating(adev, true);
1313                 break;
1314         default:
1315                 break;
1316         }
1317 }
1318
1319 /**
1320  * sdma_v4_0_rlc_resume - setup and start the async dma engines
1321  *
1322  * @adev: amdgpu_device pointer
1323  *
1324  * Set up the compute DMA queues and enable them (VEGA10).
1325  * Returns 0 for success, error for failure.
1326  */
1327 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev)
1328 {
1329         sdma_v4_0_init_pg(adev);
1330
1331         return 0;
1332 }
1333
1334 /**
1335  * sdma_v4_0_load_microcode - load the sDMA ME ucode
1336  *
1337  * @adev: amdgpu_device pointer
1338  *
1339  * Loads the sDMA0/1 ucode.
1340  * Returns 0 for success, -EINVAL if the ucode is not available.
1341  */
1342 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev)
1343 {
1344         const struct sdma_firmware_header_v1_0 *hdr;
1345         const __le32 *fw_data;
1346         u32 fw_size;
1347         int i, j;
1348
1349         /* halt the MEs */
1350         sdma_v4_0_enable(adev, false);
1351
1352         for (i = 0; i < adev->sdma.num_instances; i++) {
1353                 if (!adev->sdma.instance[i].fw)
1354                         return -EINVAL;
1355
1356                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
1357                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
1358                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1359
1360                 fw_data = (const __le32 *)
1361                         (adev->sdma.instance[i].fw->data +
1362                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1363
1364                 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0);
1365
1366                 for (j = 0; j < fw_size; j++)
1367                         WREG32_SDMA(i, mmSDMA0_UCODE_DATA,
1368                                     le32_to_cpup(fw_data++));
1369
1370                 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR,
1371                             adev->sdma.instance[i].fw_version);
1372         }
1373
1374         return 0;
1375 }
1376
1377 /**
1378  * sdma_v4_0_start - setup and start the async dma engines
1379  *
1380  * @adev: amdgpu_device pointer
1381  *
1382  * Set up the DMA engines and enable them (VEGA10).
1383  * Returns 0 for success, error for failure.
1384  */
1385 static int sdma_v4_0_start(struct amdgpu_device *adev)
1386 {
1387         struct amdgpu_ring *ring;
1388         int i, r = 0;
1389
1390         if (amdgpu_sriov_vf(adev)) {
1391                 sdma_v4_0_ctx_switch_enable(adev, false);
1392                 sdma_v4_0_enable(adev, false);
1393         } else {
1394
1395                 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1396                         r = sdma_v4_0_load_microcode(adev);
1397                         if (r)
1398                                 return r;
1399                 }
1400
1401                 /* unhalt the MEs */
1402                 sdma_v4_0_enable(adev, true);
1403                 /* enable sdma ring preemption */
1404                 sdma_v4_0_ctx_switch_enable(adev, true);
1405         }
1406
1407         /* start the gfx rings and rlc compute queues */
1408         for (i = 0; i < adev->sdma.num_instances; i++) {
1409                 uint32_t temp;
1410
1411                 WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0);
1412                 sdma_v4_0_gfx_resume(adev, i);
1413                 if (adev->sdma.has_page_queue)
1414                         sdma_v4_0_page_resume(adev, i);
1415
1416                 /* set utc l1 enable flag always to 1 */
1417                 temp = RREG32_SDMA(i, mmSDMA0_CNTL);
1418                 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
1419                 WREG32_SDMA(i, mmSDMA0_CNTL, temp);
1420
1421                 if (!amdgpu_sriov_vf(adev)) {
1422                         /* unhalt engine */
1423                         temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
1424                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
1425                         WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp);
1426                 }
1427         }
1428
1429         if (amdgpu_sriov_vf(adev)) {
1430                 sdma_v4_0_ctx_switch_enable(adev, true);
1431                 sdma_v4_0_enable(adev, true);
1432         } else {
1433                 r = sdma_v4_0_rlc_resume(adev);
1434                 if (r)
1435                         return r;
1436         }
1437
1438         for (i = 0; i < adev->sdma.num_instances; i++) {
1439                 ring = &adev->sdma.instance[i].ring;
1440
1441                 r = amdgpu_ring_test_helper(ring);
1442                 if (r)
1443                         return r;
1444
1445                 if (adev->sdma.has_page_queue) {
1446                         struct amdgpu_ring *page = &adev->sdma.instance[i].page;
1447
1448                         r = amdgpu_ring_test_helper(page);
1449                         if (r)
1450                                 return r;
1451
1452                         if (adev->mman.buffer_funcs_ring == page)
1453                                 amdgpu_ttm_set_buffer_funcs_status(adev, true);
1454                 }
1455
1456                 if (adev->mman.buffer_funcs_ring == ring)
1457                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
1458         }
1459
1460         return r;
1461 }
1462
1463 /**
1464  * sdma_v4_0_ring_test_ring - simple async dma engine test
1465  *
1466  * @ring: amdgpu_ring structure holding ring information
1467  *
1468  * Test the DMA engine by writing using it to write an
1469  * value to memory. (VEGA10).
1470  * Returns 0 for success, error for failure.
1471  */
1472 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring)
1473 {
1474         struct amdgpu_device *adev = ring->adev;
1475         unsigned i;
1476         unsigned index;
1477         int r;
1478         u32 tmp;
1479         u64 gpu_addr;
1480
1481         r = amdgpu_device_wb_get(adev, &index);
1482         if (r)
1483                 return r;
1484
1485         gpu_addr = adev->wb.gpu_addr + (index * 4);
1486         tmp = 0xCAFEDEAD;
1487         adev->wb.wb[index] = cpu_to_le32(tmp);
1488
1489         r = amdgpu_ring_alloc(ring, 5);
1490         if (r)
1491                 goto error_free_wb;
1492
1493         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1494                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
1495         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
1496         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
1497         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
1498         amdgpu_ring_write(ring, 0xDEADBEEF);
1499         amdgpu_ring_commit(ring);
1500
1501         for (i = 0; i < adev->usec_timeout; i++) {
1502                 tmp = le32_to_cpu(adev->wb.wb[index]);
1503                 if (tmp == 0xDEADBEEF)
1504                         break;
1505                 udelay(1);
1506         }
1507
1508         if (i >= adev->usec_timeout)
1509                 r = -ETIMEDOUT;
1510
1511 error_free_wb:
1512         amdgpu_device_wb_free(adev, index);
1513         return r;
1514 }
1515
1516 /**
1517  * sdma_v4_0_ring_test_ib - test an IB on the DMA engine
1518  *
1519  * @ring: amdgpu_ring structure holding ring information
1520  *
1521  * Test a simple IB in the DMA ring (VEGA10).
1522  * Returns 0 on success, error on failure.
1523  */
1524 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1525 {
1526         struct amdgpu_device *adev = ring->adev;
1527         struct amdgpu_ib ib;
1528         struct dma_fence *f = NULL;
1529         unsigned index;
1530         long r;
1531         u32 tmp = 0;
1532         u64 gpu_addr;
1533
1534         r = amdgpu_device_wb_get(adev, &index);
1535         if (r)
1536                 return r;
1537
1538         gpu_addr = adev->wb.gpu_addr + (index * 4);
1539         tmp = 0xCAFEDEAD;
1540         adev->wb.wb[index] = cpu_to_le32(tmp);
1541         memset(&ib, 0, sizeof(ib));
1542         r = amdgpu_ib_get(adev, NULL, 256, &ib);
1543         if (r)
1544                 goto err0;
1545
1546         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1547                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1548         ib.ptr[1] = lower_32_bits(gpu_addr);
1549         ib.ptr[2] = upper_32_bits(gpu_addr);
1550         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1551         ib.ptr[4] = 0xDEADBEEF;
1552         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1553         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1554         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1555         ib.length_dw = 8;
1556
1557         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1558         if (r)
1559                 goto err1;
1560
1561         r = dma_fence_wait_timeout(f, false, timeout);
1562         if (r == 0) {
1563                 r = -ETIMEDOUT;
1564                 goto err1;
1565         } else if (r < 0) {
1566                 goto err1;
1567         }
1568         tmp = le32_to_cpu(adev->wb.wb[index]);
1569         if (tmp == 0xDEADBEEF)
1570                 r = 0;
1571         else
1572                 r = -EINVAL;
1573
1574 err1:
1575         amdgpu_ib_free(adev, &ib, NULL);
1576         dma_fence_put(f);
1577 err0:
1578         amdgpu_device_wb_free(adev, index);
1579         return r;
1580 }
1581
1582
1583 /**
1584  * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART
1585  *
1586  * @ib: indirect buffer to fill with commands
1587  * @pe: addr of the page entry
1588  * @src: src addr to copy from
1589  * @count: number of page entries to update
1590  *
1591  * Update PTEs by copying them from the GART using sDMA (VEGA10).
1592  */
1593 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib,
1594                                   uint64_t pe, uint64_t src,
1595                                   unsigned count)
1596 {
1597         unsigned bytes = count * 8;
1598
1599         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1600                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1601         ib->ptr[ib->length_dw++] = bytes - 1;
1602         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1603         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1604         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1605         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1606         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1607
1608 }
1609
1610 /**
1611  * sdma_v4_0_vm_write_pte - update PTEs by writing them manually
1612  *
1613  * @ib: indirect buffer to fill with commands
1614  * @pe: addr of the page entry
1615  * @addr: dst addr to write into pe
1616  * @count: number of page entries to update
1617  * @incr: increase next addr by incr bytes
1618  * @flags: access flags
1619  *
1620  * Update PTEs by writing them manually using sDMA (VEGA10).
1621  */
1622 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1623                                    uint64_t value, unsigned count,
1624                                    uint32_t incr)
1625 {
1626         unsigned ndw = count * 2;
1627
1628         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1629                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1630         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1631         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1632         ib->ptr[ib->length_dw++] = ndw - 1;
1633         for (; ndw > 0; ndw -= 2) {
1634                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1635                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1636                 value += incr;
1637         }
1638 }
1639
1640 /**
1641  * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA
1642  *
1643  * @ib: indirect buffer to fill with commands
1644  * @pe: addr of the page entry
1645  * @addr: dst addr to write into pe
1646  * @count: number of page entries to update
1647  * @incr: increase next addr by incr bytes
1648  * @flags: access flags
1649  *
1650  * Update the page tables using sDMA (VEGA10).
1651  */
1652 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1653                                      uint64_t pe,
1654                                      uint64_t addr, unsigned count,
1655                                      uint32_t incr, uint64_t flags)
1656 {
1657         /* for physically contiguous pages (vram) */
1658         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1659         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1660         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1661         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1662         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1663         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1664         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1665         ib->ptr[ib->length_dw++] = incr; /* increment size */
1666         ib->ptr[ib->length_dw++] = 0;
1667         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1668 }
1669
1670 /**
1671  * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw
1672  *
1673  * @ib: indirect buffer to fill with padding
1674  *
1675  */
1676 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1677 {
1678         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1679         u32 pad_count;
1680         int i;
1681
1682         pad_count = (-ib->length_dw) & 7;
1683         for (i = 0; i < pad_count; i++)
1684                 if (sdma && sdma->burst_nop && (i == 0))
1685                         ib->ptr[ib->length_dw++] =
1686                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1687                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1688                 else
1689                         ib->ptr[ib->length_dw++] =
1690                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1691 }
1692
1693
1694 /**
1695  * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline
1696  *
1697  * @ring: amdgpu_ring pointer
1698  *
1699  * Make sure all previous operations are completed (CIK).
1700  */
1701 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1702 {
1703         uint32_t seq = ring->fence_drv.sync_seq;
1704         uint64_t addr = ring->fence_drv.gpu_addr;
1705
1706         /* wait for idle */
1707         sdma_v4_0_wait_reg_mem(ring, 1, 0,
1708                                addr & 0xfffffffc,
1709                                upper_32_bits(addr) & 0xffffffff,
1710                                seq, 0xffffffff, 4);
1711 }
1712
1713
1714 /**
1715  * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA
1716  *
1717  * @ring: amdgpu_ring pointer
1718  * @vm: amdgpu_vm pointer
1719  *
1720  * Update the page table base and flush the VM TLB
1721  * using sDMA (VEGA10).
1722  */
1723 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1724                                          unsigned vmid, uint64_t pd_addr)
1725 {
1726         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1727 }
1728
1729 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring,
1730                                      uint32_t reg, uint32_t val)
1731 {
1732         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1733                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1734         amdgpu_ring_write(ring, reg);
1735         amdgpu_ring_write(ring, val);
1736 }
1737
1738 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1739                                          uint32_t val, uint32_t mask)
1740 {
1741         sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
1742 }
1743
1744 static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev)
1745 {
1746         uint fw_version = adev->sdma.instance[0].fw_version;
1747
1748         switch (adev->asic_type) {
1749         case CHIP_VEGA10:
1750                 return fw_version >= 430;
1751         case CHIP_VEGA12:
1752                 /*return fw_version >= 31;*/
1753                 return false;
1754         case CHIP_VEGA20:
1755                 return fw_version >= 123;
1756         default:
1757                 return false;
1758         }
1759 }
1760
1761 static int sdma_v4_0_early_init(void *handle)
1762 {
1763         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1764         int r;
1765
1766         if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_RENOIR)
1767                 adev->sdma.num_instances = 1;
1768         else if (adev->asic_type == CHIP_ARCTURUS)
1769                 adev->sdma.num_instances = 8;
1770         else
1771                 adev->sdma.num_instances = 2;
1772
1773         r = sdma_v4_0_init_microcode(adev);
1774         if (r) {
1775                 DRM_ERROR("Failed to load sdma firmware!\n");
1776                 return r;
1777         }
1778
1779         /* TODO: Page queue breaks driver reload under SRIOV */
1780         if ((adev->asic_type == CHIP_VEGA10) && amdgpu_sriov_vf((adev)))
1781                 adev->sdma.has_page_queue = false;
1782         else if (sdma_v4_0_fw_support_paging_queue(adev))
1783                 adev->sdma.has_page_queue = true;
1784
1785         sdma_v4_0_set_ring_funcs(adev);
1786         sdma_v4_0_set_buffer_funcs(adev);
1787         sdma_v4_0_set_vm_pte_funcs(adev);
1788         sdma_v4_0_set_irq_funcs(adev);
1789         sdma_v4_0_set_ras_funcs(adev);
1790
1791         return 0;
1792 }
1793
1794 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
1795                 void *err_data,
1796                 struct amdgpu_iv_entry *entry);
1797
1798 static int sdma_v4_0_late_init(void *handle)
1799 {
1800         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1801         struct ras_ih_if ih_info = {
1802                 .cb = sdma_v4_0_process_ras_data_cb,
1803         };
1804
1805         if (adev->sdma.funcs && adev->sdma.funcs->reset_ras_error_count)
1806                 adev->sdma.funcs->reset_ras_error_count(adev);
1807
1808         if (adev->sdma.funcs && adev->sdma.funcs->ras_late_init)
1809                 return adev->sdma.funcs->ras_late_init(adev, &ih_info);
1810         else
1811                 return 0;
1812 }
1813
1814 static int sdma_v4_0_sw_init(void *handle)
1815 {
1816         struct amdgpu_ring *ring;
1817         int r, i;
1818         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1819
1820         /* SDMA trap event */
1821         for (i = 0; i < adev->sdma.num_instances; i++) {
1822                 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1823                                       SDMA0_4_0__SRCID__SDMA_TRAP,
1824                                       &adev->sdma.trap_irq);
1825                 if (r)
1826                         return r;
1827         }
1828
1829         /* SDMA SRAM ECC event */
1830         for (i = 0; i < adev->sdma.num_instances; i++) {
1831                 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1832                                       SDMA0_4_0__SRCID__SDMA_SRAM_ECC,
1833                                       &adev->sdma.ecc_irq);
1834                 if (r)
1835                         return r;
1836         }
1837
1838         for (i = 0; i < adev->sdma.num_instances; i++) {
1839                 ring = &adev->sdma.instance[i].ring;
1840                 ring->ring_obj = NULL;
1841                 ring->use_doorbell = true;
1842
1843                 DRM_INFO("use_doorbell being set to: [%s]\n",
1844                                 ring->use_doorbell?"true":"false");
1845
1846                 /* doorbell size is 2 dwords, get DWORD offset */
1847                 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1848
1849                 sprintf(ring->name, "sdma%d", i);
1850                 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1851                                      AMDGPU_SDMA_IRQ_INSTANCE0 + i);
1852                 if (r)
1853                         return r;
1854
1855                 if (adev->sdma.has_page_queue) {
1856                         ring = &adev->sdma.instance[i].page;
1857                         ring->ring_obj = NULL;
1858                         ring->use_doorbell = true;
1859
1860                         /* paging queue use same doorbell index/routing as gfx queue
1861                          * with 0x400 (4096 dwords) offset on second doorbell page
1862                          */
1863                         ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1864                         ring->doorbell_index += 0x400;
1865
1866                         sprintf(ring->name, "page%d", i);
1867                         r = amdgpu_ring_init(adev, ring, 1024,
1868                                              &adev->sdma.trap_irq,
1869                                              AMDGPU_SDMA_IRQ_INSTANCE0 + i);
1870                         if (r)
1871                                 return r;
1872                 }
1873         }
1874
1875         return r;
1876 }
1877
1878 static int sdma_v4_0_sw_fini(void *handle)
1879 {
1880         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1881         int i;
1882
1883         if (adev->sdma.funcs && adev->sdma.funcs->ras_fini)
1884                 adev->sdma.funcs->ras_fini(adev);
1885
1886         for (i = 0; i < adev->sdma.num_instances; i++) {
1887                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1888                 if (adev->sdma.has_page_queue)
1889                         amdgpu_ring_fini(&adev->sdma.instance[i].page);
1890         }
1891
1892         sdma_v4_0_destroy_inst_ctx(adev);
1893
1894         return 0;
1895 }
1896
1897 static int sdma_v4_0_hw_init(void *handle)
1898 {
1899         int r;
1900         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1901
1902         if ((adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs &&
1903                         adev->powerplay.pp_funcs->set_powergating_by_smu) ||
1904                         (adev->asic_type == CHIP_RENOIR && !adev->in_gpu_reset))
1905                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false);
1906
1907         if (!amdgpu_sriov_vf(adev))
1908                 sdma_v4_0_init_golden_registers(adev);
1909
1910         r = sdma_v4_0_start(adev);
1911
1912         return r;
1913 }
1914
1915 static int sdma_v4_0_hw_fini(void *handle)
1916 {
1917         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1918         int i;
1919
1920         if (amdgpu_sriov_vf(adev))
1921                 return 0;
1922
1923         for (i = 0; i < adev->sdma.num_instances; i++) {
1924                 amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
1925                                AMDGPU_SDMA_IRQ_INSTANCE0 + i);
1926         }
1927
1928         sdma_v4_0_ctx_switch_enable(adev, false);
1929         sdma_v4_0_enable(adev, false);
1930
1931         if ((adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs
1932                         && adev->powerplay.pp_funcs->set_powergating_by_smu) ||
1933                         adev->asic_type == CHIP_RENOIR)
1934                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true);
1935
1936         return 0;
1937 }
1938
1939 static int sdma_v4_0_suspend(void *handle)
1940 {
1941         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1942
1943         return sdma_v4_0_hw_fini(adev);
1944 }
1945
1946 static int sdma_v4_0_resume(void *handle)
1947 {
1948         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1949
1950         return sdma_v4_0_hw_init(adev);
1951 }
1952
1953 static bool sdma_v4_0_is_idle(void *handle)
1954 {
1955         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1956         u32 i;
1957
1958         for (i = 0; i < adev->sdma.num_instances; i++) {
1959                 u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG);
1960
1961                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1962                         return false;
1963         }
1964
1965         return true;
1966 }
1967
1968 static int sdma_v4_0_wait_for_idle(void *handle)
1969 {
1970         unsigned i, j;
1971         u32 sdma[AMDGPU_MAX_SDMA_INSTANCES];
1972         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1973
1974         for (i = 0; i < adev->usec_timeout; i++) {
1975                 for (j = 0; j < adev->sdma.num_instances; j++) {
1976                         sdma[j] = RREG32_SDMA(j, mmSDMA0_STATUS_REG);
1977                         if (!(sdma[j] & SDMA0_STATUS_REG__IDLE_MASK))
1978                                 break;
1979                 }
1980                 if (j == adev->sdma.num_instances)
1981                         return 0;
1982                 udelay(1);
1983         }
1984         return -ETIMEDOUT;
1985 }
1986
1987 static int sdma_v4_0_soft_reset(void *handle)
1988 {
1989         /* todo */
1990
1991         return 0;
1992 }
1993
1994 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev,
1995                                         struct amdgpu_irq_src *source,
1996                                         unsigned type,
1997                                         enum amdgpu_interrupt_state state)
1998 {
1999         u32 sdma_cntl;
2000
2001         sdma_cntl = RREG32_SDMA(type, mmSDMA0_CNTL);
2002         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
2003                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
2004         WREG32_SDMA(type, mmSDMA0_CNTL, sdma_cntl);
2005
2006         return 0;
2007 }
2008
2009 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
2010                                       struct amdgpu_irq_src *source,
2011                                       struct amdgpu_iv_entry *entry)
2012 {
2013         uint32_t instance;
2014
2015         DRM_DEBUG("IH: SDMA trap\n");
2016         instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2017         switch (entry->ring_id) {
2018         case 0:
2019                 amdgpu_fence_process(&adev->sdma.instance[instance].ring);
2020                 break;
2021         case 1:
2022                 if (adev->asic_type == CHIP_VEGA20)
2023                         amdgpu_fence_process(&adev->sdma.instance[instance].page);
2024                 break;
2025         case 2:
2026                 /* XXX compute */
2027                 break;
2028         case 3:
2029                 if (adev->asic_type != CHIP_VEGA20)
2030                         amdgpu_fence_process(&adev->sdma.instance[instance].page);
2031                 break;
2032         }
2033         return 0;
2034 }
2035
2036 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
2037                 void *err_data,
2038                 struct amdgpu_iv_entry *entry)
2039 {
2040         int instance;
2041
2042         /* When “Full RAS” is enabled, the per-IP interrupt sources should
2043          * be disabled and the driver should only look for the aggregated
2044          * interrupt via sync flood
2045          */
2046         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
2047                 goto out;
2048
2049         instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2050         if (instance < 0)
2051                 goto out;
2052
2053         amdgpu_sdma_process_ras_data_cb(adev, err_data, entry);
2054
2055 out:
2056         return AMDGPU_RAS_SUCCESS;
2057 }
2058
2059 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev,
2060                                               struct amdgpu_irq_src *source,
2061                                               struct amdgpu_iv_entry *entry)
2062 {
2063         int instance;
2064
2065         DRM_ERROR("Illegal instruction in SDMA command stream\n");
2066
2067         instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2068         if (instance < 0)
2069                 return 0;
2070
2071         switch (entry->ring_id) {
2072         case 0:
2073                 drm_sched_fault(&adev->sdma.instance[instance].ring.sched);
2074                 break;
2075         }
2076         return 0;
2077 }
2078
2079 static int sdma_v4_0_set_ecc_irq_state(struct amdgpu_device *adev,
2080                                         struct amdgpu_irq_src *source,
2081                                         unsigned type,
2082                                         enum amdgpu_interrupt_state state)
2083 {
2084         u32 sdma_edc_config;
2085
2086         sdma_edc_config = RREG32_SDMA(type, mmSDMA0_EDC_CONFIG);
2087         sdma_edc_config = REG_SET_FIELD(sdma_edc_config, SDMA0_EDC_CONFIG, ECC_INT_ENABLE,
2088                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
2089         WREG32_SDMA(type, mmSDMA0_EDC_CONFIG, sdma_edc_config);
2090
2091         return 0;
2092 }
2093
2094 static void sdma_v4_0_update_medium_grain_clock_gating(
2095                 struct amdgpu_device *adev,
2096                 bool enable)
2097 {
2098         uint32_t data, def;
2099         int i;
2100
2101         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
2102                 for (i = 0; i < adev->sdma.num_instances; i++) {
2103                         def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);
2104                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
2105                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
2106                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
2107                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
2108                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
2109                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
2110                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
2111                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
2112                         if (def != data)
2113                                 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
2114                 }
2115         } else {
2116                 for (i = 0; i < adev->sdma.num_instances; i++) {
2117                         def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);
2118                         data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
2119                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
2120                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
2121                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
2122                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
2123                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
2124                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
2125                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
2126                         if (def != data)
2127                                 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
2128                 }
2129         }
2130 }
2131
2132
2133 static void sdma_v4_0_update_medium_grain_light_sleep(
2134                 struct amdgpu_device *adev,
2135                 bool enable)
2136 {
2137         uint32_t data, def;
2138         int i;
2139
2140         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
2141                 for (i = 0; i < adev->sdma.num_instances; i++) {
2142                         /* 1-not override: enable sdma mem light sleep */
2143                         def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);
2144                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
2145                         if (def != data)
2146                                 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);
2147                 }
2148         } else {
2149                 for (i = 0; i < adev->sdma.num_instances; i++) {
2150                 /* 0-override:disable sdma mem light sleep */
2151                         def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);
2152                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
2153                         if (def != data)
2154                                 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);
2155                 }
2156         }
2157 }
2158
2159 static int sdma_v4_0_set_clockgating_state(void *handle,
2160                                           enum amd_clockgating_state state)
2161 {
2162         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2163
2164         if (amdgpu_sriov_vf(adev))
2165                 return 0;
2166
2167         switch (adev->asic_type) {
2168         case CHIP_VEGA10:
2169         case CHIP_VEGA12:
2170         case CHIP_VEGA20:
2171         case CHIP_RAVEN:
2172         case CHIP_ARCTURUS:
2173         case CHIP_RENOIR:
2174                 sdma_v4_0_update_medium_grain_clock_gating(adev,
2175                                 state == AMD_CG_STATE_GATE);
2176                 sdma_v4_0_update_medium_grain_light_sleep(adev,
2177                                 state == AMD_CG_STATE_GATE);
2178                 break;
2179         default:
2180                 break;
2181         }
2182         return 0;
2183 }
2184
2185 static int sdma_v4_0_set_powergating_state(void *handle,
2186                                           enum amd_powergating_state state)
2187 {
2188         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2189
2190         switch (adev->asic_type) {
2191         case CHIP_RAVEN:
2192                 sdma_v4_1_update_power_gating(adev,
2193                                 state == AMD_PG_STATE_GATE ? true : false);
2194                 break;
2195         default:
2196                 break;
2197         }
2198
2199         return 0;
2200 }
2201
2202 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags)
2203 {
2204         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2205         int data;
2206
2207         if (amdgpu_sriov_vf(adev))
2208                 *flags = 0;
2209
2210         /* AMD_CG_SUPPORT_SDMA_MGCG */
2211         data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
2212         if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
2213                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
2214
2215         /* AMD_CG_SUPPORT_SDMA_LS */
2216         data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
2217         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
2218                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
2219 }
2220
2221 const struct amd_ip_funcs sdma_v4_0_ip_funcs = {
2222         .name = "sdma_v4_0",
2223         .early_init = sdma_v4_0_early_init,
2224         .late_init = sdma_v4_0_late_init,
2225         .sw_init = sdma_v4_0_sw_init,
2226         .sw_fini = sdma_v4_0_sw_fini,
2227         .hw_init = sdma_v4_0_hw_init,
2228         .hw_fini = sdma_v4_0_hw_fini,
2229         .suspend = sdma_v4_0_suspend,
2230         .resume = sdma_v4_0_resume,
2231         .is_idle = sdma_v4_0_is_idle,
2232         .wait_for_idle = sdma_v4_0_wait_for_idle,
2233         .soft_reset = sdma_v4_0_soft_reset,
2234         .set_clockgating_state = sdma_v4_0_set_clockgating_state,
2235         .set_powergating_state = sdma_v4_0_set_powergating_state,
2236         .get_clockgating_state = sdma_v4_0_get_clockgating_state,
2237 };
2238
2239 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
2240         .type = AMDGPU_RING_TYPE_SDMA,
2241         .align_mask = 0xf,
2242         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2243         .support_64bit_ptrs = true,
2244         .vmhub = AMDGPU_MMHUB_0,
2245         .get_rptr = sdma_v4_0_ring_get_rptr,
2246         .get_wptr = sdma_v4_0_ring_get_wptr,
2247         .set_wptr = sdma_v4_0_ring_set_wptr,
2248         .emit_frame_size =
2249                 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2250                 3 + /* hdp invalidate */
2251                 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2252                 /* sdma_v4_0_ring_emit_vm_flush */
2253                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2254                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2255                 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2256         .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2257         .emit_ib = sdma_v4_0_ring_emit_ib,
2258         .emit_fence = sdma_v4_0_ring_emit_fence,
2259         .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2260         .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2261         .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2262         .test_ring = sdma_v4_0_ring_test_ring,
2263         .test_ib = sdma_v4_0_ring_test_ib,
2264         .insert_nop = sdma_v4_0_ring_insert_nop,
2265         .pad_ib = sdma_v4_0_ring_pad_ib,
2266         .emit_wreg = sdma_v4_0_ring_emit_wreg,
2267         .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2268         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2269 };
2270
2271 /*
2272  * On Arcturus, SDMA instance 5~7 has a different vmhub type(AMDGPU_MMHUB_1).
2273  * So create a individual constant ring_funcs for those instances.
2274  */
2275 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs_2nd_mmhub = {
2276         .type = AMDGPU_RING_TYPE_SDMA,
2277         .align_mask = 0xf,
2278         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2279         .support_64bit_ptrs = true,
2280         .vmhub = AMDGPU_MMHUB_1,
2281         .get_rptr = sdma_v4_0_ring_get_rptr,
2282         .get_wptr = sdma_v4_0_ring_get_wptr,
2283         .set_wptr = sdma_v4_0_ring_set_wptr,
2284         .emit_frame_size =
2285                 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2286                 3 + /* hdp invalidate */
2287                 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2288                 /* sdma_v4_0_ring_emit_vm_flush */
2289                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2290                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2291                 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2292         .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2293         .emit_ib = sdma_v4_0_ring_emit_ib,
2294         .emit_fence = sdma_v4_0_ring_emit_fence,
2295         .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2296         .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2297         .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2298         .test_ring = sdma_v4_0_ring_test_ring,
2299         .test_ib = sdma_v4_0_ring_test_ib,
2300         .insert_nop = sdma_v4_0_ring_insert_nop,
2301         .pad_ib = sdma_v4_0_ring_pad_ib,
2302         .emit_wreg = sdma_v4_0_ring_emit_wreg,
2303         .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2304         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2305 };
2306
2307 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = {
2308         .type = AMDGPU_RING_TYPE_SDMA,
2309         .align_mask = 0xf,
2310         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2311         .support_64bit_ptrs = true,
2312         .vmhub = AMDGPU_MMHUB_0,
2313         .get_rptr = sdma_v4_0_ring_get_rptr,
2314         .get_wptr = sdma_v4_0_page_ring_get_wptr,
2315         .set_wptr = sdma_v4_0_page_ring_set_wptr,
2316         .emit_frame_size =
2317                 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2318                 3 + /* hdp invalidate */
2319                 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2320                 /* sdma_v4_0_ring_emit_vm_flush */
2321                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2322                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2323                 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2324         .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2325         .emit_ib = sdma_v4_0_ring_emit_ib,
2326         .emit_fence = sdma_v4_0_ring_emit_fence,
2327         .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2328         .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2329         .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2330         .test_ring = sdma_v4_0_ring_test_ring,
2331         .test_ib = sdma_v4_0_ring_test_ib,
2332         .insert_nop = sdma_v4_0_ring_insert_nop,
2333         .pad_ib = sdma_v4_0_ring_pad_ib,
2334         .emit_wreg = sdma_v4_0_ring_emit_wreg,
2335         .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2336         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2337 };
2338
2339 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs_2nd_mmhub = {
2340         .type = AMDGPU_RING_TYPE_SDMA,
2341         .align_mask = 0xf,
2342         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2343         .support_64bit_ptrs = true,
2344         .vmhub = AMDGPU_MMHUB_1,
2345         .get_rptr = sdma_v4_0_ring_get_rptr,
2346         .get_wptr = sdma_v4_0_page_ring_get_wptr,
2347         .set_wptr = sdma_v4_0_page_ring_set_wptr,
2348         .emit_frame_size =
2349                 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2350                 3 + /* hdp invalidate */
2351                 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2352                 /* sdma_v4_0_ring_emit_vm_flush */
2353                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2354                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2355                 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2356         .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2357         .emit_ib = sdma_v4_0_ring_emit_ib,
2358         .emit_fence = sdma_v4_0_ring_emit_fence,
2359         .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2360         .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2361         .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2362         .test_ring = sdma_v4_0_ring_test_ring,
2363         .test_ib = sdma_v4_0_ring_test_ib,
2364         .insert_nop = sdma_v4_0_ring_insert_nop,
2365         .pad_ib = sdma_v4_0_ring_pad_ib,
2366         .emit_wreg = sdma_v4_0_ring_emit_wreg,
2367         .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2368         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2369 };
2370
2371 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
2372 {
2373         int i;
2374
2375         for (i = 0; i < adev->sdma.num_instances; i++) {
2376                 if (adev->asic_type == CHIP_ARCTURUS && i >= 5)
2377                         adev->sdma.instance[i].ring.funcs =
2378                                         &sdma_v4_0_ring_funcs_2nd_mmhub;
2379                 else
2380                         adev->sdma.instance[i].ring.funcs =
2381                                         &sdma_v4_0_ring_funcs;
2382                 adev->sdma.instance[i].ring.me = i;
2383                 if (adev->sdma.has_page_queue) {
2384                         if (adev->asic_type == CHIP_ARCTURUS && i >= 5)
2385                                 adev->sdma.instance[i].page.funcs =
2386                                         &sdma_v4_0_page_ring_funcs_2nd_mmhub;
2387                         else
2388                                 adev->sdma.instance[i].page.funcs =
2389                                         &sdma_v4_0_page_ring_funcs;
2390                         adev->sdma.instance[i].page.me = i;
2391                 }
2392         }
2393 }
2394
2395 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = {
2396         .set = sdma_v4_0_set_trap_irq_state,
2397         .process = sdma_v4_0_process_trap_irq,
2398 };
2399
2400 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = {
2401         .process = sdma_v4_0_process_illegal_inst_irq,
2402 };
2403
2404 static const struct amdgpu_irq_src_funcs sdma_v4_0_ecc_irq_funcs = {
2405         .set = sdma_v4_0_set_ecc_irq_state,
2406         .process = amdgpu_sdma_process_ecc_irq,
2407 };
2408
2409
2410
2411 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev)
2412 {
2413         switch (adev->sdma.num_instances) {
2414         case 1:
2415                 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1;
2416                 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1;
2417                 break;
2418         case 8:
2419                 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
2420                 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
2421                 break;
2422         case 2:
2423         default:
2424                 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2;
2425                 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2;
2426                 break;
2427         }
2428         adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs;
2429         adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs;
2430         adev->sdma.ecc_irq.funcs = &sdma_v4_0_ecc_irq_funcs;
2431 }
2432
2433 /**
2434  * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine
2435  *
2436  * @ring: amdgpu_ring structure holding ring information
2437  * @src_offset: src GPU address
2438  * @dst_offset: dst GPU address
2439  * @byte_count: number of bytes to xfer
2440  *
2441  * Copy GPU buffers using the DMA engine (VEGA10/12).
2442  * Used by the amdgpu ttm implementation to move pages if
2443  * registered as the asic copy callback.
2444  */
2445 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib,
2446                                        uint64_t src_offset,
2447                                        uint64_t dst_offset,
2448                                        uint32_t byte_count)
2449 {
2450         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
2451                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
2452         ib->ptr[ib->length_dw++] = byte_count - 1;
2453         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
2454         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
2455         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
2456         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2457         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2458 }
2459
2460 /**
2461  * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine
2462  *
2463  * @ring: amdgpu_ring structure holding ring information
2464  * @src_data: value to write to buffer
2465  * @dst_offset: dst GPU address
2466  * @byte_count: number of bytes to xfer
2467  *
2468  * Fill GPU buffers using the DMA engine (VEGA10/12).
2469  */
2470 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib,
2471                                        uint32_t src_data,
2472                                        uint64_t dst_offset,
2473                                        uint32_t byte_count)
2474 {
2475         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
2476         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2477         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2478         ib->ptr[ib->length_dw++] = src_data;
2479         ib->ptr[ib->length_dw++] = byte_count - 1;
2480 }
2481
2482 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = {
2483         .copy_max_bytes = 0x400000,
2484         .copy_num_dw = 7,
2485         .emit_copy_buffer = sdma_v4_0_emit_copy_buffer,
2486
2487         .fill_max_bytes = 0x400000,
2488         .fill_num_dw = 5,
2489         .emit_fill_buffer = sdma_v4_0_emit_fill_buffer,
2490 };
2491
2492 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
2493 {
2494         adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
2495         if (adev->sdma.has_page_queue)
2496                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
2497         else
2498                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
2499 }
2500
2501 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = {
2502         .copy_pte_num_dw = 7,
2503         .copy_pte = sdma_v4_0_vm_copy_pte,
2504
2505         .write_pte = sdma_v4_0_vm_write_pte,
2506         .set_pte_pde = sdma_v4_0_vm_set_pte_pde,
2507 };
2508
2509 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev)
2510 {
2511         struct drm_gpu_scheduler *sched;
2512         unsigned i;
2513
2514         adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
2515         for (i = 0; i < adev->sdma.num_instances; i++) {
2516                 if (adev->sdma.has_page_queue)
2517                         sched = &adev->sdma.instance[i].page.sched;
2518                 else
2519                         sched = &adev->sdma.instance[i].ring.sched;
2520                 adev->vm_manager.vm_pte_scheds[i] = sched;
2521         }
2522         adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
2523 }
2524
2525 static void sdma_v4_0_get_ras_error_count(uint32_t value,
2526                                         uint32_t instance,
2527                                         uint32_t *sec_count)
2528 {
2529         uint32_t i;
2530         uint32_t sec_cnt;
2531
2532         /* double bits error (multiple bits) error detection is not supported */
2533         for (i = 0; i < ARRAY_SIZE(sdma_v4_0_ras_fields); i++) {
2534                 /* the SDMA_EDC_COUNTER register in each sdma instance
2535                  * shares the same sed shift_mask
2536                  * */
2537                 sec_cnt = (value &
2538                         sdma_v4_0_ras_fields[i].sec_count_mask) >>
2539                         sdma_v4_0_ras_fields[i].sec_count_shift;
2540                 if (sec_cnt) {
2541                         DRM_INFO("Detected %s in SDMA%d, SED %d\n",
2542                                 sdma_v4_0_ras_fields[i].name,
2543                                 instance, sec_cnt);
2544                         *sec_count += sec_cnt;
2545                 }
2546         }
2547 }
2548
2549 static int sdma_v4_0_query_ras_error_count(struct amdgpu_device *adev,
2550                         uint32_t instance, void *ras_error_status)
2551 {
2552         struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
2553         uint32_t sec_count = 0;
2554         uint32_t reg_value = 0;
2555
2556         reg_value = RREG32_SDMA(instance, mmSDMA0_EDC_COUNTER);
2557         /* double bit error is not supported */
2558         if (reg_value)
2559                 sdma_v4_0_get_ras_error_count(reg_value,
2560                                 instance, &sec_count);
2561         /* err_data->ce_count should be initialized to 0
2562          * before calling into this function */
2563         err_data->ce_count += sec_count;
2564         /* double bit error is not supported
2565          * set ue count to 0 */
2566         err_data->ue_count = 0;
2567
2568         return 0;
2569 };
2570
2571 static void sdma_v4_0_reset_ras_error_count(struct amdgpu_device *adev)
2572 {
2573         int i;
2574
2575         /* read back edc counter registers to clear the counters */
2576         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2577                 for (i = 0; i < adev->sdma.num_instances; i++)
2578                         RREG32_SDMA(i, mmSDMA0_EDC_COUNTER);
2579         }
2580 }
2581
2582 static const struct amdgpu_sdma_ras_funcs sdma_v4_0_ras_funcs = {
2583         .ras_late_init = amdgpu_sdma_ras_late_init,
2584         .ras_fini = amdgpu_sdma_ras_fini,
2585         .query_ras_error_count = sdma_v4_0_query_ras_error_count,
2586         .reset_ras_error_count = sdma_v4_0_reset_ras_error_count,
2587 };
2588
2589 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev)
2590 {
2591         switch (adev->asic_type) {
2592         case CHIP_VEGA20:
2593         case CHIP_ARCTURUS:
2594                 adev->sdma.funcs = &sdma_v4_0_ras_funcs;
2595                 break;
2596         default:
2597                 break;
2598         }
2599 }
2600
2601 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = {
2602         .type = AMD_IP_BLOCK_TYPE_SDMA,
2603         .major = 4,
2604         .minor = 0,
2605         .rev = 0,
2606         .funcs = &sdma_v4_0_ip_funcs,
2607 };