2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
25 #include <linux/firmware.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
30 #include "amdgpu_ucode.h"
31 #include "amdgpu_trace.h"
33 #include "sdma0/sdma0_4_2_offset.h"
34 #include "sdma0/sdma0_4_2_sh_mask.h"
35 #include "sdma1/sdma1_4_2_offset.h"
36 #include "sdma1/sdma1_4_2_sh_mask.h"
37 #include "sdma2/sdma2_4_2_2_offset.h"
38 #include "sdma2/sdma2_4_2_2_sh_mask.h"
39 #include "sdma3/sdma3_4_2_2_offset.h"
40 #include "sdma3/sdma3_4_2_2_sh_mask.h"
41 #include "sdma4/sdma4_4_2_2_offset.h"
42 #include "sdma4/sdma4_4_2_2_sh_mask.h"
43 #include "sdma5/sdma5_4_2_2_offset.h"
44 #include "sdma5/sdma5_4_2_2_sh_mask.h"
45 #include "sdma6/sdma6_4_2_2_offset.h"
46 #include "sdma6/sdma6_4_2_2_sh_mask.h"
47 #include "sdma7/sdma7_4_2_2_offset.h"
48 #include "sdma7/sdma7_4_2_2_sh_mask.h"
49 #include "hdp/hdp_4_0_offset.h"
50 #include "sdma0/sdma0_4_1_default.h"
52 #include "soc15_common.h"
54 #include "vega10_sdma_pkt_open.h"
56 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h"
57 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h"
59 #include "amdgpu_ras.h"
61 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin");
62 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin");
63 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin");
64 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin");
65 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin");
66 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin");
67 MODULE_FIRMWARE("amdgpu/raven_sdma.bin");
68 MODULE_FIRMWARE("amdgpu/picasso_sdma.bin");
69 MODULE_FIRMWARE("amdgpu/raven2_sdma.bin");
70 MODULE_FIRMWARE("amdgpu/arcturus_sdma.bin");
71 MODULE_FIRMWARE("amdgpu/renoir_sdma.bin");
72 MODULE_FIRMWARE("amdgpu/green_sardine_sdma.bin");
74 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L
75 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
77 #define WREG32_SDMA(instance, offset, value) \
78 WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value)
79 #define RREG32_SDMA(instance, offset) \
80 RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)))
82 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev);
83 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev);
84 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev);
85 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev);
86 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev);
88 static const struct soc15_reg_golden golden_settings_sdma_4[] = {
89 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
90 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
91 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),
92 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
93 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
94 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
95 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000),
96 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
97 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
98 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
99 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
100 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
101 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000),
102 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
103 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100),
104 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
105 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
106 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
107 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000),
108 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
109 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
110 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
111 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
112 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
113 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000)
116 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = {
117 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
118 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
119 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
120 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
121 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
122 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
123 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
126 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = {
127 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
128 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001),
129 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
130 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
131 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
132 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001),
133 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
136 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = {
137 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
138 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
139 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100),
140 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
141 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051),
142 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100),
143 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
144 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100),
145 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
146 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
147 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000)
150 static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = {
151 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
154 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] =
156 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
157 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
158 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
159 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
160 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
161 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
162 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
163 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
164 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003),
165 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
166 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
167 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
168 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
169 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
170 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
171 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
172 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
173 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
174 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
175 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
176 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
177 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
178 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
179 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
180 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
181 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
182 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
185 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = {
186 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
187 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
188 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
189 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
190 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
191 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
192 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
193 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
194 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003),
195 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
196 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
197 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
198 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
199 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
200 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
201 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
202 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
203 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
204 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
205 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
206 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
207 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
208 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
209 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
210 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
211 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
212 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
215 static const struct soc15_reg_golden golden_settings_sdma_rv1[] =
217 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
218 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002)
221 static const struct soc15_reg_golden golden_settings_sdma_rv2[] =
223 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001),
224 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001)
227 static const struct soc15_reg_golden golden_settings_sdma_arct[] =
229 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
230 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
231 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
232 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
233 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
234 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
235 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
236 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
237 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
238 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
239 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
240 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
241 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
242 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
243 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
244 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
245 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
246 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
247 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
248 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
249 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
250 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
251 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
252 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
253 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
254 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
255 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
256 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
257 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
258 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
259 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
260 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_UTCL1_TIMEOUT, 0xffffffff, 0x00010001)
263 static const struct soc15_reg_golden golden_settings_sdma_4_3[] = {
264 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
265 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
266 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
267 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002),
268 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
269 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051),
270 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
271 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
272 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
273 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x03fbe1fe)
276 static const struct soc15_ras_field_entry sdma_v4_0_ras_fields[] = {
277 { "SDMA_UCODE_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
278 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UCODE_BUF_SED),
281 { "SDMA_RB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
282 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_RB_CMD_BUF_SED),
285 { "SDMA_IB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
286 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_IB_CMD_BUF_SED),
289 { "SDMA_UTCL1_RD_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
290 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RD_FIFO_SED),
293 { "SDMA_UTCL1_RDBST_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
294 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RDBST_FIFO_SED),
297 { "SDMA_DATA_LUT_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
298 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_DATA_LUT_FIFO_SED),
301 { "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
302 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF0_SED),
305 { "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
306 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF1_SED),
309 { "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
310 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF2_SED),
313 { "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
314 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF3_SED),
317 { "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
318 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF4_SED),
321 { "SDMA_MBANK_DATA_BUF5_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
322 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF5_SED),
325 { "SDMA_MBANK_DATA_BUF6_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
326 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF6_SED),
329 { "SDMA_MBANK_DATA_BUF7_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
330 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF7_SED),
333 { "SDMA_MBANK_DATA_BUF8_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
334 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF8_SED),
337 { "SDMA_MBANK_DATA_BUF9_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
338 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF9_SED),
341 { "SDMA_MBANK_DATA_BUF10_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
342 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF10_SED),
345 { "SDMA_MBANK_DATA_BUF11_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
346 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF11_SED),
349 { "SDMA_MBANK_DATA_BUF12_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
350 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF12_SED),
353 { "SDMA_MBANK_DATA_BUF13_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
354 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF13_SED),
357 { "SDMA_MBANK_DATA_BUF14_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
358 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF14_SED),
361 { "SDMA_MBANK_DATA_BUF15_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
362 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF15_SED),
365 { "SDMA_SPLIT_DAT_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
366 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_SPLIT_DAT_BUF_SED),
369 { "SDMA_MC_WR_ADDR_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
370 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MC_WR_ADDR_FIFO_SED),
375 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
376 u32 instance, u32 offset)
380 return (adev->reg_offset[SDMA0_HWIP][0][0] + offset);
382 return (adev->reg_offset[SDMA1_HWIP][0][0] + offset);
384 return (adev->reg_offset[SDMA2_HWIP][0][1] + offset);
386 return (adev->reg_offset[SDMA3_HWIP][0][1] + offset);
388 return (adev->reg_offset[SDMA4_HWIP][0][1] + offset);
390 return (adev->reg_offset[SDMA5_HWIP][0][1] + offset);
392 return (adev->reg_offset[SDMA6_HWIP][0][1] + offset);
394 return (adev->reg_offset[SDMA7_HWIP][0][1] + offset);
401 static unsigned sdma_v4_0_seq_to_irq_id(int seq_num)
405 return SOC15_IH_CLIENTID_SDMA0;
407 return SOC15_IH_CLIENTID_SDMA1;
409 return SOC15_IH_CLIENTID_SDMA2;
411 return SOC15_IH_CLIENTID_SDMA3;
413 return SOC15_IH_CLIENTID_SDMA4;
415 return SOC15_IH_CLIENTID_SDMA5;
417 return SOC15_IH_CLIENTID_SDMA6;
419 return SOC15_IH_CLIENTID_SDMA7;
426 static int sdma_v4_0_irq_id_to_seq(unsigned client_id)
429 case SOC15_IH_CLIENTID_SDMA0:
431 case SOC15_IH_CLIENTID_SDMA1:
433 case SOC15_IH_CLIENTID_SDMA2:
435 case SOC15_IH_CLIENTID_SDMA3:
437 case SOC15_IH_CLIENTID_SDMA4:
439 case SOC15_IH_CLIENTID_SDMA5:
441 case SOC15_IH_CLIENTID_SDMA6:
443 case SOC15_IH_CLIENTID_SDMA7:
451 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
453 switch (adev->asic_type) {
455 soc15_program_register_sequence(adev,
456 golden_settings_sdma_4,
457 ARRAY_SIZE(golden_settings_sdma_4));
458 soc15_program_register_sequence(adev,
459 golden_settings_sdma_vg10,
460 ARRAY_SIZE(golden_settings_sdma_vg10));
463 soc15_program_register_sequence(adev,
464 golden_settings_sdma_4,
465 ARRAY_SIZE(golden_settings_sdma_4));
466 soc15_program_register_sequence(adev,
467 golden_settings_sdma_vg12,
468 ARRAY_SIZE(golden_settings_sdma_vg12));
471 soc15_program_register_sequence(adev,
472 golden_settings_sdma0_4_2_init,
473 ARRAY_SIZE(golden_settings_sdma0_4_2_init));
474 soc15_program_register_sequence(adev,
475 golden_settings_sdma0_4_2,
476 ARRAY_SIZE(golden_settings_sdma0_4_2));
477 soc15_program_register_sequence(adev,
478 golden_settings_sdma1_4_2,
479 ARRAY_SIZE(golden_settings_sdma1_4_2));
482 soc15_program_register_sequence(adev,
483 golden_settings_sdma_arct,
484 ARRAY_SIZE(golden_settings_sdma_arct));
487 soc15_program_register_sequence(adev,
488 golden_settings_sdma_4_1,
489 ARRAY_SIZE(golden_settings_sdma_4_1));
490 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
491 soc15_program_register_sequence(adev,
492 golden_settings_sdma_rv2,
493 ARRAY_SIZE(golden_settings_sdma_rv2));
495 soc15_program_register_sequence(adev,
496 golden_settings_sdma_rv1,
497 ARRAY_SIZE(golden_settings_sdma_rv1));
500 soc15_program_register_sequence(adev,
501 golden_settings_sdma_4_3,
502 ARRAY_SIZE(golden_settings_sdma_4_3));
509 static void sdma_v4_0_setup_ulv(struct amdgpu_device *adev)
514 * The only chips with SDMAv4 and ULV are VG10 and VG20.
515 * Server SKUs take a different hysteresis setting from other SKUs.
517 switch (adev->asic_type) {
519 if (adev->pdev->device == 0x6860)
523 if (adev->pdev->device == 0x66a1)
530 for (i = 0; i < adev->sdma.num_instances; i++) {
533 temp = RREG32_SDMA(i, mmSDMA0_ULV_CNTL);
534 temp = REG_SET_FIELD(temp, SDMA0_ULV_CNTL, HYSTERESIS, 0x0);
535 WREG32_SDMA(i, mmSDMA0_ULV_CNTL, temp);
539 static int sdma_v4_0_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
542 const struct sdma_firmware_header_v1_0 *hdr;
544 err = amdgpu_ucode_validate(sdma_inst->fw);
548 hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
549 sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
550 sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
552 if (sdma_inst->feature_version >= 20)
553 sdma_inst->burst_nop = true;
558 static void sdma_v4_0_destroy_inst_ctx(struct amdgpu_device *adev)
562 for (i = 0; i < adev->sdma.num_instances; i++) {
563 release_firmware(adev->sdma.instance[i].fw);
564 adev->sdma.instance[i].fw = NULL;
566 /* arcturus shares the same FW memory across
567 all SDMA isntances */
568 if (adev->asic_type == CHIP_ARCTURUS)
572 memset((void *)adev->sdma.instance, 0,
573 sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
577 * sdma_v4_0_init_microcode - load ucode images from disk
579 * @adev: amdgpu_device pointer
581 * Use the firmware interface to load the ucode images into
582 * the driver (not loaded into hw).
583 * Returns 0 on success, error on failure.
586 // emulation only, won't work on real chip
587 // vega10 real chip need to use PSP to load firmware
588 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
590 const char *chip_name;
593 struct amdgpu_firmware_info *info = NULL;
594 const struct common_firmware_header *header = NULL;
598 switch (adev->asic_type) {
600 chip_name = "vega10";
603 chip_name = "vega12";
606 chip_name = "vega20";
609 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
610 chip_name = "raven2";
611 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
612 chip_name = "picasso";
617 chip_name = "arcturus";
620 if (adev->apu_flags & AMD_APU_IS_RENOIR)
621 chip_name = "renoir";
623 chip_name = "green_sardine";
629 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
631 err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);
635 err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[0]);
639 for (i = 1; i < adev->sdma.num_instances; i++) {
640 if (adev->asic_type == CHIP_ARCTURUS) {
641 /* Acturus will leverage the same FW memory
642 for every SDMA instance */
643 memcpy((void *)&adev->sdma.instance[i],
644 (void *)&adev->sdma.instance[0],
645 sizeof(struct amdgpu_sdma_instance));
648 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i);
650 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
654 err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[i]);
660 DRM_DEBUG("psp_load == '%s'\n",
661 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
663 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
664 for (i = 0; i < adev->sdma.num_instances; i++) {
665 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
666 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
667 info->fw = adev->sdma.instance[i].fw;
668 header = (const struct common_firmware_header *)info->fw->data;
669 adev->firmware.fw_size +=
670 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
676 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name);
677 sdma_v4_0_destroy_inst_ctx(adev);
683 * sdma_v4_0_ring_get_rptr - get the current read pointer
685 * @ring: amdgpu ring pointer
687 * Get the current rptr from the hardware (VEGA10+).
689 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring)
693 /* XXX check if swapping is necessary on BE */
694 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
696 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
697 return ((*rptr) >> 2);
701 * sdma_v4_0_ring_get_wptr - get the current write pointer
703 * @ring: amdgpu ring pointer
705 * Get the current wptr from the hardware (VEGA10+).
707 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
709 struct amdgpu_device *adev = ring->adev;
712 if (ring->use_doorbell) {
713 /* XXX check if swapping is necessary on BE */
714 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
715 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
717 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI);
719 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR);
720 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n",
728 * sdma_v4_0_page_ring_set_wptr - commit the write pointer
730 * @ring: amdgpu ring pointer
732 * Write the wptr back to the hardware (VEGA10+).
734 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
736 struct amdgpu_device *adev = ring->adev;
738 DRM_DEBUG("Setting write pointer\n");
739 if (ring->use_doorbell) {
740 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
742 DRM_DEBUG("Using doorbell -- "
743 "wptr_offs == 0x%08x "
744 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
745 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
747 lower_32_bits(ring->wptr << 2),
748 upper_32_bits(ring->wptr << 2));
749 /* XXX check if swapping is necessary on BE */
750 WRITE_ONCE(*wb, (ring->wptr << 2));
751 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
752 ring->doorbell_index, ring->wptr << 2);
753 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
755 DRM_DEBUG("Not using doorbell -- "
756 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
757 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
759 lower_32_bits(ring->wptr << 2),
761 upper_32_bits(ring->wptr << 2));
762 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR,
763 lower_32_bits(ring->wptr << 2));
764 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI,
765 upper_32_bits(ring->wptr << 2));
770 * sdma_v4_0_page_ring_get_wptr - get the current write pointer
772 * @ring: amdgpu ring pointer
774 * Get the current wptr from the hardware (VEGA10+).
776 static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring)
778 struct amdgpu_device *adev = ring->adev;
781 if (ring->use_doorbell) {
782 /* XXX check if swapping is necessary on BE */
783 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
785 wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI);
787 wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR);
794 * sdma_v4_0_ring_set_wptr - commit the write pointer
796 * @ring: amdgpu ring pointer
798 * Write the wptr back to the hardware (VEGA10+).
800 static void sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring *ring)
802 struct amdgpu_device *adev = ring->adev;
804 if (ring->use_doorbell) {
805 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
807 /* XXX check if swapping is necessary on BE */
808 WRITE_ONCE(*wb, (ring->wptr << 2));
809 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
811 uint64_t wptr = ring->wptr << 2;
813 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR,
814 lower_32_bits(wptr));
815 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI,
816 upper_32_bits(wptr));
820 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
822 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
825 for (i = 0; i < count; i++)
826 if (sdma && sdma->burst_nop && (i == 0))
827 amdgpu_ring_write(ring, ring->funcs->nop |
828 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
830 amdgpu_ring_write(ring, ring->funcs->nop);
834 * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine
836 * @ring: amdgpu ring pointer
837 * @job: job to retrieve vmid from
838 * @ib: IB object to schedule
841 * Schedule an IB in the DMA ring (VEGA10).
843 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
844 struct amdgpu_job *job,
845 struct amdgpu_ib *ib,
848 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
850 /* IB packet must end on a 8 DW boundary */
851 sdma_v4_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
853 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
854 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
855 /* base must be 32 byte aligned */
856 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
857 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
858 amdgpu_ring_write(ring, ib->length_dw);
859 amdgpu_ring_write(ring, 0);
860 amdgpu_ring_write(ring, 0);
864 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring,
865 int mem_space, int hdp,
866 uint32_t addr0, uint32_t addr1,
867 uint32_t ref, uint32_t mask,
870 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
871 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) |
872 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) |
873 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
876 amdgpu_ring_write(ring, addr0);
877 amdgpu_ring_write(ring, addr1);
880 amdgpu_ring_write(ring, addr0 << 2);
881 amdgpu_ring_write(ring, addr1 << 2);
883 amdgpu_ring_write(ring, ref); /* reference */
884 amdgpu_ring_write(ring, mask); /* mask */
885 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
886 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */
890 * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
892 * @ring: amdgpu ring pointer
894 * Emit an hdp flush packet on the requested DMA ring.
896 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
898 struct amdgpu_device *adev = ring->adev;
899 u32 ref_and_mask = 0;
900 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
902 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
904 sdma_v4_0_wait_reg_mem(ring, 0, 1,
905 adev->nbio.funcs->get_hdp_flush_done_offset(adev),
906 adev->nbio.funcs->get_hdp_flush_req_offset(adev),
907 ref_and_mask, ref_and_mask, 10);
911 * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring
913 * @ring: amdgpu ring pointer
915 * @seq: sequence number
916 * @flags: fence related flags
918 * Add a DMA fence packet to the ring to write
919 * the fence seq number and DMA trap packet to generate
920 * an interrupt if needed (VEGA10).
922 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
925 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
926 /* write the fence */
927 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
928 /* zero in first two bits */
930 amdgpu_ring_write(ring, lower_32_bits(addr));
931 amdgpu_ring_write(ring, upper_32_bits(addr));
932 amdgpu_ring_write(ring, lower_32_bits(seq));
934 /* optionally write high bits as well */
937 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
938 /* zero in first two bits */
940 amdgpu_ring_write(ring, lower_32_bits(addr));
941 amdgpu_ring_write(ring, upper_32_bits(addr));
942 amdgpu_ring_write(ring, upper_32_bits(seq));
945 /* generate an interrupt */
946 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
947 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
952 * sdma_v4_0_gfx_stop - stop the gfx async dma engines
954 * @adev: amdgpu_device pointer
956 * Stop the gfx async dma ring buffers (VEGA10).
958 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev)
960 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
961 u32 rb_cntl, ib_cntl;
964 for (i = 0; i < adev->sdma.num_instances; i++) {
965 sdma[i] = &adev->sdma.instance[i].ring;
967 if ((adev->mman.buffer_funcs_ring == sdma[i]) && unset != 1) {
968 amdgpu_ttm_set_buffer_funcs_status(adev, false);
972 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
973 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
974 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
975 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
976 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
977 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
982 * sdma_v4_0_rlc_stop - stop the compute async dma engines
984 * @adev: amdgpu_device pointer
986 * Stop the compute async dma queues (VEGA10).
988 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev)
994 * sdma_v4_0_page_stop - stop the page async dma engines
996 * @adev: amdgpu_device pointer
998 * Stop the page async dma ring buffers (VEGA10).
1000 static void sdma_v4_0_page_stop(struct amdgpu_device *adev)
1002 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
1003 u32 rb_cntl, ib_cntl;
1007 for (i = 0; i < adev->sdma.num_instances; i++) {
1008 sdma[i] = &adev->sdma.instance[i].page;
1010 if ((adev->mman.buffer_funcs_ring == sdma[i]) &&
1012 amdgpu_ttm_set_buffer_funcs_status(adev, false);
1016 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);
1017 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
1019 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
1020 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL);
1021 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL,
1023 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
1028 * sdma_v4_0_ctx_switch_enable - stop the async dma engines context switch
1030 * @adev: amdgpu_device pointer
1031 * @enable: enable/disable the DMA MEs context switch.
1033 * Halt or unhalt the async dma engines context switch (VEGA10).
1035 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
1037 u32 f32_cntl, phase_quantum = 0;
1040 if (amdgpu_sdma_phase_quantum) {
1041 unsigned value = amdgpu_sdma_phase_quantum;
1044 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
1045 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
1046 value = (value + 1) >> 1;
1049 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
1050 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
1051 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
1052 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
1053 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
1054 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
1056 "clamping sdma_phase_quantum to %uK clock cycles\n",
1060 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
1061 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
1064 for (i = 0; i < adev->sdma.num_instances; i++) {
1065 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL);
1066 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
1067 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
1068 if (enable && amdgpu_sdma_phase_quantum) {
1069 WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum);
1070 WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum);
1071 WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum);
1073 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl);
1076 * Enable SDMA utilization. Its only supported on
1077 * Arcturus for the moment and firmware version 14
1080 if (adev->asic_type == CHIP_ARCTURUS &&
1081 adev->sdma.instance[i].fw_version >= 14)
1082 WREG32_SDMA(i, mmSDMA0_PUB_DUMMY_REG2, enable);
1088 * sdma_v4_0_enable - stop the async dma engines
1090 * @adev: amdgpu_device pointer
1091 * @enable: enable/disable the DMA MEs.
1093 * Halt or unhalt the async dma engines (VEGA10).
1095 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable)
1101 sdma_v4_0_gfx_stop(adev);
1102 sdma_v4_0_rlc_stop(adev);
1103 if (adev->sdma.has_page_queue)
1104 sdma_v4_0_page_stop(adev);
1107 for (i = 0; i < adev->sdma.num_instances; i++) {
1108 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
1109 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
1110 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl);
1115 * sdma_v4_0_rb_cntl - get parameters for rb_cntl
1117 static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl)
1119 /* Set ring buffer size in dwords */
1120 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4);
1122 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
1124 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
1125 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
1126 RPTR_WRITEBACK_SWAP_ENABLE, 1);
1132 * sdma_v4_0_gfx_resume - setup and start the async dma engines
1134 * @adev: amdgpu_device pointer
1135 * @i: instance to resume
1137 * Set up the gfx DMA ring buffers and enable them (VEGA10).
1138 * Returns 0 for success, error for failure.
1140 static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i)
1142 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring;
1143 u32 rb_cntl, ib_cntl, wptr_poll_cntl;
1146 u32 doorbell_offset;
1149 wb_offset = (ring->rptr_offs * 4);
1151 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
1152 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl);
1153 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
1155 /* Initialize the ring buffer's read and write pointers */
1156 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0);
1157 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0);
1158 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0);
1159 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0);
1161 /* set the wb address whether it's enabled or not */
1162 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI,
1163 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
1164 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO,
1165 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
1167 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
1168 RPTR_WRITEBACK_ENABLE, 1);
1170 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8);
1171 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40);
1175 /* before programing wptr to a less value, need set minor_ptr_update first */
1176 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1);
1178 doorbell = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL);
1179 doorbell_offset = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET);
1181 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE,
1182 ring->use_doorbell);
1183 doorbell_offset = REG_SET_FIELD(doorbell_offset,
1184 SDMA0_GFX_DOORBELL_OFFSET,
1185 OFFSET, ring->doorbell_index);
1186 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell);
1187 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset);
1189 sdma_v4_0_ring_set_wptr(ring);
1191 /* set minor_ptr_update to 0 after wptr programed */
1192 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0);
1194 /* setup the wptr shadow polling */
1195 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1196 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO,
1197 lower_32_bits(wptr_gpu_addr));
1198 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI,
1199 upper_32_bits(wptr_gpu_addr));
1200 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL);
1201 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
1202 SDMA0_GFX_RB_WPTR_POLL_CNTL,
1203 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
1204 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
1207 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
1208 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
1210 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
1211 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
1213 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
1215 /* enable DMA IBs */
1216 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
1218 ring->sched.ready = true;
1222 * sdma_v4_0_page_resume - setup and start the async dma engines
1224 * @adev: amdgpu_device pointer
1225 * @i: instance to resume
1227 * Set up the page DMA ring buffers and enable them (VEGA10).
1228 * Returns 0 for success, error for failure.
1230 static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i)
1232 struct amdgpu_ring *ring = &adev->sdma.instance[i].page;
1233 u32 rb_cntl, ib_cntl, wptr_poll_cntl;
1236 u32 doorbell_offset;
1239 wb_offset = (ring->rptr_offs * 4);
1241 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);
1242 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl);
1243 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
1245 /* Initialize the ring buffer's read and write pointers */
1246 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR, 0);
1247 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_HI, 0);
1248 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR, 0);
1249 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_HI, 0);
1251 /* set the wb address whether it's enabled or not */
1252 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_HI,
1253 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
1254 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_LO,
1255 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
1257 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
1258 RPTR_WRITEBACK_ENABLE, 1);
1260 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE, ring->gpu_addr >> 8);
1261 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE_HI, ring->gpu_addr >> 40);
1265 /* before programing wptr to a less value, need set minor_ptr_update first */
1266 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 1);
1268 doorbell = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL);
1269 doorbell_offset = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET);
1271 doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE,
1272 ring->use_doorbell);
1273 doorbell_offset = REG_SET_FIELD(doorbell_offset,
1274 SDMA0_PAGE_DOORBELL_OFFSET,
1275 OFFSET, ring->doorbell_index);
1276 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell);
1277 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset);
1279 /* paging queue doorbell range is setup at sdma_v4_0_gfx_resume */
1280 sdma_v4_0_page_ring_set_wptr(ring);
1282 /* set minor_ptr_update to 0 after wptr programed */
1283 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0);
1285 /* setup the wptr shadow polling */
1286 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1287 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO,
1288 lower_32_bits(wptr_gpu_addr));
1289 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI,
1290 upper_32_bits(wptr_gpu_addr));
1291 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL);
1292 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
1293 SDMA0_PAGE_RB_WPTR_POLL_CNTL,
1294 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
1295 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
1298 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1);
1299 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
1301 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL);
1302 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_ENABLE, 1);
1304 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1);
1306 /* enable DMA IBs */
1307 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
1309 ring->sched.ready = true;
1313 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable)
1317 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) {
1318 /* enable idle interrupt */
1319 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1320 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1323 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1325 /* disable idle interrupt */
1326 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1327 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1329 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1333 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev)
1337 /* Enable HW based PG. */
1338 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1339 data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK;
1341 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1343 /* enable interrupt */
1344 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1345 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1347 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1349 /* Configure hold time to filter in-valid power on/off request. Use default right now */
1350 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1351 data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK;
1352 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK);
1353 /* Configure switch time for hysteresis purpose. Use default right now */
1354 data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK;
1355 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK);
1357 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1360 static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
1362 if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA))
1365 switch (adev->asic_type) {
1368 sdma_v4_1_init_power_gating(adev);
1369 sdma_v4_1_update_power_gating(adev, true);
1377 * sdma_v4_0_rlc_resume - setup and start the async dma engines
1379 * @adev: amdgpu_device pointer
1381 * Set up the compute DMA queues and enable them (VEGA10).
1382 * Returns 0 for success, error for failure.
1384 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev)
1386 sdma_v4_0_init_pg(adev);
1392 * sdma_v4_0_load_microcode - load the sDMA ME ucode
1394 * @adev: amdgpu_device pointer
1396 * Loads the sDMA0/1 ucode.
1397 * Returns 0 for success, -EINVAL if the ucode is not available.
1399 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev)
1401 const struct sdma_firmware_header_v1_0 *hdr;
1402 const __le32 *fw_data;
1407 sdma_v4_0_enable(adev, false);
1409 for (i = 0; i < adev->sdma.num_instances; i++) {
1410 if (!adev->sdma.instance[i].fw)
1413 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
1414 amdgpu_ucode_print_sdma_hdr(&hdr->header);
1415 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1417 fw_data = (const __le32 *)
1418 (adev->sdma.instance[i].fw->data +
1419 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1421 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0);
1423 for (j = 0; j < fw_size; j++)
1424 WREG32_SDMA(i, mmSDMA0_UCODE_DATA,
1425 le32_to_cpup(fw_data++));
1427 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR,
1428 adev->sdma.instance[i].fw_version);
1435 * sdma_v4_0_start - setup and start the async dma engines
1437 * @adev: amdgpu_device pointer
1439 * Set up the DMA engines and enable them (VEGA10).
1440 * Returns 0 for success, error for failure.
1442 static int sdma_v4_0_start(struct amdgpu_device *adev)
1444 struct amdgpu_ring *ring;
1447 if (amdgpu_sriov_vf(adev)) {
1448 sdma_v4_0_ctx_switch_enable(adev, false);
1449 sdma_v4_0_enable(adev, false);
1452 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1453 r = sdma_v4_0_load_microcode(adev);
1458 /* unhalt the MEs */
1459 sdma_v4_0_enable(adev, true);
1460 /* enable sdma ring preemption */
1461 sdma_v4_0_ctx_switch_enable(adev, true);
1464 /* start the gfx rings and rlc compute queues */
1465 for (i = 0; i < adev->sdma.num_instances; i++) {
1468 WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0);
1469 sdma_v4_0_gfx_resume(adev, i);
1470 if (adev->sdma.has_page_queue)
1471 sdma_v4_0_page_resume(adev, i);
1473 /* set utc l1 enable flag always to 1 */
1474 temp = RREG32_SDMA(i, mmSDMA0_CNTL);
1475 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
1476 WREG32_SDMA(i, mmSDMA0_CNTL, temp);
1478 if (!amdgpu_sriov_vf(adev)) {
1480 temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
1481 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
1482 WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp);
1486 if (amdgpu_sriov_vf(adev)) {
1487 sdma_v4_0_ctx_switch_enable(adev, true);
1488 sdma_v4_0_enable(adev, true);
1490 r = sdma_v4_0_rlc_resume(adev);
1495 for (i = 0; i < adev->sdma.num_instances; i++) {
1496 ring = &adev->sdma.instance[i].ring;
1498 r = amdgpu_ring_test_helper(ring);
1502 if (adev->sdma.has_page_queue) {
1503 struct amdgpu_ring *page = &adev->sdma.instance[i].page;
1505 r = amdgpu_ring_test_helper(page);
1509 if (adev->mman.buffer_funcs_ring == page)
1510 amdgpu_ttm_set_buffer_funcs_status(adev, true);
1513 if (adev->mman.buffer_funcs_ring == ring)
1514 amdgpu_ttm_set_buffer_funcs_status(adev, true);
1521 * sdma_v4_0_ring_test_ring - simple async dma engine test
1523 * @ring: amdgpu_ring structure holding ring information
1525 * Test the DMA engine by writing using it to write an
1526 * value to memory. (VEGA10).
1527 * Returns 0 for success, error for failure.
1529 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring)
1531 struct amdgpu_device *adev = ring->adev;
1538 r = amdgpu_device_wb_get(adev, &index);
1542 gpu_addr = adev->wb.gpu_addr + (index * 4);
1544 adev->wb.wb[index] = cpu_to_le32(tmp);
1546 r = amdgpu_ring_alloc(ring, 5);
1550 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1551 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
1552 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
1553 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
1554 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
1555 amdgpu_ring_write(ring, 0xDEADBEEF);
1556 amdgpu_ring_commit(ring);
1558 for (i = 0; i < adev->usec_timeout; i++) {
1559 tmp = le32_to_cpu(adev->wb.wb[index]);
1560 if (tmp == 0xDEADBEEF)
1565 if (i >= adev->usec_timeout)
1569 amdgpu_device_wb_free(adev, index);
1574 * sdma_v4_0_ring_test_ib - test an IB on the DMA engine
1576 * @ring: amdgpu_ring structure holding ring information
1577 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1579 * Test a simple IB in the DMA ring (VEGA10).
1580 * Returns 0 on success, error on failure.
1582 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1584 struct amdgpu_device *adev = ring->adev;
1585 struct amdgpu_ib ib;
1586 struct dma_fence *f = NULL;
1592 r = amdgpu_device_wb_get(adev, &index);
1596 gpu_addr = adev->wb.gpu_addr + (index * 4);
1598 adev->wb.wb[index] = cpu_to_le32(tmp);
1599 memset(&ib, 0, sizeof(ib));
1600 r = amdgpu_ib_get(adev, NULL, 256,
1601 AMDGPU_IB_POOL_DIRECT, &ib);
1605 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1606 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1607 ib.ptr[1] = lower_32_bits(gpu_addr);
1608 ib.ptr[2] = upper_32_bits(gpu_addr);
1609 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1610 ib.ptr[4] = 0xDEADBEEF;
1611 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1612 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1613 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1616 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1620 r = dma_fence_wait_timeout(f, false, timeout);
1627 tmp = le32_to_cpu(adev->wb.wb[index]);
1628 if (tmp == 0xDEADBEEF)
1634 amdgpu_ib_free(adev, &ib, NULL);
1637 amdgpu_device_wb_free(adev, index);
1643 * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART
1645 * @ib: indirect buffer to fill with commands
1646 * @pe: addr of the page entry
1647 * @src: src addr to copy from
1648 * @count: number of page entries to update
1650 * Update PTEs by copying them from the GART using sDMA (VEGA10).
1652 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib,
1653 uint64_t pe, uint64_t src,
1656 unsigned bytes = count * 8;
1658 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1659 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1660 ib->ptr[ib->length_dw++] = bytes - 1;
1661 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1662 ib->ptr[ib->length_dw++] = lower_32_bits(src);
1663 ib->ptr[ib->length_dw++] = upper_32_bits(src);
1664 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1665 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1670 * sdma_v4_0_vm_write_pte - update PTEs by writing them manually
1672 * @ib: indirect buffer to fill with commands
1673 * @pe: addr of the page entry
1674 * @value: dst addr to write into pe
1675 * @count: number of page entries to update
1676 * @incr: increase next addr by incr bytes
1678 * Update PTEs by writing them manually using sDMA (VEGA10).
1680 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1681 uint64_t value, unsigned count,
1684 unsigned ndw = count * 2;
1686 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1687 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1688 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1689 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1690 ib->ptr[ib->length_dw++] = ndw - 1;
1691 for (; ndw > 0; ndw -= 2) {
1692 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1693 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1699 * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA
1701 * @ib: indirect buffer to fill with commands
1702 * @pe: addr of the page entry
1703 * @addr: dst addr to write into pe
1704 * @count: number of page entries to update
1705 * @incr: increase next addr by incr bytes
1706 * @flags: access flags
1708 * Update the page tables using sDMA (VEGA10).
1710 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1712 uint64_t addr, unsigned count,
1713 uint32_t incr, uint64_t flags)
1715 /* for physically contiguous pages (vram) */
1716 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1717 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1718 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1719 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1720 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1721 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1722 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1723 ib->ptr[ib->length_dw++] = incr; /* increment size */
1724 ib->ptr[ib->length_dw++] = 0;
1725 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1729 * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw
1731 * @ring: amdgpu_ring structure holding ring information
1732 * @ib: indirect buffer to fill with padding
1734 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1736 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1740 pad_count = (-ib->length_dw) & 7;
1741 for (i = 0; i < pad_count; i++)
1742 if (sdma && sdma->burst_nop && (i == 0))
1743 ib->ptr[ib->length_dw++] =
1744 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1745 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1747 ib->ptr[ib->length_dw++] =
1748 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1753 * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline
1755 * @ring: amdgpu_ring pointer
1757 * Make sure all previous operations are completed (CIK).
1759 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1761 uint32_t seq = ring->fence_drv.sync_seq;
1762 uint64_t addr = ring->fence_drv.gpu_addr;
1765 sdma_v4_0_wait_reg_mem(ring, 1, 0,
1767 upper_32_bits(addr) & 0xffffffff,
1768 seq, 0xffffffff, 4);
1773 * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA
1775 * @ring: amdgpu_ring pointer
1776 * @vmid: vmid number to use
1779 * Update the page table base and flush the VM TLB
1780 * using sDMA (VEGA10).
1782 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1783 unsigned vmid, uint64_t pd_addr)
1785 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1788 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring,
1789 uint32_t reg, uint32_t val)
1791 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1792 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1793 amdgpu_ring_write(ring, reg);
1794 amdgpu_ring_write(ring, val);
1797 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1798 uint32_t val, uint32_t mask)
1800 sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
1803 static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev)
1805 uint fw_version = adev->sdma.instance[0].fw_version;
1807 switch (adev->asic_type) {
1809 return fw_version >= 430;
1811 /*return fw_version >= 31;*/
1814 return fw_version >= 123;
1820 static int sdma_v4_0_early_init(void *handle)
1822 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1825 if (adev->flags & AMD_IS_APU)
1826 adev->sdma.num_instances = 1;
1827 else if (adev->asic_type == CHIP_ARCTURUS)
1828 adev->sdma.num_instances = 8;
1830 adev->sdma.num_instances = 2;
1832 r = sdma_v4_0_init_microcode(adev);
1834 DRM_ERROR("Failed to load sdma firmware!\n");
1838 /* TODO: Page queue breaks driver reload under SRIOV */
1839 if ((adev->asic_type == CHIP_VEGA10) && amdgpu_sriov_vf((adev)))
1840 adev->sdma.has_page_queue = false;
1841 else if (sdma_v4_0_fw_support_paging_queue(adev))
1842 adev->sdma.has_page_queue = true;
1844 sdma_v4_0_set_ring_funcs(adev);
1845 sdma_v4_0_set_buffer_funcs(adev);
1846 sdma_v4_0_set_vm_pte_funcs(adev);
1847 sdma_v4_0_set_irq_funcs(adev);
1848 sdma_v4_0_set_ras_funcs(adev);
1853 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
1855 struct amdgpu_iv_entry *entry);
1857 static int sdma_v4_0_late_init(void *handle)
1859 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1860 struct ras_ih_if ih_info = {
1861 .cb = sdma_v4_0_process_ras_data_cb,
1864 sdma_v4_0_setup_ulv(adev);
1866 if (adev->sdma.funcs && adev->sdma.funcs->reset_ras_error_count)
1867 adev->sdma.funcs->reset_ras_error_count(adev);
1869 if (adev->sdma.funcs && adev->sdma.funcs->ras_late_init)
1870 return adev->sdma.funcs->ras_late_init(adev, &ih_info);
1875 static int sdma_v4_0_sw_init(void *handle)
1877 struct amdgpu_ring *ring;
1879 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1881 /* SDMA trap event */
1882 for (i = 0; i < adev->sdma.num_instances; i++) {
1883 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1884 SDMA0_4_0__SRCID__SDMA_TRAP,
1885 &adev->sdma.trap_irq);
1890 /* SDMA SRAM ECC event */
1891 for (i = 0; i < adev->sdma.num_instances; i++) {
1892 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1893 SDMA0_4_0__SRCID__SDMA_SRAM_ECC,
1894 &adev->sdma.ecc_irq);
1899 for (i = 0; i < adev->sdma.num_instances; i++) {
1900 ring = &adev->sdma.instance[i].ring;
1901 ring->ring_obj = NULL;
1902 ring->use_doorbell = true;
1904 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1905 ring->use_doorbell?"true":"false");
1907 /* doorbell size is 2 dwords, get DWORD offset */
1908 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1910 sprintf(ring->name, "sdma%d", i);
1911 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1912 AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1913 AMDGPU_RING_PRIO_DEFAULT);
1917 if (adev->sdma.has_page_queue) {
1918 ring = &adev->sdma.instance[i].page;
1919 ring->ring_obj = NULL;
1920 ring->use_doorbell = true;
1922 /* paging queue use same doorbell index/routing as gfx queue
1923 * with 0x400 (4096 dwords) offset on second doorbell page
1925 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1926 ring->doorbell_index += 0x400;
1928 sprintf(ring->name, "page%d", i);
1929 r = amdgpu_ring_init(adev, ring, 1024,
1930 &adev->sdma.trap_irq,
1931 AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1932 AMDGPU_RING_PRIO_DEFAULT);
1941 static int sdma_v4_0_sw_fini(void *handle)
1943 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1946 if (adev->sdma.funcs && adev->sdma.funcs->ras_fini)
1947 adev->sdma.funcs->ras_fini(adev);
1949 for (i = 0; i < adev->sdma.num_instances; i++) {
1950 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1951 if (adev->sdma.has_page_queue)
1952 amdgpu_ring_fini(&adev->sdma.instance[i].page);
1955 sdma_v4_0_destroy_inst_ctx(adev);
1960 static int sdma_v4_0_hw_init(void *handle)
1963 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1965 if (adev->flags & AMD_IS_APU)
1966 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false);
1968 if (!amdgpu_sriov_vf(adev))
1969 sdma_v4_0_init_golden_registers(adev);
1971 r = sdma_v4_0_start(adev);
1976 static int sdma_v4_0_hw_fini(void *handle)
1978 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1981 if (amdgpu_sriov_vf(adev))
1984 for (i = 0; i < adev->sdma.num_instances; i++) {
1985 amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
1986 AMDGPU_SDMA_IRQ_INSTANCE0 + i);
1989 sdma_v4_0_ctx_switch_enable(adev, false);
1990 sdma_v4_0_enable(adev, false);
1992 if (adev->flags & AMD_IS_APU)
1993 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true);
1998 static int sdma_v4_0_suspend(void *handle)
2000 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2002 return sdma_v4_0_hw_fini(adev);
2005 static int sdma_v4_0_resume(void *handle)
2007 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2009 return sdma_v4_0_hw_init(adev);
2012 static bool sdma_v4_0_is_idle(void *handle)
2014 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2017 for (i = 0; i < adev->sdma.num_instances; i++) {
2018 u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG);
2020 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
2027 static int sdma_v4_0_wait_for_idle(void *handle)
2030 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES];
2031 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2033 for (i = 0; i < adev->usec_timeout; i++) {
2034 for (j = 0; j < adev->sdma.num_instances; j++) {
2035 sdma[j] = RREG32_SDMA(j, mmSDMA0_STATUS_REG);
2036 if (!(sdma[j] & SDMA0_STATUS_REG__IDLE_MASK))
2039 if (j == adev->sdma.num_instances)
2046 static int sdma_v4_0_soft_reset(void *handle)
2053 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev,
2054 struct amdgpu_irq_src *source,
2056 enum amdgpu_interrupt_state state)
2060 sdma_cntl = RREG32_SDMA(type, mmSDMA0_CNTL);
2061 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
2062 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
2063 WREG32_SDMA(type, mmSDMA0_CNTL, sdma_cntl);
2068 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
2069 struct amdgpu_irq_src *source,
2070 struct amdgpu_iv_entry *entry)
2074 DRM_DEBUG("IH: SDMA trap\n");
2075 instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2076 switch (entry->ring_id) {
2078 amdgpu_fence_process(&adev->sdma.instance[instance].ring);
2081 if (adev->asic_type == CHIP_VEGA20)
2082 amdgpu_fence_process(&adev->sdma.instance[instance].page);
2088 if (adev->asic_type != CHIP_VEGA20)
2089 amdgpu_fence_process(&adev->sdma.instance[instance].page);
2095 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
2097 struct amdgpu_iv_entry *entry)
2101 /* When “Full RAS” is enabled, the per-IP interrupt sources should
2102 * be disabled and the driver should only look for the aggregated
2103 * interrupt via sync flood
2105 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
2108 instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2112 amdgpu_sdma_process_ras_data_cb(adev, err_data, entry);
2115 return AMDGPU_RAS_SUCCESS;
2118 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev,
2119 struct amdgpu_irq_src *source,
2120 struct amdgpu_iv_entry *entry)
2124 DRM_ERROR("Illegal instruction in SDMA command stream\n");
2126 instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2130 switch (entry->ring_id) {
2132 drm_sched_fault(&adev->sdma.instance[instance].ring.sched);
2138 static int sdma_v4_0_set_ecc_irq_state(struct amdgpu_device *adev,
2139 struct amdgpu_irq_src *source,
2141 enum amdgpu_interrupt_state state)
2143 u32 sdma_edc_config;
2145 sdma_edc_config = RREG32_SDMA(type, mmSDMA0_EDC_CONFIG);
2146 sdma_edc_config = REG_SET_FIELD(sdma_edc_config, SDMA0_EDC_CONFIG, ECC_INT_ENABLE,
2147 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
2148 WREG32_SDMA(type, mmSDMA0_EDC_CONFIG, sdma_edc_config);
2153 static void sdma_v4_0_update_medium_grain_clock_gating(
2154 struct amdgpu_device *adev,
2160 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
2161 for (i = 0; i < adev->sdma.num_instances; i++) {
2162 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);
2163 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
2164 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
2165 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
2166 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
2167 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
2168 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
2169 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
2170 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
2172 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
2175 for (i = 0; i < adev->sdma.num_instances; i++) {
2176 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);
2177 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
2178 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
2179 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
2180 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
2181 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
2182 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
2183 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
2184 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
2186 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
2192 static void sdma_v4_0_update_medium_grain_light_sleep(
2193 struct amdgpu_device *adev,
2199 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
2200 for (i = 0; i < adev->sdma.num_instances; i++) {
2201 /* 1-not override: enable sdma mem light sleep */
2202 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);
2203 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
2205 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);
2208 for (i = 0; i < adev->sdma.num_instances; i++) {
2209 /* 0-override:disable sdma mem light sleep */
2210 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);
2211 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
2213 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);
2218 static int sdma_v4_0_set_clockgating_state(void *handle,
2219 enum amd_clockgating_state state)
2221 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2223 if (amdgpu_sriov_vf(adev))
2226 switch (adev->asic_type) {
2233 sdma_v4_0_update_medium_grain_clock_gating(adev,
2234 state == AMD_CG_STATE_GATE);
2235 sdma_v4_0_update_medium_grain_light_sleep(adev,
2236 state == AMD_CG_STATE_GATE);
2244 static int sdma_v4_0_set_powergating_state(void *handle,
2245 enum amd_powergating_state state)
2247 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2249 switch (adev->asic_type) {
2252 sdma_v4_1_update_power_gating(adev,
2253 state == AMD_PG_STATE_GATE ? true : false);
2262 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags)
2264 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2267 if (amdgpu_sriov_vf(adev))
2270 /* AMD_CG_SUPPORT_SDMA_MGCG */
2271 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
2272 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
2273 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
2275 /* AMD_CG_SUPPORT_SDMA_LS */
2276 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
2277 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
2278 *flags |= AMD_CG_SUPPORT_SDMA_LS;
2281 const struct amd_ip_funcs sdma_v4_0_ip_funcs = {
2282 .name = "sdma_v4_0",
2283 .early_init = sdma_v4_0_early_init,
2284 .late_init = sdma_v4_0_late_init,
2285 .sw_init = sdma_v4_0_sw_init,
2286 .sw_fini = sdma_v4_0_sw_fini,
2287 .hw_init = sdma_v4_0_hw_init,
2288 .hw_fini = sdma_v4_0_hw_fini,
2289 .suspend = sdma_v4_0_suspend,
2290 .resume = sdma_v4_0_resume,
2291 .is_idle = sdma_v4_0_is_idle,
2292 .wait_for_idle = sdma_v4_0_wait_for_idle,
2293 .soft_reset = sdma_v4_0_soft_reset,
2294 .set_clockgating_state = sdma_v4_0_set_clockgating_state,
2295 .set_powergating_state = sdma_v4_0_set_powergating_state,
2296 .get_clockgating_state = sdma_v4_0_get_clockgating_state,
2299 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
2300 .type = AMDGPU_RING_TYPE_SDMA,
2302 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2303 .support_64bit_ptrs = true,
2304 .vmhub = AMDGPU_MMHUB_0,
2305 .get_rptr = sdma_v4_0_ring_get_rptr,
2306 .get_wptr = sdma_v4_0_ring_get_wptr,
2307 .set_wptr = sdma_v4_0_ring_set_wptr,
2309 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2310 3 + /* hdp invalidate */
2311 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2312 /* sdma_v4_0_ring_emit_vm_flush */
2313 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2314 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2315 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2316 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2317 .emit_ib = sdma_v4_0_ring_emit_ib,
2318 .emit_fence = sdma_v4_0_ring_emit_fence,
2319 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2320 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2321 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2322 .test_ring = sdma_v4_0_ring_test_ring,
2323 .test_ib = sdma_v4_0_ring_test_ib,
2324 .insert_nop = sdma_v4_0_ring_insert_nop,
2325 .pad_ib = sdma_v4_0_ring_pad_ib,
2326 .emit_wreg = sdma_v4_0_ring_emit_wreg,
2327 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2328 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2332 * On Arcturus, SDMA instance 5~7 has a different vmhub type(AMDGPU_MMHUB_1).
2333 * So create a individual constant ring_funcs for those instances.
2335 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs_2nd_mmhub = {
2336 .type = AMDGPU_RING_TYPE_SDMA,
2338 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2339 .support_64bit_ptrs = true,
2340 .vmhub = AMDGPU_MMHUB_1,
2341 .get_rptr = sdma_v4_0_ring_get_rptr,
2342 .get_wptr = sdma_v4_0_ring_get_wptr,
2343 .set_wptr = sdma_v4_0_ring_set_wptr,
2345 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2346 3 + /* hdp invalidate */
2347 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2348 /* sdma_v4_0_ring_emit_vm_flush */
2349 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2350 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2351 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2352 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2353 .emit_ib = sdma_v4_0_ring_emit_ib,
2354 .emit_fence = sdma_v4_0_ring_emit_fence,
2355 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2356 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2357 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2358 .test_ring = sdma_v4_0_ring_test_ring,
2359 .test_ib = sdma_v4_0_ring_test_ib,
2360 .insert_nop = sdma_v4_0_ring_insert_nop,
2361 .pad_ib = sdma_v4_0_ring_pad_ib,
2362 .emit_wreg = sdma_v4_0_ring_emit_wreg,
2363 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2364 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2367 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = {
2368 .type = AMDGPU_RING_TYPE_SDMA,
2370 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2371 .support_64bit_ptrs = true,
2372 .vmhub = AMDGPU_MMHUB_0,
2373 .get_rptr = sdma_v4_0_ring_get_rptr,
2374 .get_wptr = sdma_v4_0_page_ring_get_wptr,
2375 .set_wptr = sdma_v4_0_page_ring_set_wptr,
2377 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2378 3 + /* hdp invalidate */
2379 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2380 /* sdma_v4_0_ring_emit_vm_flush */
2381 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2382 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2383 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2384 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2385 .emit_ib = sdma_v4_0_ring_emit_ib,
2386 .emit_fence = sdma_v4_0_ring_emit_fence,
2387 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2388 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2389 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2390 .test_ring = sdma_v4_0_ring_test_ring,
2391 .test_ib = sdma_v4_0_ring_test_ib,
2392 .insert_nop = sdma_v4_0_ring_insert_nop,
2393 .pad_ib = sdma_v4_0_ring_pad_ib,
2394 .emit_wreg = sdma_v4_0_ring_emit_wreg,
2395 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2396 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2399 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs_2nd_mmhub = {
2400 .type = AMDGPU_RING_TYPE_SDMA,
2402 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2403 .support_64bit_ptrs = true,
2404 .vmhub = AMDGPU_MMHUB_1,
2405 .get_rptr = sdma_v4_0_ring_get_rptr,
2406 .get_wptr = sdma_v4_0_page_ring_get_wptr,
2407 .set_wptr = sdma_v4_0_page_ring_set_wptr,
2409 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2410 3 + /* hdp invalidate */
2411 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2412 /* sdma_v4_0_ring_emit_vm_flush */
2413 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2414 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2415 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2416 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2417 .emit_ib = sdma_v4_0_ring_emit_ib,
2418 .emit_fence = sdma_v4_0_ring_emit_fence,
2419 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2420 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2421 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2422 .test_ring = sdma_v4_0_ring_test_ring,
2423 .test_ib = sdma_v4_0_ring_test_ib,
2424 .insert_nop = sdma_v4_0_ring_insert_nop,
2425 .pad_ib = sdma_v4_0_ring_pad_ib,
2426 .emit_wreg = sdma_v4_0_ring_emit_wreg,
2427 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2428 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2431 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
2435 for (i = 0; i < adev->sdma.num_instances; i++) {
2436 if (adev->asic_type == CHIP_ARCTURUS && i >= 5)
2437 adev->sdma.instance[i].ring.funcs =
2438 &sdma_v4_0_ring_funcs_2nd_mmhub;
2440 adev->sdma.instance[i].ring.funcs =
2441 &sdma_v4_0_ring_funcs;
2442 adev->sdma.instance[i].ring.me = i;
2443 if (adev->sdma.has_page_queue) {
2444 if (adev->asic_type == CHIP_ARCTURUS && i >= 5)
2445 adev->sdma.instance[i].page.funcs =
2446 &sdma_v4_0_page_ring_funcs_2nd_mmhub;
2448 adev->sdma.instance[i].page.funcs =
2449 &sdma_v4_0_page_ring_funcs;
2450 adev->sdma.instance[i].page.me = i;
2455 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = {
2456 .set = sdma_v4_0_set_trap_irq_state,
2457 .process = sdma_v4_0_process_trap_irq,
2460 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = {
2461 .process = sdma_v4_0_process_illegal_inst_irq,
2464 static const struct amdgpu_irq_src_funcs sdma_v4_0_ecc_irq_funcs = {
2465 .set = sdma_v4_0_set_ecc_irq_state,
2466 .process = amdgpu_sdma_process_ecc_irq,
2471 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev)
2473 switch (adev->sdma.num_instances) {
2475 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1;
2476 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1;
2479 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
2480 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
2484 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2;
2485 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2;
2488 adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs;
2489 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs;
2490 adev->sdma.ecc_irq.funcs = &sdma_v4_0_ecc_irq_funcs;
2494 * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine
2496 * @ib: indirect buffer to copy to
2497 * @src_offset: src GPU address
2498 * @dst_offset: dst GPU address
2499 * @byte_count: number of bytes to xfer
2500 * @tmz: if a secure copy should be used
2502 * Copy GPU buffers using the DMA engine (VEGA10/12).
2503 * Used by the amdgpu ttm implementation to move pages if
2504 * registered as the asic copy callback.
2506 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib,
2507 uint64_t src_offset,
2508 uint64_t dst_offset,
2509 uint32_t byte_count,
2512 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
2513 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
2514 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
2515 ib->ptr[ib->length_dw++] = byte_count - 1;
2516 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
2517 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
2518 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
2519 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2520 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2524 * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine
2526 * @ib: indirect buffer to copy to
2527 * @src_data: value to write to buffer
2528 * @dst_offset: dst GPU address
2529 * @byte_count: number of bytes to xfer
2531 * Fill GPU buffers using the DMA engine (VEGA10/12).
2533 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib,
2535 uint64_t dst_offset,
2536 uint32_t byte_count)
2538 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
2539 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2540 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2541 ib->ptr[ib->length_dw++] = src_data;
2542 ib->ptr[ib->length_dw++] = byte_count - 1;
2545 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = {
2546 .copy_max_bytes = 0x400000,
2548 .emit_copy_buffer = sdma_v4_0_emit_copy_buffer,
2550 .fill_max_bytes = 0x400000,
2552 .emit_fill_buffer = sdma_v4_0_emit_fill_buffer,
2555 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
2557 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
2558 if (adev->sdma.has_page_queue)
2559 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
2561 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
2564 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = {
2565 .copy_pte_num_dw = 7,
2566 .copy_pte = sdma_v4_0_vm_copy_pte,
2568 .write_pte = sdma_v4_0_vm_write_pte,
2569 .set_pte_pde = sdma_v4_0_vm_set_pte_pde,
2572 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev)
2574 struct drm_gpu_scheduler *sched;
2577 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
2578 for (i = 0; i < adev->sdma.num_instances; i++) {
2579 if (adev->sdma.has_page_queue)
2580 sched = &adev->sdma.instance[i].page.sched;
2582 sched = &adev->sdma.instance[i].ring.sched;
2583 adev->vm_manager.vm_pte_scheds[i] = sched;
2585 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
2588 static void sdma_v4_0_get_ras_error_count(uint32_t value,
2590 uint32_t *sec_count)
2595 /* double bits error (multiple bits) error detection is not supported */
2596 for (i = 0; i < ARRAY_SIZE(sdma_v4_0_ras_fields); i++) {
2597 /* the SDMA_EDC_COUNTER register in each sdma instance
2598 * shares the same sed shift_mask
2601 sdma_v4_0_ras_fields[i].sec_count_mask) >>
2602 sdma_v4_0_ras_fields[i].sec_count_shift;
2604 DRM_INFO("Detected %s in SDMA%d, SED %d\n",
2605 sdma_v4_0_ras_fields[i].name,
2607 *sec_count += sec_cnt;
2612 static int sdma_v4_0_query_ras_error_count(struct amdgpu_device *adev,
2613 uint32_t instance, void *ras_error_status)
2615 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
2616 uint32_t sec_count = 0;
2617 uint32_t reg_value = 0;
2619 reg_value = RREG32_SDMA(instance, mmSDMA0_EDC_COUNTER);
2620 /* double bit error is not supported */
2622 sdma_v4_0_get_ras_error_count(reg_value,
2623 instance, &sec_count);
2624 /* err_data->ce_count should be initialized to 0
2625 * before calling into this function */
2626 err_data->ce_count += sec_count;
2627 /* double bit error is not supported
2628 * set ue count to 0 */
2629 err_data->ue_count = 0;
2634 static void sdma_v4_0_reset_ras_error_count(struct amdgpu_device *adev)
2638 /* read back edc counter registers to clear the counters */
2639 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2640 for (i = 0; i < adev->sdma.num_instances; i++)
2641 RREG32_SDMA(i, mmSDMA0_EDC_COUNTER);
2645 static const struct amdgpu_sdma_ras_funcs sdma_v4_0_ras_funcs = {
2646 .ras_late_init = amdgpu_sdma_ras_late_init,
2647 .ras_fini = amdgpu_sdma_ras_fini,
2648 .query_ras_error_count = sdma_v4_0_query_ras_error_count,
2649 .reset_ras_error_count = sdma_v4_0_reset_ras_error_count,
2652 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev)
2654 switch (adev->asic_type) {
2657 adev->sdma.funcs = &sdma_v4_0_ras_funcs;
2664 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = {
2665 .type = AMD_IP_BLOCK_TYPE_SDMA,
2669 .funcs = &sdma_v4_0_ip_funcs,