drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_ucode.h"
  31 #include "amdgpu_trace.h"
  32
  33 #include "sdma0/sdma0_4_2_offset.h"
  34 #include "sdma0/sdma0_4_2_sh_mask.h"
  35 #include "sdma1/sdma1_4_2_offset.h"
  36 #include "sdma1/sdma1_4_2_sh_mask.h"
  37 #include "sdma2/sdma2_4_2_2_offset.h"
  38 #include "sdma2/sdma2_4_2_2_sh_mask.h"
  39 #include "sdma3/sdma3_4_2_2_offset.h"
  40 #include "sdma3/sdma3_4_2_2_sh_mask.h"
  41 #include "sdma4/sdma4_4_2_2_offset.h"
  42 #include "sdma4/sdma4_4_2_2_sh_mask.h"
  43 #include "sdma5/sdma5_4_2_2_offset.h"
  44 #include "sdma5/sdma5_4_2_2_sh_mask.h"
  45 #include "sdma6/sdma6_4_2_2_offset.h"
  46 #include "sdma6/sdma6_4_2_2_sh_mask.h"
  47 #include "sdma7/sdma7_4_2_2_offset.h"
  48 #include "sdma7/sdma7_4_2_2_sh_mask.h"
  49 #include "sdma0/sdma0_4_1_default.h"
  50
  51 #include "soc15_common.h"
  52 #include "soc15.h"
  53 #include "vega10_sdma_pkt_open.h"
  54
  55 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h"
  56 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h"
  57
  58 #include "amdgpu_ras.h"
  59 #include "sdma_v4_4.h"
  60
  61 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin");
  62 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin");
  63 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin");
  64 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin");
  65 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin");
  66 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin");
  67 MODULE_FIRMWARE("amdgpu/raven_sdma.bin");
  68 MODULE_FIRMWARE("amdgpu/picasso_sdma.bin");
  69 MODULE_FIRMWARE("amdgpu/raven2_sdma.bin");
  70 MODULE_FIRMWARE("amdgpu/arcturus_sdma.bin");
  71 MODULE_FIRMWARE("amdgpu/renoir_sdma.bin");
  72 MODULE_FIRMWARE("amdgpu/green_sardine_sdma.bin");
  73 MODULE_FIRMWARE("amdgpu/aldebaran_sdma.bin");
  74
  75 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK  0x000000F8L
  76 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
  77
  78 #define WREG32_SDMA(instance, offset, value) \
  79         WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value)
  80 #define RREG32_SDMA(instance, offset) \
  81         RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)))
  82
  83 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev);
  84 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev);
  85 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  86 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev);
  87 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev);
  88
  89 static const struct soc15_reg_golden golden_settings_sdma_4[] = {
  90         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
  91         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
  92         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),
  93         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  94         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
  95         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  96         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000),
  97         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
  98         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  99         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
 100         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 101         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
 102         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000),
 103         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
 104         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100),
 105         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 106         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
 107         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 108         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000),
 109         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
 110         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 111         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
 112         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 113         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
 114         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000)
 115 };
 116
 117 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = {
 118         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
 119         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
 120         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 121         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
 122         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
 123         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
 124         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 125 };
 126
 127 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = {
 128         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
 129         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001),
 130         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 131         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
 132         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
 133         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001),
 134         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 135 };
 136
 137 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = {
 138         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
 139         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
 140         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100),
 141         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 142         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051),
 143         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100),
 144         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 145         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100),
 146         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 147         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003e0),
 148         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000)
 149 };
 150
 151 static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = {
 152         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
 153 };
 154
 155 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] =
 156 {
 157         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 158         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
 159         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 160         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 161         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 162         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 163         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 164         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 165         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003),
 166         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 167         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
 168         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 169         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 170         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 171         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 172         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 173         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 174         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 175         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 176         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 177         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 178         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 179         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 180         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 181         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 182         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
 183         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 184 };
 185
 186 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = {
 187         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 188         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
 189         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 190         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 191         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 192         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 193         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 194         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 195         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003),
 196         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 197         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
 198         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 199         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 200         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 201         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 202         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 203         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 204         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 205         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 206         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 207         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 208         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 209         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 210         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 211         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 212         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
 213         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 214 };
 215
 216 static const struct soc15_reg_golden golden_settings_sdma_rv1[] =
 217 {
 218         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
 219         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002)
 220 };
 221
 222 static const struct soc15_reg_golden golden_settings_sdma_rv2[] =
 223 {
 224         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001),
 225         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001)
 226 };
 227
 228 static const struct soc15_reg_golden golden_settings_sdma_arct[] =
 229 {
 230         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 231         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 232         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 233         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 234         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 235         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 236         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 237         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 238         SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 239         SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 240         SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 241         SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 242         SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 243         SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 244         SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 245         SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 246         SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 247         SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 248         SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 249         SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 250         SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 251         SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 252         SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 253         SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 254         SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 255         SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 256         SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 257         SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 258         SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 259         SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 260         SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 261         SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_UTCL1_TIMEOUT, 0xffffffff, 0x00010001)
 262 };
 263
 264 static const struct soc15_reg_golden golden_settings_sdma_aldebaran[] = {
 265         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
 266         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
 267         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 268         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
 269         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
 270         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 271         SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
 272         SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
 273         SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA2_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 274         SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
 275         SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
 276         SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 277         SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
 278         SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
 279         SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 280 };
 281
 282 static const struct soc15_reg_golden golden_settings_sdma_4_3[] = {
 283         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 284         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
 285         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
 286         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002),
 287         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 288         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051),
 289         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 290         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 291         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003e0),
 292         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x03fbe1fe)
 293 };
 294
 295 static const struct soc15_ras_field_entry sdma_v4_0_ras_fields[] = {
 296         { "SDMA_UCODE_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 297         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UCODE_BUF_SED),
 298         0, 0,
 299         },
 300         { "SDMA_RB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 301         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_RB_CMD_BUF_SED),
 302         0, 0,
 303         },
 304         { "SDMA_IB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 305         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_IB_CMD_BUF_SED),
 306         0, 0,
 307         },
 308         { "SDMA_UTCL1_RD_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 309         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RD_FIFO_SED),
 310         0, 0,
 311         },
 312         { "SDMA_UTCL1_RDBST_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 313         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RDBST_FIFO_SED),
 314         0, 0,
 315         },
 316         { "SDMA_DATA_LUT_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 317         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_DATA_LUT_FIFO_SED),
 318         0, 0,
 319         },
 320         { "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 321         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF0_SED),
 322         0, 0,
 323         },
 324         { "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 325         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF1_SED),
 326         0, 0,
 327         },
 328         { "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 329         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF2_SED),
 330         0, 0,
 331         },
 332         { "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 333         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF3_SED),
 334         0, 0,
 335         },
 336         { "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 337         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF4_SED),
 338         0, 0,
 339         },
 340         { "SDMA_MBANK_DATA_BUF5_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 341         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF5_SED),
 342         0, 0,
 343         },
 344         { "SDMA_MBANK_DATA_BUF6_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 345         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF6_SED),
 346         0, 0,
 347         },
 348         { "SDMA_MBANK_DATA_BUF7_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 349         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF7_SED),
 350         0, 0,
 351         },
 352         { "SDMA_MBANK_DATA_BUF8_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 353         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF8_SED),
 354         0, 0,
 355         },
 356         { "SDMA_MBANK_DATA_BUF9_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 357         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF9_SED),
 358         0, 0,
 359         },
 360         { "SDMA_MBANK_DATA_BUF10_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 361         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF10_SED),
 362         0, 0,
 363         },
 364         { "SDMA_MBANK_DATA_BUF11_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 365         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF11_SED),
 366         0, 0,
 367         },
 368         { "SDMA_MBANK_DATA_BUF12_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 369         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF12_SED),
 370         0, 0,
 371         },
 372         { "SDMA_MBANK_DATA_BUF13_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 373         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF13_SED),
 374         0, 0,
 375         },
 376         { "SDMA_MBANK_DATA_BUF14_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 377         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF14_SED),
 378         0, 0,
 379         },
 380         { "SDMA_MBANK_DATA_BUF15_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 381         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF15_SED),
 382         0, 0,
 383         },
 384         { "SDMA_SPLIT_DAT_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 385         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_SPLIT_DAT_BUF_SED),
 386         0, 0,
 387         },
 388         { "SDMA_MC_WR_ADDR_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 389         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MC_WR_ADDR_FIFO_SED),
 390         0, 0,
 391         },
 392 };
 393
 394 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
 395                 u32 instance, u32 offset)
 396 {
 397         switch (instance) {
 398         case 0:
 399                 return (adev->reg_offset[SDMA0_HWIP][0][0] + offset);
 400         case 1:
 401                 return (adev->reg_offset[SDMA1_HWIP][0][0] + offset);
 402         case 2:
 403                 return (adev->reg_offset[SDMA2_HWIP][0][1] + offset);
 404         case 3:
 405                 return (adev->reg_offset[SDMA3_HWIP][0][1] + offset);
 406         case 4:
 407                 return (adev->reg_offset[SDMA4_HWIP][0][1] + offset);
 408         case 5:
 409                 return (adev->reg_offset[SDMA5_HWIP][0][1] + offset);
 410         case 6:
 411                 return (adev->reg_offset[SDMA6_HWIP][0][1] + offset);
 412         case 7:
 413                 return (adev->reg_offset[SDMA7_HWIP][0][1] + offset);
 414         default:
 415                 break;
 416         }
 417         return 0;
 418 }
 419
 420 static unsigned sdma_v4_0_seq_to_irq_id(int seq_num)
 421 {
 422         switch (seq_num) {
 423         case 0:
 424                 return SOC15_IH_CLIENTID_SDMA0;
 425         case 1:
 426                 return SOC15_IH_CLIENTID_SDMA1;
 427         case 2:
 428                 return SOC15_IH_CLIENTID_SDMA2;
 429         case 3:
 430                 return SOC15_IH_CLIENTID_SDMA3;
 431         case 4:
 432                 return SOC15_IH_CLIENTID_SDMA4;
 433         case 5:
 434                 return SOC15_IH_CLIENTID_SDMA5;
 435         case 6:
 436                 return SOC15_IH_CLIENTID_SDMA6;
 437         case 7:
 438                 return SOC15_IH_CLIENTID_SDMA7;
 439         default:
 440                 break;
 441         }
 442         return -EINVAL;
 443 }
 444
 445 static int sdma_v4_0_irq_id_to_seq(unsigned client_id)
 446 {
 447         switch (client_id) {
 448         case SOC15_IH_CLIENTID_SDMA0:
 449                 return 0;
 450         case SOC15_IH_CLIENTID_SDMA1:
 451                 return 1;
 452         case SOC15_IH_CLIENTID_SDMA2:
 453                 return 2;
 454         case SOC15_IH_CLIENTID_SDMA3:
 455                 return 3;
 456         case SOC15_IH_CLIENTID_SDMA4:
 457                 return 4;
 458         case SOC15_IH_CLIENTID_SDMA5:
 459                 return 5;
 460         case SOC15_IH_CLIENTID_SDMA6:
 461                 return 6;
 462         case SOC15_IH_CLIENTID_SDMA7:
 463                 return 7;
 464         default:
 465                 break;
 466         }
 467         return -EINVAL;
 468 }
 469
 470 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
 471 {
 472         switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
 473         case IP_VERSION(4, 0, 0):
 474                 soc15_program_register_sequence(adev,
 475                                                 golden_settings_sdma_4,
 476                                                 ARRAY_SIZE(golden_settings_sdma_4));
 477                 soc15_program_register_sequence(adev,
 478                                                 golden_settings_sdma_vg10,
 479                                                 ARRAY_SIZE(golden_settings_sdma_vg10));
 480                 break;
 481         case IP_VERSION(4, 0, 1):
 482                 soc15_program_register_sequence(adev,
 483                                                 golden_settings_sdma_4,
 484                                                 ARRAY_SIZE(golden_settings_sdma_4));
 485                 soc15_program_register_sequence(adev,
 486                                                 golden_settings_sdma_vg12,
 487                                                 ARRAY_SIZE(golden_settings_sdma_vg12));
 488                 break;
 489         case IP_VERSION(4, 2, 0):
 490                 soc15_program_register_sequence(adev,
 491                                                 golden_settings_sdma0_4_2_init,
 492                                                 ARRAY_SIZE(golden_settings_sdma0_4_2_init));
 493                 soc15_program_register_sequence(adev,
 494                                                 golden_settings_sdma0_4_2,
 495                                                 ARRAY_SIZE(golden_settings_sdma0_4_2));
 496                 soc15_program_register_sequence(adev,
 497                                                 golden_settings_sdma1_4_2,
 498                                                 ARRAY_SIZE(golden_settings_sdma1_4_2));
 499                 break;
 500         case IP_VERSION(4, 2, 2):
 501                 soc15_program_register_sequence(adev,
 502                                                 golden_settings_sdma_arct,
 503                                                 ARRAY_SIZE(golden_settings_sdma_arct));
 504                 break;
 505         case IP_VERSION(4, 4, 0):
 506                 soc15_program_register_sequence(adev,
 507                                                 golden_settings_sdma_aldebaran,
 508                                                 ARRAY_SIZE(golden_settings_sdma_aldebaran));
 509                 break;
 510         case IP_VERSION(4, 1, 0):
 511         case IP_VERSION(4, 1, 1):
 512                 soc15_program_register_sequence(adev,
 513                                                 golden_settings_sdma_4_1,
 514                                                 ARRAY_SIZE(golden_settings_sdma_4_1));
 515                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
 516                         soc15_program_register_sequence(adev,
 517                                                         golden_settings_sdma_rv2,
 518                                                         ARRAY_SIZE(golden_settings_sdma_rv2));
 519                 else
 520                         soc15_program_register_sequence(adev,
 521                                                         golden_settings_sdma_rv1,
 522                                                         ARRAY_SIZE(golden_settings_sdma_rv1));
 523                 break;
 524         case IP_VERSION(4, 1, 2):
 525                 soc15_program_register_sequence(adev,
 526                                                 golden_settings_sdma_4_3,
 527                                                 ARRAY_SIZE(golden_settings_sdma_4_3));
 528                 break;
 529         default:
 530                 break;
 531         }
 532 }
 533
 534 static void sdma_v4_0_setup_ulv(struct amdgpu_device *adev)
 535 {
 536         int i;
 537
 538         /*
 539          * The only chips with SDMAv4 and ULV are VG10 and VG20.
 540          * Server SKUs take a different hysteresis setting from other SKUs.
 541          */
 542         switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
 543         case IP_VERSION(4, 0, 0):
 544                 if (adev->pdev->device == 0x6860)
 545                         break;
 546                 return;
 547         case IP_VERSION(4, 2, 0):
 548                 if (adev->pdev->device == 0x66a1)
 549                         break;
 550                 return;
 551         default:
 552                 return;
 553         }
 554
 555         for (i = 0; i < adev->sdma.num_instances; i++) {
 556                 uint32_t temp;
 557
 558                 temp = RREG32_SDMA(i, mmSDMA0_ULV_CNTL);
 559                 temp = REG_SET_FIELD(temp, SDMA0_ULV_CNTL, HYSTERESIS, 0x0);
 560                 WREG32_SDMA(i, mmSDMA0_ULV_CNTL, temp);
 561         }
 562 }
 563
 564 /**
 565  * sdma_v4_0_init_microcode - load ucode images from disk
 566  *
 567  * @adev: amdgpu_device pointer
 568  *
 569  * Use the firmware interface to load the ucode images into
 570  * the driver (not loaded into hw).
 571  * Returns 0 on success, error on failure.
 572  */
 573
 574 // emulation only, won't work on real chip
 575 // vega10 real chip need to use PSP to load firmware
 576 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
 577 {
 578         int ret, i;
 579
 580         for (i = 0; i < adev->sdma.num_instances; i++) {
 581                 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) ==
 582                             IP_VERSION(4, 2, 2) ||
 583                     amdgpu_ip_version(adev, SDMA0_HWIP, 0) ==
 584                             IP_VERSION(4, 4, 0)) {
 585                         /* Acturus & Aldebaran will leverage the same FW memory
 586                            for every SDMA instance */
 587                         ret = amdgpu_sdma_init_microcode(adev, 0, true);
 588                         break;
 589                 } else {
 590                         ret = amdgpu_sdma_init_microcode(adev, i, false);
 591                         if (ret)
 592                                 return ret;
 593                 }
 594         }
 595
 596         return ret;
 597 }
 598
 599 /**
 600  * sdma_v4_0_ring_get_rptr - get the current read pointer
 601  *
 602  * @ring: amdgpu ring pointer
 603  *
 604  * Get the current rptr from the hardware (VEGA10+).
 605  */
 606 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring)
 607 {
 608         u64 *rptr;
 609
 610         /* XXX check if swapping is necessary on BE */
 611         rptr = ((u64 *)ring->rptr_cpu_addr);
 612
 613         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 614         return ((*rptr) >> 2);
 615 }
 616
 617 /**
 618  * sdma_v4_0_ring_get_wptr - get the current write pointer
 619  *
 620  * @ring: amdgpu ring pointer
 621  *
 622  * Get the current wptr from the hardware (VEGA10+).
 623  */
 624 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
 625 {
 626         struct amdgpu_device *adev = ring->adev;
 627         u64 wptr;
 628
 629         if (ring->use_doorbell) {
 630                 /* XXX check if swapping is necessary on BE */
 631                 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
 632                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 633         } else {
 634                 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI);
 635                 wptr = wptr << 32;
 636                 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR);
 637                 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n",
 638                                 ring->me, wptr);
 639         }
 640
 641         return wptr >> 2;
 642 }
 643
 644 /**
 645  * sdma_v4_0_ring_set_wptr - commit the write pointer
 646  *
 647  * @ring: amdgpu ring pointer
 648  *
 649  * Write the wptr back to the hardware (VEGA10+).
 650  */
 651 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
 652 {
 653         struct amdgpu_device *adev = ring->adev;
 654
 655         DRM_DEBUG("Setting write pointer\n");
 656         if (ring->use_doorbell) {
 657                 u64 *wb = (u64 *)ring->wptr_cpu_addr;
 658
 659                 DRM_DEBUG("Using doorbell -- "
 660                                 "wptr_offs == 0x%08x "
 661                                 "lower_32_bits(ring->wptr << 2) == 0x%08x "
 662                                 "upper_32_bits(ring->wptr << 2) == 0x%08x\n",
 663                                 ring->wptr_offs,
 664                                 lower_32_bits(ring->wptr << 2),
 665                                 upper_32_bits(ring->wptr << 2));
 666                 /* XXX check if swapping is necessary on BE */
 667                 WRITE_ONCE(*wb, (ring->wptr << 2));
 668                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 669                                 ring->doorbell_index, ring->wptr << 2);
 670                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 671         } else {
 672                 DRM_DEBUG("Not using doorbell -- "
 673                                 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 674                                 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 675                                 ring->me,
 676                                 lower_32_bits(ring->wptr << 2),
 677                                 ring->me,
 678                                 upper_32_bits(ring->wptr << 2));
 679                 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR,
 680                             lower_32_bits(ring->wptr << 2));
 681                 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI,
 682                             upper_32_bits(ring->wptr << 2));
 683         }
 684 }
 685
 686 /**
 687  * sdma_v4_0_page_ring_get_wptr - get the current write pointer
 688  *
 689  * @ring: amdgpu ring pointer
 690  *
 691  * Get the current wptr from the hardware (VEGA10+).
 692  */
 693 static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring)
 694 {
 695         struct amdgpu_device *adev = ring->adev;
 696         u64 wptr;
 697
 698         if (ring->use_doorbell) {
 699                 /* XXX check if swapping is necessary on BE */
 700                 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
 701         } else {
 702                 wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI);
 703                 wptr = wptr << 32;
 704                 wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR);
 705         }
 706
 707         return wptr >> 2;
 708 }
 709
 710 /**
 711  * sdma_v4_0_page_ring_set_wptr - commit the write pointer
 712  *
 713  * @ring: amdgpu ring pointer
 714  *
 715  * Write the wptr back to the hardware (VEGA10+).
 716  */
 717 static void sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring *ring)
 718 {
 719         struct amdgpu_device *adev = ring->adev;
 720
 721         if (ring->use_doorbell) {
 722                 u64 *wb = (u64 *)ring->wptr_cpu_addr;
 723
 724                 /* XXX check if swapping is necessary on BE */
 725                 WRITE_ONCE(*wb, (ring->wptr << 2));
 726                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 727         } else {
 728                 uint64_t wptr = ring->wptr << 2;
 729
 730                 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR,
 731                             lower_32_bits(wptr));
 732                 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI,
 733                             upper_32_bits(wptr));
 734         }
 735 }
 736
 737 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 738 {
 739         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 740         int i;
 741
 742         for (i = 0; i < count; i++)
 743                 if (sdma && sdma->burst_nop && (i == 0))
 744                         amdgpu_ring_write(ring, ring->funcs->nop |
 745                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 746                 else
 747                         amdgpu_ring_write(ring, ring->funcs->nop);
 748 }
 749
 750 /**
 751  * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine
 752  *
 753  * @ring: amdgpu ring pointer
 754  * @job: job to retrieve vmid from
 755  * @ib: IB object to schedule
 756  * @flags: unused
 757  *
 758  * Schedule an IB in the DMA ring (VEGA10).
 759  */
 760 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
 761                                    struct amdgpu_job *job,
 762                                    struct amdgpu_ib *ib,
 763                                    uint32_t flags)
 764 {
 765         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 766
 767         /* IB packet must end on a 8 DW boundary */
 768         sdma_v4_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 769
 770         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 771                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 772         /* base must be 32 byte aligned */
 773         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 774         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 775         amdgpu_ring_write(ring, ib->length_dw);
 776         amdgpu_ring_write(ring, 0);
 777         amdgpu_ring_write(ring, 0);
 778
 779 }
 780
 781 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring,
 782                                    int mem_space, int hdp,
 783                                    uint32_t addr0, uint32_t addr1,
 784                                    uint32_t ref, uint32_t mask,
 785                                    uint32_t inv)
 786 {
 787         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 788                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) |
 789                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) |
 790                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 791         if (mem_space) {
 792                 /* memory */
 793                 amdgpu_ring_write(ring, addr0);
 794                 amdgpu_ring_write(ring, addr1);
 795         } else {
 796                 /* registers */
 797                 amdgpu_ring_write(ring, addr0 << 2);
 798                 amdgpu_ring_write(ring, addr1 << 2);
 799         }
 800         amdgpu_ring_write(ring, ref); /* reference */
 801         amdgpu_ring_write(ring, mask); /* mask */
 802         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 803                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */
 804 }
 805
 806 /**
 807  * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 808  *
 809  * @ring: amdgpu ring pointer
 810  *
 811  * Emit an hdp flush packet on the requested DMA ring.
 812  */
 813 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 814 {
 815         struct amdgpu_device *adev = ring->adev;
 816         u32 ref_and_mask = 0;
 817         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 818
 819         ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
 820
 821         sdma_v4_0_wait_reg_mem(ring, 0, 1,
 822                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
 823                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
 824                                ref_and_mask, ref_and_mask, 10);
 825 }
 826
 827 /**
 828  * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring
 829  *
 830  * @ring: amdgpu ring pointer
 831  * @addr: address
 832  * @seq: sequence number
 833  * @flags: fence related flags
 834  *
 835  * Add a DMA fence packet to the ring to write
 836  * the fence seq number and DMA trap packet to generate
 837  * an interrupt if needed (VEGA10).
 838  */
 839 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 840                                       unsigned flags)
 841 {
 842         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 843         /* write the fence */
 844         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 845         /* zero in first two bits */
 846         BUG_ON(addr & 0x3);
 847         amdgpu_ring_write(ring, lower_32_bits(addr));
 848         amdgpu_ring_write(ring, upper_32_bits(addr));
 849         amdgpu_ring_write(ring, lower_32_bits(seq));
 850
 851         /* optionally write high bits as well */
 852         if (write64bit) {
 853                 addr += 4;
 854                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 855                 /* zero in first two bits */
 856                 BUG_ON(addr & 0x3);
 857                 amdgpu_ring_write(ring, lower_32_bits(addr));
 858                 amdgpu_ring_write(ring, upper_32_bits(addr));
 859                 amdgpu_ring_write(ring, upper_32_bits(seq));
 860         }
 861
 862         /* generate an interrupt */
 863         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 864         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 865 }
 866
 867
 868 /**
 869  * sdma_v4_0_gfx_enable - enable the gfx async dma engines
 870  *
 871  * @adev: amdgpu_device pointer
 872  * @enable: enable SDMA RB/IB
 873  * control the gfx async dma ring buffers (VEGA10).
 874  */
 875 static void sdma_v4_0_gfx_enable(struct amdgpu_device *adev, bool enable)
 876 {
 877         u32 rb_cntl, ib_cntl;
 878         int i;
 879
 880         for (i = 0; i < adev->sdma.num_instances; i++) {
 881                 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
 882                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, enable ? 1 : 0);
 883                 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
 884                 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
 885                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, enable ? 1 : 0);
 886                 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
 887         }
 888 }
 889
 890 /**
 891  * sdma_v4_0_rlc_stop - stop the compute async dma engines
 892  *
 893  * @adev: amdgpu_device pointer
 894  *
 895  * Stop the compute async dma queues (VEGA10).
 896  */
 897 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev)
 898 {
 899         /* XXX todo */
 900 }
 901
 902 /**
 903  * sdma_v4_0_page_stop - stop the page async dma engines
 904  *
 905  * @adev: amdgpu_device pointer
 906  *
 907  * Stop the page async dma ring buffers (VEGA10).
 908  */
 909 static void sdma_v4_0_page_stop(struct amdgpu_device *adev)
 910 {
 911         u32 rb_cntl, ib_cntl;
 912         int i;
 913
 914         for (i = 0; i < adev->sdma.num_instances; i++) {
 915                 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);
 916                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
 917                                         RB_ENABLE, 0);
 918                 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
 919                 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL);
 920                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL,
 921                                         IB_ENABLE, 0);
 922                 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
 923         }
 924 }
 925
 926 /**
 927  * sdma_v4_0_ctx_switch_enable - stop the async dma engines context switch
 928  *
 929  * @adev: amdgpu_device pointer
 930  * @enable: enable/disable the DMA MEs context switch.
 931  *
 932  * Halt or unhalt the async dma engines context switch (VEGA10).
 933  */
 934 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 935 {
 936         u32 f32_cntl, phase_quantum = 0;
 937         int i;
 938
 939         if (amdgpu_sdma_phase_quantum) {
 940                 unsigned value = amdgpu_sdma_phase_quantum;
 941                 unsigned unit = 0;
 942
 943                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 944                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 945                         value = (value + 1) >> 1;
 946                         unit++;
 947                 }
 948                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 949                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 950                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 951                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 952                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 953                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 954                         WARN_ONCE(1,
 955                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 956                                   value << unit);
 957                 }
 958                 phase_quantum =
 959                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 960                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 961         }
 962
 963         for (i = 0; i < adev->sdma.num_instances; i++) {
 964                 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL);
 965                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 966                                 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 967                 if (enable && amdgpu_sdma_phase_quantum) {
 968                         WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum);
 969                         WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum);
 970                         WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum);
 971                 }
 972                 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl);
 973
 974                 /*
 975                  * Enable SDMA utilization. Its only supported on
 976                  * Arcturus for the moment and firmware version 14
 977                  * and above.
 978                  */
 979                 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) ==
 980                             IP_VERSION(4, 2, 2) &&
 981                     adev->sdma.instance[i].fw_version >= 14)
 982                         WREG32_SDMA(i, mmSDMA0_PUB_DUMMY_REG2, enable);
 983                 /* Extend page fault timeout to avoid interrupt storm */
 984                 WREG32_SDMA(i, mmSDMA0_UTCL1_TIMEOUT, 0x00800080);
 985         }
 986
 987 }
 988
 989 /**
 990  * sdma_v4_0_enable - stop the async dma engines
 991  *
 992  * @adev: amdgpu_device pointer
 993  * @enable: enable/disable the DMA MEs.
 994  *
 995  * Halt or unhalt the async dma engines (VEGA10).
 996  */
 997 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable)
 998 {
 999         u32 f32_cntl;
1000         int i;
1001
1002         if (!enable) {
1003                 sdma_v4_0_gfx_enable(adev, enable);
1004                 sdma_v4_0_rlc_stop(adev);
1005                 if (adev->sdma.has_page_queue)
1006                         sdma_v4_0_page_stop(adev);
1007         }
1008
1009         for (i = 0; i < adev->sdma.num_instances; i++) {
1010                 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
1011                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
1012                 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl);
1013         }
1014 }
1015
1016 /*
1017  * sdma_v4_0_rb_cntl - get parameters for rb_cntl
1018  */
1019 static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl)
1020 {
1021         /* Set ring buffer size in dwords */
1022         uint32_t rb_bufsz = order_base_2(ring->ring_size / 4);
1023
1024         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
1025 #ifdef __BIG_ENDIAN
1026         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
1027         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
1028                                 RPTR_WRITEBACK_SWAP_ENABLE, 1);
1029 #endif
1030         return rb_cntl;
1031 }
1032
1033 /**
1034  * sdma_v4_0_gfx_resume - setup and start the async dma engines
1035  *
1036  * @adev: amdgpu_device pointer
1037  * @i: instance to resume
1038  *
1039  * Set up the gfx DMA ring buffers and enable them (VEGA10).
1040  * Returns 0 for success, error for failure.
1041  */
1042 static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i)
1043 {
1044         struct amdgpu_ring *ring = &adev->sdma.instance[i].ring;
1045         u32 rb_cntl, ib_cntl, wptr_poll_cntl;
1046         u32 doorbell;
1047         u32 doorbell_offset;
1048         u64 wptr_gpu_addr;
1049
1050         rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
1051         rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl);
1052         WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
1053
1054         /* Initialize the ring buffer's read and write pointers */
1055         WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0);
1056         WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0);
1057         WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0);
1058         WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0);
1059
1060         /* set the wb address whether it's enabled or not */
1061         WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI,
1062                upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
1063         WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO,
1064                lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
1065
1066         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
1067                                 RPTR_WRITEBACK_ENABLE, 1);
1068
1069         WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8);
1070         WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40);
1071
1072         ring->wptr = 0;
1073
1074         /* before programing wptr to a less value, need set minor_ptr_update first */
1075         WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1);
1076
1077         doorbell = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL);
1078         doorbell_offset = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET);
1079
1080         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE,
1081                                  ring->use_doorbell);
1082         doorbell_offset = REG_SET_FIELD(doorbell_offset,
1083                                         SDMA0_GFX_DOORBELL_OFFSET,
1084                                         OFFSET, ring->doorbell_index);
1085         WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell);
1086         WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset);
1087
1088         sdma_v4_0_ring_set_wptr(ring);
1089
1090         /* set minor_ptr_update to 0 after wptr programed */
1091         WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0);
1092
1093         /* setup the wptr shadow polling */
1094         wptr_gpu_addr = ring->wptr_gpu_addr;
1095         WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO,
1096                     lower_32_bits(wptr_gpu_addr));
1097         WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI,
1098                     upper_32_bits(wptr_gpu_addr));
1099         wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL);
1100         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
1101                                        SDMA0_GFX_RB_WPTR_POLL_CNTL,
1102                                        F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
1103         WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
1104
1105         /* enable DMA RB */
1106         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
1107         WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
1108
1109         ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
1110         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
1111 #ifdef __BIG_ENDIAN
1112         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
1113 #endif
1114         /* enable DMA IBs */
1115         WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
1116 }
1117
1118 /**
1119  * sdma_v4_0_page_resume - setup and start the async dma engines
1120  *
1121  * @adev: amdgpu_device pointer
1122  * @i: instance to resume
1123  *
1124  * Set up the page DMA ring buffers and enable them (VEGA10).
1125  * Returns 0 for success, error for failure.
1126  */
1127 static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i)
1128 {
1129         struct amdgpu_ring *ring = &adev->sdma.instance[i].page;
1130         u32 rb_cntl, ib_cntl, wptr_poll_cntl;
1131         u32 doorbell;
1132         u32 doorbell_offset;
1133         u64 wptr_gpu_addr;
1134
1135         rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);
1136         rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl);
1137         WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
1138
1139         /* Initialize the ring buffer's read and write pointers */
1140         WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR, 0);
1141         WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_HI, 0);
1142         WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR, 0);
1143         WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_HI, 0);
1144
1145         /* set the wb address whether it's enabled or not */
1146         WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_HI,
1147                upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
1148         WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_LO,
1149                lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
1150
1151         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
1152                                 RPTR_WRITEBACK_ENABLE, 1);
1153
1154         WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE, ring->gpu_addr >> 8);
1155         WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE_HI, ring->gpu_addr >> 40);
1156
1157         ring->wptr = 0;
1158
1159         /* before programing wptr to a less value, need set minor_ptr_update first */
1160         WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 1);
1161
1162         doorbell = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL);
1163         doorbell_offset = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET);
1164
1165         doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE,
1166                                  ring->use_doorbell);
1167         doorbell_offset = REG_SET_FIELD(doorbell_offset,
1168                                         SDMA0_PAGE_DOORBELL_OFFSET,
1169                                         OFFSET, ring->doorbell_index);
1170         WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell);
1171         WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset);
1172
1173         /* paging queue doorbell range is setup at sdma_v4_0_gfx_resume */
1174         sdma_v4_0_page_ring_set_wptr(ring);
1175
1176         /* set minor_ptr_update to 0 after wptr programed */
1177         WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0);
1178
1179         /* setup the wptr shadow polling */
1180         wptr_gpu_addr = ring->wptr_gpu_addr;
1181         WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO,
1182                     lower_32_bits(wptr_gpu_addr));
1183         WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI,
1184                     upper_32_bits(wptr_gpu_addr));
1185         wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL);
1186         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
1187                                        SDMA0_PAGE_RB_WPTR_POLL_CNTL,
1188                                        F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
1189         WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
1190
1191         /* enable DMA RB */
1192         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1);
1193         WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
1194
1195         ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL);
1196         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_ENABLE, 1);
1197 #ifdef __BIG_ENDIAN
1198         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1);
1199 #endif
1200         /* enable DMA IBs */
1201         WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
1202 }
1203
1204 static void
1205 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable)
1206 {
1207         uint32_t def, data;
1208
1209         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) {
1210                 /* enable idle interrupt */
1211                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1212                 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1213
1214                 if (data != def)
1215                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1216         } else {
1217                 /* disable idle interrupt */
1218                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1219                 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1220                 if (data != def)
1221                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1222         }
1223 }
1224
1225 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev)
1226 {
1227         uint32_t def, data;
1228
1229         /* Enable HW based PG. */
1230         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1231         data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK;
1232         if (data != def)
1233                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1234
1235         /* enable interrupt */
1236         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1237         data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1238         if (data != def)
1239                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1240
1241         /* Configure hold time to filter in-valid power on/off request. Use default right now */
1242         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1243         data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK;
1244         data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK);
1245         /* Configure switch time for hysteresis purpose. Use default right now */
1246         data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK;
1247         data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK);
1248         if(data != def)
1249                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1250 }
1251
1252 static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
1253 {
1254         if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA))
1255                 return;
1256
1257         switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
1258         case IP_VERSION(4, 1, 0):
1259         case IP_VERSION(4, 1, 1):
1260         case IP_VERSION(4, 1, 2):
1261                 sdma_v4_1_init_power_gating(adev);
1262                 sdma_v4_1_update_power_gating(adev, true);
1263                 break;
1264         default:
1265                 break;
1266         }
1267 }
1268
1269 /**
1270  * sdma_v4_0_rlc_resume - setup and start the async dma engines
1271  *
1272  * @adev: amdgpu_device pointer
1273  *
1274  * Set up the compute DMA queues and enable them (VEGA10).
1275  * Returns 0 for success, error for failure.
1276  */
1277 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev)
1278 {
1279         sdma_v4_0_init_pg(adev);
1280
1281         return 0;
1282 }
1283
1284 /**
1285  * sdma_v4_0_load_microcode - load the sDMA ME ucode
1286  *
1287  * @adev: amdgpu_device pointer
1288  *
1289  * Loads the sDMA0/1 ucode.
1290  * Returns 0 for success, -EINVAL if the ucode is not available.
1291  */
1292 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev)
1293 {
1294         const struct sdma_firmware_header_v1_0 *hdr;
1295         const __le32 *fw_data;
1296         u32 fw_size;
1297         int i, j;
1298
1299         /* halt the MEs */
1300         sdma_v4_0_enable(adev, false);
1301
1302         for (i = 0; i < adev->sdma.num_instances; i++) {
1303                 if (!adev->sdma.instance[i].fw)
1304                         return -EINVAL;
1305
1306                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
1307                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
1308                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1309
1310                 fw_data = (const __le32 *)
1311                         (adev->sdma.instance[i].fw->data +
1312                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1313
1314                 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0);
1315
1316                 for (j = 0; j < fw_size; j++)
1317                         WREG32_SDMA(i, mmSDMA0_UCODE_DATA,
1318                                     le32_to_cpup(fw_data++));
1319
1320                 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR,
1321                             adev->sdma.instance[i].fw_version);
1322         }
1323
1324         return 0;
1325 }
1326
1327 /**
1328  * sdma_v4_0_start - setup and start the async dma engines
1329  *
1330  * @adev: amdgpu_device pointer
1331  *
1332  * Set up the DMA engines and enable them (VEGA10).
1333  * Returns 0 for success, error for failure.
1334  */
1335 static int sdma_v4_0_start(struct amdgpu_device *adev)
1336 {
1337         struct amdgpu_ring *ring;
1338         int i, r = 0;
1339
1340         if (amdgpu_sriov_vf(adev)) {
1341                 sdma_v4_0_ctx_switch_enable(adev, false);
1342                 sdma_v4_0_enable(adev, false);
1343         } else {
1344
1345                 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1346                         r = sdma_v4_0_load_microcode(adev);
1347                         if (r)
1348                                 return r;
1349                 }
1350
1351                 /* unhalt the MEs */
1352                 sdma_v4_0_enable(adev, true);
1353                 /* enable sdma ring preemption */
1354                 sdma_v4_0_ctx_switch_enable(adev, true);
1355         }
1356
1357         /* start the gfx rings and rlc compute queues */
1358         for (i = 0; i < adev->sdma.num_instances; i++) {
1359                 uint32_t temp;
1360
1361                 WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0);
1362                 sdma_v4_0_gfx_resume(adev, i);
1363                 if (adev->sdma.has_page_queue)
1364                         sdma_v4_0_page_resume(adev, i);
1365
1366                 /* set utc l1 enable flag always to 1 */
1367                 temp = RREG32_SDMA(i, mmSDMA0_CNTL);
1368                 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
1369                 WREG32_SDMA(i, mmSDMA0_CNTL, temp);
1370
1371                 if (!amdgpu_sriov_vf(adev)) {
1372                         /* unhalt engine */
1373                         temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
1374                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
1375                         WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp);
1376                 }
1377         }
1378
1379         if (amdgpu_sriov_vf(adev)) {
1380                 sdma_v4_0_ctx_switch_enable(adev, true);
1381                 sdma_v4_0_enable(adev, true);
1382         } else {
1383                 r = sdma_v4_0_rlc_resume(adev);
1384                 if (r)
1385                         return r;
1386         }
1387
1388         for (i = 0; i < adev->sdma.num_instances; i++) {
1389                 ring = &adev->sdma.instance[i].ring;
1390
1391                 r = amdgpu_ring_test_helper(ring);
1392                 if (r)
1393                         return r;
1394
1395                 if (adev->sdma.has_page_queue) {
1396                         struct amdgpu_ring *page = &adev->sdma.instance[i].page;
1397
1398                         r = amdgpu_ring_test_helper(page);
1399                         if (r)
1400                                 return r;
1401                 }
1402         }
1403
1404         return r;
1405 }
1406
1407 /**
1408  * sdma_v4_0_ring_test_ring - simple async dma engine test
1409  *
1410  * @ring: amdgpu_ring structure holding ring information
1411  *
1412  * Test the DMA engine by writing using it to write an
1413  * value to memory. (VEGA10).
1414  * Returns 0 for success, error for failure.
1415  */
1416 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring)
1417 {
1418         struct amdgpu_device *adev = ring->adev;
1419         unsigned i;
1420         unsigned index;
1421         int r;
1422         u32 tmp;
1423         u64 gpu_addr;
1424
1425         r = amdgpu_device_wb_get(adev, &index);
1426         if (r)
1427                 return r;
1428
1429         gpu_addr = adev->wb.gpu_addr + (index * 4);
1430         tmp = 0xCAFEDEAD;
1431         adev->wb.wb[index] = cpu_to_le32(tmp);
1432
1433         r = amdgpu_ring_alloc(ring, 5);
1434         if (r)
1435                 goto error_free_wb;
1436
1437         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1438                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
1439         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
1440         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
1441         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
1442         amdgpu_ring_write(ring, 0xDEADBEEF);
1443         amdgpu_ring_commit(ring);
1444
1445         for (i = 0; i < adev->usec_timeout; i++) {
1446                 tmp = le32_to_cpu(adev->wb.wb[index]);
1447                 if (tmp == 0xDEADBEEF)
1448                         break;
1449                 udelay(1);
1450         }
1451
1452         if (i >= adev->usec_timeout)
1453                 r = -ETIMEDOUT;
1454
1455 error_free_wb:
1456         amdgpu_device_wb_free(adev, index);
1457         return r;
1458 }
1459
1460 /**
1461  * sdma_v4_0_ring_test_ib - test an IB on the DMA engine
1462  *
1463  * @ring: amdgpu_ring structure holding ring information
1464  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1465  *
1466  * Test a simple IB in the DMA ring (VEGA10).
1467  * Returns 0 on success, error on failure.
1468  */
1469 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1470 {
1471         struct amdgpu_device *adev = ring->adev;
1472         struct amdgpu_ib ib;
1473         struct dma_fence *f = NULL;
1474         unsigned index;
1475         long r;
1476         u32 tmp = 0;
1477         u64 gpu_addr;
1478
1479         r = amdgpu_device_wb_get(adev, &index);
1480         if (r)
1481                 return r;
1482
1483         gpu_addr = adev->wb.gpu_addr + (index * 4);
1484         tmp = 0xCAFEDEAD;
1485         adev->wb.wb[index] = cpu_to_le32(tmp);
1486         memset(&ib, 0, sizeof(ib));
1487         r = amdgpu_ib_get(adev, NULL, 256,
1488                                         AMDGPU_IB_POOL_DIRECT, &ib);
1489         if (r)
1490                 goto err0;
1491
1492         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1493                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1494         ib.ptr[1] = lower_32_bits(gpu_addr);
1495         ib.ptr[2] = upper_32_bits(gpu_addr);
1496         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1497         ib.ptr[4] = 0xDEADBEEF;
1498         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1499         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1500         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1501         ib.length_dw = 8;
1502
1503         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1504         if (r)
1505                 goto err1;
1506
1507         r = dma_fence_wait_timeout(f, false, timeout);
1508         if (r == 0) {
1509                 r = -ETIMEDOUT;
1510                 goto err1;
1511         } else if (r < 0) {
1512                 goto err1;
1513         }
1514         tmp = le32_to_cpu(adev->wb.wb[index]);
1515         if (tmp == 0xDEADBEEF)
1516                 r = 0;
1517         else
1518                 r = -EINVAL;
1519
1520 err1:
1521         amdgpu_ib_free(adev, &ib, NULL);
1522         dma_fence_put(f);
1523 err0:
1524         amdgpu_device_wb_free(adev, index);
1525         return r;
1526 }
1527
1528
1529 /**
1530  * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART
1531  *
1532  * @ib: indirect buffer to fill with commands
1533  * @pe: addr of the page entry
1534  * @src: src addr to copy from
1535  * @count: number of page entries to update
1536  *
1537  * Update PTEs by copying them from the GART using sDMA (VEGA10).
1538  */
1539 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib,
1540                                   uint64_t pe, uint64_t src,
1541                                   unsigned count)
1542 {
1543         unsigned bytes = count * 8;
1544
1545         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1546                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1547         ib->ptr[ib->length_dw++] = bytes - 1;
1548         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1549         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1550         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1551         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1552         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1553
1554 }
1555
1556 /**
1557  * sdma_v4_0_vm_write_pte - update PTEs by writing them manually
1558  *
1559  * @ib: indirect buffer to fill with commands
1560  * @pe: addr of the page entry
1561  * @value: dst addr to write into pe
1562  * @count: number of page entries to update
1563  * @incr: increase next addr by incr bytes
1564  *
1565  * Update PTEs by writing them manually using sDMA (VEGA10).
1566  */
1567 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1568                                    uint64_t value, unsigned count,
1569                                    uint32_t incr)
1570 {
1571         unsigned ndw = count * 2;
1572
1573         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1574                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1575         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1576         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1577         ib->ptr[ib->length_dw++] = ndw - 1;
1578         for (; ndw > 0; ndw -= 2) {
1579                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1580                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1581                 value += incr;
1582         }
1583 }
1584
1585 /**
1586  * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA
1587  *
1588  * @ib: indirect buffer to fill with commands
1589  * @pe: addr of the page entry
1590  * @addr: dst addr to write into pe
1591  * @count: number of page entries to update
1592  * @incr: increase next addr by incr bytes
1593  * @flags: access flags
1594  *
1595  * Update the page tables using sDMA (VEGA10).
1596  */
1597 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1598                                      uint64_t pe,
1599                                      uint64_t addr, unsigned count,
1600                                      uint32_t incr, uint64_t flags)
1601 {
1602         /* for physically contiguous pages (vram) */
1603         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1604         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1605         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1606         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1607         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1608         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1609         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1610         ib->ptr[ib->length_dw++] = incr; /* increment size */
1611         ib->ptr[ib->length_dw++] = 0;
1612         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1613 }
1614
1615 /**
1616  * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw
1617  *
1618  * @ring: amdgpu_ring structure holding ring information
1619  * @ib: indirect buffer to fill with padding
1620  */
1621 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1622 {
1623         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1624         u32 pad_count;
1625         int i;
1626
1627         pad_count = (-ib->length_dw) & 7;
1628         for (i = 0; i < pad_count; i++)
1629                 if (sdma && sdma->burst_nop && (i == 0))
1630                         ib->ptr[ib->length_dw++] =
1631                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1632                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1633                 else
1634                         ib->ptr[ib->length_dw++] =
1635                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1636 }
1637
1638
1639 /**
1640  * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline
1641  *
1642  * @ring: amdgpu_ring pointer
1643  *
1644  * Make sure all previous operations are completed (CIK).
1645  */
1646 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1647 {
1648         uint32_t seq = ring->fence_drv.sync_seq;
1649         uint64_t addr = ring->fence_drv.gpu_addr;
1650
1651         /* wait for idle */
1652         sdma_v4_0_wait_reg_mem(ring, 1, 0,
1653                                addr & 0xfffffffc,
1654                                upper_32_bits(addr) & 0xffffffff,
1655                                seq, 0xffffffff, 4);
1656 }
1657
1658
1659 /**
1660  * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA
1661  *
1662  * @ring: amdgpu_ring pointer
1663  * @vmid: vmid number to use
1664  * @pd_addr: address
1665  *
1666  * Update the page table base and flush the VM TLB
1667  * using sDMA (VEGA10).
1668  */
1669 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1670                                          unsigned vmid, uint64_t pd_addr)
1671 {
1672         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1673 }
1674
1675 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring,
1676                                      uint32_t reg, uint32_t val)
1677 {
1678         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1679                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1680         amdgpu_ring_write(ring, reg);
1681         amdgpu_ring_write(ring, val);
1682 }
1683
1684 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1685                                          uint32_t val, uint32_t mask)
1686 {
1687         sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
1688 }
1689
1690 static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev)
1691 {
1692         uint fw_version = adev->sdma.instance[0].fw_version;
1693
1694         switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
1695         case IP_VERSION(4, 0, 0):
1696                 return fw_version >= 430;
1697         case IP_VERSION(4, 0, 1):
1698                 /*return fw_version >= 31;*/
1699                 return false;
1700         case IP_VERSION(4, 2, 0):
1701                 return fw_version >= 123;
1702         default:
1703                 return false;
1704         }
1705 }
1706
1707 static int sdma_v4_0_early_init(void *handle)
1708 {
1709         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1710         int r;
1711
1712         r = sdma_v4_0_init_microcode(adev);
1713         if (r)
1714                 return r;
1715
1716         /* TODO: Page queue breaks driver reload under SRIOV */
1717         if ((amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 0, 0)) &&
1718             amdgpu_sriov_vf((adev)))
1719                 adev->sdma.has_page_queue = false;
1720         else if (sdma_v4_0_fw_support_paging_queue(adev))
1721                 adev->sdma.has_page_queue = true;
1722
1723         sdma_v4_0_set_ring_funcs(adev);
1724         sdma_v4_0_set_buffer_funcs(adev);
1725         sdma_v4_0_set_vm_pte_funcs(adev);
1726         sdma_v4_0_set_irq_funcs(adev);
1727         sdma_v4_0_set_ras_funcs(adev);
1728
1729         return 0;
1730 }
1731
1732 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
1733                 void *err_data,
1734                 struct amdgpu_iv_entry *entry);
1735
1736 static int sdma_v4_0_late_init(void *handle)
1737 {
1738         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1739
1740         sdma_v4_0_setup_ulv(adev);
1741
1742         if (!amdgpu_persistent_edc_harvesting_supported(adev))
1743                 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__SDMA);
1744
1745         return 0;
1746 }
1747
1748 static int sdma_v4_0_sw_init(void *handle)
1749 {
1750         struct amdgpu_ring *ring;
1751         int r, i;
1752         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1753
1754         /* SDMA trap event */
1755         for (i = 0; i < adev->sdma.num_instances; i++) {
1756                 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1757                                       SDMA0_4_0__SRCID__SDMA_TRAP,
1758                                       &adev->sdma.trap_irq);
1759                 if (r)
1760                         return r;
1761         }
1762
1763         /* SDMA SRAM ECC event */
1764         for (i = 0; i < adev->sdma.num_instances; i++) {
1765                 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1766                                       SDMA0_4_0__SRCID__SDMA_SRAM_ECC,
1767                                       &adev->sdma.ecc_irq);
1768                 if (r)
1769                         return r;
1770         }
1771
1772         /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/
1773         for (i = 0; i < adev->sdma.num_instances; i++) {
1774                 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1775                                       SDMA0_4_0__SRCID__SDMA_VM_HOLE,
1776                                       &adev->sdma.vm_hole_irq);
1777                 if (r)
1778                         return r;
1779
1780                 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1781                                       SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID,
1782                                       &adev->sdma.doorbell_invalid_irq);
1783                 if (r)
1784                         return r;
1785
1786                 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1787                                       SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT,
1788                                       &adev->sdma.pool_timeout_irq);
1789                 if (r)
1790                         return r;
1791
1792                 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1793                                       SDMA0_4_0__SRCID__SDMA_SRBMWRITE,
1794                                       &adev->sdma.srbm_write_irq);
1795                 if (r)
1796                         return r;
1797         }
1798
1799         for (i = 0; i < adev->sdma.num_instances; i++) {
1800                 ring = &adev->sdma.instance[i].ring;
1801                 ring->ring_obj = NULL;
1802                 ring->use_doorbell = true;
1803
1804                 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1805                                 ring->use_doorbell?"true":"false");
1806
1807                 /* doorbell size is 2 dwords, get DWORD offset */
1808                 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1809
1810                 /*
1811                  * On Arcturus, SDMA instance 5~7 has a different vmhub
1812                  * type(AMDGPU_MMHUB1).
1813                  */
1814                 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) ==
1815                             IP_VERSION(4, 2, 2) &&
1816                     i >= 5)
1817                         ring->vm_hub = AMDGPU_MMHUB1(0);
1818                 else
1819                         ring->vm_hub = AMDGPU_MMHUB0(0);
1820
1821                 sprintf(ring->name, "sdma%d", i);
1822                 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1823                                      AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1824                                      AMDGPU_RING_PRIO_DEFAULT, NULL);
1825                 if (r)
1826                         return r;
1827
1828                 if (adev->sdma.has_page_queue) {
1829                         ring = &adev->sdma.instance[i].page;
1830                         ring->ring_obj = NULL;
1831                         ring->use_doorbell = true;
1832
1833                         /* paging queue use same doorbell index/routing as gfx queue
1834                          * with 0x400 (4096 dwords) offset on second doorbell page
1835                          */
1836                         if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) >=
1837                                     IP_VERSION(4, 0, 0) &&
1838                             amdgpu_ip_version(adev, SDMA0_HWIP, 0) <
1839                                     IP_VERSION(4, 2, 0)) {
1840                                 ring->doorbell_index =
1841                                         adev->doorbell_index.sdma_engine[i] << 1;
1842                                 ring->doorbell_index += 0x400;
1843                         } else {
1844                                 /* From vega20, the sdma_doorbell_range in 1st
1845                                  * doorbell page is reserved for page queue.
1846                                  */
1847                                 ring->doorbell_index =
1848                                         (adev->doorbell_index.sdma_engine[i] + 1) << 1;
1849                         }
1850
1851                         if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) ==
1852                                     IP_VERSION(4, 2, 2) &&
1853                             i >= 5)
1854                                 ring->vm_hub = AMDGPU_MMHUB1(0);
1855                         else
1856                                 ring->vm_hub = AMDGPU_MMHUB0(0);
1857
1858                         sprintf(ring->name, "page%d", i);
1859                         r = amdgpu_ring_init(adev, ring, 1024,
1860                                              &adev->sdma.trap_irq,
1861                                              AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1862                                              AMDGPU_RING_PRIO_DEFAULT, NULL);
1863                         if (r)
1864                                 return r;
1865                 }
1866         }
1867
1868         if (amdgpu_sdma_ras_sw_init(adev)) {
1869                 dev_err(adev->dev, "Failed to initialize sdma ras block!\n");
1870                 return -EINVAL;
1871         }
1872
1873         return r;
1874 }
1875
1876 static int sdma_v4_0_sw_fini(void *handle)
1877 {
1878         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1879         int i;
1880
1881         for (i = 0; i < adev->sdma.num_instances; i++) {
1882                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1883                 if (adev->sdma.has_page_queue)
1884                         amdgpu_ring_fini(&adev->sdma.instance[i].page);
1885         }
1886
1887         if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 2, 2) ||
1888             amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 0))
1889                 amdgpu_sdma_destroy_inst_ctx(adev, true);
1890         else
1891                 amdgpu_sdma_destroy_inst_ctx(adev, false);
1892
1893         return 0;
1894 }
1895
1896 static int sdma_v4_0_hw_init(void *handle)
1897 {
1898         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1899
1900         if (adev->flags & AMD_IS_APU)
1901                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false);
1902
1903         if (!amdgpu_sriov_vf(adev))
1904                 sdma_v4_0_init_golden_registers(adev);
1905
1906         return sdma_v4_0_start(adev);
1907 }
1908
1909 static int sdma_v4_0_hw_fini(void *handle)
1910 {
1911         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1912         int i;
1913
1914         if (amdgpu_sriov_vf(adev))
1915                 return 0;
1916
1917         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
1918                 for (i = 0; i < adev->sdma.num_instances; i++) {
1919                         amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
1920                                        AMDGPU_SDMA_IRQ_INSTANCE0 + i);
1921                 }
1922         }
1923
1924         sdma_v4_0_ctx_switch_enable(adev, false);
1925         sdma_v4_0_enable(adev, false);
1926
1927         if (adev->flags & AMD_IS_APU)
1928                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true);
1929
1930         return 0;
1931 }
1932
1933 static int sdma_v4_0_suspend(void *handle)
1934 {
1935         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1936
1937         /* SMU saves SDMA state for us */
1938         if (adev->in_s0ix) {
1939                 sdma_v4_0_gfx_enable(adev, false);
1940                 return 0;
1941         }
1942
1943         return sdma_v4_0_hw_fini(adev);
1944 }
1945
1946 static int sdma_v4_0_resume(void *handle)
1947 {
1948         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1949
1950         /* SMU restores SDMA state for us */
1951         if (adev->in_s0ix) {
1952                 sdma_v4_0_enable(adev, true);
1953                 sdma_v4_0_gfx_enable(adev, true);
1954                 return 0;
1955         }
1956
1957         return sdma_v4_0_hw_init(adev);
1958 }
1959
1960 static bool sdma_v4_0_is_idle(void *handle)
1961 {
1962         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1963         u32 i;
1964
1965         for (i = 0; i < adev->sdma.num_instances; i++) {
1966                 u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG);
1967
1968                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1969                         return false;
1970         }
1971
1972         return true;
1973 }
1974
1975 static int sdma_v4_0_wait_for_idle(void *handle)
1976 {
1977         unsigned i, j;
1978         u32 sdma[AMDGPU_MAX_SDMA_INSTANCES];
1979         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1980
1981         for (i = 0; i < adev->usec_timeout; i++) {
1982                 for (j = 0; j < adev->sdma.num_instances; j++) {
1983                         sdma[j] = RREG32_SDMA(j, mmSDMA0_STATUS_REG);
1984                         if (!(sdma[j] & SDMA0_STATUS_REG__IDLE_MASK))
1985                                 break;
1986                 }
1987                 if (j == adev->sdma.num_instances)
1988                         return 0;
1989                 udelay(1);
1990         }
1991         return -ETIMEDOUT;
1992 }
1993
1994 static int sdma_v4_0_soft_reset(void *handle)
1995 {
1996         /* todo */
1997
1998         return 0;
1999 }
2000
2001 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev,
2002                                         struct amdgpu_irq_src *source,
2003                                         unsigned type,
2004                                         enum amdgpu_interrupt_state state)
2005 {
2006         u32 sdma_cntl;
2007
2008         sdma_cntl = RREG32_SDMA(type, mmSDMA0_CNTL);
2009         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
2010                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
2011         WREG32_SDMA(type, mmSDMA0_CNTL, sdma_cntl);
2012
2013         return 0;
2014 }
2015
2016 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
2017                                       struct amdgpu_irq_src *source,
2018                                       struct amdgpu_iv_entry *entry)
2019 {
2020         uint32_t instance;
2021
2022         DRM_DEBUG("IH: SDMA trap\n");
2023         instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2024         switch (entry->ring_id) {
2025         case 0:
2026                 amdgpu_fence_process(&adev->sdma.instance[instance].ring);
2027                 break;
2028         case 1:
2029                 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) ==
2030                     IP_VERSION(4, 2, 0))
2031                         amdgpu_fence_process(&adev->sdma.instance[instance].page);
2032                 break;
2033         case 2:
2034                 /* XXX compute */
2035                 break;
2036         case 3:
2037                 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) !=
2038                     IP_VERSION(4, 2, 0))
2039                         amdgpu_fence_process(&adev->sdma.instance[instance].page);
2040                 break;
2041         }
2042         return 0;
2043 }
2044
2045 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
2046                 void *err_data,
2047                 struct amdgpu_iv_entry *entry)
2048 {
2049         int instance;
2050
2051         /* When “Full RAS” is enabled, the per-IP interrupt sources should
2052          * be disabled and the driver should only look for the aggregated
2053          * interrupt via sync flood
2054          */
2055         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
2056                 goto out;
2057
2058         instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2059         if (instance < 0)
2060                 goto out;
2061
2062         amdgpu_sdma_process_ras_data_cb(adev, err_data, entry);
2063
2064 out:
2065         return AMDGPU_RAS_SUCCESS;
2066 }
2067
2068 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev,
2069                                               struct amdgpu_irq_src *source,
2070                                               struct amdgpu_iv_entry *entry)
2071 {
2072         int instance;
2073
2074         DRM_ERROR("Illegal instruction in SDMA command stream\n");
2075
2076         instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2077         if (instance < 0)
2078                 return 0;
2079
2080         switch (entry->ring_id) {
2081         case 0:
2082                 drm_sched_fault(&adev->sdma.instance[instance].ring.sched);
2083                 break;
2084         }
2085         return 0;
2086 }
2087
2088 static int sdma_v4_0_set_ecc_irq_state(struct amdgpu_device *adev,
2089                                         struct amdgpu_irq_src *source,
2090                                         unsigned type,
2091                                         enum amdgpu_interrupt_state state)
2092 {
2093         u32 sdma_edc_config;
2094
2095         sdma_edc_config = RREG32_SDMA(type, mmSDMA0_EDC_CONFIG);
2096         sdma_edc_config = REG_SET_FIELD(sdma_edc_config, SDMA0_EDC_CONFIG, ECC_INT_ENABLE,
2097                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
2098         WREG32_SDMA(type, mmSDMA0_EDC_CONFIG, sdma_edc_config);
2099
2100         return 0;
2101 }
2102
2103 static int sdma_v4_0_print_iv_entry(struct amdgpu_device *adev,
2104                                               struct amdgpu_iv_entry *entry)
2105 {
2106         int instance;
2107         struct amdgpu_task_info task_info;
2108         u64 addr;
2109
2110         instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2111         if (instance < 0 || instance >= adev->sdma.num_instances) {
2112                 dev_err(adev->dev, "sdma instance invalid %d\n", instance);
2113                 return -EINVAL;
2114         }
2115
2116         addr = (u64)entry->src_data[0] << 12;
2117         addr |= ((u64)entry->src_data[1] & 0xf) << 44;
2118
2119         memset(&task_info, 0, sizeof(struct amdgpu_task_info));
2120         amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
2121
2122         dev_dbg_ratelimited(adev->dev,
2123                    "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u "
2124                    "pasid:%u, for process %s pid %d thread %s pid %d\n",
2125                    instance, addr, entry->src_id, entry->ring_id, entry->vmid,
2126                    entry->pasid, task_info.process_name, task_info.tgid,
2127                    task_info.task_name, task_info.pid);
2128         return 0;
2129 }
2130
2131 static int sdma_v4_0_process_vm_hole_irq(struct amdgpu_device *adev,
2132                                               struct amdgpu_irq_src *source,
2133                                               struct amdgpu_iv_entry *entry)
2134 {
2135         dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n");
2136         sdma_v4_0_print_iv_entry(adev, entry);
2137         return 0;
2138 }
2139
2140 static int sdma_v4_0_process_doorbell_invalid_irq(struct amdgpu_device *adev,
2141                                               struct amdgpu_irq_src *source,
2142                                               struct amdgpu_iv_entry *entry)
2143 {
2144         dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n");
2145         sdma_v4_0_print_iv_entry(adev, entry);
2146         return 0;
2147 }
2148
2149 static int sdma_v4_0_process_pool_timeout_irq(struct amdgpu_device *adev,
2150                                               struct amdgpu_irq_src *source,
2151                                               struct amdgpu_iv_entry *entry)
2152 {
2153         dev_dbg_ratelimited(adev->dev,
2154                 "Polling register/memory timeout executing POLL_REG/MEM with finite timer\n");
2155         sdma_v4_0_print_iv_entry(adev, entry);
2156         return 0;
2157 }
2158
2159 static int sdma_v4_0_process_srbm_write_irq(struct amdgpu_device *adev,
2160                                               struct amdgpu_irq_src *source,
2161                                               struct amdgpu_iv_entry *entry)
2162 {
2163         dev_dbg_ratelimited(adev->dev,
2164                 "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n");
2165         sdma_v4_0_print_iv_entry(adev, entry);
2166         return 0;
2167 }
2168
2169 static void sdma_v4_0_update_medium_grain_clock_gating(
2170                 struct amdgpu_device *adev,
2171                 bool enable)
2172 {
2173         uint32_t data, def;
2174         int i;
2175
2176         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
2177                 for (i = 0; i < adev->sdma.num_instances; i++) {
2178                         def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);
2179                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
2180                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
2181                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
2182                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
2183                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
2184                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
2185                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
2186                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
2187                         if (def != data)
2188                                 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
2189                 }
2190         } else {
2191                 for (i = 0; i < adev->sdma.num_instances; i++) {
2192                         def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);
2193                         data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
2194                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
2195                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
2196                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
2197                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
2198                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
2199                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
2200                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
2201                         if (def != data)
2202                                 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
2203                 }
2204         }
2205 }
2206
2207
2208 static void sdma_v4_0_update_medium_grain_light_sleep(
2209                 struct amdgpu_device *adev,
2210                 bool enable)
2211 {
2212         uint32_t data, def;
2213         int i;
2214
2215         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
2216                 for (i = 0; i < adev->sdma.num_instances; i++) {
2217                         /* 1-not override: enable sdma mem light sleep */
2218                         def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);
2219                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
2220                         if (def != data)
2221                                 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);
2222                 }
2223         } else {
2224                 for (i = 0; i < adev->sdma.num_instances; i++) {
2225                 /* 0-override:disable sdma mem light sleep */
2226                         def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);
2227                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
2228                         if (def != data)
2229                                 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);
2230                 }
2231         }
2232 }
2233
2234 static int sdma_v4_0_set_clockgating_state(void *handle,
2235                                           enum amd_clockgating_state state)
2236 {
2237         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2238
2239         if (amdgpu_sriov_vf(adev))
2240                 return 0;
2241
2242         sdma_v4_0_update_medium_grain_clock_gating(adev,
2243                         state == AMD_CG_STATE_GATE);
2244         sdma_v4_0_update_medium_grain_light_sleep(adev,
2245                         state == AMD_CG_STATE_GATE);
2246         return 0;
2247 }
2248
2249 static int sdma_v4_0_set_powergating_state(void *handle,
2250                                           enum amd_powergating_state state)
2251 {
2252         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2253
2254         switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
2255         case IP_VERSION(4, 1, 0):
2256         case IP_VERSION(4, 1, 1):
2257         case IP_VERSION(4, 1, 2):
2258                 sdma_v4_1_update_power_gating(adev,
2259                                 state == AMD_PG_STATE_GATE);
2260                 break;
2261         default:
2262                 break;
2263         }
2264
2265         return 0;
2266 }
2267
2268 static void sdma_v4_0_get_clockgating_state(void *handle, u64 *flags)
2269 {
2270         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2271         int data;
2272
2273         if (amdgpu_sriov_vf(adev))
2274                 *flags = 0;
2275
2276         /* AMD_CG_SUPPORT_SDMA_MGCG */
2277         data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
2278         if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
2279                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
2280
2281         /* AMD_CG_SUPPORT_SDMA_LS */
2282         data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
2283         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
2284                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
2285 }
2286
2287 const struct amd_ip_funcs sdma_v4_0_ip_funcs = {
2288         .name = "sdma_v4_0",
2289         .early_init = sdma_v4_0_early_init,
2290         .late_init = sdma_v4_0_late_init,
2291         .sw_init = sdma_v4_0_sw_init,
2292         .sw_fini = sdma_v4_0_sw_fini,
2293         .hw_init = sdma_v4_0_hw_init,
2294         .hw_fini = sdma_v4_0_hw_fini,
2295         .suspend = sdma_v4_0_suspend,
2296         .resume = sdma_v4_0_resume,
2297         .is_idle = sdma_v4_0_is_idle,
2298         .wait_for_idle = sdma_v4_0_wait_for_idle,
2299         .soft_reset = sdma_v4_0_soft_reset,
2300         .set_clockgating_state = sdma_v4_0_set_clockgating_state,
2301         .set_powergating_state = sdma_v4_0_set_powergating_state,
2302         .get_clockgating_state = sdma_v4_0_get_clockgating_state,
2303 };
2304
2305 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
2306         .type = AMDGPU_RING_TYPE_SDMA,
2307         .align_mask = 0xff,
2308         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2309         .support_64bit_ptrs = true,
2310         .secure_submission_supported = true,
2311         .get_rptr = sdma_v4_0_ring_get_rptr,
2312         .get_wptr = sdma_v4_0_ring_get_wptr,
2313         .set_wptr = sdma_v4_0_ring_set_wptr,
2314         .emit_frame_size =
2315                 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2316                 3 + /* hdp invalidate */
2317                 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2318                 /* sdma_v4_0_ring_emit_vm_flush */
2319                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2320                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2321                 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2322         .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2323         .emit_ib = sdma_v4_0_ring_emit_ib,
2324         .emit_fence = sdma_v4_0_ring_emit_fence,
2325         .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2326         .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2327         .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2328         .test_ring = sdma_v4_0_ring_test_ring,
2329         .test_ib = sdma_v4_0_ring_test_ib,
2330         .insert_nop = sdma_v4_0_ring_insert_nop,
2331         .pad_ib = sdma_v4_0_ring_pad_ib,
2332         .emit_wreg = sdma_v4_0_ring_emit_wreg,
2333         .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2334         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2335 };
2336
2337 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = {
2338         .type = AMDGPU_RING_TYPE_SDMA,
2339         .align_mask = 0xff,
2340         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2341         .support_64bit_ptrs = true,
2342         .secure_submission_supported = true,
2343         .get_rptr = sdma_v4_0_ring_get_rptr,
2344         .get_wptr = sdma_v4_0_page_ring_get_wptr,
2345         .set_wptr = sdma_v4_0_page_ring_set_wptr,
2346         .emit_frame_size =
2347                 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2348                 3 + /* hdp invalidate */
2349                 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2350                 /* sdma_v4_0_ring_emit_vm_flush */
2351                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2352                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2353                 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2354         .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2355         .emit_ib = sdma_v4_0_ring_emit_ib,
2356         .emit_fence = sdma_v4_0_ring_emit_fence,
2357         .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2358         .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2359         .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2360         .test_ring = sdma_v4_0_ring_test_ring,
2361         .test_ib = sdma_v4_0_ring_test_ib,
2362         .insert_nop = sdma_v4_0_ring_insert_nop,
2363         .pad_ib = sdma_v4_0_ring_pad_ib,
2364         .emit_wreg = sdma_v4_0_ring_emit_wreg,
2365         .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2366         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2367 };
2368
2369 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
2370 {
2371         int i;
2372
2373         for (i = 0; i < adev->sdma.num_instances; i++) {
2374                 adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs;
2375                 adev->sdma.instance[i].ring.me = i;
2376                 if (adev->sdma.has_page_queue) {
2377                         adev->sdma.instance[i].page.funcs =
2378                                         &sdma_v4_0_page_ring_funcs;
2379                         adev->sdma.instance[i].page.me = i;
2380                 }
2381         }
2382 }
2383
2384 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = {
2385         .set = sdma_v4_0_set_trap_irq_state,
2386         .process = sdma_v4_0_process_trap_irq,
2387 };
2388
2389 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = {
2390         .process = sdma_v4_0_process_illegal_inst_irq,
2391 };
2392
2393 static const struct amdgpu_irq_src_funcs sdma_v4_0_ecc_irq_funcs = {
2394         .set = sdma_v4_0_set_ecc_irq_state,
2395         .process = amdgpu_sdma_process_ecc_irq,
2396 };
2397
2398 static const struct amdgpu_irq_src_funcs sdma_v4_0_vm_hole_irq_funcs = {
2399         .process = sdma_v4_0_process_vm_hole_irq,
2400 };
2401
2402 static const struct amdgpu_irq_src_funcs sdma_v4_0_doorbell_invalid_irq_funcs = {
2403         .process = sdma_v4_0_process_doorbell_invalid_irq,
2404 };
2405
2406 static const struct amdgpu_irq_src_funcs sdma_v4_0_pool_timeout_irq_funcs = {
2407         .process = sdma_v4_0_process_pool_timeout_irq,
2408 };
2409
2410 static const struct amdgpu_irq_src_funcs sdma_v4_0_srbm_write_irq_funcs = {
2411         .process = sdma_v4_0_process_srbm_write_irq,
2412 };
2413
2414 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev)
2415 {
2416         adev->sdma.trap_irq.num_types = adev->sdma.num_instances;
2417         adev->sdma.ecc_irq.num_types = adev->sdma.num_instances;
2418         /*For Arcturus and Aldebaran, add another 4 irq handler*/
2419         switch (adev->sdma.num_instances) {
2420         case 5:
2421         case 8:
2422                 adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances;
2423                 adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances;
2424                 adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances;
2425                 adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances;
2426                 break;
2427         default:
2428                 break;
2429         }
2430         adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs;
2431         adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs;
2432         adev->sdma.ecc_irq.funcs = &sdma_v4_0_ecc_irq_funcs;
2433         adev->sdma.vm_hole_irq.funcs = &sdma_v4_0_vm_hole_irq_funcs;
2434         adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_0_doorbell_invalid_irq_funcs;
2435         adev->sdma.pool_timeout_irq.funcs = &sdma_v4_0_pool_timeout_irq_funcs;
2436         adev->sdma.srbm_write_irq.funcs = &sdma_v4_0_srbm_write_irq_funcs;
2437 }
2438
2439 /**
2440  * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine
2441  *
2442  * @ib: indirect buffer to copy to
2443  * @src_offset: src GPU address
2444  * @dst_offset: dst GPU address
2445  * @byte_count: number of bytes to xfer
2446  * @tmz: if a secure copy should be used
2447  *
2448  * Copy GPU buffers using the DMA engine (VEGA10/12).
2449  * Used by the amdgpu ttm implementation to move pages if
2450  * registered as the asic copy callback.
2451  */
2452 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib,
2453                                        uint64_t src_offset,
2454                                        uint64_t dst_offset,
2455                                        uint32_t byte_count,
2456                                        bool tmz)
2457 {
2458         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
2459                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
2460                 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
2461         ib->ptr[ib->length_dw++] = byte_count - 1;
2462         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
2463         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
2464         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
2465         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2466         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2467 }
2468
2469 /**
2470  * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine
2471  *
2472  * @ib: indirect buffer to copy to
2473  * @src_data: value to write to buffer
2474  * @dst_offset: dst GPU address
2475  * @byte_count: number of bytes to xfer
2476  *
2477  * Fill GPU buffers using the DMA engine (VEGA10/12).
2478  */
2479 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib,
2480                                        uint32_t src_data,
2481                                        uint64_t dst_offset,
2482                                        uint32_t byte_count)
2483 {
2484         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
2485         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2486         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2487         ib->ptr[ib->length_dw++] = src_data;
2488         ib->ptr[ib->length_dw++] = byte_count - 1;
2489 }
2490
2491 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = {
2492         .copy_max_bytes = 0x400000,
2493         .copy_num_dw = 7,
2494         .emit_copy_buffer = sdma_v4_0_emit_copy_buffer,
2495
2496         .fill_max_bytes = 0x400000,
2497         .fill_num_dw = 5,
2498         .emit_fill_buffer = sdma_v4_0_emit_fill_buffer,
2499 };
2500
2501 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
2502 {
2503         adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
2504         if (adev->sdma.has_page_queue)
2505                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
2506         else
2507                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
2508 }
2509
2510 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = {
2511         .copy_pte_num_dw = 7,
2512         .copy_pte = sdma_v4_0_vm_copy_pte,
2513
2514         .write_pte = sdma_v4_0_vm_write_pte,
2515         .set_pte_pde = sdma_v4_0_vm_set_pte_pde,
2516 };
2517
2518 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev)
2519 {
2520         struct drm_gpu_scheduler *sched;
2521         unsigned i;
2522
2523         adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
2524         for (i = 0; i < adev->sdma.num_instances; i++) {
2525                 if (adev->sdma.has_page_queue)
2526                         sched = &adev->sdma.instance[i].page.sched;
2527                 else
2528                         sched = &adev->sdma.instance[i].ring.sched;
2529                 adev->vm_manager.vm_pte_scheds[i] = sched;
2530         }
2531         adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
2532 }
2533
2534 static void sdma_v4_0_get_ras_error_count(uint32_t value,
2535                                         uint32_t instance,
2536                                         uint32_t *sec_count)
2537 {
2538         uint32_t i;
2539         uint32_t sec_cnt;
2540
2541         /* double bits error (multiple bits) error detection is not supported */
2542         for (i = 0; i < ARRAY_SIZE(sdma_v4_0_ras_fields); i++) {
2543                 /* the SDMA_EDC_COUNTER register in each sdma instance
2544                  * shares the same sed shift_mask
2545                  * */
2546                 sec_cnt = (value &
2547                         sdma_v4_0_ras_fields[i].sec_count_mask) >>
2548                         sdma_v4_0_ras_fields[i].sec_count_shift;
2549                 if (sec_cnt) {
2550                         DRM_INFO("Detected %s in SDMA%d, SED %d\n",
2551                                 sdma_v4_0_ras_fields[i].name,
2552                                 instance, sec_cnt);
2553                         *sec_count += sec_cnt;
2554                 }
2555         }
2556 }
2557
2558 static int sdma_v4_0_query_ras_error_count_by_instance(struct amdgpu_device *adev,
2559                         uint32_t instance, void *ras_error_status)
2560 {
2561         struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
2562         uint32_t sec_count = 0;
2563         uint32_t reg_value = 0;
2564
2565         reg_value = RREG32_SDMA(instance, mmSDMA0_EDC_COUNTER);
2566         /* double bit error is not supported */
2567         if (reg_value)
2568                 sdma_v4_0_get_ras_error_count(reg_value,
2569                                 instance, &sec_count);
2570         /* err_data->ce_count should be initialized to 0
2571          * before calling into this function */
2572         err_data->ce_count += sec_count;
2573         /* double bit error is not supported
2574          * set ue count to 0 */
2575         err_data->ue_count = 0;
2576
2577         return 0;
2578 };
2579
2580 static void sdma_v4_0_query_ras_error_count(struct amdgpu_device *adev,  void *ras_error_status)
2581 {
2582         int i = 0;
2583
2584         for (i = 0; i < adev->sdma.num_instances; i++) {
2585                 if (sdma_v4_0_query_ras_error_count_by_instance(adev, i, ras_error_status)) {
2586                         dev_err(adev->dev, "Query ras error count failed in SDMA%d\n", i);
2587                         return;
2588                 }
2589         }
2590 }
2591
2592 static void sdma_v4_0_reset_ras_error_count(struct amdgpu_device *adev)
2593 {
2594         int i;
2595
2596         /* read back edc counter registers to clear the counters */
2597         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2598                 for (i = 0; i < adev->sdma.num_instances; i++)
2599                         RREG32_SDMA(i, mmSDMA0_EDC_COUNTER);
2600         }
2601 }
2602
2603 const struct amdgpu_ras_block_hw_ops sdma_v4_0_ras_hw_ops = {
2604         .query_ras_error_count = sdma_v4_0_query_ras_error_count,
2605         .reset_ras_error_count = sdma_v4_0_reset_ras_error_count,
2606 };
2607
2608 static struct amdgpu_sdma_ras sdma_v4_0_ras = {
2609         .ras_block = {
2610                 .hw_ops = &sdma_v4_0_ras_hw_ops,
2611                 .ras_cb = sdma_v4_0_process_ras_data_cb,
2612         },
2613 };
2614
2615 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev)
2616 {
2617         switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
2618         case IP_VERSION(4, 2, 0):
2619         case IP_VERSION(4, 2, 2):
2620                 adev->sdma.ras = &sdma_v4_0_ras;
2621                 break;
2622         case IP_VERSION(4, 4, 0):
2623                 adev->sdma.ras = &sdma_v4_4_ras;
2624                 break;
2625         default:
2626                 break;
2627         }
2628 }
2629
2630 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = {
2631         .type = AMD_IP_BLOCK_TYPE_SDMA,
2632         .major = 4,
2633         .minor = 0,
2634         .rev = 0,
2635         .funcs = &sdma_v4_0_ip_funcs,
2636 };