drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29
  30 #include "vega10/soc15ip.h"
  31 #include "vega10/SDMA0/sdma0_4_0_offset.h"
  32 #include "vega10/SDMA0/sdma0_4_0_sh_mask.h"
  33 #include "vega10/SDMA1/sdma1_4_0_offset.h"
  34 #include "vega10/SDMA1/sdma1_4_0_sh_mask.h"
  35 #include "vega10/MMHUB/mmhub_1_0_offset.h"
  36 #include "vega10/MMHUB/mmhub_1_0_sh_mask.h"
  37 #include "vega10/HDP/hdp_4_0_offset.h"
  38 #include "raven1/SDMA0/sdma0_4_1_default.h"
  39
  40 #include "soc15_common.h"
  41 #include "soc15.h"
  42 #include "vega10_sdma_pkt_open.h"
  43
  44 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin");
  45 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin");
  46 MODULE_FIRMWARE("amdgpu/raven_sdma.bin");
  47
  48 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK  0x000000F8L
  49 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
  50
  51 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev);
  52 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev);
  53 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  54 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev);
  55
  56 static const u32 golden_settings_sdma_4[] = {
  57         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 0x02831f07,
  58         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), 0xff000ff0, 0x3f000100,
  59         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_IB_CNTL), 0x800f0100, 0x00000100,
  60         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000,
  61         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL), 0x800f0100, 0x00000100,
  62         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
  63         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), 0x003ff006, 0x0003c000,
  64         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL), 0x800f0100, 0x00000100,
  65         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
  66         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL), 0x800f0100, 0x00000100,
  67         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
  68         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UTCL1_PAGE), 0x000003ff, 0x000003c0,
  69         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CHICKEN_BITS), 0xfe931f07, 0x02831f07,
  70         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), 0xffffffff, 0x3f000100,
  71         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_IB_CNTL), 0x800f0100, 0x00000100,
  72         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
  73         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL), 0x800f0100, 0x00000100,
  74         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
  75         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), 0x003ff000, 0x0003c000,
  76         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL), 0x800f0100, 0x00000100,
  77         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
  78         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL), 0x800f0100, 0x00000100,
  79         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
  80         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_UTCL1_PAGE), 0x000003ff, 0x000003c0
  81 };
  82
  83 static const u32 golden_settings_sdma_vg10[] = {
  84         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG), 0x0018773f, 0x00104002,
  85         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00104002,
  86         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG), 0x0018773f, 0x00104002,
  87         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00104002
  88 };
  89
  90 static const u32 golden_settings_sdma_4_1[] =
  91 {
  92         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 0x02831f07,
  93         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), 0xffffffff, 0x3f000100,
  94         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_IB_CNTL), 0x800f0111, 0x00000100,
  95         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000,
  96         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), 0xfc3fffff, 0x40000051,
  97         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL), 0x800f0111, 0x00000100,
  98         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000,
  99         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL), 0x800f0111, 0x00000100,
 100         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000,
 101         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UTCL1_PAGE), 0x000003ff, 0x000003c0
 102 };
 103
 104 static const u32 golden_settings_sdma_rv1[] =
 105 {
 106         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG), 0x0018773f, 0x00000002,
 107         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00000002
 108 };
 109
 110 static u32 sdma_v4_0_get_reg_offset(u32 instance, u32 internal_offset)
 111 {
 112         u32 base = 0;
 113
 114         switch (instance) {
 115         case 0:
 116                 base = SDMA0_BASE.instance[0].segment[0];
 117                 break;
 118         case 1:
 119                 base = SDMA1_BASE.instance[0].segment[0];
 120                 break;
 121         default:
 122                 BUG();
 123                 break;
 124         }
 125
 126         return base + internal_offset;
 127 }
 128
 129 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
 130 {
 131         switch (adev->asic_type) {
 132         case CHIP_VEGA10:
 133                 amdgpu_program_register_sequence(adev,
 134                                                  golden_settings_sdma_4,
 135                                                  (const u32)ARRAY_SIZE(golden_settings_sdma_4));
 136                 amdgpu_program_register_sequence(adev,
 137                                                  golden_settings_sdma_vg10,
 138                                                  (const u32)ARRAY_SIZE(golden_settings_sdma_vg10));
 139                 break;
 140         case CHIP_RAVEN:
 141                 amdgpu_program_register_sequence(adev,
 142                                                  golden_settings_sdma_4_1,
 143                                                  (const u32)ARRAY_SIZE(golden_settings_sdma_4_1));
 144                 amdgpu_program_register_sequence(adev,
 145                                                  golden_settings_sdma_rv1,
 146                                                  (const u32)ARRAY_SIZE(golden_settings_sdma_rv1));
 147                 break;
 148         default:
 149                 break;
 150         }
 151 }
 152
 153 /**
 154  * sdma_v4_0_init_microcode - load ucode images from disk
 155  *
 156  * @adev: amdgpu_device pointer
 157  *
 158  * Use the firmware interface to load the ucode images into
 159  * the driver (not loaded into hw).
 160  * Returns 0 on success, error on failure.
 161  */
 162
 163 // emulation only, won't work on real chip
 164 // vega10 real chip need to use PSP to load firmware
 165 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
 166 {
 167         const char *chip_name;
 168         char fw_name[30];
 169         int err = 0, i;
 170         struct amdgpu_firmware_info *info = NULL;
 171         const struct common_firmware_header *header = NULL;
 172         const struct sdma_firmware_header_v1_0 *hdr;
 173
 174         DRM_DEBUG("\n");
 175
 176         switch (adev->asic_type) {
 177         case CHIP_VEGA10:
 178                 chip_name = "vega10";
 179                 break;
 180         case CHIP_RAVEN:
 181                 chip_name = "raven";
 182                 break;
 183         default:
 184                 BUG();
 185         }
 186
 187         for (i = 0; i < adev->sdma.num_instances; i++) {
 188                 if (i == 0)
 189                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 190                 else
 191                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 192                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 193                 if (err)
 194                         goto out;
 195                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 196                 if (err)
 197                         goto out;
 198                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 199                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 200                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 201                 if (adev->sdma.instance[i].feature_version >= 20)
 202                         adev->sdma.instance[i].burst_nop = true;
 203                 DRM_DEBUG("psp_load == '%s'\n",
 204                                 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
 205
 206                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 207                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 208                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 209                         info->fw = adev->sdma.instance[i].fw;
 210                         header = (const struct common_firmware_header *)info->fw->data;
 211                         adev->firmware.fw_size +=
 212                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 213                 }
 214         }
 215 out:
 216         if (err) {
 217                 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name);
 218                 for (i = 0; i < adev->sdma.num_instances; i++) {
 219                         release_firmware(adev->sdma.instance[i].fw);
 220                         adev->sdma.instance[i].fw = NULL;
 221                 }
 222         }
 223         return err;
 224 }
 225
 226 /**
 227  * sdma_v4_0_ring_get_rptr - get the current read pointer
 228  *
 229  * @ring: amdgpu ring pointer
 230  *
 231  * Get the current rptr from the hardware (VEGA10+).
 232  */
 233 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring)
 234 {
 235         u64 *rptr;
 236
 237         /* XXX check if swapping is necessary on BE */
 238         rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
 239
 240         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 241         return ((*rptr) >> 2);
 242 }
 243
 244 /**
 245  * sdma_v4_0_ring_get_wptr - get the current write pointer
 246  *
 247  * @ring: amdgpu ring pointer
 248  *
 249  * Get the current wptr from the hardware (VEGA10+).
 250  */
 251 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
 252 {
 253         struct amdgpu_device *adev = ring->adev;
 254         u64 *wptr = NULL;
 255         uint64_t local_wptr = 0;
 256
 257         if (ring->use_doorbell) {
 258                 /* XXX check if swapping is necessary on BE */
 259                 wptr = ((u64 *)&adev->wb.wb[ring->wptr_offs]);
 260                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", *wptr);
 261                 *wptr = (*wptr) >> 2;
 262                 DRM_DEBUG("wptr/doorbell after shift == 0x%016llx\n", *wptr);
 263         } else {
 264                 u32 lowbit, highbit;
 265                 int me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
 266
 267                 wptr = &local_wptr;
 268                 lowbit = RREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR)) >> 2;
 269                 highbit = RREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
 270
 271                 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",
 272                                 me, highbit, lowbit);
 273                 *wptr = highbit;
 274                 *wptr = (*wptr) << 32;
 275                 *wptr |= lowbit;
 276         }
 277
 278         return *wptr;
 279 }
 280
 281 /**
 282  * sdma_v4_0_ring_set_wptr - commit the write pointer
 283  *
 284  * @ring: amdgpu ring pointer
 285  *
 286  * Write the wptr back to the hardware (VEGA10+).
 287  */
 288 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
 289 {
 290         int i;
 291         u32 offset;
 292         struct amdgpu_device *adev = ring->adev;
 293
 294         DRM_DEBUG("Setting write pointer\n");
 295         if (ring->use_doorbell) {
 296                 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
 297
 298                 DRM_DEBUG("Using doorbell -- "
 299                                 "wptr_offs == 0x%08x "
 300                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 301                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 302                                 ring->wptr_offs,
 303                                 lower_32_bits(ring->wptr << 2),
 304                                 upper_32_bits(ring->wptr << 2));
 305                 /* XXX check if swapping is necessary on BE */
 306                 WRITE_ONCE(*wb, (ring->wptr << 2));
 307                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 308                                 ring->doorbell_index, ring->wptr << 2);
 309
 310                 if (amdgpu_sriov_vf(adev)) {
 311                         for (i = 0; i < adev->sdma.num_instances; i++) {
 312                                 if (&adev->sdma.instance[i].ring == ring) {
 313                                         offset = adev->sdma.instance[i].poll_mem_offs;
 314                                         atomic64_set((atomic64_t *)&adev->wb.wb[offset],
 315                                                      (ring->wptr << 2));
 316                                         nbio_v6_1_hdp_flush(adev);
 317                                 }
 318                         }
 319                 }
 320                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 321         } else {
 322                 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 323
 324                 DRM_DEBUG("Not using doorbell -- "
 325                                 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 326                                 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 327                                 me,
 328                                 lower_32_bits(ring->wptr << 2),
 329                                 me,
 330                                 upper_32_bits(ring->wptr << 2));
 331                 WREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
 332                 WREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
 333         }
 334 }
 335
 336 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 337 {
 338         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 339         int i;
 340
 341         for (i = 0; i < count; i++)
 342                 if (sdma && sdma->burst_nop && (i == 0))
 343                         amdgpu_ring_write(ring, ring->funcs->nop |
 344                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 345                 else
 346                         amdgpu_ring_write(ring, ring->funcs->nop);
 347 }
 348
 349 /**
 350  * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine
 351  *
 352  * @ring: amdgpu ring pointer
 353  * @ib: IB object to schedule
 354  *
 355  * Schedule an IB in the DMA ring (VEGA10).
 356  */
 357 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
 358                                         struct amdgpu_ib *ib,
 359                                         unsigned vm_id, bool ctx_switch)
 360 {
 361         u32 vmid = vm_id & 0xf;
 362
 363         /* IB packet must end on a 8 DW boundary */
 364         sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
 365
 366         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 367                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
 368         /* base must be 32 byte aligned */
 369         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 370         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 371         amdgpu_ring_write(ring, ib->length_dw);
 372         amdgpu_ring_write(ring, 0);
 373         amdgpu_ring_write(ring, 0);
 374
 375 }
 376
 377 /**
 378  * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 379  *
 380  * @ring: amdgpu ring pointer
 381  *
 382  * Emit an hdp flush packet on the requested DMA ring.
 383  */
 384 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 385 {
 386         u32 ref_and_mask = 0;
 387         struct nbio_hdp_flush_reg *nbio_hf_reg;
 388
 389         if (ring->adev->flags & AMD_IS_APU)
 390                 nbio_hf_reg = &nbio_v7_0_hdp_flush_reg;
 391         else
 392                 nbio_hf_reg = &nbio_v6_1_hdp_flush_reg;
 393
 394         if (ring == &ring->adev->sdma.instance[0].ring)
 395                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
 396         else
 397                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
 398
 399         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 400                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 401                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 402         amdgpu_ring_write(ring, nbio_hf_reg->hdp_flush_done_offset << 2);
 403         amdgpu_ring_write(ring, nbio_hf_reg->hdp_flush_req_offset << 2);
 404         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 405         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 406         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 407                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 408 }
 409
 410 static void sdma_v4_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
 411 {
 412         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 413                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 414         amdgpu_ring_write(ring, SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0));
 415         amdgpu_ring_write(ring, 1);
 416 }
 417
 418 /**
 419  * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring
 420  *
 421  * @ring: amdgpu ring pointer
 422  * @fence: amdgpu fence object
 423  *
 424  * Add a DMA fence packet to the ring to write
 425  * the fence seq number and DMA trap packet to generate
 426  * an interrupt if needed (VEGA10).
 427  */
 428 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 429                                       unsigned flags)
 430 {
 431         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 432         /* write the fence */
 433         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 434         /* zero in first two bits */
 435         BUG_ON(addr & 0x3);
 436         amdgpu_ring_write(ring, lower_32_bits(addr));
 437         amdgpu_ring_write(ring, upper_32_bits(addr));
 438         amdgpu_ring_write(ring, lower_32_bits(seq));
 439
 440         /* optionally write high bits as well */
 441         if (write64bit) {
 442                 addr += 4;
 443                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 444                 /* zero in first two bits */
 445                 BUG_ON(addr & 0x3);
 446                 amdgpu_ring_write(ring, lower_32_bits(addr));
 447                 amdgpu_ring_write(ring, upper_32_bits(addr));
 448                 amdgpu_ring_write(ring, upper_32_bits(seq));
 449         }
 450
 451         /* generate an interrupt */
 452         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 453         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 454 }
 455
 456
 457 /**
 458  * sdma_v4_0_gfx_stop - stop the gfx async dma engines
 459  *
 460  * @adev: amdgpu_device pointer
 461  *
 462  * Stop the gfx async dma ring buffers (VEGA10).
 463  */
 464 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev)
 465 {
 466         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 467         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 468         u32 rb_cntl, ib_cntl;
 469         int i;
 470
 471         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 472             (adev->mman.buffer_funcs_ring == sdma1))
 473                 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 474
 475         for (i = 0; i < adev->sdma.num_instances; i++) {
 476                 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL));
 477                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 478                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 479                 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL));
 480                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 481                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 482         }
 483
 484         sdma0->ready = false;
 485         sdma1->ready = false;
 486 }
 487
 488 /**
 489  * sdma_v4_0_rlc_stop - stop the compute async dma engines
 490  *
 491  * @adev: amdgpu_device pointer
 492  *
 493  * Stop the compute async dma queues (VEGA10).
 494  */
 495 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev)
 496 {
 497         /* XXX todo */
 498 }
 499
 500 /**
 501  * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
 502  *
 503  * @adev: amdgpu_device pointer
 504  * @enable: enable/disable the DMA MEs context switch.
 505  *
 506  * Halt or unhalt the async dma engines context switch (VEGA10).
 507  */
 508 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 509 {
 510         u32 f32_cntl, phase_quantum = 0;
 511         int i;
 512
 513         if (amdgpu_sdma_phase_quantum) {
 514                 unsigned value = amdgpu_sdma_phase_quantum;
 515                 unsigned unit = 0;
 516
 517                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 518                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 519                         value = (value + 1) >> 1;
 520                         unit++;
 521                 }
 522                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 523                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 524                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 525                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 526                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 527                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 528                         WARN_ONCE(1,
 529                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 530                                   value << unit);
 531                 }
 532                 phase_quantum =
 533                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 534                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 535         }
 536
 537         for (i = 0; i < adev->sdma.num_instances; i++) {
 538                 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL));
 539                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 540                                 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 541                 if (enable && amdgpu_sdma_phase_quantum) {
 542                         WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_PHASE0_QUANTUM),
 543                                phase_quantum);
 544                         WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_PHASE1_QUANTUM),
 545                                phase_quantum);
 546                         WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_PHASE2_QUANTUM),
 547                                phase_quantum);
 548                 }
 549                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL), f32_cntl);
 550         }
 551
 552 }
 553
 554 /**
 555  * sdma_v4_0_enable - stop the async dma engines
 556  *
 557  * @adev: amdgpu_device pointer
 558  * @enable: enable/disable the DMA MEs.
 559  *
 560  * Halt or unhalt the async dma engines (VEGA10).
 561  */
 562 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable)
 563 {
 564         u32 f32_cntl;
 565         int i;
 566
 567         if (enable == false) {
 568                 sdma_v4_0_gfx_stop(adev);
 569                 sdma_v4_0_rlc_stop(adev);
 570         }
 571
 572         for (i = 0; i < adev->sdma.num_instances; i++) {
 573                 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL));
 574                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 575                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL), f32_cntl);
 576         }
 577 }
 578
 579 /**
 580  * sdma_v4_0_gfx_resume - setup and start the async dma engines
 581  *
 582  * @adev: amdgpu_device pointer
 583  *
 584  * Set up the gfx DMA ring buffers and enable them (VEGA10).
 585  * Returns 0 for success, error for failure.
 586  */
 587 static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
 588 {
 589         struct amdgpu_ring *ring;
 590         u32 rb_cntl, ib_cntl, wptr_poll_addr_lo, wptr_poll_addr_hi, wptr_poll_cntl;
 591         u32 rb_bufsz;
 592         u32 wb_offset, poll_offset;
 593         u32 doorbell;
 594         u32 doorbell_offset;
 595         u32 temp;
 596         int i, r;
 597
 598         for (i = 0; i < adev->sdma.num_instances; i++) {
 599                 ring = &adev->sdma.instance[i].ring;
 600                 wb_offset = (ring->rptr_offs * 4);
 601
 602                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 603
 604                 /* Set ring buffer size in dwords */
 605                 rb_bufsz = order_base_2(ring->ring_size / 4);
 606                 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL));
 607                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 608 #ifdef __BIG_ENDIAN
 609                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 610                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 611                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 612 #endif
 613                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 614
 615                 /* Initialize the ring buffer's read and write pointers */
 616                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR), 0);
 617                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR_HI), 0);
 618                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR), 0);
 619                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 620
 621                 /* set the wb address whether it's enabled or not */
 622                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
 623                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 624                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
 625                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 626
 627                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 628
 629                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
 630                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
 631
 632                 ring->wptr = 0;
 633
 634                 /* before programing wptr to a less value, need set minor_ptr_update first */
 635                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
 636
 637                 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 638                         WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
 639                         WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
 640                 }
 641
 642                 doorbell = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL));
 643                 doorbell_offset = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL_OFFSET));
 644
 645                 if (ring->use_doorbell) {
 646                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 647                         doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
 648                                         OFFSET, ring->doorbell_index);
 649                 } else {
 650                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 651                 }
 652                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL), doorbell);
 653                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
 654                 if (adev->flags & AMD_IS_APU)
 655                         nbio_v7_0_sdma_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index);
 656                 else
 657                         nbio_v6_1_sdma_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index);
 658
 659                 if (amdgpu_sriov_vf(adev))
 660                         sdma_v4_0_ring_set_wptr(ring);
 661
 662                 /* set minor_ptr_update to 0 after wptr programed */
 663                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
 664
 665                 /* set utc l1 enable flag always to 1 */
 666                 temp = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL));
 667                 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
 668                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL), temp);
 669
 670                 if (!amdgpu_sriov_vf(adev)) {
 671                         /* unhalt engine */
 672                         temp = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL));
 673                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 674                         WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL), temp);
 675                 }
 676
 677                 /* enable DMA RB */
 678                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 679                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 680
 681                 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL));
 682                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 683 #ifdef __BIG_ENDIAN
 684                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 685 #endif
 686                 /* enable DMA IBs */
 687                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 688
 689                 ring->ready = true;
 690
 691                 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
 692                         sdma_v4_0_ctx_switch_enable(adev, true);
 693                         sdma_v4_0_enable(adev, true);
 694                 }
 695
 696                 r = amdgpu_ring_test_ring(ring);
 697                 if (r) {
 698                         ring->ready = false;
 699                         return r;
 700                 }
 701
 702                 if (adev->mman.buffer_funcs_ring == ring)
 703                         amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
 704
 705                 if (amdgpu_sriov_vf(adev)) {
 706                         poll_offset = adev->sdma.instance[i].poll_mem_offs * 4;
 707
 708                         wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 709                         wptr_poll_addr_lo = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO));
 710                         wptr_poll_addr_lo = REG_SET_FIELD(wptr_poll_addr_lo, SDMA0_GFX_RB_WPTR_POLL_ADDR_LO, ADDR,
 711                                                                 lower_32_bits(adev->wb.gpu_addr + poll_offset) >> 2);
 712                         wptr_poll_addr_hi = upper_32_bits(adev->wb.gpu_addr + poll_offset);
 713                         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1);
 714
 715                         WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), wptr_poll_addr_lo);
 716                         WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), wptr_poll_addr_hi);
 717                         WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl);
 718                 }
 719         }
 720
 721         return 0;
 722 }
 723
 724 static void
 725 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable)
 726 {
 727         uint32_t def, data;
 728
 729         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) {
 730                 /* disable idle interrupt */
 731                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
 732                 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
 733
 734                 if (data != def)
 735                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
 736         } else {
 737                 /* disable idle interrupt */
 738                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
 739                 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
 740                 if (data != def)
 741                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
 742         }
 743 }
 744
 745 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev)
 746 {
 747         uint32_t def, data;
 748
 749         /* Enable HW based PG. */
 750         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
 751         data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK;
 752         if (data != def)
 753                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
 754
 755         /* enable interrupt */
 756         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
 757         data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
 758         if (data != def)
 759                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
 760
 761         /* Configure hold time to filter in-valid power on/off request. Use default right now */
 762         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
 763         data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK;
 764         data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK);
 765         /* Configure switch time for hysteresis purpose. Use default right now */
 766         data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK;
 767         data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK);
 768         if(data != def)
 769                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
 770 }
 771
 772 static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
 773 {
 774         if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA))
 775                 return;
 776
 777         switch (adev->asic_type) {
 778         case CHIP_RAVEN:
 779                 sdma_v4_1_init_power_gating(adev);
 780                 sdma_v4_1_update_power_gating(adev, true);
 781                 break;
 782         default:
 783                 break;
 784         }
 785 }
 786
 787 /**
 788  * sdma_v4_0_rlc_resume - setup and start the async dma engines
 789  *
 790  * @adev: amdgpu_device pointer
 791  *
 792  * Set up the compute DMA queues and enable them (VEGA10).
 793  * Returns 0 for success, error for failure.
 794  */
 795 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev)
 796 {
 797         sdma_v4_0_init_pg(adev);
 798
 799         return 0;
 800 }
 801
 802 /**
 803  * sdma_v4_0_load_microcode - load the sDMA ME ucode
 804  *
 805  * @adev: amdgpu_device pointer
 806  *
 807  * Loads the sDMA0/1 ucode.
 808  * Returns 0 for success, -EINVAL if the ucode is not available.
 809  */
 810 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev)
 811 {
 812         const struct sdma_firmware_header_v1_0 *hdr;
 813         const __le32 *fw_data;
 814         u32 fw_size;
 815         u32 digest_size = 0;
 816         int i, j;
 817
 818         /* halt the MEs */
 819         sdma_v4_0_enable(adev, false);
 820
 821         for (i = 0; i < adev->sdma.num_instances; i++) {
 822                 uint16_t version_major;
 823                 uint16_t version_minor;
 824                 if (!adev->sdma.instance[i].fw)
 825                         return -EINVAL;
 826
 827                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 828                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 829                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 830
 831                 version_major = le16_to_cpu(hdr->header.header_version_major);
 832                 version_minor = le16_to_cpu(hdr->header.header_version_minor);
 833
 834                 if (version_major == 1 && version_minor >= 1) {
 835                         const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr = (const struct sdma_firmware_header_v1_1 *) hdr;
 836                         digest_size = le32_to_cpu(sdma_v1_1_hdr->digest_size);
 837                 }
 838
 839                 fw_size -= digest_size;
 840
 841                 fw_data = (const __le32 *)
 842                         (adev->sdma.instance[i].fw->data +
 843                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 844
 845                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_ADDR), 0);
 846
 847
 848                 for (j = 0; j < fw_size; j++)
 849                         WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 850
 851                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
 852         }
 853
 854         return 0;
 855 }
 856
 857 /**
 858  * sdma_v4_0_start - setup and start the async dma engines
 859  *
 860  * @adev: amdgpu_device pointer
 861  *
 862  * Set up the DMA engines and enable them (VEGA10).
 863  * Returns 0 for success, error for failure.
 864  */
 865 static int sdma_v4_0_start(struct amdgpu_device *adev)
 866 {
 867         int r = 0;
 868
 869         if (amdgpu_sriov_vf(adev)) {
 870                 sdma_v4_0_ctx_switch_enable(adev, false);
 871                 sdma_v4_0_enable(adev, false);
 872
 873                 /* set RB registers */
 874                 r = sdma_v4_0_gfx_resume(adev);
 875                 return r;
 876         }
 877
 878         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 879                 r = sdma_v4_0_load_microcode(adev);
 880                 if (r)
 881                         return r;
 882         }
 883
 884         /* unhalt the MEs */
 885         sdma_v4_0_enable(adev, true);
 886         /* enable sdma ring preemption */
 887         sdma_v4_0_ctx_switch_enable(adev, true);
 888
 889         /* start the gfx rings and rlc compute queues */
 890         r = sdma_v4_0_gfx_resume(adev);
 891         if (r)
 892                 return r;
 893         r = sdma_v4_0_rlc_resume(adev);
 894
 895         return r;
 896 }
 897
 898 /**
 899  * sdma_v4_0_ring_test_ring - simple async dma engine test
 900  *
 901  * @ring: amdgpu_ring structure holding ring information
 902  *
 903  * Test the DMA engine by writing using it to write an
 904  * value to memory. (VEGA10).
 905  * Returns 0 for success, error for failure.
 906  */
 907 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring)
 908 {
 909         struct amdgpu_device *adev = ring->adev;
 910         unsigned i;
 911         unsigned index;
 912         int r;
 913         u32 tmp;
 914         u64 gpu_addr;
 915
 916         r = amdgpu_wb_get(adev, &index);
 917         if (r) {
 918                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 919                 return r;
 920         }
 921
 922         gpu_addr = adev->wb.gpu_addr + (index * 4);
 923         tmp = 0xCAFEDEAD;
 924         adev->wb.wb[index] = cpu_to_le32(tmp);
 925
 926         r = amdgpu_ring_alloc(ring, 5);
 927         if (r) {
 928                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 929                 amdgpu_wb_free(adev, index);
 930                 return r;
 931         }
 932
 933         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 934                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 935         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 936         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 937         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 938         amdgpu_ring_write(ring, 0xDEADBEEF);
 939         amdgpu_ring_commit(ring);
 940
 941         for (i = 0; i < adev->usec_timeout; i++) {
 942                 tmp = le32_to_cpu(adev->wb.wb[index]);
 943                 if (tmp == 0xDEADBEEF)
 944                         break;
 945                 DRM_UDELAY(1);
 946         }
 947
 948         if (i < adev->usec_timeout) {
 949                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 950         } else {
 951                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 952                           ring->idx, tmp);
 953                 r = -EINVAL;
 954         }
 955         amdgpu_wb_free(adev, index);
 956
 957         return r;
 958 }
 959
 960 /**
 961  * sdma_v4_0_ring_test_ib - test an IB on the DMA engine
 962  *
 963  * @ring: amdgpu_ring structure holding ring information
 964  *
 965  * Test a simple IB in the DMA ring (VEGA10).
 966  * Returns 0 on success, error on failure.
 967  */
 968 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 969 {
 970         struct amdgpu_device *adev = ring->adev;
 971         struct amdgpu_ib ib;
 972         struct dma_fence *f = NULL;
 973         unsigned index;
 974         long r;
 975         u32 tmp = 0;
 976         u64 gpu_addr;
 977
 978         r = amdgpu_wb_get(adev, &index);
 979         if (r) {
 980                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 981                 return r;
 982         }
 983
 984         gpu_addr = adev->wb.gpu_addr + (index * 4);
 985         tmp = 0xCAFEDEAD;
 986         adev->wb.wb[index] = cpu_to_le32(tmp);
 987         memset(&ib, 0, sizeof(ib));
 988         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 989         if (r) {
 990                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 991                 goto err0;
 992         }
 993
 994         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 995                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 996         ib.ptr[1] = lower_32_bits(gpu_addr);
 997         ib.ptr[2] = upper_32_bits(gpu_addr);
 998         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
 999         ib.ptr[4] = 0xDEADBEEF;
1000         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1001         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1002         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1003         ib.length_dw = 8;
1004
1005         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1006         if (r)
1007                 goto err1;
1008
1009         r = dma_fence_wait_timeout(f, false, timeout);
1010         if (r == 0) {
1011                 DRM_ERROR("amdgpu: IB test timed out\n");
1012                 r = -ETIMEDOUT;
1013                 goto err1;
1014         } else if (r < 0) {
1015                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1016                 goto err1;
1017         }
1018         tmp = le32_to_cpu(adev->wb.wb[index]);
1019         if (tmp == 0xDEADBEEF) {
1020                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
1021                 r = 0;
1022         } else {
1023                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
1024                 r = -EINVAL;
1025         }
1026 err1:
1027         amdgpu_ib_free(adev, &ib, NULL);
1028         dma_fence_put(f);
1029 err0:
1030         amdgpu_wb_free(adev, index);
1031         return r;
1032 }
1033
1034
1035 /**
1036  * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART
1037  *
1038  * @ib: indirect buffer to fill with commands
1039  * @pe: addr of the page entry
1040  * @src: src addr to copy from
1041  * @count: number of page entries to update
1042  *
1043  * Update PTEs by copying them from the GART using sDMA (VEGA10).
1044  */
1045 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib,
1046                                   uint64_t pe, uint64_t src,
1047                                   unsigned count)
1048 {
1049         unsigned bytes = count * 8;
1050
1051         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1052                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1053         ib->ptr[ib->length_dw++] = bytes - 1;
1054         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1055         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1056         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1057         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1058         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1059
1060 }
1061
1062 /**
1063  * sdma_v4_0_vm_write_pte - update PTEs by writing them manually
1064  *
1065  * @ib: indirect buffer to fill with commands
1066  * @pe: addr of the page entry
1067  * @addr: dst addr to write into pe
1068  * @count: number of page entries to update
1069  * @incr: increase next addr by incr bytes
1070  * @flags: access flags
1071  *
1072  * Update PTEs by writing them manually using sDMA (VEGA10).
1073  */
1074 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1075                                    uint64_t value, unsigned count,
1076                                    uint32_t incr)
1077 {
1078         unsigned ndw = count * 2;
1079
1080         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1081                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1082         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1083         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1084         ib->ptr[ib->length_dw++] = ndw - 1;
1085         for (; ndw > 0; ndw -= 2) {
1086                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1087                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1088                 value += incr;
1089         }
1090 }
1091
1092 /**
1093  * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA
1094  *
1095  * @ib: indirect buffer to fill with commands
1096  * @pe: addr of the page entry
1097  * @addr: dst addr to write into pe
1098  * @count: number of page entries to update
1099  * @incr: increase next addr by incr bytes
1100  * @flags: access flags
1101  *
1102  * Update the page tables using sDMA (VEGA10).
1103  */
1104 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1105                                      uint64_t pe,
1106                                      uint64_t addr, unsigned count,
1107                                      uint32_t incr, uint64_t flags)
1108 {
1109         /* for physically contiguous pages (vram) */
1110         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1111         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1112         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1113         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1114         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1115         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1116         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1117         ib->ptr[ib->length_dw++] = incr; /* increment size */
1118         ib->ptr[ib->length_dw++] = 0;
1119         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1120 }
1121
1122 /**
1123  * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw
1124  *
1125  * @ib: indirect buffer to fill with padding
1126  *
1127  */
1128 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1129 {
1130         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
1131         u32 pad_count;
1132         int i;
1133
1134         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
1135         for (i = 0; i < pad_count; i++)
1136                 if (sdma && sdma->burst_nop && (i == 0))
1137                         ib->ptr[ib->length_dw++] =
1138                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1139                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1140                 else
1141                         ib->ptr[ib->length_dw++] =
1142                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1143 }
1144
1145
1146 /**
1147  * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline
1148  *
1149  * @ring: amdgpu_ring pointer
1150  *
1151  * Make sure all previous operations are completed (CIK).
1152  */
1153 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1154 {
1155         uint32_t seq = ring->fence_drv.sync_seq;
1156         uint64_t addr = ring->fence_drv.gpu_addr;
1157
1158         /* wait for idle */
1159         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1160                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1161                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1162                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1163         amdgpu_ring_write(ring, addr & 0xfffffffc);
1164         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1165         amdgpu_ring_write(ring, seq); /* reference */
1166         amdgpu_ring_write(ring, 0xfffffff); /* mask */
1167         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1168                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1169 }
1170
1171
1172 /**
1173  * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA
1174  *
1175  * @ring: amdgpu_ring pointer
1176  * @vm: amdgpu_vm pointer
1177  *
1178  * Update the page table base and flush the VM TLB
1179  * using sDMA (VEGA10).
1180  */
1181 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1182                                          unsigned vm_id, uint64_t pd_addr)
1183 {
1184         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1185         uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
1186         unsigned eng = ring->vm_inv_eng;
1187
1188         pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
1189         pd_addr |= AMDGPU_PTE_VALID;
1190
1191         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1192                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1193         amdgpu_ring_write(ring, hub->ctx0_ptb_addr_lo32 + vm_id * 2);
1194         amdgpu_ring_write(ring, lower_32_bits(pd_addr));
1195
1196         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1197                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1198         amdgpu_ring_write(ring, hub->ctx0_ptb_addr_hi32 + vm_id * 2);
1199         amdgpu_ring_write(ring, upper_32_bits(pd_addr));
1200
1201         /* flush TLB */
1202         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1203                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1204         amdgpu_ring_write(ring, hub->vm_inv_eng0_req + eng);
1205         amdgpu_ring_write(ring, req);
1206
1207         /* wait for flush */
1208         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1209                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1210                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1211         amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);
1212         amdgpu_ring_write(ring, 0);
1213         amdgpu_ring_write(ring, 1 << vm_id); /* reference */
1214         amdgpu_ring_write(ring, 1 << vm_id); /* mask */
1215         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1216                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1217 }
1218
1219 static int sdma_v4_0_early_init(void *handle)
1220 {
1221         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1222
1223         if (adev->asic_type == CHIP_RAVEN)
1224                 adev->sdma.num_instances = 1;
1225         else
1226                 adev->sdma.num_instances = 2;
1227
1228         sdma_v4_0_set_ring_funcs(adev);
1229         sdma_v4_0_set_buffer_funcs(adev);
1230         sdma_v4_0_set_vm_pte_funcs(adev);
1231         sdma_v4_0_set_irq_funcs(adev);
1232
1233         return 0;
1234 }
1235
1236
1237 static int sdma_v4_0_sw_init(void *handle)
1238 {
1239         struct amdgpu_ring *ring;
1240         int r, i;
1241         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1242
1243         /* SDMA trap event */
1244         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_SDMA0, 224,
1245                               &adev->sdma.trap_irq);
1246         if (r)
1247                 return r;
1248
1249         /* SDMA trap event */
1250         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_SDMA1, 224,
1251                               &adev->sdma.trap_irq);
1252         if (r)
1253                 return r;
1254
1255         r = sdma_v4_0_init_microcode(adev);
1256         if (r) {
1257                 DRM_ERROR("Failed to load sdma firmware!\n");
1258                 return r;
1259         }
1260
1261         for (i = 0; i < adev->sdma.num_instances; i++) {
1262                 ring = &adev->sdma.instance[i].ring;
1263                 ring->ring_obj = NULL;
1264                 ring->use_doorbell = true;
1265
1266                 DRM_INFO("use_doorbell being set to: [%s]\n",
1267                                 ring->use_doorbell?"true":"false");
1268
1269                 ring->doorbell_index = (i == 0) ?
1270                         (AMDGPU_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset
1271                         : (AMDGPU_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset
1272
1273                 sprintf(ring->name, "sdma%d", i);
1274                 r = amdgpu_ring_init(adev, ring, 1024,
1275                                      &adev->sdma.trap_irq,
1276                                      (i == 0) ?
1277                                      AMDGPU_SDMA_IRQ_TRAP0 :
1278                                      AMDGPU_SDMA_IRQ_TRAP1);
1279
1280                 if (amdgpu_sriov_vf(adev)) {
1281                         r = amdgpu_wb_get_64bit(adev,
1282                                                 &adev->sdma.instance[i].poll_mem_offs);
1283                         if (r) {
1284                                 dev_err(adev->dev, "(%d) failed to allocate SDMA poll mem wb.\n", r);
1285                                 return r;
1286                         }
1287                 }
1288                 if (r)
1289                         return r;
1290         }
1291
1292         return r;
1293 }
1294
1295 static int sdma_v4_0_sw_fini(void *handle)
1296 {
1297         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1298         int i;
1299
1300         for (i = 0; i < adev->sdma.num_instances; i++) {
1301                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1302
1303                 if (amdgpu_sriov_vf(adev))
1304                         amdgpu_wb_free_64bit(adev,
1305                                              adev->sdma.instance[i].poll_mem_offs);
1306         }
1307         return 0;
1308 }
1309
1310 static int sdma_v4_0_hw_init(void *handle)
1311 {
1312         int r;
1313         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1314
1315         sdma_v4_0_init_golden_registers(adev);
1316
1317         r = sdma_v4_0_start(adev);
1318
1319         return r;
1320 }
1321
1322 static int sdma_v4_0_hw_fini(void *handle)
1323 {
1324         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1325
1326         if (amdgpu_sriov_vf(adev))
1327                 return 0;
1328
1329         sdma_v4_0_ctx_switch_enable(adev, false);
1330         sdma_v4_0_enable(adev, false);
1331
1332         return 0;
1333 }
1334
1335 static int sdma_v4_0_suspend(void *handle)
1336 {
1337         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1338
1339         return sdma_v4_0_hw_fini(adev);
1340 }
1341
1342 static int sdma_v4_0_resume(void *handle)
1343 {
1344         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1345
1346         return sdma_v4_0_hw_init(adev);
1347 }
1348
1349 static bool sdma_v4_0_is_idle(void *handle)
1350 {
1351         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1352         u32 i;
1353
1354         for (i = 0; i < adev->sdma.num_instances; i++) {
1355                 u32 tmp = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_STATUS_REG));
1356
1357                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1358                         return false;
1359         }
1360
1361         return true;
1362 }
1363
1364 static int sdma_v4_0_wait_for_idle(void *handle)
1365 {
1366         unsigned i;
1367         u32 sdma0, sdma1;
1368         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1369
1370         for (i = 0; i < adev->usec_timeout; i++) {
1371                 sdma0 = RREG32(sdma_v4_0_get_reg_offset(0, mmSDMA0_STATUS_REG));
1372                 sdma1 = RREG32(sdma_v4_0_get_reg_offset(1, mmSDMA0_STATUS_REG));
1373
1374                 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1375                         return 0;
1376                 udelay(1);
1377         }
1378         return -ETIMEDOUT;
1379 }
1380
1381 static int sdma_v4_0_soft_reset(void *handle)
1382 {
1383         /* todo */
1384
1385         return 0;
1386 }
1387
1388 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev,
1389                                         struct amdgpu_irq_src *source,
1390                                         unsigned type,
1391                                         enum amdgpu_interrupt_state state)
1392 {
1393         u32 sdma_cntl;
1394
1395         u32 reg_offset = (type == AMDGPU_SDMA_IRQ_TRAP0) ?
1396                 sdma_v4_0_get_reg_offset(0, mmSDMA0_CNTL) :
1397                 sdma_v4_0_get_reg_offset(1, mmSDMA0_CNTL);
1398
1399         sdma_cntl = RREG32(reg_offset);
1400         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1401                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1402         WREG32(reg_offset, sdma_cntl);
1403
1404         return 0;
1405 }
1406
1407 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
1408                                       struct amdgpu_irq_src *source,
1409                                       struct amdgpu_iv_entry *entry)
1410 {
1411         DRM_DEBUG("IH: SDMA trap\n");
1412         switch (entry->client_id) {
1413         case AMDGPU_IH_CLIENTID_SDMA0:
1414                 switch (entry->ring_id) {
1415                 case 0:
1416                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1417                         break;
1418                 case 1:
1419                         /* XXX compute */
1420                         break;
1421                 case 2:
1422                         /* XXX compute */
1423                         break;
1424                 case 3:
1425                         /* XXX page queue*/
1426                         break;
1427                 }
1428                 break;
1429         case AMDGPU_IH_CLIENTID_SDMA1:
1430                 switch (entry->ring_id) {
1431                 case 0:
1432                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1433                         break;
1434                 case 1:
1435                         /* XXX compute */
1436                         break;
1437                 case 2:
1438                         /* XXX compute */
1439                         break;
1440                 case 3:
1441                         /* XXX page queue*/
1442                         break;
1443                 }
1444                 break;
1445         }
1446         return 0;
1447 }
1448
1449 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1450                                               struct amdgpu_irq_src *source,
1451                                               struct amdgpu_iv_entry *entry)
1452 {
1453         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1454         schedule_work(&adev->reset_work);
1455         return 0;
1456 }
1457
1458
1459 static void sdma_v4_0_update_medium_grain_clock_gating(
1460                 struct amdgpu_device *adev,
1461                 bool enable)
1462 {
1463         uint32_t data, def;
1464
1465         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1466                 /* enable sdma0 clock gating */
1467                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
1468                 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1469                           SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1470                           SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1471                           SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1472                           SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1473                           SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1474                           SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1475                           SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1476                 if (def != data)
1477                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);
1478
1479                 if (adev->asic_type == CHIP_VEGA10) {
1480                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));
1481                         data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1482                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1483                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1484                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1485                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1486                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1487                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1488                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1489                         if (def != data)
1490                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);
1491                 }
1492         } else {
1493                 /* disable sdma0 clock gating */
1494                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
1495                 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1496                          SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1497                          SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1498                          SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1499                          SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1500                          SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1501                          SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1502                          SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1503
1504                 if (def != data)
1505                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);
1506
1507                 if (adev->asic_type == CHIP_VEGA10) {
1508                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));
1509                         data |= (SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1510                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1511                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1512                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1513                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1514                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1515                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1516                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1517                         if (def != data)
1518                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);
1519                 }
1520         }
1521 }
1522
1523
1524 static void sdma_v4_0_update_medium_grain_light_sleep(
1525                 struct amdgpu_device *adev,
1526                 bool enable)
1527 {
1528         uint32_t data, def;
1529
1530         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1531                 /* 1-not override: enable sdma0 mem light sleep */
1532                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1533                 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1534                 if (def != data)
1535                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1536
1537                 /* 1-not override: enable sdma1 mem light sleep */
1538                 if (adev->asic_type == CHIP_VEGA10) {
1539                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));
1540                         data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1541                         if (def != data)
1542                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);
1543                 }
1544         } else {
1545                 /* 0-override:disable sdma0 mem light sleep */
1546                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1547                 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1548                 if (def != data)
1549                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1550
1551                 /* 0-override:disable sdma1 mem light sleep */
1552                 if (adev->asic_type == CHIP_VEGA10) {
1553                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));
1554                         data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1555                         if (def != data)
1556                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);
1557                 }
1558         }
1559 }
1560
1561 static int sdma_v4_0_set_clockgating_state(void *handle,
1562                                           enum amd_clockgating_state state)
1563 {
1564         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1565
1566         if (amdgpu_sriov_vf(adev))
1567                 return 0;
1568
1569         switch (adev->asic_type) {
1570         case CHIP_VEGA10:
1571         case CHIP_RAVEN:
1572                 sdma_v4_0_update_medium_grain_clock_gating(adev,
1573                                 state == AMD_CG_STATE_GATE ? true : false);
1574                 sdma_v4_0_update_medium_grain_light_sleep(adev,
1575                                 state == AMD_CG_STATE_GATE ? true : false);
1576                 break;
1577         default:
1578                 break;
1579         }
1580         return 0;
1581 }
1582
1583 static int sdma_v4_0_set_powergating_state(void *handle,
1584                                           enum amd_powergating_state state)
1585 {
1586         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1587
1588         switch (adev->asic_type) {
1589         case CHIP_RAVEN:
1590                 sdma_v4_1_update_power_gating(adev,
1591                                 state == AMD_PG_STATE_GATE ? true : false);
1592                 break;
1593         default:
1594                 break;
1595         }
1596
1597         return 0;
1598 }
1599
1600 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags)
1601 {
1602         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1603         int data;
1604
1605         if (amdgpu_sriov_vf(adev))
1606                 *flags = 0;
1607
1608         /* AMD_CG_SUPPORT_SDMA_MGCG */
1609         data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
1610         if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
1611                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1612
1613         /* AMD_CG_SUPPORT_SDMA_LS */
1614         data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1615         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1616                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1617 }
1618
1619 const struct amd_ip_funcs sdma_v4_0_ip_funcs = {
1620         .name = "sdma_v4_0",
1621         .early_init = sdma_v4_0_early_init,
1622         .late_init = NULL,
1623         .sw_init = sdma_v4_0_sw_init,
1624         .sw_fini = sdma_v4_0_sw_fini,
1625         .hw_init = sdma_v4_0_hw_init,
1626         .hw_fini = sdma_v4_0_hw_fini,
1627         .suspend = sdma_v4_0_suspend,
1628         .resume = sdma_v4_0_resume,
1629         .is_idle = sdma_v4_0_is_idle,
1630         .wait_for_idle = sdma_v4_0_wait_for_idle,
1631         .soft_reset = sdma_v4_0_soft_reset,
1632         .set_clockgating_state = sdma_v4_0_set_clockgating_state,
1633         .set_powergating_state = sdma_v4_0_set_powergating_state,
1634         .get_clockgating_state = sdma_v4_0_get_clockgating_state,
1635 };
1636
1637 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
1638         .type = AMDGPU_RING_TYPE_SDMA,
1639         .align_mask = 0xf,
1640         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1641         .support_64bit_ptrs = true,
1642         .vmhub = AMDGPU_MMHUB,
1643         .get_rptr = sdma_v4_0_ring_get_rptr,
1644         .get_wptr = sdma_v4_0_ring_get_wptr,
1645         .set_wptr = sdma_v4_0_ring_set_wptr,
1646         .emit_frame_size =
1647                 6 + /* sdma_v4_0_ring_emit_hdp_flush */
1648                 3 + /* sdma_v4_0_ring_emit_hdp_invalidate */
1649                 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
1650                 18 + /* sdma_v4_0_ring_emit_vm_flush */
1651                 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
1652         .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
1653         .emit_ib = sdma_v4_0_ring_emit_ib,
1654         .emit_fence = sdma_v4_0_ring_emit_fence,
1655         .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
1656         .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
1657         .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
1658         .emit_hdp_invalidate = sdma_v4_0_ring_emit_hdp_invalidate,
1659         .test_ring = sdma_v4_0_ring_test_ring,
1660         .test_ib = sdma_v4_0_ring_test_ib,
1661         .insert_nop = sdma_v4_0_ring_insert_nop,
1662         .pad_ib = sdma_v4_0_ring_pad_ib,
1663 };
1664
1665 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
1666 {
1667         int i;
1668
1669         for (i = 0; i < adev->sdma.num_instances; i++)
1670                 adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs;
1671 }
1672
1673 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = {
1674         .set = sdma_v4_0_set_trap_irq_state,
1675         .process = sdma_v4_0_process_trap_irq,
1676 };
1677
1678 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = {
1679         .process = sdma_v4_0_process_illegal_inst_irq,
1680 };
1681
1682 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev)
1683 {
1684         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1685         adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs;
1686         adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs;
1687 }
1688
1689 /**
1690  * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine
1691  *
1692  * @ring: amdgpu_ring structure holding ring information
1693  * @src_offset: src GPU address
1694  * @dst_offset: dst GPU address
1695  * @byte_count: number of bytes to xfer
1696  *
1697  * Copy GPU buffers using the DMA engine (VEGA10).
1698  * Used by the amdgpu ttm implementation to move pages if
1699  * registered as the asic copy callback.
1700  */
1701 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib,
1702                                        uint64_t src_offset,
1703                                        uint64_t dst_offset,
1704                                        uint32_t byte_count)
1705 {
1706         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1707                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1708         ib->ptr[ib->length_dw++] = byte_count - 1;
1709         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1710         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1711         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1712         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1713         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1714 }
1715
1716 /**
1717  * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine
1718  *
1719  * @ring: amdgpu_ring structure holding ring information
1720  * @src_data: value to write to buffer
1721  * @dst_offset: dst GPU address
1722  * @byte_count: number of bytes to xfer
1723  *
1724  * Fill GPU buffers using the DMA engine (VEGA10).
1725  */
1726 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib,
1727                                        uint32_t src_data,
1728                                        uint64_t dst_offset,
1729                                        uint32_t byte_count)
1730 {
1731         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1732         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1733         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1734         ib->ptr[ib->length_dw++] = src_data;
1735         ib->ptr[ib->length_dw++] = byte_count - 1;
1736 }
1737
1738 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = {
1739         .copy_max_bytes = 0x400000,
1740         .copy_num_dw = 7,
1741         .emit_copy_buffer = sdma_v4_0_emit_copy_buffer,
1742
1743         .fill_max_bytes = 0x400000,
1744         .fill_num_dw = 5,
1745         .emit_fill_buffer = sdma_v4_0_emit_fill_buffer,
1746 };
1747
1748 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
1749 {
1750         if (adev->mman.buffer_funcs == NULL) {
1751                 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
1752                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1753         }
1754 }
1755
1756 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = {
1757         .copy_pte = sdma_v4_0_vm_copy_pte,
1758         .write_pte = sdma_v4_0_vm_write_pte,
1759         .set_pte_pde = sdma_v4_0_vm_set_pte_pde,
1760 };
1761
1762 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1763 {
1764         unsigned i;
1765
1766         if (adev->vm_manager.vm_pte_funcs == NULL) {
1767                 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
1768                 for (i = 0; i < adev->sdma.num_instances; i++)
1769                         adev->vm_manager.vm_pte_rings[i] =
1770                                 &adev->sdma.instance[i].ring;
1771
1772                 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1773         }
1774 }
1775
1776 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = {
1777         .type = AMD_IP_BLOCK_TYPE_SDMA,
1778         .major = 4,
1779         .minor = 0,
1780         .rev = 0,
1781         .funcs = &sdma_v4_0_ip_funcs,
1782 };