drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_ucode.h"
  31 #include "amdgpu_trace.h"
  32
  33 #include "sdma0/sdma0_4_2_offset.h"
  34 #include "sdma0/sdma0_4_2_sh_mask.h"
  35 #include "sdma1/sdma1_4_2_offset.h"
  36 #include "sdma1/sdma1_4_2_sh_mask.h"
  37 #include "sdma2/sdma2_4_2_2_offset.h"
  38 #include "sdma2/sdma2_4_2_2_sh_mask.h"
  39 #include "sdma3/sdma3_4_2_2_offset.h"
  40 #include "sdma3/sdma3_4_2_2_sh_mask.h"
  41 #include "sdma4/sdma4_4_2_2_offset.h"
  42 #include "sdma4/sdma4_4_2_2_sh_mask.h"
  43 #include "sdma5/sdma5_4_2_2_offset.h"
  44 #include "sdma5/sdma5_4_2_2_sh_mask.h"
  45 #include "sdma6/sdma6_4_2_2_offset.h"
  46 #include "sdma6/sdma6_4_2_2_sh_mask.h"
  47 #include "sdma7/sdma7_4_2_2_offset.h"
  48 #include "sdma7/sdma7_4_2_2_sh_mask.h"
  49 #include "sdma0/sdma0_4_1_default.h"
  50
  51 #include "soc15_common.h"
  52 #include "soc15.h"
  53 #include "vega10_sdma_pkt_open.h"
  54
  55 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h"
  56 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h"
  57
  58 #include "amdgpu_ras.h"
  59 #include "sdma_v4_4.h"
  60
  61 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin");
  62 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin");
  63 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin");
  64 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin");
  65 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin");
  66 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin");
  67 MODULE_FIRMWARE("amdgpu/raven_sdma.bin");
  68 MODULE_FIRMWARE("amdgpu/picasso_sdma.bin");
  69 MODULE_FIRMWARE("amdgpu/raven2_sdma.bin");
  70 MODULE_FIRMWARE("amdgpu/arcturus_sdma.bin");
  71 MODULE_FIRMWARE("amdgpu/renoir_sdma.bin");
  72 MODULE_FIRMWARE("amdgpu/green_sardine_sdma.bin");
  73 MODULE_FIRMWARE("amdgpu/aldebaran_sdma.bin");
  74
  75 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK  0x000000F8L
  76 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
  77
  78 #define WREG32_SDMA(instance, offset, value) \
  79         WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value)
  80 #define RREG32_SDMA(instance, offset) \
  81         RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)))
  82
  83 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev);
  84 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev);
  85 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  86 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev);
  87 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev);
  88
  89 static const struct soc15_reg_golden golden_settings_sdma_4[] = {
  90         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
  91         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
  92         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),
  93         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  94         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
  95         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  96         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000),
  97         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
  98         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  99         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
 100         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 101         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
 102         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000),
 103         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
 104         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100),
 105         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 106         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
 107         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 108         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000),
 109         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
 110         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 111         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
 112         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 113         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
 114         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000)
 115 };
 116
 117 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = {
 118         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
 119         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
 120         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 121         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
 122         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
 123         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
 124         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 125 };
 126
 127 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = {
 128         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
 129         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001),
 130         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 131         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
 132         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
 133         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001),
 134         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 135 };
 136
 137 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = {
 138         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
 139         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
 140         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100),
 141         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 142         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051),
 143         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100),
 144         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 145         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100),
 146         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 147         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
 148         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000)
 149 };
 150
 151 static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = {
 152         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
 153 };
 154
 155 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] =
 156 {
 157         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 158         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
 159         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 160         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 161         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 162         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 163         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 164         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 165         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003),
 166         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 167         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
 168         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 169         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 170         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 171         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 172         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 173         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 174         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 175         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 176         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 177         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 178         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 179         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 180         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 181         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 182         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
 183         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 184 };
 185
 186 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = {
 187         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 188         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
 189         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 190         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 191         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 192         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 193         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 194         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 195         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003),
 196         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 197         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
 198         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 199         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 200         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 201         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 202         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 203         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 204         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 205         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 206         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 207         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 208         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 209         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 210         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 211         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 212         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
 213         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 214 };
 215
 216 static const struct soc15_reg_golden golden_settings_sdma_rv1[] =
 217 {
 218         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
 219         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002)
 220 };
 221
 222 static const struct soc15_reg_golden golden_settings_sdma_rv2[] =
 223 {
 224         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001),
 225         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001)
 226 };
 227
 228 static const struct soc15_reg_golden golden_settings_sdma_arct[] =
 229 {
 230         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 231         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 232         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 233         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 234         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 235         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 236         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 237         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 238         SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 239         SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 240         SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 241         SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 242         SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 243         SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 244         SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 245         SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 246         SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 247         SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 248         SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 249         SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 250         SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 251         SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 252         SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 253         SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 254         SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 255         SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 256         SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 257         SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 258         SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 259         SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 260         SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 261         SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_UTCL1_TIMEOUT, 0xffffffff, 0x00010001)
 262 };
 263
 264 static const struct soc15_reg_golden golden_settings_sdma_aldebaran[] = {
 265         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
 266         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
 267         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 268         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
 269         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
 270         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 271         SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
 272         SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
 273         SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA2_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 274         SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
 275         SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
 276         SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 277         SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
 278         SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
 279         SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
 280 };
 281
 282 static const struct soc15_reg_golden golden_settings_sdma_4_3[] = {
 283         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
 284         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
 285         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
 286         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002),
 287         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 288         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051),
 289         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 290         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 291         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
 292         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x03fbe1fe)
 293 };
 294
 295 static const struct soc15_ras_field_entry sdma_v4_0_ras_fields[] = {
 296         { "SDMA_UCODE_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 297         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UCODE_BUF_SED),
 298         0, 0,
 299         },
 300         { "SDMA_RB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 301         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_RB_CMD_BUF_SED),
 302         0, 0,
 303         },
 304         { "SDMA_IB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 305         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_IB_CMD_BUF_SED),
 306         0, 0,
 307         },
 308         { "SDMA_UTCL1_RD_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 309         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RD_FIFO_SED),
 310         0, 0,
 311         },
 312         { "SDMA_UTCL1_RDBST_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 313         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RDBST_FIFO_SED),
 314         0, 0,
 315         },
 316         { "SDMA_DATA_LUT_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 317         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_DATA_LUT_FIFO_SED),
 318         0, 0,
 319         },
 320         { "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 321         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF0_SED),
 322         0, 0,
 323         },
 324         { "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 325         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF1_SED),
 326         0, 0,
 327         },
 328         { "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 329         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF2_SED),
 330         0, 0,
 331         },
 332         { "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 333         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF3_SED),
 334         0, 0,
 335         },
 336         { "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 337         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF4_SED),
 338         0, 0,
 339         },
 340         { "SDMA_MBANK_DATA_BUF5_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 341         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF5_SED),
 342         0, 0,
 343         },
 344         { "SDMA_MBANK_DATA_BUF6_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 345         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF6_SED),
 346         0, 0,
 347         },
 348         { "SDMA_MBANK_DATA_BUF7_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 349         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF7_SED),
 350         0, 0,
 351         },
 352         { "SDMA_MBANK_DATA_BUF8_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 353         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF8_SED),
 354         0, 0,
 355         },
 356         { "SDMA_MBANK_DATA_BUF9_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 357         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF9_SED),
 358         0, 0,
 359         },
 360         { "SDMA_MBANK_DATA_BUF10_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 361         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF10_SED),
 362         0, 0,
 363         },
 364         { "SDMA_MBANK_DATA_BUF11_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 365         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF11_SED),
 366         0, 0,
 367         },
 368         { "SDMA_MBANK_DATA_BUF12_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 369         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF12_SED),
 370         0, 0,
 371         },
 372         { "SDMA_MBANK_DATA_BUF13_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 373         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF13_SED),
 374         0, 0,
 375         },
 376         { "SDMA_MBANK_DATA_BUF14_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 377         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF14_SED),
 378         0, 0,
 379         },
 380         { "SDMA_MBANK_DATA_BUF15_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 381         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF15_SED),
 382         0, 0,
 383         },
 384         { "SDMA_SPLIT_DAT_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 385         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_SPLIT_DAT_BUF_SED),
 386         0, 0,
 387         },
 388         { "SDMA_MC_WR_ADDR_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
 389         SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MC_WR_ADDR_FIFO_SED),
 390         0, 0,
 391         },
 392 };
 393
 394 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
 395                 u32 instance, u32 offset)
 396 {
 397         switch (instance) {
 398         case 0:
 399                 return (adev->reg_offset[SDMA0_HWIP][0][0] + offset);
 400         case 1:
 401                 return (adev->reg_offset[SDMA1_HWIP][0][0] + offset);
 402         case 2:
 403                 return (adev->reg_offset[SDMA2_HWIP][0][1] + offset);
 404         case 3:
 405                 return (adev->reg_offset[SDMA3_HWIP][0][1] + offset);
 406         case 4:
 407                 return (adev->reg_offset[SDMA4_HWIP][0][1] + offset);
 408         case 5:
 409                 return (adev->reg_offset[SDMA5_HWIP][0][1] + offset);
 410         case 6:
 411                 return (adev->reg_offset[SDMA6_HWIP][0][1] + offset);
 412         case 7:
 413                 return (adev->reg_offset[SDMA7_HWIP][0][1] + offset);
 414         default:
 415                 break;
 416         }
 417         return 0;
 418 }
 419
 420 static unsigned sdma_v4_0_seq_to_irq_id(int seq_num)
 421 {
 422         switch (seq_num) {
 423         case 0:
 424                 return SOC15_IH_CLIENTID_SDMA0;
 425         case 1:
 426                 return SOC15_IH_CLIENTID_SDMA1;
 427         case 2:
 428                 return SOC15_IH_CLIENTID_SDMA2;
 429         case 3:
 430                 return SOC15_IH_CLIENTID_SDMA3;
 431         case 4:
 432                 return SOC15_IH_CLIENTID_SDMA4;
 433         case 5:
 434                 return SOC15_IH_CLIENTID_SDMA5;
 435         case 6:
 436                 return SOC15_IH_CLIENTID_SDMA6;
 437         case 7:
 438                 return SOC15_IH_CLIENTID_SDMA7;
 439         default:
 440                 break;
 441         }
 442         return -EINVAL;
 443 }
 444
 445 static int sdma_v4_0_irq_id_to_seq(unsigned client_id)
 446 {
 447         switch (client_id) {
 448         case SOC15_IH_CLIENTID_SDMA0:
 449                 return 0;
 450         case SOC15_IH_CLIENTID_SDMA1:
 451                 return 1;
 452         case SOC15_IH_CLIENTID_SDMA2:
 453                 return 2;
 454         case SOC15_IH_CLIENTID_SDMA3:
 455                 return 3;
 456         case SOC15_IH_CLIENTID_SDMA4:
 457                 return 4;
 458         case SOC15_IH_CLIENTID_SDMA5:
 459                 return 5;
 460         case SOC15_IH_CLIENTID_SDMA6:
 461                 return 6;
 462         case SOC15_IH_CLIENTID_SDMA7:
 463                 return 7;
 464         default:
 465                 break;
 466         }
 467         return -EINVAL;
 468 }
 469
 470 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
 471 {
 472         switch (adev->asic_type) {
 473         case CHIP_VEGA10:
 474                 soc15_program_register_sequence(adev,
 475                                                 golden_settings_sdma_4,
 476                                                 ARRAY_SIZE(golden_settings_sdma_4));
 477                 soc15_program_register_sequence(adev,
 478                                                 golden_settings_sdma_vg10,
 479                                                 ARRAY_SIZE(golden_settings_sdma_vg10));
 480                 break;
 481         case CHIP_VEGA12:
 482                 soc15_program_register_sequence(adev,
 483                                                 golden_settings_sdma_4,
 484                                                 ARRAY_SIZE(golden_settings_sdma_4));
 485                 soc15_program_register_sequence(adev,
 486                                                 golden_settings_sdma_vg12,
 487                                                 ARRAY_SIZE(golden_settings_sdma_vg12));
 488                 break;
 489         case CHIP_VEGA20:
 490                 soc15_program_register_sequence(adev,
 491                                                 golden_settings_sdma0_4_2_init,
 492                                                 ARRAY_SIZE(golden_settings_sdma0_4_2_init));
 493                 soc15_program_register_sequence(adev,
 494                                                 golden_settings_sdma0_4_2,
 495                                                 ARRAY_SIZE(golden_settings_sdma0_4_2));
 496                 soc15_program_register_sequence(adev,
 497                                                 golden_settings_sdma1_4_2,
 498                                                 ARRAY_SIZE(golden_settings_sdma1_4_2));
 499                 break;
 500         case CHIP_ARCTURUS:
 501                 soc15_program_register_sequence(adev,
 502                                                 golden_settings_sdma_arct,
 503                                                 ARRAY_SIZE(golden_settings_sdma_arct));
 504                 break;
 505         case CHIP_ALDEBARAN:
 506                 soc15_program_register_sequence(adev,
 507                                                 golden_settings_sdma_aldebaran,
 508                                                 ARRAY_SIZE(golden_settings_sdma_aldebaran));
 509                 break;
 510         case CHIP_RAVEN:
 511                 soc15_program_register_sequence(adev,
 512                                                 golden_settings_sdma_4_1,
 513                                                 ARRAY_SIZE(golden_settings_sdma_4_1));
 514                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
 515                         soc15_program_register_sequence(adev,
 516                                                         golden_settings_sdma_rv2,
 517                                                         ARRAY_SIZE(golden_settings_sdma_rv2));
 518                 else
 519                         soc15_program_register_sequence(adev,
 520                                                         golden_settings_sdma_rv1,
 521                                                         ARRAY_SIZE(golden_settings_sdma_rv1));
 522                 break;
 523         case CHIP_RENOIR:
 524                 soc15_program_register_sequence(adev,
 525                                                 golden_settings_sdma_4_3,
 526                                                 ARRAY_SIZE(golden_settings_sdma_4_3));
 527                 break;
 528         default:
 529                 break;
 530         }
 531 }
 532
 533 static void sdma_v4_0_setup_ulv(struct amdgpu_device *adev)
 534 {
 535         int i;
 536
 537         /*
 538          * The only chips with SDMAv4 and ULV are VG10 and VG20.
 539          * Server SKUs take a different hysteresis setting from other SKUs.
 540          */
 541         switch (adev->asic_type) {
 542         case CHIP_VEGA10:
 543                 if (adev->pdev->device == 0x6860)
 544                         break;
 545                 return;
 546         case CHIP_VEGA20:
 547                 if (adev->pdev->device == 0x66a1)
 548                         break;
 549                 return;
 550         default:
 551                 return;
 552         }
 553
 554         for (i = 0; i < adev->sdma.num_instances; i++) {
 555                 uint32_t temp;
 556
 557                 temp = RREG32_SDMA(i, mmSDMA0_ULV_CNTL);
 558                 temp = REG_SET_FIELD(temp, SDMA0_ULV_CNTL, HYSTERESIS, 0x0);
 559                 WREG32_SDMA(i, mmSDMA0_ULV_CNTL, temp);
 560         }
 561 }
 562
 563 static int sdma_v4_0_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
 564 {
 565         int err = 0;
 566         const struct sdma_firmware_header_v1_0 *hdr;
 567
 568         err = amdgpu_ucode_validate(sdma_inst->fw);
 569         if (err)
 570                 return err;
 571
 572         hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
 573         sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
 574         sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
 575
 576         if (sdma_inst->feature_version >= 20)
 577                 sdma_inst->burst_nop = true;
 578
 579         return 0;
 580 }
 581
 582 static void sdma_v4_0_destroy_inst_ctx(struct amdgpu_device *adev)
 583 {
 584         int i;
 585
 586         for (i = 0; i < adev->sdma.num_instances; i++) {
 587                 release_firmware(adev->sdma.instance[i].fw);
 588                 adev->sdma.instance[i].fw = NULL;
 589
 590                 /* arcturus shares the same FW memory across
 591                    all SDMA isntances */
 592                 if (adev->asic_type == CHIP_ARCTURUS ||
 593                     adev->asic_type == CHIP_ALDEBARAN)
 594                         break;
 595         }
 596
 597         memset((void *)adev->sdma.instance, 0,
 598                 sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
 599 }
 600
 601 /**
 602  * sdma_v4_0_init_microcode - load ucode images from disk
 603  *
 604  * @adev: amdgpu_device pointer
 605  *
 606  * Use the firmware interface to load the ucode images into
 607  * the driver (not loaded into hw).
 608  * Returns 0 on success, error on failure.
 609  */
 610
 611 // emulation only, won't work on real chip
 612 // vega10 real chip need to use PSP to load firmware
 613 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
 614 {
 615         const char *chip_name;
 616         char fw_name[30];
 617         int err = 0, i;
 618         struct amdgpu_firmware_info *info = NULL;
 619         const struct common_firmware_header *header = NULL;
 620
 621         DRM_DEBUG("\n");
 622
 623         switch (adev->asic_type) {
 624         case CHIP_VEGA10:
 625                 chip_name = "vega10";
 626                 break;
 627         case CHIP_VEGA12:
 628                 chip_name = "vega12";
 629                 break;
 630         case CHIP_VEGA20:
 631                 chip_name = "vega20";
 632                 break;
 633         case CHIP_RAVEN:
 634                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
 635                         chip_name = "raven2";
 636                 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
 637                         chip_name = "picasso";
 638                 else
 639                         chip_name = "raven";
 640                 break;
 641         case CHIP_ARCTURUS:
 642                 chip_name = "arcturus";
 643                 break;
 644         case CHIP_RENOIR:
 645                 if (adev->apu_flags & AMD_APU_IS_RENOIR)
 646                         chip_name = "renoir";
 647                 else
 648                         chip_name = "green_sardine";
 649                 break;
 650         case CHIP_ALDEBARAN:
 651                 chip_name = "aldebaran";
 652                 break;
 653         default:
 654                 BUG();
 655         }
 656
 657         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 658
 659         err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);
 660         if (err)
 661                 goto out;
 662
 663         err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[0]);
 664         if (err)
 665                 goto out;
 666
 667         for (i = 1; i < adev->sdma.num_instances; i++) {
 668                 if (adev->asic_type == CHIP_ARCTURUS ||
 669                     adev->asic_type == CHIP_ALDEBARAN) {
 670                         /* Acturus & Aldebaran will leverage the same FW memory
 671                            for every SDMA instance */
 672                         memcpy((void *)&adev->sdma.instance[i],
 673                                (void *)&adev->sdma.instance[0],
 674                                sizeof(struct amdgpu_sdma_instance));
 675                 }
 676                 else {
 677                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i);
 678
 679                         err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 680                         if (err)
 681                                 goto out;
 682
 683                         err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[i]);
 684                         if (err)
 685                                 goto out;
 686                 }
 687         }
 688
 689         DRM_DEBUG("psp_load == '%s'\n",
 690                 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
 691
 692         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 693                 for (i = 0; i < adev->sdma.num_instances; i++) {
 694                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 695                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 696                         info->fw = adev->sdma.instance[i].fw;
 697                         header = (const struct common_firmware_header *)info->fw->data;
 698                         adev->firmware.fw_size +=
 699                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 700                 }
 701         }
 702
 703 out:
 704         if (err) {
 705                 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name);
 706                 sdma_v4_0_destroy_inst_ctx(adev);
 707         }
 708         return err;
 709 }
 710
 711 /**
 712  * sdma_v4_0_ring_get_rptr - get the current read pointer
 713  *
 714  * @ring: amdgpu ring pointer
 715  *
 716  * Get the current rptr from the hardware (VEGA10+).
 717  */
 718 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring)
 719 {
 720         u64 *rptr;
 721
 722         /* XXX check if swapping is necessary on BE */
 723         rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
 724
 725         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 726         return ((*rptr) >> 2);
 727 }
 728
 729 /**
 730  * sdma_v4_0_ring_get_wptr - get the current write pointer
 731  *
 732  * @ring: amdgpu ring pointer
 733  *
 734  * Get the current wptr from the hardware (VEGA10+).
 735  */
 736 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
 737 {
 738         struct amdgpu_device *adev = ring->adev;
 739         u64 wptr;
 740
 741         if (ring->use_doorbell) {
 742                 /* XXX check if swapping is necessary on BE */
 743                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 744                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 745         } else {
 746                 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI);
 747                 wptr = wptr << 32;
 748                 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR);
 749                 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n",
 750                                 ring->me, wptr);
 751         }
 752
 753         return wptr >> 2;
 754 }
 755
 756 /**
 757  * sdma_v4_0_page_ring_set_wptr - commit the write pointer
 758  *
 759  * @ring: amdgpu ring pointer
 760  *
 761  * Write the wptr back to the hardware (VEGA10+).
 762  */
 763 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
 764 {
 765         struct amdgpu_device *adev = ring->adev;
 766
 767         DRM_DEBUG("Setting write pointer\n");
 768         if (ring->use_doorbell) {
 769                 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
 770
 771                 DRM_DEBUG("Using doorbell -- "
 772                                 "wptr_offs == 0x%08x "
 773                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 774                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 775                                 ring->wptr_offs,
 776                                 lower_32_bits(ring->wptr << 2),
 777                                 upper_32_bits(ring->wptr << 2));
 778                 /* XXX check if swapping is necessary on BE */
 779                 WRITE_ONCE(*wb, (ring->wptr << 2));
 780                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 781                                 ring->doorbell_index, ring->wptr << 2);
 782                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 783         } else {
 784                 DRM_DEBUG("Not using doorbell -- "
 785                                 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 786                                 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 787                                 ring->me,
 788                                 lower_32_bits(ring->wptr << 2),
 789                                 ring->me,
 790                                 upper_32_bits(ring->wptr << 2));
 791                 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR,
 792                             lower_32_bits(ring->wptr << 2));
 793                 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI,
 794                             upper_32_bits(ring->wptr << 2));
 795         }
 796 }
 797
 798 /**
 799  * sdma_v4_0_page_ring_get_wptr - get the current write pointer
 800  *
 801  * @ring: amdgpu ring pointer
 802  *
 803  * Get the current wptr from the hardware (VEGA10+).
 804  */
 805 static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring)
 806 {
 807         struct amdgpu_device *adev = ring->adev;
 808         u64 wptr;
 809
 810         if (ring->use_doorbell) {
 811                 /* XXX check if swapping is necessary on BE */
 812                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 813         } else {
 814                 wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI);
 815                 wptr = wptr << 32;
 816                 wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR);
 817         }
 818
 819         return wptr >> 2;
 820 }
 821
 822 /**
 823  * sdma_v4_0_ring_set_wptr - commit the write pointer
 824  *
 825  * @ring: amdgpu ring pointer
 826  *
 827  * Write the wptr back to the hardware (VEGA10+).
 828  */
 829 static void sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring *ring)
 830 {
 831         struct amdgpu_device *adev = ring->adev;
 832
 833         if (ring->use_doorbell) {
 834                 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
 835
 836                 /* XXX check if swapping is necessary on BE */
 837                 WRITE_ONCE(*wb, (ring->wptr << 2));
 838                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 839         } else {
 840                 uint64_t wptr = ring->wptr << 2;
 841
 842                 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR,
 843                             lower_32_bits(wptr));
 844                 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI,
 845                             upper_32_bits(wptr));
 846         }
 847 }
 848
 849 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 850 {
 851         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 852         int i;
 853
 854         for (i = 0; i < count; i++)
 855                 if (sdma && sdma->burst_nop && (i == 0))
 856                         amdgpu_ring_write(ring, ring->funcs->nop |
 857                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 858                 else
 859                         amdgpu_ring_write(ring, ring->funcs->nop);
 860 }
 861
 862 /**
 863  * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine
 864  *
 865  * @ring: amdgpu ring pointer
 866  * @job: job to retrieve vmid from
 867  * @ib: IB object to schedule
 868  * @flags: unused
 869  *
 870  * Schedule an IB in the DMA ring (VEGA10).
 871  */
 872 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
 873                                    struct amdgpu_job *job,
 874                                    struct amdgpu_ib *ib,
 875                                    uint32_t flags)
 876 {
 877         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 878
 879         /* IB packet must end on a 8 DW boundary */
 880         sdma_v4_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 881
 882         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 883                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 884         /* base must be 32 byte aligned */
 885         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 886         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 887         amdgpu_ring_write(ring, ib->length_dw);
 888         amdgpu_ring_write(ring, 0);
 889         amdgpu_ring_write(ring, 0);
 890
 891 }
 892
 893 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring,
 894                                    int mem_space, int hdp,
 895                                    uint32_t addr0, uint32_t addr1,
 896                                    uint32_t ref, uint32_t mask,
 897                                    uint32_t inv)
 898 {
 899         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 900                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) |
 901                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) |
 902                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 903         if (mem_space) {
 904                 /* memory */
 905                 amdgpu_ring_write(ring, addr0);
 906                 amdgpu_ring_write(ring, addr1);
 907         } else {
 908                 /* registers */
 909                 amdgpu_ring_write(ring, addr0 << 2);
 910                 amdgpu_ring_write(ring, addr1 << 2);
 911         }
 912         amdgpu_ring_write(ring, ref); /* reference */
 913         amdgpu_ring_write(ring, mask); /* mask */
 914         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 915                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */
 916 }
 917
 918 /**
 919  * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 920  *
 921  * @ring: amdgpu ring pointer
 922  *
 923  * Emit an hdp flush packet on the requested DMA ring.
 924  */
 925 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 926 {
 927         struct amdgpu_device *adev = ring->adev;
 928         u32 ref_and_mask = 0;
 929         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 930
 931         ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
 932
 933         sdma_v4_0_wait_reg_mem(ring, 0, 1,
 934                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
 935                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
 936                                ref_and_mask, ref_and_mask, 10);
 937 }
 938
 939 /**
 940  * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring
 941  *
 942  * @ring: amdgpu ring pointer
 943  * @addr: address
 944  * @seq: sequence number
 945  * @flags: fence related flags
 946  *
 947  * Add a DMA fence packet to the ring to write
 948  * the fence seq number and DMA trap packet to generate
 949  * an interrupt if needed (VEGA10).
 950  */
 951 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 952                                       unsigned flags)
 953 {
 954         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 955         /* write the fence */
 956         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 957         /* zero in first two bits */
 958         BUG_ON(addr & 0x3);
 959         amdgpu_ring_write(ring, lower_32_bits(addr));
 960         amdgpu_ring_write(ring, upper_32_bits(addr));
 961         amdgpu_ring_write(ring, lower_32_bits(seq));
 962
 963         /* optionally write high bits as well */
 964         if (write64bit) {
 965                 addr += 4;
 966                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 967                 /* zero in first two bits */
 968                 BUG_ON(addr & 0x3);
 969                 amdgpu_ring_write(ring, lower_32_bits(addr));
 970                 amdgpu_ring_write(ring, upper_32_bits(addr));
 971                 amdgpu_ring_write(ring, upper_32_bits(seq));
 972         }
 973
 974         /* generate an interrupt */
 975         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 976         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 977 }
 978
 979
 980 /**
 981  * sdma_v4_0_gfx_stop - stop the gfx async dma engines
 982  *
 983  * @adev: amdgpu_device pointer
 984  *
 985  * Stop the gfx async dma ring buffers (VEGA10).
 986  */
 987 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev)
 988 {
 989         struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
 990         u32 rb_cntl, ib_cntl;
 991         int i, unset = 0;
 992
 993         for (i = 0; i < adev->sdma.num_instances; i++) {
 994                 sdma[i] = &adev->sdma.instance[i].ring;
 995
 996                 if ((adev->mman.buffer_funcs_ring == sdma[i]) && unset != 1) {
 997                         amdgpu_ttm_set_buffer_funcs_status(adev, false);
 998                         unset = 1;
 999                 }
1000
1001                 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
1002                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
1003                 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
1004                 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
1005                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
1006                 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
1007         }
1008 }
1009
1010 /**
1011  * sdma_v4_0_rlc_stop - stop the compute async dma engines
1012  *
1013  * @adev: amdgpu_device pointer
1014  *
1015  * Stop the compute async dma queues (VEGA10).
1016  */
1017 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev)
1018 {
1019         /* XXX todo */
1020 }
1021
1022 /**
1023  * sdma_v4_0_page_stop - stop the page async dma engines
1024  *
1025  * @adev: amdgpu_device pointer
1026  *
1027  * Stop the page async dma ring buffers (VEGA10).
1028  */
1029 static void sdma_v4_0_page_stop(struct amdgpu_device *adev)
1030 {
1031         struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
1032         u32 rb_cntl, ib_cntl;
1033         int i;
1034         bool unset = false;
1035
1036         for (i = 0; i < adev->sdma.num_instances; i++) {
1037                 sdma[i] = &adev->sdma.instance[i].page;
1038
1039                 if ((adev->mman.buffer_funcs_ring == sdma[i]) &&
1040                         (!unset)) {
1041                         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1042                         unset = true;
1043                 }
1044
1045                 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);
1046                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
1047                                         RB_ENABLE, 0);
1048                 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
1049                 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL);
1050                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL,
1051                                         IB_ENABLE, 0);
1052                 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
1053         }
1054 }
1055
1056 /**
1057  * sdma_v4_0_ctx_switch_enable - stop the async dma engines context switch
1058  *
1059  * @adev: amdgpu_device pointer
1060  * @enable: enable/disable the DMA MEs context switch.
1061  *
1062  * Halt or unhalt the async dma engines context switch (VEGA10).
1063  */
1064 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
1065 {
1066         u32 f32_cntl, phase_quantum = 0;
1067         int i;
1068
1069         if (amdgpu_sdma_phase_quantum) {
1070                 unsigned value = amdgpu_sdma_phase_quantum;
1071                 unsigned unit = 0;
1072
1073                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
1074                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
1075                         value = (value + 1) >> 1;
1076                         unit++;
1077                 }
1078                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
1079                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
1080                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
1081                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
1082                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
1083                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
1084                         WARN_ONCE(1,
1085                         "clamping sdma_phase_quantum to %uK clock cycles\n",
1086                                   value << unit);
1087                 }
1088                 phase_quantum =
1089                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
1090                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
1091         }
1092
1093         for (i = 0; i < adev->sdma.num_instances; i++) {
1094                 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL);
1095                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
1096                                 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
1097                 if (enable && amdgpu_sdma_phase_quantum) {
1098                         WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum);
1099                         WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum);
1100                         WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum);
1101                 }
1102                 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl);
1103
1104                 /*
1105                  * Enable SDMA utilization. Its only supported on
1106                  * Arcturus for the moment and firmware version 14
1107                  * and above.
1108                  */
1109                 if (adev->asic_type == CHIP_ARCTURUS &&
1110                     adev->sdma.instance[i].fw_version >= 14)
1111                         WREG32_SDMA(i, mmSDMA0_PUB_DUMMY_REG2, enable);
1112         }
1113
1114 }
1115
1116 /**
1117  * sdma_v4_0_enable - stop the async dma engines
1118  *
1119  * @adev: amdgpu_device pointer
1120  * @enable: enable/disable the DMA MEs.
1121  *
1122  * Halt or unhalt the async dma engines (VEGA10).
1123  */
1124 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable)
1125 {
1126         u32 f32_cntl;
1127         int i;
1128
1129         if (!enable) {
1130                 sdma_v4_0_gfx_stop(adev);
1131                 sdma_v4_0_rlc_stop(adev);
1132                 if (adev->sdma.has_page_queue)
1133                         sdma_v4_0_page_stop(adev);
1134         }
1135
1136         for (i = 0; i < adev->sdma.num_instances; i++) {
1137                 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
1138                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
1139                 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl);
1140         }
1141 }
1142
1143 /*
1144  * sdma_v4_0_rb_cntl - get parameters for rb_cntl
1145  */
1146 static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl)
1147 {
1148         /* Set ring buffer size in dwords */
1149         uint32_t rb_bufsz = order_base_2(ring->ring_size / 4);
1150
1151         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
1152 #ifdef __BIG_ENDIAN
1153         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
1154         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
1155                                 RPTR_WRITEBACK_SWAP_ENABLE, 1);
1156 #endif
1157         return rb_cntl;
1158 }
1159
1160 /**
1161  * sdma_v4_0_gfx_resume - setup and start the async dma engines
1162  *
1163  * @adev: amdgpu_device pointer
1164  * @i: instance to resume
1165  *
1166  * Set up the gfx DMA ring buffers and enable them (VEGA10).
1167  * Returns 0 for success, error for failure.
1168  */
1169 static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i)
1170 {
1171         struct amdgpu_ring *ring = &adev->sdma.instance[i].ring;
1172         u32 rb_cntl, ib_cntl, wptr_poll_cntl;
1173         u32 wb_offset;
1174         u32 doorbell;
1175         u32 doorbell_offset;
1176         u64 wptr_gpu_addr;
1177
1178         wb_offset = (ring->rptr_offs * 4);
1179
1180         rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
1181         rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl);
1182         WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
1183
1184         /* Initialize the ring buffer's read and write pointers */
1185         WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0);
1186         WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0);
1187         WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0);
1188         WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0);
1189
1190         /* set the wb address whether it's enabled or not */
1191         WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI,
1192                upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
1193         WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO,
1194                lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
1195
1196         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
1197                                 RPTR_WRITEBACK_ENABLE, 1);
1198
1199         WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8);
1200         WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40);
1201
1202         ring->wptr = 0;
1203
1204         /* before programing wptr to a less value, need set minor_ptr_update first */
1205         WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1);
1206
1207         doorbell = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL);
1208         doorbell_offset = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET);
1209
1210         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE,
1211                                  ring->use_doorbell);
1212         doorbell_offset = REG_SET_FIELD(doorbell_offset,
1213                                         SDMA0_GFX_DOORBELL_OFFSET,
1214                                         OFFSET, ring->doorbell_index);
1215         WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell);
1216         WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset);
1217
1218         sdma_v4_0_ring_set_wptr(ring);
1219
1220         /* set minor_ptr_update to 0 after wptr programed */
1221         WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0);
1222
1223         /* setup the wptr shadow polling */
1224         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1225         WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO,
1226                     lower_32_bits(wptr_gpu_addr));
1227         WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI,
1228                     upper_32_bits(wptr_gpu_addr));
1229         wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL);
1230         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
1231                                        SDMA0_GFX_RB_WPTR_POLL_CNTL,
1232                                        F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
1233         WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
1234
1235         /* enable DMA RB */
1236         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
1237         WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
1238
1239         ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
1240         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
1241 #ifdef __BIG_ENDIAN
1242         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
1243 #endif
1244         /* enable DMA IBs */
1245         WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
1246
1247         ring->sched.ready = true;
1248 }
1249
1250 /**
1251  * sdma_v4_0_page_resume - setup and start the async dma engines
1252  *
1253  * @adev: amdgpu_device pointer
1254  * @i: instance to resume
1255  *
1256  * Set up the page DMA ring buffers and enable them (VEGA10).
1257  * Returns 0 for success, error for failure.
1258  */
1259 static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i)
1260 {
1261         struct amdgpu_ring *ring = &adev->sdma.instance[i].page;
1262         u32 rb_cntl, ib_cntl, wptr_poll_cntl;
1263         u32 wb_offset;
1264         u32 doorbell;
1265         u32 doorbell_offset;
1266         u64 wptr_gpu_addr;
1267
1268         wb_offset = (ring->rptr_offs * 4);
1269
1270         rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);
1271         rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl);
1272         WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
1273
1274         /* Initialize the ring buffer's read and write pointers */
1275         WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR, 0);
1276         WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_HI, 0);
1277         WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR, 0);
1278         WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_HI, 0);
1279
1280         /* set the wb address whether it's enabled or not */
1281         WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_HI,
1282                upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
1283         WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_LO,
1284                lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
1285
1286         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
1287                                 RPTR_WRITEBACK_ENABLE, 1);
1288
1289         WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE, ring->gpu_addr >> 8);
1290         WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE_HI, ring->gpu_addr >> 40);
1291
1292         ring->wptr = 0;
1293
1294         /* before programing wptr to a less value, need set minor_ptr_update first */
1295         WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 1);
1296
1297         doorbell = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL);
1298         doorbell_offset = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET);
1299
1300         doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE,
1301                                  ring->use_doorbell);
1302         doorbell_offset = REG_SET_FIELD(doorbell_offset,
1303                                         SDMA0_PAGE_DOORBELL_OFFSET,
1304                                         OFFSET, ring->doorbell_index);
1305         WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell);
1306         WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset);
1307
1308         /* paging queue doorbell range is setup at sdma_v4_0_gfx_resume */
1309         sdma_v4_0_page_ring_set_wptr(ring);
1310
1311         /* set minor_ptr_update to 0 after wptr programed */
1312         WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0);
1313
1314         /* setup the wptr shadow polling */
1315         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1316         WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO,
1317                     lower_32_bits(wptr_gpu_addr));
1318         WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI,
1319                     upper_32_bits(wptr_gpu_addr));
1320         wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL);
1321         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
1322                                        SDMA0_PAGE_RB_WPTR_POLL_CNTL,
1323                                        F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
1324         WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
1325
1326         /* enable DMA RB */
1327         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1);
1328         WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
1329
1330         ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL);
1331         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_ENABLE, 1);
1332 #ifdef __BIG_ENDIAN
1333         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1);
1334 #endif
1335         /* enable DMA IBs */
1336         WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
1337
1338         ring->sched.ready = true;
1339 }
1340
1341 static void
1342 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable)
1343 {
1344         uint32_t def, data;
1345
1346         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) {
1347                 /* enable idle interrupt */
1348                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1349                 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1350
1351                 if (data != def)
1352                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1353         } else {
1354                 /* disable idle interrupt */
1355                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1356                 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1357                 if (data != def)
1358                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1359         }
1360 }
1361
1362 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev)
1363 {
1364         uint32_t def, data;
1365
1366         /* Enable HW based PG. */
1367         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1368         data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK;
1369         if (data != def)
1370                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1371
1372         /* enable interrupt */
1373         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1374         data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1375         if (data != def)
1376                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1377
1378         /* Configure hold time to filter in-valid power on/off request. Use default right now */
1379         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1380         data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK;
1381         data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK);
1382         /* Configure switch time for hysteresis purpose. Use default right now */
1383         data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK;
1384         data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK);
1385         if(data != def)
1386                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1387 }
1388
1389 static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
1390 {
1391         if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA))
1392                 return;
1393
1394         switch (adev->asic_type) {
1395         case CHIP_RAVEN:
1396         case CHIP_RENOIR:
1397                 sdma_v4_1_init_power_gating(adev);
1398                 sdma_v4_1_update_power_gating(adev, true);
1399                 break;
1400         default:
1401                 break;
1402         }
1403 }
1404
1405 /**
1406  * sdma_v4_0_rlc_resume - setup and start the async dma engines
1407  *
1408  * @adev: amdgpu_device pointer
1409  *
1410  * Set up the compute DMA queues and enable them (VEGA10).
1411  * Returns 0 for success, error for failure.
1412  */
1413 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev)
1414 {
1415         sdma_v4_0_init_pg(adev);
1416
1417         return 0;
1418 }
1419
1420 /**
1421  * sdma_v4_0_load_microcode - load the sDMA ME ucode
1422  *
1423  * @adev: amdgpu_device pointer
1424  *
1425  * Loads the sDMA0/1 ucode.
1426  * Returns 0 for success, -EINVAL if the ucode is not available.
1427  */
1428 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev)
1429 {
1430         const struct sdma_firmware_header_v1_0 *hdr;
1431         const __le32 *fw_data;
1432         u32 fw_size;
1433         int i, j;
1434
1435         /* halt the MEs */
1436         sdma_v4_0_enable(adev, false);
1437
1438         for (i = 0; i < adev->sdma.num_instances; i++) {
1439                 if (!adev->sdma.instance[i].fw)
1440                         return -EINVAL;
1441
1442                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
1443                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
1444                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1445
1446                 fw_data = (const __le32 *)
1447                         (adev->sdma.instance[i].fw->data +
1448                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1449
1450                 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0);
1451
1452                 for (j = 0; j < fw_size; j++)
1453                         WREG32_SDMA(i, mmSDMA0_UCODE_DATA,
1454                                     le32_to_cpup(fw_data++));
1455
1456                 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR,
1457                             adev->sdma.instance[i].fw_version);
1458         }
1459
1460         return 0;
1461 }
1462
1463 /**
1464  * sdma_v4_0_start - setup and start the async dma engines
1465  *
1466  * @adev: amdgpu_device pointer
1467  *
1468  * Set up the DMA engines and enable them (VEGA10).
1469  * Returns 0 for success, error for failure.
1470  */
1471 static int sdma_v4_0_start(struct amdgpu_device *adev)
1472 {
1473         struct amdgpu_ring *ring;
1474         int i, r = 0;
1475
1476         if (amdgpu_sriov_vf(adev)) {
1477                 sdma_v4_0_ctx_switch_enable(adev, false);
1478                 sdma_v4_0_enable(adev, false);
1479         } else {
1480
1481                 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1482                         r = sdma_v4_0_load_microcode(adev);
1483                         if (r)
1484                                 return r;
1485                 }
1486
1487                 /* unhalt the MEs */
1488                 sdma_v4_0_enable(adev, true);
1489                 /* enable sdma ring preemption */
1490                 sdma_v4_0_ctx_switch_enable(adev, true);
1491         }
1492
1493         /* start the gfx rings and rlc compute queues */
1494         for (i = 0; i < adev->sdma.num_instances; i++) {
1495                 uint32_t temp;
1496
1497                 WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0);
1498                 sdma_v4_0_gfx_resume(adev, i);
1499                 if (adev->sdma.has_page_queue)
1500                         sdma_v4_0_page_resume(adev, i);
1501
1502                 /* set utc l1 enable flag always to 1 */
1503                 temp = RREG32_SDMA(i, mmSDMA0_CNTL);
1504                 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
1505                 WREG32_SDMA(i, mmSDMA0_CNTL, temp);
1506
1507                 if (!amdgpu_sriov_vf(adev)) {
1508                         /* unhalt engine */
1509                         temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
1510                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
1511                         WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp);
1512                 }
1513         }
1514
1515         if (amdgpu_sriov_vf(adev)) {
1516                 sdma_v4_0_ctx_switch_enable(adev, true);
1517                 sdma_v4_0_enable(adev, true);
1518         } else {
1519                 r = sdma_v4_0_rlc_resume(adev);
1520                 if (r)
1521                         return r;
1522         }
1523
1524         for (i = 0; i < adev->sdma.num_instances; i++) {
1525                 ring = &adev->sdma.instance[i].ring;
1526
1527                 r = amdgpu_ring_test_helper(ring);
1528                 if (r)
1529                         return r;
1530
1531                 if (adev->sdma.has_page_queue) {
1532                         struct amdgpu_ring *page = &adev->sdma.instance[i].page;
1533
1534                         r = amdgpu_ring_test_helper(page);
1535                         if (r)
1536                                 return r;
1537
1538                         if (adev->mman.buffer_funcs_ring == page)
1539                                 amdgpu_ttm_set_buffer_funcs_status(adev, true);
1540                 }
1541
1542                 if (adev->mman.buffer_funcs_ring == ring)
1543                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
1544         }
1545
1546         return r;
1547 }
1548
1549 /**
1550  * sdma_v4_0_ring_test_ring - simple async dma engine test
1551  *
1552  * @ring: amdgpu_ring structure holding ring information
1553  *
1554  * Test the DMA engine by writing using it to write an
1555  * value to memory. (VEGA10).
1556  * Returns 0 for success, error for failure.
1557  */
1558 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring)
1559 {
1560         struct amdgpu_device *adev = ring->adev;
1561         unsigned i;
1562         unsigned index;
1563         int r;
1564         u32 tmp;
1565         u64 gpu_addr;
1566
1567         r = amdgpu_device_wb_get(adev, &index);
1568         if (r)
1569                 return r;
1570
1571         gpu_addr = adev->wb.gpu_addr + (index * 4);
1572         tmp = 0xCAFEDEAD;
1573         adev->wb.wb[index] = cpu_to_le32(tmp);
1574
1575         r = amdgpu_ring_alloc(ring, 5);
1576         if (r)
1577                 goto error_free_wb;
1578
1579         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1580                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
1581         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
1582         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
1583         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
1584         amdgpu_ring_write(ring, 0xDEADBEEF);
1585         amdgpu_ring_commit(ring);
1586
1587         for (i = 0; i < adev->usec_timeout; i++) {
1588                 tmp = le32_to_cpu(adev->wb.wb[index]);
1589                 if (tmp == 0xDEADBEEF)
1590                         break;
1591                 udelay(1);
1592         }
1593
1594         if (i >= adev->usec_timeout)
1595                 r = -ETIMEDOUT;
1596
1597 error_free_wb:
1598         amdgpu_device_wb_free(adev, index);
1599         return r;
1600 }
1601
1602 /**
1603  * sdma_v4_0_ring_test_ib - test an IB on the DMA engine
1604  *
1605  * @ring: amdgpu_ring structure holding ring information
1606  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1607  *
1608  * Test a simple IB in the DMA ring (VEGA10).
1609  * Returns 0 on success, error on failure.
1610  */
1611 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1612 {
1613         struct amdgpu_device *adev = ring->adev;
1614         struct amdgpu_ib ib;
1615         struct dma_fence *f = NULL;
1616         unsigned index;
1617         long r;
1618         u32 tmp = 0;
1619         u64 gpu_addr;
1620
1621         r = amdgpu_device_wb_get(adev, &index);
1622         if (r)
1623                 return r;
1624
1625         gpu_addr = adev->wb.gpu_addr + (index * 4);
1626         tmp = 0xCAFEDEAD;
1627         adev->wb.wb[index] = cpu_to_le32(tmp);
1628         memset(&ib, 0, sizeof(ib));
1629         r = amdgpu_ib_get(adev, NULL, 256,
1630                                         AMDGPU_IB_POOL_DIRECT, &ib);
1631         if (r)
1632                 goto err0;
1633
1634         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1635                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1636         ib.ptr[1] = lower_32_bits(gpu_addr);
1637         ib.ptr[2] = upper_32_bits(gpu_addr);
1638         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1639         ib.ptr[4] = 0xDEADBEEF;
1640         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1641         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1642         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1643         ib.length_dw = 8;
1644
1645         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1646         if (r)
1647                 goto err1;
1648
1649         r = dma_fence_wait_timeout(f, false, timeout);
1650         if (r == 0) {
1651                 r = -ETIMEDOUT;
1652                 goto err1;
1653         } else if (r < 0) {
1654                 goto err1;
1655         }
1656         tmp = le32_to_cpu(adev->wb.wb[index]);
1657         if (tmp == 0xDEADBEEF)
1658                 r = 0;
1659         else
1660                 r = -EINVAL;
1661
1662 err1:
1663         amdgpu_ib_free(adev, &ib, NULL);
1664         dma_fence_put(f);
1665 err0:
1666         amdgpu_device_wb_free(adev, index);
1667         return r;
1668 }
1669
1670
1671 /**
1672  * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART
1673  *
1674  * @ib: indirect buffer to fill with commands
1675  * @pe: addr of the page entry
1676  * @src: src addr to copy from
1677  * @count: number of page entries to update
1678  *
1679  * Update PTEs by copying them from the GART using sDMA (VEGA10).
1680  */
1681 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib,
1682                                   uint64_t pe, uint64_t src,
1683                                   unsigned count)
1684 {
1685         unsigned bytes = count * 8;
1686
1687         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1688                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1689         ib->ptr[ib->length_dw++] = bytes - 1;
1690         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1691         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1692         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1693         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1694         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1695
1696 }
1697
1698 /**
1699  * sdma_v4_0_vm_write_pte - update PTEs by writing them manually
1700  *
1701  * @ib: indirect buffer to fill with commands
1702  * @pe: addr of the page entry
1703  * @value: dst addr to write into pe
1704  * @count: number of page entries to update
1705  * @incr: increase next addr by incr bytes
1706  *
1707  * Update PTEs by writing them manually using sDMA (VEGA10).
1708  */
1709 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1710                                    uint64_t value, unsigned count,
1711                                    uint32_t incr)
1712 {
1713         unsigned ndw = count * 2;
1714
1715         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1716                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1717         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1718         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1719         ib->ptr[ib->length_dw++] = ndw - 1;
1720         for (; ndw > 0; ndw -= 2) {
1721                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1722                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1723                 value += incr;
1724         }
1725 }
1726
1727 /**
1728  * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA
1729  *
1730  * @ib: indirect buffer to fill with commands
1731  * @pe: addr of the page entry
1732  * @addr: dst addr to write into pe
1733  * @count: number of page entries to update
1734  * @incr: increase next addr by incr bytes
1735  * @flags: access flags
1736  *
1737  * Update the page tables using sDMA (VEGA10).
1738  */
1739 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1740                                      uint64_t pe,
1741                                      uint64_t addr, unsigned count,
1742                                      uint32_t incr, uint64_t flags)
1743 {
1744         /* for physically contiguous pages (vram) */
1745         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1746         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1747         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1748         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1749         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1750         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1751         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1752         ib->ptr[ib->length_dw++] = incr; /* increment size */
1753         ib->ptr[ib->length_dw++] = 0;
1754         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1755 }
1756
1757 /**
1758  * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw
1759  *
1760  * @ring: amdgpu_ring structure holding ring information
1761  * @ib: indirect buffer to fill with padding
1762  */
1763 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1764 {
1765         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1766         u32 pad_count;
1767         int i;
1768
1769         pad_count = (-ib->length_dw) & 7;
1770         for (i = 0; i < pad_count; i++)
1771                 if (sdma && sdma->burst_nop && (i == 0))
1772                         ib->ptr[ib->length_dw++] =
1773                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1774                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1775                 else
1776                         ib->ptr[ib->length_dw++] =
1777                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1778 }
1779
1780
1781 /**
1782  * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline
1783  *
1784  * @ring: amdgpu_ring pointer
1785  *
1786  * Make sure all previous operations are completed (CIK).
1787  */
1788 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1789 {
1790         uint32_t seq = ring->fence_drv.sync_seq;
1791         uint64_t addr = ring->fence_drv.gpu_addr;
1792
1793         /* wait for idle */
1794         sdma_v4_0_wait_reg_mem(ring, 1, 0,
1795                                addr & 0xfffffffc,
1796                                upper_32_bits(addr) & 0xffffffff,
1797                                seq, 0xffffffff, 4);
1798 }
1799
1800
1801 /**
1802  * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA
1803  *
1804  * @ring: amdgpu_ring pointer
1805  * @vmid: vmid number to use
1806  * @pd_addr: address
1807  *
1808  * Update the page table base and flush the VM TLB
1809  * using sDMA (VEGA10).
1810  */
1811 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1812                                          unsigned vmid, uint64_t pd_addr)
1813 {
1814         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1815 }
1816
1817 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring,
1818                                      uint32_t reg, uint32_t val)
1819 {
1820         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1821                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1822         amdgpu_ring_write(ring, reg);
1823         amdgpu_ring_write(ring, val);
1824 }
1825
1826 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1827                                          uint32_t val, uint32_t mask)
1828 {
1829         sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
1830 }
1831
1832 static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev)
1833 {
1834         uint fw_version = adev->sdma.instance[0].fw_version;
1835
1836         switch (adev->asic_type) {
1837         case CHIP_VEGA10:
1838                 return fw_version >= 430;
1839         case CHIP_VEGA12:
1840                 /*return fw_version >= 31;*/
1841                 return false;
1842         case CHIP_VEGA20:
1843                 return fw_version >= 123;
1844         default:
1845                 return false;
1846         }
1847 }
1848
1849 static int sdma_v4_0_early_init(void *handle)
1850 {
1851         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1852         int r;
1853
1854         if (adev->flags & AMD_IS_APU)
1855                 adev->sdma.num_instances = 1;
1856         else if (adev->asic_type == CHIP_ARCTURUS)
1857                 adev->sdma.num_instances = 8;
1858         else if (adev->asic_type == CHIP_ALDEBARAN)
1859                 adev->sdma.num_instances = 5;
1860         else
1861                 adev->sdma.num_instances = 2;
1862
1863         r = sdma_v4_0_init_microcode(adev);
1864         if (r) {
1865                 DRM_ERROR("Failed to load sdma firmware!\n");
1866                 return r;
1867         }
1868
1869         /* TODO: Page queue breaks driver reload under SRIOV */
1870         if ((adev->asic_type == CHIP_VEGA10) && amdgpu_sriov_vf((adev)))
1871                 adev->sdma.has_page_queue = false;
1872         else if (sdma_v4_0_fw_support_paging_queue(adev))
1873                 adev->sdma.has_page_queue = true;
1874
1875         sdma_v4_0_set_ring_funcs(adev);
1876         sdma_v4_0_set_buffer_funcs(adev);
1877         sdma_v4_0_set_vm_pte_funcs(adev);
1878         sdma_v4_0_set_irq_funcs(adev);
1879         sdma_v4_0_set_ras_funcs(adev);
1880
1881         return 0;
1882 }
1883
1884 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
1885                 void *err_data,
1886                 struct amdgpu_iv_entry *entry);
1887
1888 static int sdma_v4_0_late_init(void *handle)
1889 {
1890         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1891         struct ras_ih_if ih_info = {
1892                 .cb = sdma_v4_0_process_ras_data_cb,
1893         };
1894
1895         sdma_v4_0_setup_ulv(adev);
1896
1897         if (adev->sdma.funcs && adev->sdma.funcs->reset_ras_error_count)
1898                 adev->sdma.funcs->reset_ras_error_count(adev);
1899
1900         if (adev->sdma.funcs && adev->sdma.funcs->ras_late_init)
1901                 return adev->sdma.funcs->ras_late_init(adev, &ih_info);
1902         else
1903                 return 0;
1904 }
1905
1906 static int sdma_v4_0_sw_init(void *handle)
1907 {
1908         struct amdgpu_ring *ring;
1909         int r, i;
1910         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1911
1912         /* SDMA trap event */
1913         for (i = 0; i < adev->sdma.num_instances; i++) {
1914                 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1915                                       SDMA0_4_0__SRCID__SDMA_TRAP,
1916                                       &adev->sdma.trap_irq);
1917                 if (r)
1918                         return r;
1919         }
1920
1921         /* SDMA SRAM ECC event */
1922         for (i = 0; i < adev->sdma.num_instances; i++) {
1923                 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1924                                       SDMA0_4_0__SRCID__SDMA_SRAM_ECC,
1925                                       &adev->sdma.ecc_irq);
1926                 if (r)
1927                         return r;
1928         }
1929
1930         /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/
1931         for (i = 0; i < adev->sdma.num_instances; i++) {
1932                 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1933                                       SDMA0_4_0__SRCID__SDMA_VM_HOLE,
1934                                       &adev->sdma.vm_hole_irq);
1935                 if (r)
1936                         return r;
1937
1938                 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1939                                       SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID,
1940                                       &adev->sdma.doorbell_invalid_irq);
1941                 if (r)
1942                         return r;
1943
1944                 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1945                                       SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT,
1946                                       &adev->sdma.pool_timeout_irq);
1947                 if (r)
1948                         return r;
1949
1950                 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1951                                       SDMA0_4_0__SRCID__SDMA_SRBMWRITE,
1952                                       &adev->sdma.srbm_write_irq);
1953                 if (r)
1954                         return r;
1955         }
1956
1957         for (i = 0; i < adev->sdma.num_instances; i++) {
1958                 ring = &adev->sdma.instance[i].ring;
1959                 ring->ring_obj = NULL;
1960                 ring->use_doorbell = true;
1961
1962                 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1963                                 ring->use_doorbell?"true":"false");
1964
1965                 /* doorbell size is 2 dwords, get DWORD offset */
1966                 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1967
1968                 sprintf(ring->name, "sdma%d", i);
1969                 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1970                                      AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1971                                      AMDGPU_RING_PRIO_DEFAULT);
1972                 if (r)
1973                         return r;
1974
1975                 if (adev->sdma.has_page_queue) {
1976                         ring = &adev->sdma.instance[i].page;
1977                         ring->ring_obj = NULL;
1978                         ring->use_doorbell = true;
1979
1980                         /* paging queue use same doorbell index/routing as gfx queue
1981                          * with 0x400 (4096 dwords) offset on second doorbell page
1982                          */
1983                         ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1984                         ring->doorbell_index += 0x400;
1985
1986                         sprintf(ring->name, "page%d", i);
1987                         r = amdgpu_ring_init(adev, ring, 1024,
1988                                              &adev->sdma.trap_irq,
1989                                              AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1990                                              AMDGPU_RING_PRIO_DEFAULT);
1991                         if (r)
1992                                 return r;
1993                 }
1994         }
1995
1996         return r;
1997 }
1998
1999 static int sdma_v4_0_sw_fini(void *handle)
2000 {
2001         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2002         int i;
2003
2004         if (adev->sdma.funcs && adev->sdma.funcs->ras_fini)
2005                 adev->sdma.funcs->ras_fini(adev);
2006
2007         for (i = 0; i < adev->sdma.num_instances; i++) {
2008                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
2009                 if (adev->sdma.has_page_queue)
2010                         amdgpu_ring_fini(&adev->sdma.instance[i].page);
2011         }
2012
2013         sdma_v4_0_destroy_inst_ctx(adev);
2014
2015         return 0;
2016 }
2017
2018 static int sdma_v4_0_hw_init(void *handle)
2019 {
2020         int r;
2021         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2022
2023         if (adev->flags & AMD_IS_APU)
2024                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false);
2025
2026         if (!amdgpu_sriov_vf(adev))
2027                 sdma_v4_0_init_golden_registers(adev);
2028
2029         r = sdma_v4_0_start(adev);
2030
2031         return r;
2032 }
2033
2034 static int sdma_v4_0_hw_fini(void *handle)
2035 {
2036         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2037         int i;
2038
2039         if (amdgpu_sriov_vf(adev))
2040                 return 0;
2041
2042         for (i = 0; i < adev->sdma.num_instances; i++) {
2043                 amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
2044                                AMDGPU_SDMA_IRQ_INSTANCE0 + i);
2045         }
2046
2047         sdma_v4_0_ctx_switch_enable(adev, false);
2048         sdma_v4_0_enable(adev, false);
2049
2050         if (adev->flags & AMD_IS_APU)
2051                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true);
2052
2053         return 0;
2054 }
2055
2056 static int sdma_v4_0_suspend(void *handle)
2057 {
2058         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2059
2060         return sdma_v4_0_hw_fini(adev);
2061 }
2062
2063 static int sdma_v4_0_resume(void *handle)
2064 {
2065         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2066
2067         return sdma_v4_0_hw_init(adev);
2068 }
2069
2070 static bool sdma_v4_0_is_idle(void *handle)
2071 {
2072         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2073         u32 i;
2074
2075         for (i = 0; i < adev->sdma.num_instances; i++) {
2076                 u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG);
2077
2078                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
2079                         return false;
2080         }
2081
2082         return true;
2083 }
2084
2085 static int sdma_v4_0_wait_for_idle(void *handle)
2086 {
2087         unsigned i, j;
2088         u32 sdma[AMDGPU_MAX_SDMA_INSTANCES];
2089         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2090
2091         for (i = 0; i < adev->usec_timeout; i++) {
2092                 for (j = 0; j < adev->sdma.num_instances; j++) {
2093                         sdma[j] = RREG32_SDMA(j, mmSDMA0_STATUS_REG);
2094                         if (!(sdma[j] & SDMA0_STATUS_REG__IDLE_MASK))
2095                                 break;
2096                 }
2097                 if (j == adev->sdma.num_instances)
2098                         return 0;
2099                 udelay(1);
2100         }
2101         return -ETIMEDOUT;
2102 }
2103
2104 static int sdma_v4_0_soft_reset(void *handle)
2105 {
2106         /* todo */
2107
2108         return 0;
2109 }
2110
2111 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev,
2112                                         struct amdgpu_irq_src *source,
2113                                         unsigned type,
2114                                         enum amdgpu_interrupt_state state)
2115 {
2116         u32 sdma_cntl;
2117
2118         sdma_cntl = RREG32_SDMA(type, mmSDMA0_CNTL);
2119         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
2120                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
2121         WREG32_SDMA(type, mmSDMA0_CNTL, sdma_cntl);
2122
2123         return 0;
2124 }
2125
2126 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
2127                                       struct amdgpu_irq_src *source,
2128                                       struct amdgpu_iv_entry *entry)
2129 {
2130         uint32_t instance;
2131
2132         DRM_DEBUG("IH: SDMA trap\n");
2133         instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2134         switch (entry->ring_id) {
2135         case 0:
2136                 amdgpu_fence_process(&adev->sdma.instance[instance].ring);
2137                 break;
2138         case 1:
2139                 if (adev->asic_type == CHIP_VEGA20)
2140                         amdgpu_fence_process(&adev->sdma.instance[instance].page);
2141                 break;
2142         case 2:
2143                 /* XXX compute */
2144                 break;
2145         case 3:
2146                 if (adev->asic_type != CHIP_VEGA20)
2147                         amdgpu_fence_process(&adev->sdma.instance[instance].page);
2148                 break;
2149         }
2150         return 0;
2151 }
2152
2153 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
2154                 void *err_data,
2155                 struct amdgpu_iv_entry *entry)
2156 {
2157         int instance;
2158
2159         /* When “Full RAS” is enabled, the per-IP interrupt sources should
2160          * be disabled and the driver should only look for the aggregated
2161          * interrupt via sync flood
2162          */
2163         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
2164                 goto out;
2165
2166         instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2167         if (instance < 0)
2168                 goto out;
2169
2170         amdgpu_sdma_process_ras_data_cb(adev, err_data, entry);
2171
2172 out:
2173         return AMDGPU_RAS_SUCCESS;
2174 }
2175
2176 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev,
2177                                               struct amdgpu_irq_src *source,
2178                                               struct amdgpu_iv_entry *entry)
2179 {
2180         int instance;
2181
2182         DRM_ERROR("Illegal instruction in SDMA command stream\n");
2183
2184         instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2185         if (instance < 0)
2186                 return 0;
2187
2188         switch (entry->ring_id) {
2189         case 0:
2190                 drm_sched_fault(&adev->sdma.instance[instance].ring.sched);
2191                 break;
2192         }
2193         return 0;
2194 }
2195
2196 static int sdma_v4_0_set_ecc_irq_state(struct amdgpu_device *adev,
2197                                         struct amdgpu_irq_src *source,
2198                                         unsigned type,
2199                                         enum amdgpu_interrupt_state state)
2200 {
2201         u32 sdma_edc_config;
2202
2203         sdma_edc_config = RREG32_SDMA(type, mmSDMA0_EDC_CONFIG);
2204         sdma_edc_config = REG_SET_FIELD(sdma_edc_config, SDMA0_EDC_CONFIG, ECC_INT_ENABLE,
2205                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
2206         WREG32_SDMA(type, mmSDMA0_EDC_CONFIG, sdma_edc_config);
2207
2208         return 0;
2209 }
2210
2211 static int sdma_v4_0_print_iv_entry(struct amdgpu_device *adev,
2212                                               struct amdgpu_iv_entry *entry)
2213 {
2214         int instance;
2215         struct amdgpu_task_info task_info;
2216         u64 addr;
2217
2218         instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2219         if (instance < 0 || instance >= adev->sdma.num_instances) {
2220                 dev_err(adev->dev, "sdma instance invalid %d\n", instance);
2221                 return -EINVAL;
2222         }
2223
2224         addr = (u64)entry->src_data[0] << 12;
2225         addr |= ((u64)entry->src_data[1] & 0xf) << 44;
2226
2227         memset(&task_info, 0, sizeof(struct amdgpu_task_info));
2228         amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
2229
2230         dev_info(adev->dev,
2231                    "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u "
2232                    "pasid:%u, for process %s pid %d thread %s pid %d\n",
2233                    instance, addr, entry->src_id, entry->ring_id, entry->vmid,
2234                    entry->pasid, task_info.process_name, task_info.tgid,
2235                    task_info.task_name, task_info.pid);
2236         return 0;
2237 }
2238
2239 static int sdma_v4_0_process_vm_hole_irq(struct amdgpu_device *adev,
2240                                               struct amdgpu_irq_src *source,
2241                                               struct amdgpu_iv_entry *entry)
2242 {
2243         dev_err(adev->dev, "MC or SEM address in VM hole\n");
2244         sdma_v4_0_print_iv_entry(adev, entry);
2245         return 0;
2246 }
2247
2248 static int sdma_v4_0_process_doorbell_invalid_irq(struct amdgpu_device *adev,
2249                                               struct amdgpu_irq_src *source,
2250                                               struct amdgpu_iv_entry *entry)
2251 {
2252         dev_err(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n");
2253         sdma_v4_0_print_iv_entry(adev, entry);
2254         return 0;
2255 }
2256
2257 static int sdma_v4_0_process_pool_timeout_irq(struct amdgpu_device *adev,
2258                                               struct amdgpu_irq_src *source,
2259                                               struct amdgpu_iv_entry *entry)
2260 {
2261         dev_err(adev->dev,
2262                 "Polling register/memory timeout executing POLL_REG/MEM with finite timer\n");
2263         sdma_v4_0_print_iv_entry(adev, entry);
2264         return 0;
2265 }
2266
2267 static int sdma_v4_0_process_srbm_write_irq(struct amdgpu_device *adev,
2268                                               struct amdgpu_irq_src *source,
2269                                               struct amdgpu_iv_entry *entry)
2270 {
2271         dev_err(adev->dev,
2272                 "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n");
2273         sdma_v4_0_print_iv_entry(adev, entry);
2274         return 0;
2275 }
2276
2277 static void sdma_v4_0_update_medium_grain_clock_gating(
2278                 struct amdgpu_device *adev,
2279                 bool enable)
2280 {
2281         uint32_t data, def;
2282         int i;
2283
2284         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
2285                 for (i = 0; i < adev->sdma.num_instances; i++) {
2286                         def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);
2287                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
2288                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
2289                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
2290                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
2291                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
2292                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
2293                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
2294                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
2295                         if (def != data)
2296                                 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
2297                 }
2298         } else {
2299                 for (i = 0; i < adev->sdma.num_instances; i++) {
2300                         def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);
2301                         data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
2302                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
2303                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
2304                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
2305                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
2306                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
2307                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
2308                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
2309                         if (def != data)
2310                                 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
2311                 }
2312         }
2313 }
2314
2315
2316 static void sdma_v4_0_update_medium_grain_light_sleep(
2317                 struct amdgpu_device *adev,
2318                 bool enable)
2319 {
2320         uint32_t data, def;
2321         int i;
2322
2323         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
2324                 for (i = 0; i < adev->sdma.num_instances; i++) {
2325                         /* 1-not override: enable sdma mem light sleep */
2326                         def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);
2327                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
2328                         if (def != data)
2329                                 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);
2330                 }
2331         } else {
2332                 for (i = 0; i < adev->sdma.num_instances; i++) {
2333                 /* 0-override:disable sdma mem light sleep */
2334                         def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);
2335                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
2336                         if (def != data)
2337                                 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);
2338                 }
2339         }
2340 }
2341
2342 static int sdma_v4_0_set_clockgating_state(void *handle,
2343                                           enum amd_clockgating_state state)
2344 {
2345         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2346
2347         if (amdgpu_sriov_vf(adev))
2348                 return 0;
2349
2350         sdma_v4_0_update_medium_grain_clock_gating(adev,
2351                         state == AMD_CG_STATE_GATE);
2352         sdma_v4_0_update_medium_grain_light_sleep(adev,
2353                         state == AMD_CG_STATE_GATE);
2354         return 0;
2355 }
2356
2357 static int sdma_v4_0_set_powergating_state(void *handle,
2358                                           enum amd_powergating_state state)
2359 {
2360         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2361
2362         switch (adev->asic_type) {
2363         case CHIP_RAVEN:
2364         case CHIP_RENOIR:
2365                 sdma_v4_1_update_power_gating(adev,
2366                                 state == AMD_PG_STATE_GATE);
2367                 break;
2368         default:
2369                 break;
2370         }
2371
2372         return 0;
2373 }
2374
2375 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags)
2376 {
2377         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2378         int data;
2379
2380         if (amdgpu_sriov_vf(adev))
2381                 *flags = 0;
2382
2383         /* AMD_CG_SUPPORT_SDMA_MGCG */
2384         data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
2385         if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
2386                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
2387
2388         /* AMD_CG_SUPPORT_SDMA_LS */
2389         data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
2390         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
2391                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
2392 }
2393
2394 const struct amd_ip_funcs sdma_v4_0_ip_funcs = {
2395         .name = "sdma_v4_0",
2396         .early_init = sdma_v4_0_early_init,
2397         .late_init = sdma_v4_0_late_init,
2398         .sw_init = sdma_v4_0_sw_init,
2399         .sw_fini = sdma_v4_0_sw_fini,
2400         .hw_init = sdma_v4_0_hw_init,
2401         .hw_fini = sdma_v4_0_hw_fini,
2402         .suspend = sdma_v4_0_suspend,
2403         .resume = sdma_v4_0_resume,
2404         .is_idle = sdma_v4_0_is_idle,
2405         .wait_for_idle = sdma_v4_0_wait_for_idle,
2406         .soft_reset = sdma_v4_0_soft_reset,
2407         .set_clockgating_state = sdma_v4_0_set_clockgating_state,
2408         .set_powergating_state = sdma_v4_0_set_powergating_state,
2409         .get_clockgating_state = sdma_v4_0_get_clockgating_state,
2410 };
2411
2412 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
2413         .type = AMDGPU_RING_TYPE_SDMA,
2414         .align_mask = 0xf,
2415         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2416         .support_64bit_ptrs = true,
2417         .vmhub = AMDGPU_MMHUB_0,
2418         .get_rptr = sdma_v4_0_ring_get_rptr,
2419         .get_wptr = sdma_v4_0_ring_get_wptr,
2420         .set_wptr = sdma_v4_0_ring_set_wptr,
2421         .emit_frame_size =
2422                 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2423                 3 + /* hdp invalidate */
2424                 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2425                 /* sdma_v4_0_ring_emit_vm_flush */
2426                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2427                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2428                 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2429         .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2430         .emit_ib = sdma_v4_0_ring_emit_ib,
2431         .emit_fence = sdma_v4_0_ring_emit_fence,
2432         .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2433         .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2434         .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2435         .test_ring = sdma_v4_0_ring_test_ring,
2436         .test_ib = sdma_v4_0_ring_test_ib,
2437         .insert_nop = sdma_v4_0_ring_insert_nop,
2438         .pad_ib = sdma_v4_0_ring_pad_ib,
2439         .emit_wreg = sdma_v4_0_ring_emit_wreg,
2440         .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2441         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2442 };
2443
2444 /*
2445  * On Arcturus, SDMA instance 5~7 has a different vmhub type(AMDGPU_MMHUB_1).
2446  * So create a individual constant ring_funcs for those instances.
2447  */
2448 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs_2nd_mmhub = {
2449         .type = AMDGPU_RING_TYPE_SDMA,
2450         .align_mask = 0xf,
2451         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2452         .support_64bit_ptrs = true,
2453         .vmhub = AMDGPU_MMHUB_1,
2454         .get_rptr = sdma_v4_0_ring_get_rptr,
2455         .get_wptr = sdma_v4_0_ring_get_wptr,
2456         .set_wptr = sdma_v4_0_ring_set_wptr,
2457         .emit_frame_size =
2458                 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2459                 3 + /* hdp invalidate */
2460                 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2461                 /* sdma_v4_0_ring_emit_vm_flush */
2462                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2463                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2464                 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2465         .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2466         .emit_ib = sdma_v4_0_ring_emit_ib,
2467         .emit_fence = sdma_v4_0_ring_emit_fence,
2468         .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2469         .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2470         .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2471         .test_ring = sdma_v4_0_ring_test_ring,
2472         .test_ib = sdma_v4_0_ring_test_ib,
2473         .insert_nop = sdma_v4_0_ring_insert_nop,
2474         .pad_ib = sdma_v4_0_ring_pad_ib,
2475         .emit_wreg = sdma_v4_0_ring_emit_wreg,
2476         .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2477         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2478 };
2479
2480 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = {
2481         .type = AMDGPU_RING_TYPE_SDMA,
2482         .align_mask = 0xf,
2483         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2484         .support_64bit_ptrs = true,
2485         .vmhub = AMDGPU_MMHUB_0,
2486         .get_rptr = sdma_v4_0_ring_get_rptr,
2487         .get_wptr = sdma_v4_0_page_ring_get_wptr,
2488         .set_wptr = sdma_v4_0_page_ring_set_wptr,
2489         .emit_frame_size =
2490                 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2491                 3 + /* hdp invalidate */
2492                 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2493                 /* sdma_v4_0_ring_emit_vm_flush */
2494                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2495                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2496                 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2497         .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2498         .emit_ib = sdma_v4_0_ring_emit_ib,
2499         .emit_fence = sdma_v4_0_ring_emit_fence,
2500         .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2501         .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2502         .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2503         .test_ring = sdma_v4_0_ring_test_ring,
2504         .test_ib = sdma_v4_0_ring_test_ib,
2505         .insert_nop = sdma_v4_0_ring_insert_nop,
2506         .pad_ib = sdma_v4_0_ring_pad_ib,
2507         .emit_wreg = sdma_v4_0_ring_emit_wreg,
2508         .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2509         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2510 };
2511
2512 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs_2nd_mmhub = {
2513         .type = AMDGPU_RING_TYPE_SDMA,
2514         .align_mask = 0xf,
2515         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2516         .support_64bit_ptrs = true,
2517         .vmhub = AMDGPU_MMHUB_1,
2518         .get_rptr = sdma_v4_0_ring_get_rptr,
2519         .get_wptr = sdma_v4_0_page_ring_get_wptr,
2520         .set_wptr = sdma_v4_0_page_ring_set_wptr,
2521         .emit_frame_size =
2522                 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2523                 3 + /* hdp invalidate */
2524                 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2525                 /* sdma_v4_0_ring_emit_vm_flush */
2526                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2527                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2528                 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2529         .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2530         .emit_ib = sdma_v4_0_ring_emit_ib,
2531         .emit_fence = sdma_v4_0_ring_emit_fence,
2532         .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2533         .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2534         .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2535         .test_ring = sdma_v4_0_ring_test_ring,
2536         .test_ib = sdma_v4_0_ring_test_ib,
2537         .insert_nop = sdma_v4_0_ring_insert_nop,
2538         .pad_ib = sdma_v4_0_ring_pad_ib,
2539         .emit_wreg = sdma_v4_0_ring_emit_wreg,
2540         .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2541         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2542 };
2543
2544 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
2545 {
2546         int i;
2547
2548         for (i = 0; i < adev->sdma.num_instances; i++) {
2549                 if (adev->asic_type == CHIP_ARCTURUS && i >= 5)
2550                         adev->sdma.instance[i].ring.funcs =
2551                                         &sdma_v4_0_ring_funcs_2nd_mmhub;
2552                 else
2553                         adev->sdma.instance[i].ring.funcs =
2554                                         &sdma_v4_0_ring_funcs;
2555                 adev->sdma.instance[i].ring.me = i;
2556                 if (adev->sdma.has_page_queue) {
2557                         if (adev->asic_type == CHIP_ARCTURUS && i >= 5)
2558                                 adev->sdma.instance[i].page.funcs =
2559                                         &sdma_v4_0_page_ring_funcs_2nd_mmhub;
2560                         else
2561                                 adev->sdma.instance[i].page.funcs =
2562                                         &sdma_v4_0_page_ring_funcs;
2563                         adev->sdma.instance[i].page.me = i;
2564                 }
2565         }
2566 }
2567
2568 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = {
2569         .set = sdma_v4_0_set_trap_irq_state,
2570         .process = sdma_v4_0_process_trap_irq,
2571 };
2572
2573 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = {
2574         .process = sdma_v4_0_process_illegal_inst_irq,
2575 };
2576
2577 static const struct amdgpu_irq_src_funcs sdma_v4_0_ecc_irq_funcs = {
2578         .set = sdma_v4_0_set_ecc_irq_state,
2579         .process = amdgpu_sdma_process_ecc_irq,
2580 };
2581
2582 static const struct amdgpu_irq_src_funcs sdma_v4_0_vm_hole_irq_funcs = {
2583         .process = sdma_v4_0_process_vm_hole_irq,
2584 };
2585
2586 static const struct amdgpu_irq_src_funcs sdma_v4_0_doorbell_invalid_irq_funcs = {
2587         .process = sdma_v4_0_process_doorbell_invalid_irq,
2588 };
2589
2590 static const struct amdgpu_irq_src_funcs sdma_v4_0_pool_timeout_irq_funcs = {
2591         .process = sdma_v4_0_process_pool_timeout_irq,
2592 };
2593
2594 static const struct amdgpu_irq_src_funcs sdma_v4_0_srbm_write_irq_funcs = {
2595         .process = sdma_v4_0_process_srbm_write_irq,
2596 };
2597
2598 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev)
2599 {
2600         switch (adev->sdma.num_instances) {
2601         case 1:
2602                 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1;
2603                 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1;
2604                 break;
2605         case 5:
2606                 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE5;
2607                 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE5;
2608                 break;
2609         case 8:
2610                 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
2611                 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
2612                 adev->sdma.vm_hole_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE5;
2613                 adev->sdma.doorbell_invalid_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
2614                 adev->sdma.pool_timeout_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
2615                 adev->sdma.srbm_write_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
2616                 break;
2617         case 2:
2618         default:
2619                 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2;
2620                 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2;
2621                 break;
2622         }
2623         adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs;
2624         adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs;
2625         adev->sdma.ecc_irq.funcs = &sdma_v4_0_ecc_irq_funcs;
2626         adev->sdma.vm_hole_irq.funcs = &sdma_v4_0_vm_hole_irq_funcs;
2627         adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_0_doorbell_invalid_irq_funcs;
2628         adev->sdma.pool_timeout_irq.funcs = &sdma_v4_0_pool_timeout_irq_funcs;
2629         adev->sdma.srbm_write_irq.funcs = &sdma_v4_0_srbm_write_irq_funcs;
2630 }
2631
2632 /**
2633  * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine
2634  *
2635  * @ib: indirect buffer to copy to
2636  * @src_offset: src GPU address
2637  * @dst_offset: dst GPU address
2638  * @byte_count: number of bytes to xfer
2639  * @tmz: if a secure copy should be used
2640  *
2641  * Copy GPU buffers using the DMA engine (VEGA10/12).
2642  * Used by the amdgpu ttm implementation to move pages if
2643  * registered as the asic copy callback.
2644  */
2645 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib,
2646                                        uint64_t src_offset,
2647                                        uint64_t dst_offset,
2648                                        uint32_t byte_count,
2649                                        bool tmz)
2650 {
2651         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
2652                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
2653                 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
2654         ib->ptr[ib->length_dw++] = byte_count - 1;
2655         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
2656         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
2657         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
2658         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2659         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2660 }
2661
2662 /**
2663  * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine
2664  *
2665  * @ib: indirect buffer to copy to
2666  * @src_data: value to write to buffer
2667  * @dst_offset: dst GPU address
2668  * @byte_count: number of bytes to xfer
2669  *
2670  * Fill GPU buffers using the DMA engine (VEGA10/12).
2671  */
2672 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib,
2673                                        uint32_t src_data,
2674                                        uint64_t dst_offset,
2675                                        uint32_t byte_count)
2676 {
2677         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
2678         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2679         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2680         ib->ptr[ib->length_dw++] = src_data;
2681         ib->ptr[ib->length_dw++] = byte_count - 1;
2682 }
2683
2684 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = {
2685         .copy_max_bytes = 0x400000,
2686         .copy_num_dw = 7,
2687         .emit_copy_buffer = sdma_v4_0_emit_copy_buffer,
2688
2689         .fill_max_bytes = 0x400000,
2690         .fill_num_dw = 5,
2691         .emit_fill_buffer = sdma_v4_0_emit_fill_buffer,
2692 };
2693
2694 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
2695 {
2696         adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
2697         if (adev->sdma.has_page_queue)
2698                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
2699         else
2700                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
2701 }
2702
2703 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = {
2704         .copy_pte_num_dw = 7,
2705         .copy_pte = sdma_v4_0_vm_copy_pte,
2706
2707         .write_pte = sdma_v4_0_vm_write_pte,
2708         .set_pte_pde = sdma_v4_0_vm_set_pte_pde,
2709 };
2710
2711 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev)
2712 {
2713         struct drm_gpu_scheduler *sched;
2714         unsigned i;
2715
2716         adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
2717         for (i = 0; i < adev->sdma.num_instances; i++) {
2718                 if (adev->sdma.has_page_queue)
2719                         sched = &adev->sdma.instance[i].page.sched;
2720                 else
2721                         sched = &adev->sdma.instance[i].ring.sched;
2722                 adev->vm_manager.vm_pte_scheds[i] = sched;
2723         }
2724         adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
2725 }
2726
2727 static void sdma_v4_0_get_ras_error_count(uint32_t value,
2728                                         uint32_t instance,
2729                                         uint32_t *sec_count)
2730 {
2731         uint32_t i;
2732         uint32_t sec_cnt;
2733
2734         /* double bits error (multiple bits) error detection is not supported */
2735         for (i = 0; i < ARRAY_SIZE(sdma_v4_0_ras_fields); i++) {
2736                 /* the SDMA_EDC_COUNTER register in each sdma instance
2737                  * shares the same sed shift_mask
2738                  * */
2739                 sec_cnt = (value &
2740                         sdma_v4_0_ras_fields[i].sec_count_mask) >>
2741                         sdma_v4_0_ras_fields[i].sec_count_shift;
2742                 if (sec_cnt) {
2743                         DRM_INFO("Detected %s in SDMA%d, SED %d\n",
2744                                 sdma_v4_0_ras_fields[i].name,
2745                                 instance, sec_cnt);
2746                         *sec_count += sec_cnt;
2747                 }
2748         }
2749 }
2750
2751 static int sdma_v4_0_query_ras_error_count(struct amdgpu_device *adev,
2752                         uint32_t instance, void *ras_error_status)
2753 {
2754         struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
2755         uint32_t sec_count = 0;
2756         uint32_t reg_value = 0;
2757
2758         reg_value = RREG32_SDMA(instance, mmSDMA0_EDC_COUNTER);
2759         /* double bit error is not supported */
2760         if (reg_value)
2761                 sdma_v4_0_get_ras_error_count(reg_value,
2762                                 instance, &sec_count);
2763         /* err_data->ce_count should be initialized to 0
2764          * before calling into this function */
2765         err_data->ce_count += sec_count;
2766         /* double bit error is not supported
2767          * set ue count to 0 */
2768         err_data->ue_count = 0;
2769
2770         return 0;
2771 };
2772
2773 static void sdma_v4_0_reset_ras_error_count(struct amdgpu_device *adev)
2774 {
2775         int i;
2776
2777         /* read back edc counter registers to clear the counters */
2778         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2779                 for (i = 0; i < adev->sdma.num_instances; i++)
2780                         RREG32_SDMA(i, mmSDMA0_EDC_COUNTER);
2781         }
2782 }
2783
2784 static const struct amdgpu_sdma_ras_funcs sdma_v4_0_ras_funcs = {
2785         .ras_late_init = amdgpu_sdma_ras_late_init,
2786         .ras_fini = amdgpu_sdma_ras_fini,
2787         .query_ras_error_count = sdma_v4_0_query_ras_error_count,
2788         .reset_ras_error_count = sdma_v4_0_reset_ras_error_count,
2789 };
2790
2791 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev)
2792 {
2793         switch (adev->asic_type) {
2794         case CHIP_VEGA20:
2795         case CHIP_ARCTURUS:
2796                 adev->sdma.funcs = &sdma_v4_0_ras_funcs;
2797                 break;
2798         case CHIP_ALDEBARAN:
2799                 adev->sdma.funcs = &sdma_v4_4_ras_funcs;
2800                 break;
2801         default:
2802                 break;
2803         }
2804 }
2805
2806 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = {
2807         .type = AMD_IP_BLOCK_TYPE_SDMA,
2808         .major = 4,
2809         .minor = 0,
2810         .rev = 0,
2811         .funcs = &sdma_v4_0_ip_funcs,
2812 };