2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
25 #include <linux/firmware.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
30 #include "amdgpu_ucode.h"
31 #include "amdgpu_trace.h"
33 #include "sdma0/sdma0_4_2_offset.h"
34 #include "sdma0/sdma0_4_2_sh_mask.h"
35 #include "sdma1/sdma1_4_2_offset.h"
36 #include "sdma1/sdma1_4_2_sh_mask.h"
37 #include "sdma2/sdma2_4_2_2_offset.h"
38 #include "sdma2/sdma2_4_2_2_sh_mask.h"
39 #include "sdma3/sdma3_4_2_2_offset.h"
40 #include "sdma3/sdma3_4_2_2_sh_mask.h"
41 #include "sdma4/sdma4_4_2_2_offset.h"
42 #include "sdma4/sdma4_4_2_2_sh_mask.h"
43 #include "sdma5/sdma5_4_2_2_offset.h"
44 #include "sdma5/sdma5_4_2_2_sh_mask.h"
45 #include "sdma6/sdma6_4_2_2_offset.h"
46 #include "sdma6/sdma6_4_2_2_sh_mask.h"
47 #include "sdma7/sdma7_4_2_2_offset.h"
48 #include "sdma7/sdma7_4_2_2_sh_mask.h"
49 #include "hdp/hdp_4_0_offset.h"
50 #include "sdma0/sdma0_4_1_default.h"
52 #include "soc15_common.h"
54 #include "vega10_sdma_pkt_open.h"
56 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h"
57 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h"
59 #include "amdgpu_ras.h"
61 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin");
62 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin");
63 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin");
64 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin");
65 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin");
66 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin");
67 MODULE_FIRMWARE("amdgpu/raven_sdma.bin");
68 MODULE_FIRMWARE("amdgpu/picasso_sdma.bin");
69 MODULE_FIRMWARE("amdgpu/raven2_sdma.bin");
70 MODULE_FIRMWARE("amdgpu/arcturus_sdma.bin");
71 MODULE_FIRMWARE("amdgpu/renoir_sdma.bin");
73 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L
74 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
76 #define WREG32_SDMA(instance, offset, value) \
77 WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value)
78 #define RREG32_SDMA(instance, offset) \
79 RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)))
81 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev);
82 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev);
83 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev);
84 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev);
85 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev);
87 static const struct soc15_reg_golden golden_settings_sdma_4[] = {
88 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
89 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
90 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),
91 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
92 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
93 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
94 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000),
95 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
96 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
97 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
98 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
99 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
100 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000),
101 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
102 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100),
103 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
104 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
105 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
106 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000),
107 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
108 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
109 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
110 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
111 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
112 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000)
115 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = {
116 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
117 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
118 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
119 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
120 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
121 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
122 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
125 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = {
126 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
127 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001),
128 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
129 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
130 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
131 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001),
132 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
135 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = {
136 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
137 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
138 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100),
139 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
140 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051),
141 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100),
142 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
143 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100),
144 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
145 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
146 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000)
149 static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = {
150 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
153 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] =
155 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
156 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
157 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
158 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
159 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
160 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
161 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
162 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
163 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003),
164 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
165 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
166 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
167 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
168 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
169 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
170 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
171 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
172 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
173 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
174 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
175 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
176 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
177 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
178 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
179 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
180 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
181 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
184 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = {
185 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
186 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
187 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
188 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
189 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
190 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
191 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
192 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
193 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003),
194 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
195 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
196 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
197 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
198 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
199 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
200 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
201 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
202 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
203 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
204 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
205 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
206 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
207 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
208 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
209 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
210 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
211 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
214 static const struct soc15_reg_golden golden_settings_sdma_rv1[] =
216 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
217 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002)
220 static const struct soc15_reg_golden golden_settings_sdma_rv2[] =
222 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001),
223 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001)
226 static const struct soc15_reg_golden golden_settings_sdma_arct[] =
228 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
229 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
230 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
231 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
232 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
233 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
234 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
235 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
236 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
237 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
238 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
239 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
240 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
241 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
242 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
243 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
244 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
245 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
246 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
247 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
248 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
249 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
250 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
251 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
252 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
253 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
254 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
255 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
256 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
257 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
258 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
259 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_UTCL1_TIMEOUT, 0xffffffff, 0x00010001)
262 static const struct soc15_reg_golden golden_settings_sdma_4_3[] = {
263 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
264 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
265 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
266 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002),
267 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
268 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051),
269 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
270 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
271 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
272 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x03fbe1fe)
275 static const struct soc15_ras_field_entry sdma_v4_0_ras_fields[] = {
276 { "SDMA_UCODE_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
277 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UCODE_BUF_SED),
280 { "SDMA_RB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
281 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_RB_CMD_BUF_SED),
284 { "SDMA_IB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
285 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_IB_CMD_BUF_SED),
288 { "SDMA_UTCL1_RD_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
289 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RD_FIFO_SED),
292 { "SDMA_UTCL1_RDBST_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
293 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RDBST_FIFO_SED),
296 { "SDMA_DATA_LUT_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
297 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_DATA_LUT_FIFO_SED),
300 { "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
301 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF0_SED),
304 { "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
305 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF1_SED),
308 { "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
309 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF2_SED),
312 { "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
313 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF3_SED),
316 { "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
317 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF4_SED),
320 { "SDMA_MBANK_DATA_BUF5_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
321 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF5_SED),
324 { "SDMA_MBANK_DATA_BUF6_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
325 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF6_SED),
328 { "SDMA_MBANK_DATA_BUF7_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
329 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF7_SED),
332 { "SDMA_MBANK_DATA_BUF8_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
333 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF8_SED),
336 { "SDMA_MBANK_DATA_BUF9_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
337 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF9_SED),
340 { "SDMA_MBANK_DATA_BUF10_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
341 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF10_SED),
344 { "SDMA_MBANK_DATA_BUF11_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
345 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF11_SED),
348 { "SDMA_MBANK_DATA_BUF12_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
349 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF12_SED),
352 { "SDMA_MBANK_DATA_BUF13_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
353 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF13_SED),
356 { "SDMA_MBANK_DATA_BUF14_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
357 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF14_SED),
360 { "SDMA_MBANK_DATA_BUF15_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
361 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF15_SED),
364 { "SDMA_SPLIT_DAT_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
365 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_SPLIT_DAT_BUF_SED),
368 { "SDMA_MC_WR_ADDR_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
369 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MC_WR_ADDR_FIFO_SED),
374 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
375 u32 instance, u32 offset)
379 return (adev->reg_offset[SDMA0_HWIP][0][0] + offset);
381 return (adev->reg_offset[SDMA1_HWIP][0][0] + offset);
383 return (adev->reg_offset[SDMA2_HWIP][0][1] + offset);
385 return (adev->reg_offset[SDMA3_HWIP][0][1] + offset);
387 return (adev->reg_offset[SDMA4_HWIP][0][1] + offset);
389 return (adev->reg_offset[SDMA5_HWIP][0][1] + offset);
391 return (adev->reg_offset[SDMA6_HWIP][0][1] + offset);
393 return (adev->reg_offset[SDMA7_HWIP][0][1] + offset);
400 static unsigned sdma_v4_0_seq_to_irq_id(int seq_num)
404 return SOC15_IH_CLIENTID_SDMA0;
406 return SOC15_IH_CLIENTID_SDMA1;
408 return SOC15_IH_CLIENTID_SDMA2;
410 return SOC15_IH_CLIENTID_SDMA3;
412 return SOC15_IH_CLIENTID_SDMA4;
414 return SOC15_IH_CLIENTID_SDMA5;
416 return SOC15_IH_CLIENTID_SDMA6;
418 return SOC15_IH_CLIENTID_SDMA7;
425 static int sdma_v4_0_irq_id_to_seq(unsigned client_id)
428 case SOC15_IH_CLIENTID_SDMA0:
430 case SOC15_IH_CLIENTID_SDMA1:
432 case SOC15_IH_CLIENTID_SDMA2:
434 case SOC15_IH_CLIENTID_SDMA3:
436 case SOC15_IH_CLIENTID_SDMA4:
438 case SOC15_IH_CLIENTID_SDMA5:
440 case SOC15_IH_CLIENTID_SDMA6:
442 case SOC15_IH_CLIENTID_SDMA7:
450 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
452 switch (adev->asic_type) {
454 soc15_program_register_sequence(adev,
455 golden_settings_sdma_4,
456 ARRAY_SIZE(golden_settings_sdma_4));
457 soc15_program_register_sequence(adev,
458 golden_settings_sdma_vg10,
459 ARRAY_SIZE(golden_settings_sdma_vg10));
462 soc15_program_register_sequence(adev,
463 golden_settings_sdma_4,
464 ARRAY_SIZE(golden_settings_sdma_4));
465 soc15_program_register_sequence(adev,
466 golden_settings_sdma_vg12,
467 ARRAY_SIZE(golden_settings_sdma_vg12));
470 soc15_program_register_sequence(adev,
471 golden_settings_sdma0_4_2_init,
472 ARRAY_SIZE(golden_settings_sdma0_4_2_init));
473 soc15_program_register_sequence(adev,
474 golden_settings_sdma0_4_2,
475 ARRAY_SIZE(golden_settings_sdma0_4_2));
476 soc15_program_register_sequence(adev,
477 golden_settings_sdma1_4_2,
478 ARRAY_SIZE(golden_settings_sdma1_4_2));
481 soc15_program_register_sequence(adev,
482 golden_settings_sdma_arct,
483 ARRAY_SIZE(golden_settings_sdma_arct));
486 soc15_program_register_sequence(adev,
487 golden_settings_sdma_4_1,
488 ARRAY_SIZE(golden_settings_sdma_4_1));
489 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
490 soc15_program_register_sequence(adev,
491 golden_settings_sdma_rv2,
492 ARRAY_SIZE(golden_settings_sdma_rv2));
494 soc15_program_register_sequence(adev,
495 golden_settings_sdma_rv1,
496 ARRAY_SIZE(golden_settings_sdma_rv1));
499 soc15_program_register_sequence(adev,
500 golden_settings_sdma_4_3,
501 ARRAY_SIZE(golden_settings_sdma_4_3));
508 static void sdma_v4_0_setup_ulv(struct amdgpu_device *adev)
513 * The only chips with SDMAv4 and ULV are VG10 and VG20.
514 * Server SKUs take a different hysteresis setting from other SKUs.
516 switch (adev->asic_type) {
518 if (adev->pdev->device == 0x6860)
522 if (adev->pdev->device == 0x66a1)
529 for (i = 0; i < adev->sdma.num_instances; i++) {
532 temp = RREG32_SDMA(i, mmSDMA0_ULV_CNTL);
533 temp = REG_SET_FIELD(temp, SDMA0_ULV_CNTL, HYSTERESIS, 0x0);
534 WREG32_SDMA(i, mmSDMA0_ULV_CNTL, temp);
538 static int sdma_v4_0_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
541 const struct sdma_firmware_header_v1_0 *hdr;
543 err = amdgpu_ucode_validate(sdma_inst->fw);
547 hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
548 sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
549 sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
551 if (sdma_inst->feature_version >= 20)
552 sdma_inst->burst_nop = true;
557 static void sdma_v4_0_destroy_inst_ctx(struct amdgpu_device *adev)
561 for (i = 0; i < adev->sdma.num_instances; i++) {
562 release_firmware(adev->sdma.instance[i].fw);
563 adev->sdma.instance[i].fw = NULL;
565 /* arcturus shares the same FW memory across
566 all SDMA isntances */
567 if (adev->asic_type == CHIP_ARCTURUS)
571 memset((void*)adev->sdma.instance, 0,
572 sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
576 * sdma_v4_0_init_microcode - load ucode images from disk
578 * @adev: amdgpu_device pointer
580 * Use the firmware interface to load the ucode images into
581 * the driver (not loaded into hw).
582 * Returns 0 on success, error on failure.
585 // emulation only, won't work on real chip
586 // vega10 real chip need to use PSP to load firmware
587 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
589 const char *chip_name;
592 struct amdgpu_firmware_info *info = NULL;
593 const struct common_firmware_header *header = NULL;
597 switch (adev->asic_type) {
599 chip_name = "vega10";
602 chip_name = "vega12";
605 chip_name = "vega20";
608 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
609 chip_name = "raven2";
610 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
611 chip_name = "picasso";
616 chip_name = "arcturus";
619 chip_name = "renoir";
625 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
627 err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);
631 err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[0]);
635 for (i = 1; i < adev->sdma.num_instances; i++) {
636 if (adev->asic_type == CHIP_ARCTURUS) {
637 /* Acturus will leverage the same FW memory
638 for every SDMA instance */
639 memcpy((void*)&adev->sdma.instance[i],
640 (void*)&adev->sdma.instance[0],
641 sizeof(struct amdgpu_sdma_instance));
644 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i);
646 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
650 err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[i]);
656 DRM_DEBUG("psp_load == '%s'\n",
657 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
659 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
660 for (i = 0; i < adev->sdma.num_instances; i++) {
661 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
662 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
663 info->fw = adev->sdma.instance[i].fw;
664 header = (const struct common_firmware_header *)info->fw->data;
665 adev->firmware.fw_size +=
666 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
672 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name);
673 sdma_v4_0_destroy_inst_ctx(adev);
679 * sdma_v4_0_ring_get_rptr - get the current read pointer
681 * @ring: amdgpu ring pointer
683 * Get the current rptr from the hardware (VEGA10+).
685 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring)
689 /* XXX check if swapping is necessary on BE */
690 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
692 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
693 return ((*rptr) >> 2);
697 * sdma_v4_0_ring_get_wptr - get the current write pointer
699 * @ring: amdgpu ring pointer
701 * Get the current wptr from the hardware (VEGA10+).
703 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
705 struct amdgpu_device *adev = ring->adev;
708 if (ring->use_doorbell) {
709 /* XXX check if swapping is necessary on BE */
710 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
711 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
713 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI);
715 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR);
716 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n",
724 * sdma_v4_0_page_ring_set_wptr - commit the write pointer
726 * @ring: amdgpu ring pointer
728 * Write the wptr back to the hardware (VEGA10+).
730 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
732 struct amdgpu_device *adev = ring->adev;
734 DRM_DEBUG("Setting write pointer\n");
735 if (ring->use_doorbell) {
736 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
738 DRM_DEBUG("Using doorbell -- "
739 "wptr_offs == 0x%08x "
740 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
741 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
743 lower_32_bits(ring->wptr << 2),
744 upper_32_bits(ring->wptr << 2));
745 /* XXX check if swapping is necessary on BE */
746 WRITE_ONCE(*wb, (ring->wptr << 2));
747 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
748 ring->doorbell_index, ring->wptr << 2);
749 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
751 DRM_DEBUG("Not using doorbell -- "
752 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
753 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
755 lower_32_bits(ring->wptr << 2),
757 upper_32_bits(ring->wptr << 2));
758 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR,
759 lower_32_bits(ring->wptr << 2));
760 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI,
761 upper_32_bits(ring->wptr << 2));
766 * sdma_v4_0_page_ring_get_wptr - get the current write pointer
768 * @ring: amdgpu ring pointer
770 * Get the current wptr from the hardware (VEGA10+).
772 static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring)
774 struct amdgpu_device *adev = ring->adev;
777 if (ring->use_doorbell) {
778 /* XXX check if swapping is necessary on BE */
779 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
781 wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI);
783 wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR);
790 * sdma_v4_0_ring_set_wptr - commit the write pointer
792 * @ring: amdgpu ring pointer
794 * Write the wptr back to the hardware (VEGA10+).
796 static void sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring *ring)
798 struct amdgpu_device *adev = ring->adev;
800 if (ring->use_doorbell) {
801 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
803 /* XXX check if swapping is necessary on BE */
804 WRITE_ONCE(*wb, (ring->wptr << 2));
805 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
807 uint64_t wptr = ring->wptr << 2;
809 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR,
810 lower_32_bits(wptr));
811 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI,
812 upper_32_bits(wptr));
816 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
818 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
821 for (i = 0; i < count; i++)
822 if (sdma && sdma->burst_nop && (i == 0))
823 amdgpu_ring_write(ring, ring->funcs->nop |
824 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
826 amdgpu_ring_write(ring, ring->funcs->nop);
830 * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine
832 * @ring: amdgpu ring pointer
833 * @ib: IB object to schedule
835 * Schedule an IB in the DMA ring (VEGA10).
837 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
838 struct amdgpu_job *job,
839 struct amdgpu_ib *ib,
842 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
844 /* IB packet must end on a 8 DW boundary */
845 sdma_v4_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
847 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
848 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
849 /* base must be 32 byte aligned */
850 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
851 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
852 amdgpu_ring_write(ring, ib->length_dw);
853 amdgpu_ring_write(ring, 0);
854 amdgpu_ring_write(ring, 0);
858 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring,
859 int mem_space, int hdp,
860 uint32_t addr0, uint32_t addr1,
861 uint32_t ref, uint32_t mask,
864 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
865 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) |
866 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) |
867 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
870 amdgpu_ring_write(ring, addr0);
871 amdgpu_ring_write(ring, addr1);
874 amdgpu_ring_write(ring, addr0 << 2);
875 amdgpu_ring_write(ring, addr1 << 2);
877 amdgpu_ring_write(ring, ref); /* reference */
878 amdgpu_ring_write(ring, mask); /* mask */
879 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
880 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */
884 * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
886 * @ring: amdgpu ring pointer
888 * Emit an hdp flush packet on the requested DMA ring.
890 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
892 struct amdgpu_device *adev = ring->adev;
893 u32 ref_and_mask = 0;
894 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
896 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
898 sdma_v4_0_wait_reg_mem(ring, 0, 1,
899 adev->nbio.funcs->get_hdp_flush_done_offset(adev),
900 adev->nbio.funcs->get_hdp_flush_req_offset(adev),
901 ref_and_mask, ref_and_mask, 10);
905 * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring
907 * @ring: amdgpu ring pointer
908 * @fence: amdgpu fence object
910 * Add a DMA fence packet to the ring to write
911 * the fence seq number and DMA trap packet to generate
912 * an interrupt if needed (VEGA10).
914 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
917 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
918 /* write the fence */
919 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
920 /* zero in first two bits */
922 amdgpu_ring_write(ring, lower_32_bits(addr));
923 amdgpu_ring_write(ring, upper_32_bits(addr));
924 amdgpu_ring_write(ring, lower_32_bits(seq));
926 /* optionally write high bits as well */
929 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
930 /* zero in first two bits */
932 amdgpu_ring_write(ring, lower_32_bits(addr));
933 amdgpu_ring_write(ring, upper_32_bits(addr));
934 amdgpu_ring_write(ring, upper_32_bits(seq));
937 /* generate an interrupt */
938 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
939 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
944 * sdma_v4_0_gfx_stop - stop the gfx async dma engines
946 * @adev: amdgpu_device pointer
948 * Stop the gfx async dma ring buffers (VEGA10).
950 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev)
952 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
953 u32 rb_cntl, ib_cntl;
956 for (i = 0; i < adev->sdma.num_instances; i++) {
957 sdma[i] = &adev->sdma.instance[i].ring;
959 if ((adev->mman.buffer_funcs_ring == sdma[i]) && unset != 1) {
960 amdgpu_ttm_set_buffer_funcs_status(adev, false);
964 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
965 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
966 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
967 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
968 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
969 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
974 * sdma_v4_0_rlc_stop - stop the compute async dma engines
976 * @adev: amdgpu_device pointer
978 * Stop the compute async dma queues (VEGA10).
980 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev)
986 * sdma_v4_0_page_stop - stop the page async dma engines
988 * @adev: amdgpu_device pointer
990 * Stop the page async dma ring buffers (VEGA10).
992 static void sdma_v4_0_page_stop(struct amdgpu_device *adev)
994 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
995 u32 rb_cntl, ib_cntl;
999 for (i = 0; i < adev->sdma.num_instances; i++) {
1000 sdma[i] = &adev->sdma.instance[i].page;
1002 if ((adev->mman.buffer_funcs_ring == sdma[i]) &&
1004 amdgpu_ttm_set_buffer_funcs_status(adev, false);
1008 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);
1009 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
1011 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
1012 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL);
1013 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL,
1015 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
1020 * sdma_v4_0_ctx_switch_enable - stop the async dma engines context switch
1022 * @adev: amdgpu_device pointer
1023 * @enable: enable/disable the DMA MEs context switch.
1025 * Halt or unhalt the async dma engines context switch (VEGA10).
1027 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
1029 u32 f32_cntl, phase_quantum = 0;
1032 if (amdgpu_sdma_phase_quantum) {
1033 unsigned value = amdgpu_sdma_phase_quantum;
1036 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
1037 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
1038 value = (value + 1) >> 1;
1041 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
1042 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
1043 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
1044 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
1045 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
1046 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
1048 "clamping sdma_phase_quantum to %uK clock cycles\n",
1052 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
1053 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
1056 for (i = 0; i < adev->sdma.num_instances; i++) {
1057 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL);
1058 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
1059 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
1060 if (enable && amdgpu_sdma_phase_quantum) {
1061 WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum);
1062 WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum);
1063 WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum);
1065 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl);
1071 * sdma_v4_0_enable - stop the async dma engines
1073 * @adev: amdgpu_device pointer
1074 * @enable: enable/disable the DMA MEs.
1076 * Halt or unhalt the async dma engines (VEGA10).
1078 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable)
1083 if (enable == false) {
1084 sdma_v4_0_gfx_stop(adev);
1085 sdma_v4_0_rlc_stop(adev);
1086 if (adev->sdma.has_page_queue)
1087 sdma_v4_0_page_stop(adev);
1090 for (i = 0; i < adev->sdma.num_instances; i++) {
1091 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
1092 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
1093 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl);
1098 * sdma_v4_0_rb_cntl - get parameters for rb_cntl
1100 static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl)
1102 /* Set ring buffer size in dwords */
1103 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4);
1105 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
1107 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
1108 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
1109 RPTR_WRITEBACK_SWAP_ENABLE, 1);
1115 * sdma_v4_0_gfx_resume - setup and start the async dma engines
1117 * @adev: amdgpu_device pointer
1118 * @i: instance to resume
1120 * Set up the gfx DMA ring buffers and enable them (VEGA10).
1121 * Returns 0 for success, error for failure.
1123 static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i)
1125 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring;
1126 u32 rb_cntl, ib_cntl, wptr_poll_cntl;
1129 u32 doorbell_offset;
1132 wb_offset = (ring->rptr_offs * 4);
1134 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
1135 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl);
1136 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
1138 /* Initialize the ring buffer's read and write pointers */
1139 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0);
1140 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0);
1141 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0);
1142 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0);
1144 /* set the wb address whether it's enabled or not */
1145 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI,
1146 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
1147 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO,
1148 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
1150 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
1151 RPTR_WRITEBACK_ENABLE, 1);
1153 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8);
1154 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40);
1158 /* before programing wptr to a less value, need set minor_ptr_update first */
1159 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1);
1161 doorbell = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL);
1162 doorbell_offset = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET);
1164 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE,
1165 ring->use_doorbell);
1166 doorbell_offset = REG_SET_FIELD(doorbell_offset,
1167 SDMA0_GFX_DOORBELL_OFFSET,
1168 OFFSET, ring->doorbell_index);
1169 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell);
1170 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset);
1172 sdma_v4_0_ring_set_wptr(ring);
1174 /* set minor_ptr_update to 0 after wptr programed */
1175 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0);
1177 /* setup the wptr shadow polling */
1178 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1179 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO,
1180 lower_32_bits(wptr_gpu_addr));
1181 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI,
1182 upper_32_bits(wptr_gpu_addr));
1183 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL);
1184 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
1185 SDMA0_GFX_RB_WPTR_POLL_CNTL,
1186 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
1187 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
1190 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
1191 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
1193 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
1194 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
1196 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
1198 /* enable DMA IBs */
1199 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
1201 ring->sched.ready = true;
1205 * sdma_v4_0_page_resume - setup and start the async dma engines
1207 * @adev: amdgpu_device pointer
1208 * @i: instance to resume
1210 * Set up the page DMA ring buffers and enable them (VEGA10).
1211 * Returns 0 for success, error for failure.
1213 static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i)
1215 struct amdgpu_ring *ring = &adev->sdma.instance[i].page;
1216 u32 rb_cntl, ib_cntl, wptr_poll_cntl;
1219 u32 doorbell_offset;
1222 wb_offset = (ring->rptr_offs * 4);
1224 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);
1225 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl);
1226 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
1228 /* Initialize the ring buffer's read and write pointers */
1229 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR, 0);
1230 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_HI, 0);
1231 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR, 0);
1232 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_HI, 0);
1234 /* set the wb address whether it's enabled or not */
1235 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_HI,
1236 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
1237 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_LO,
1238 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
1240 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
1241 RPTR_WRITEBACK_ENABLE, 1);
1243 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE, ring->gpu_addr >> 8);
1244 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE_HI, ring->gpu_addr >> 40);
1248 /* before programing wptr to a less value, need set minor_ptr_update first */
1249 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 1);
1251 doorbell = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL);
1252 doorbell_offset = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET);
1254 doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE,
1255 ring->use_doorbell);
1256 doorbell_offset = REG_SET_FIELD(doorbell_offset,
1257 SDMA0_PAGE_DOORBELL_OFFSET,
1258 OFFSET, ring->doorbell_index);
1259 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell);
1260 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset);
1262 /* paging queue doorbell range is setup at sdma_v4_0_gfx_resume */
1263 sdma_v4_0_page_ring_set_wptr(ring);
1265 /* set minor_ptr_update to 0 after wptr programed */
1266 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0);
1268 /* setup the wptr shadow polling */
1269 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1270 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO,
1271 lower_32_bits(wptr_gpu_addr));
1272 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI,
1273 upper_32_bits(wptr_gpu_addr));
1274 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL);
1275 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
1276 SDMA0_PAGE_RB_WPTR_POLL_CNTL,
1277 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
1278 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
1281 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1);
1282 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
1284 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL);
1285 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_ENABLE, 1);
1287 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1);
1289 /* enable DMA IBs */
1290 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
1292 ring->sched.ready = true;
1296 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable)
1300 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) {
1301 /* enable idle interrupt */
1302 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1303 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1306 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1308 /* disable idle interrupt */
1309 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1310 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1312 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1316 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev)
1320 /* Enable HW based PG. */
1321 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1322 data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK;
1324 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1326 /* enable interrupt */
1327 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1328 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1330 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1332 /* Configure hold time to filter in-valid power on/off request. Use default right now */
1333 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1334 data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK;
1335 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK);
1336 /* Configure switch time for hysteresis purpose. Use default right now */
1337 data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK;
1338 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK);
1340 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1343 static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
1345 if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA))
1348 switch (adev->asic_type) {
1351 sdma_v4_1_init_power_gating(adev);
1352 sdma_v4_1_update_power_gating(adev, true);
1360 * sdma_v4_0_rlc_resume - setup and start the async dma engines
1362 * @adev: amdgpu_device pointer
1364 * Set up the compute DMA queues and enable them (VEGA10).
1365 * Returns 0 for success, error for failure.
1367 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev)
1369 sdma_v4_0_init_pg(adev);
1375 * sdma_v4_0_load_microcode - load the sDMA ME ucode
1377 * @adev: amdgpu_device pointer
1379 * Loads the sDMA0/1 ucode.
1380 * Returns 0 for success, -EINVAL if the ucode is not available.
1382 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev)
1384 const struct sdma_firmware_header_v1_0 *hdr;
1385 const __le32 *fw_data;
1390 sdma_v4_0_enable(adev, false);
1392 for (i = 0; i < adev->sdma.num_instances; i++) {
1393 if (!adev->sdma.instance[i].fw)
1396 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
1397 amdgpu_ucode_print_sdma_hdr(&hdr->header);
1398 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1400 fw_data = (const __le32 *)
1401 (adev->sdma.instance[i].fw->data +
1402 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1404 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0);
1406 for (j = 0; j < fw_size; j++)
1407 WREG32_SDMA(i, mmSDMA0_UCODE_DATA,
1408 le32_to_cpup(fw_data++));
1410 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR,
1411 adev->sdma.instance[i].fw_version);
1418 * sdma_v4_0_start - setup and start the async dma engines
1420 * @adev: amdgpu_device pointer
1422 * Set up the DMA engines and enable them (VEGA10).
1423 * Returns 0 for success, error for failure.
1425 static int sdma_v4_0_start(struct amdgpu_device *adev)
1427 struct amdgpu_ring *ring;
1430 if (amdgpu_sriov_vf(adev)) {
1431 sdma_v4_0_ctx_switch_enable(adev, false);
1432 sdma_v4_0_enable(adev, false);
1435 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1436 r = sdma_v4_0_load_microcode(adev);
1441 /* unhalt the MEs */
1442 sdma_v4_0_enable(adev, true);
1443 /* enable sdma ring preemption */
1444 sdma_v4_0_ctx_switch_enable(adev, true);
1447 /* start the gfx rings and rlc compute queues */
1448 for (i = 0; i < adev->sdma.num_instances; i++) {
1451 WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0);
1452 sdma_v4_0_gfx_resume(adev, i);
1453 if (adev->sdma.has_page_queue)
1454 sdma_v4_0_page_resume(adev, i);
1456 /* set utc l1 enable flag always to 1 */
1457 temp = RREG32_SDMA(i, mmSDMA0_CNTL);
1458 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
1459 WREG32_SDMA(i, mmSDMA0_CNTL, temp);
1461 if (!amdgpu_sriov_vf(adev)) {
1463 temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
1464 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
1465 WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp);
1469 if (amdgpu_sriov_vf(adev)) {
1470 sdma_v4_0_ctx_switch_enable(adev, true);
1471 sdma_v4_0_enable(adev, true);
1473 r = sdma_v4_0_rlc_resume(adev);
1478 for (i = 0; i < adev->sdma.num_instances; i++) {
1479 ring = &adev->sdma.instance[i].ring;
1481 r = amdgpu_ring_test_helper(ring);
1485 if (adev->sdma.has_page_queue) {
1486 struct amdgpu_ring *page = &adev->sdma.instance[i].page;
1488 r = amdgpu_ring_test_helper(page);
1492 if (adev->mman.buffer_funcs_ring == page)
1493 amdgpu_ttm_set_buffer_funcs_status(adev, true);
1496 if (adev->mman.buffer_funcs_ring == ring)
1497 amdgpu_ttm_set_buffer_funcs_status(adev, true);
1504 * sdma_v4_0_ring_test_ring - simple async dma engine test
1506 * @ring: amdgpu_ring structure holding ring information
1508 * Test the DMA engine by writing using it to write an
1509 * value to memory. (VEGA10).
1510 * Returns 0 for success, error for failure.
1512 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring)
1514 struct amdgpu_device *adev = ring->adev;
1521 r = amdgpu_device_wb_get(adev, &index);
1525 gpu_addr = adev->wb.gpu_addr + (index * 4);
1527 adev->wb.wb[index] = cpu_to_le32(tmp);
1529 r = amdgpu_ring_alloc(ring, 5);
1533 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1534 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
1535 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
1536 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
1537 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
1538 amdgpu_ring_write(ring, 0xDEADBEEF);
1539 amdgpu_ring_commit(ring);
1541 for (i = 0; i < adev->usec_timeout; i++) {
1542 tmp = le32_to_cpu(adev->wb.wb[index]);
1543 if (tmp == 0xDEADBEEF)
1548 if (i >= adev->usec_timeout)
1552 amdgpu_device_wb_free(adev, index);
1557 * sdma_v4_0_ring_test_ib - test an IB on the DMA engine
1559 * @ring: amdgpu_ring structure holding ring information
1561 * Test a simple IB in the DMA ring (VEGA10).
1562 * Returns 0 on success, error on failure.
1564 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1566 struct amdgpu_device *adev = ring->adev;
1567 struct amdgpu_ib ib;
1568 struct dma_fence *f = NULL;
1574 r = amdgpu_device_wb_get(adev, &index);
1578 gpu_addr = adev->wb.gpu_addr + (index * 4);
1580 adev->wb.wb[index] = cpu_to_le32(tmp);
1581 memset(&ib, 0, sizeof(ib));
1582 r = amdgpu_ib_get(adev, NULL, 256,
1583 AMDGPU_IB_POOL_DIRECT, &ib);
1587 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1588 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1589 ib.ptr[1] = lower_32_bits(gpu_addr);
1590 ib.ptr[2] = upper_32_bits(gpu_addr);
1591 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1592 ib.ptr[4] = 0xDEADBEEF;
1593 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1594 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1595 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1598 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1602 r = dma_fence_wait_timeout(f, false, timeout);
1609 tmp = le32_to_cpu(adev->wb.wb[index]);
1610 if (tmp == 0xDEADBEEF)
1616 amdgpu_ib_free(adev, &ib, NULL);
1619 amdgpu_device_wb_free(adev, index);
1625 * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART
1627 * @ib: indirect buffer to fill with commands
1628 * @pe: addr of the page entry
1629 * @src: src addr to copy from
1630 * @count: number of page entries to update
1632 * Update PTEs by copying them from the GART using sDMA (VEGA10).
1634 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib,
1635 uint64_t pe, uint64_t src,
1638 unsigned bytes = count * 8;
1640 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1641 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1642 ib->ptr[ib->length_dw++] = bytes - 1;
1643 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1644 ib->ptr[ib->length_dw++] = lower_32_bits(src);
1645 ib->ptr[ib->length_dw++] = upper_32_bits(src);
1646 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1647 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1652 * sdma_v4_0_vm_write_pte - update PTEs by writing them manually
1654 * @ib: indirect buffer to fill with commands
1655 * @pe: addr of the page entry
1656 * @addr: dst addr to write into pe
1657 * @count: number of page entries to update
1658 * @incr: increase next addr by incr bytes
1659 * @flags: access flags
1661 * Update PTEs by writing them manually using sDMA (VEGA10).
1663 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1664 uint64_t value, unsigned count,
1667 unsigned ndw = count * 2;
1669 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1670 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1671 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1672 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1673 ib->ptr[ib->length_dw++] = ndw - 1;
1674 for (; ndw > 0; ndw -= 2) {
1675 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1676 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1682 * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA
1684 * @ib: indirect buffer to fill with commands
1685 * @pe: addr of the page entry
1686 * @addr: dst addr to write into pe
1687 * @count: number of page entries to update
1688 * @incr: increase next addr by incr bytes
1689 * @flags: access flags
1691 * Update the page tables using sDMA (VEGA10).
1693 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1695 uint64_t addr, unsigned count,
1696 uint32_t incr, uint64_t flags)
1698 /* for physically contiguous pages (vram) */
1699 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1700 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1701 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1702 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1703 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1704 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1705 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1706 ib->ptr[ib->length_dw++] = incr; /* increment size */
1707 ib->ptr[ib->length_dw++] = 0;
1708 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1712 * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw
1714 * @ib: indirect buffer to fill with padding
1717 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1719 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1723 pad_count = (-ib->length_dw) & 7;
1724 for (i = 0; i < pad_count; i++)
1725 if (sdma && sdma->burst_nop && (i == 0))
1726 ib->ptr[ib->length_dw++] =
1727 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1728 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1730 ib->ptr[ib->length_dw++] =
1731 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1736 * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline
1738 * @ring: amdgpu_ring pointer
1740 * Make sure all previous operations are completed (CIK).
1742 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1744 uint32_t seq = ring->fence_drv.sync_seq;
1745 uint64_t addr = ring->fence_drv.gpu_addr;
1748 sdma_v4_0_wait_reg_mem(ring, 1, 0,
1750 upper_32_bits(addr) & 0xffffffff,
1751 seq, 0xffffffff, 4);
1756 * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA
1758 * @ring: amdgpu_ring pointer
1759 * @vm: amdgpu_vm pointer
1761 * Update the page table base and flush the VM TLB
1762 * using sDMA (VEGA10).
1764 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1765 unsigned vmid, uint64_t pd_addr)
1767 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1770 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring,
1771 uint32_t reg, uint32_t val)
1773 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1774 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1775 amdgpu_ring_write(ring, reg);
1776 amdgpu_ring_write(ring, val);
1779 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1780 uint32_t val, uint32_t mask)
1782 sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
1785 static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev)
1787 uint fw_version = adev->sdma.instance[0].fw_version;
1789 switch (adev->asic_type) {
1791 return fw_version >= 430;
1793 /*return fw_version >= 31;*/
1796 return fw_version >= 123;
1802 static int sdma_v4_0_early_init(void *handle)
1804 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1807 if (adev->flags & AMD_IS_APU)
1808 adev->sdma.num_instances = 1;
1809 else if (adev->asic_type == CHIP_ARCTURUS)
1810 adev->sdma.num_instances = 8;
1812 adev->sdma.num_instances = 2;
1814 r = sdma_v4_0_init_microcode(adev);
1816 DRM_ERROR("Failed to load sdma firmware!\n");
1820 /* TODO: Page queue breaks driver reload under SRIOV */
1821 if ((adev->asic_type == CHIP_VEGA10) && amdgpu_sriov_vf((adev)))
1822 adev->sdma.has_page_queue = false;
1823 else if (sdma_v4_0_fw_support_paging_queue(adev))
1824 adev->sdma.has_page_queue = true;
1826 sdma_v4_0_set_ring_funcs(adev);
1827 sdma_v4_0_set_buffer_funcs(adev);
1828 sdma_v4_0_set_vm_pte_funcs(adev);
1829 sdma_v4_0_set_irq_funcs(adev);
1830 sdma_v4_0_set_ras_funcs(adev);
1835 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
1837 struct amdgpu_iv_entry *entry);
1839 static int sdma_v4_0_late_init(void *handle)
1841 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1842 struct ras_ih_if ih_info = {
1843 .cb = sdma_v4_0_process_ras_data_cb,
1846 sdma_v4_0_setup_ulv(adev);
1848 if (adev->sdma.funcs && adev->sdma.funcs->reset_ras_error_count)
1849 adev->sdma.funcs->reset_ras_error_count(adev);
1851 if (adev->sdma.funcs && adev->sdma.funcs->ras_late_init)
1852 return adev->sdma.funcs->ras_late_init(adev, &ih_info);
1857 static int sdma_v4_0_sw_init(void *handle)
1859 struct amdgpu_ring *ring;
1861 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1863 /* SDMA trap event */
1864 for (i = 0; i < adev->sdma.num_instances; i++) {
1865 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1866 SDMA0_4_0__SRCID__SDMA_TRAP,
1867 &adev->sdma.trap_irq);
1872 /* SDMA SRAM ECC event */
1873 for (i = 0; i < adev->sdma.num_instances; i++) {
1874 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1875 SDMA0_4_0__SRCID__SDMA_SRAM_ECC,
1876 &adev->sdma.ecc_irq);
1881 for (i = 0; i < adev->sdma.num_instances; i++) {
1882 ring = &adev->sdma.instance[i].ring;
1883 ring->ring_obj = NULL;
1884 ring->use_doorbell = true;
1886 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1887 ring->use_doorbell?"true":"false");
1889 /* doorbell size is 2 dwords, get DWORD offset */
1890 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1892 sprintf(ring->name, "sdma%d", i);
1893 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1894 AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1895 AMDGPU_RING_PRIO_DEFAULT);
1899 if (adev->sdma.has_page_queue) {
1900 ring = &adev->sdma.instance[i].page;
1901 ring->ring_obj = NULL;
1902 ring->use_doorbell = true;
1904 /* paging queue use same doorbell index/routing as gfx queue
1905 * with 0x400 (4096 dwords) offset on second doorbell page
1907 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1908 ring->doorbell_index += 0x400;
1910 sprintf(ring->name, "page%d", i);
1911 r = amdgpu_ring_init(adev, ring, 1024,
1912 &adev->sdma.trap_irq,
1913 AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1914 AMDGPU_RING_PRIO_DEFAULT);
1923 static int sdma_v4_0_sw_fini(void *handle)
1925 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1928 if (adev->sdma.funcs && adev->sdma.funcs->ras_fini)
1929 adev->sdma.funcs->ras_fini(adev);
1931 for (i = 0; i < adev->sdma.num_instances; i++) {
1932 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1933 if (adev->sdma.has_page_queue)
1934 amdgpu_ring_fini(&adev->sdma.instance[i].page);
1937 sdma_v4_0_destroy_inst_ctx(adev);
1942 static int sdma_v4_0_hw_init(void *handle)
1945 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1947 if (adev->flags & AMD_IS_APU)
1948 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false);
1950 if (!amdgpu_sriov_vf(adev))
1951 sdma_v4_0_init_golden_registers(adev);
1953 r = sdma_v4_0_start(adev);
1958 static int sdma_v4_0_hw_fini(void *handle)
1960 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1963 if (amdgpu_sriov_vf(adev))
1966 for (i = 0; i < adev->sdma.num_instances; i++) {
1967 amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
1968 AMDGPU_SDMA_IRQ_INSTANCE0 + i);
1971 sdma_v4_0_ctx_switch_enable(adev, false);
1972 sdma_v4_0_enable(adev, false);
1974 if (adev->flags & AMD_IS_APU)
1975 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true);
1980 static int sdma_v4_0_suspend(void *handle)
1982 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1984 return sdma_v4_0_hw_fini(adev);
1987 static int sdma_v4_0_resume(void *handle)
1989 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1991 return sdma_v4_0_hw_init(adev);
1994 static bool sdma_v4_0_is_idle(void *handle)
1996 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1999 for (i = 0; i < adev->sdma.num_instances; i++) {
2000 u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG);
2002 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
2009 static int sdma_v4_0_wait_for_idle(void *handle)
2012 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES];
2013 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2015 for (i = 0; i < adev->usec_timeout; i++) {
2016 for (j = 0; j < adev->sdma.num_instances; j++) {
2017 sdma[j] = RREG32_SDMA(j, mmSDMA0_STATUS_REG);
2018 if (!(sdma[j] & SDMA0_STATUS_REG__IDLE_MASK))
2021 if (j == adev->sdma.num_instances)
2028 static int sdma_v4_0_soft_reset(void *handle)
2035 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev,
2036 struct amdgpu_irq_src *source,
2038 enum amdgpu_interrupt_state state)
2042 sdma_cntl = RREG32_SDMA(type, mmSDMA0_CNTL);
2043 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
2044 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
2045 WREG32_SDMA(type, mmSDMA0_CNTL, sdma_cntl);
2050 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
2051 struct amdgpu_irq_src *source,
2052 struct amdgpu_iv_entry *entry)
2056 DRM_DEBUG("IH: SDMA trap\n");
2057 instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2058 switch (entry->ring_id) {
2060 amdgpu_fence_process(&adev->sdma.instance[instance].ring);
2063 if (adev->asic_type == CHIP_VEGA20)
2064 amdgpu_fence_process(&adev->sdma.instance[instance].page);
2070 if (adev->asic_type != CHIP_VEGA20)
2071 amdgpu_fence_process(&adev->sdma.instance[instance].page);
2077 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
2079 struct amdgpu_iv_entry *entry)
2083 /* When “Full RAS” is enabled, the per-IP interrupt sources should
2084 * be disabled and the driver should only look for the aggregated
2085 * interrupt via sync flood
2087 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
2090 instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2094 amdgpu_sdma_process_ras_data_cb(adev, err_data, entry);
2097 return AMDGPU_RAS_SUCCESS;
2100 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev,
2101 struct amdgpu_irq_src *source,
2102 struct amdgpu_iv_entry *entry)
2106 DRM_ERROR("Illegal instruction in SDMA command stream\n");
2108 instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2112 switch (entry->ring_id) {
2114 drm_sched_fault(&adev->sdma.instance[instance].ring.sched);
2120 static int sdma_v4_0_set_ecc_irq_state(struct amdgpu_device *adev,
2121 struct amdgpu_irq_src *source,
2123 enum amdgpu_interrupt_state state)
2125 u32 sdma_edc_config;
2127 sdma_edc_config = RREG32_SDMA(type, mmSDMA0_EDC_CONFIG);
2128 sdma_edc_config = REG_SET_FIELD(sdma_edc_config, SDMA0_EDC_CONFIG, ECC_INT_ENABLE,
2129 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
2130 WREG32_SDMA(type, mmSDMA0_EDC_CONFIG, sdma_edc_config);
2135 static void sdma_v4_0_update_medium_grain_clock_gating(
2136 struct amdgpu_device *adev,
2142 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
2143 for (i = 0; i < adev->sdma.num_instances; i++) {
2144 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);
2145 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
2146 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
2147 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
2148 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
2149 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
2150 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
2151 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
2152 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
2154 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
2157 for (i = 0; i < adev->sdma.num_instances; i++) {
2158 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);
2159 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
2160 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
2161 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
2162 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
2163 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
2164 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
2165 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
2166 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
2168 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
2174 static void sdma_v4_0_update_medium_grain_light_sleep(
2175 struct amdgpu_device *adev,
2181 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
2182 for (i = 0; i < adev->sdma.num_instances; i++) {
2183 /* 1-not override: enable sdma mem light sleep */
2184 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);
2185 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
2187 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);
2190 for (i = 0; i < adev->sdma.num_instances; i++) {
2191 /* 0-override:disable sdma mem light sleep */
2192 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);
2193 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
2195 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);
2200 static int sdma_v4_0_set_clockgating_state(void *handle,
2201 enum amd_clockgating_state state)
2203 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2205 if (amdgpu_sriov_vf(adev))
2208 switch (adev->asic_type) {
2215 sdma_v4_0_update_medium_grain_clock_gating(adev,
2216 state == AMD_CG_STATE_GATE);
2217 sdma_v4_0_update_medium_grain_light_sleep(adev,
2218 state == AMD_CG_STATE_GATE);
2226 static int sdma_v4_0_set_powergating_state(void *handle,
2227 enum amd_powergating_state state)
2229 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2231 switch (adev->asic_type) {
2234 sdma_v4_1_update_power_gating(adev,
2235 state == AMD_PG_STATE_GATE ? true : false);
2244 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags)
2246 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2249 if (amdgpu_sriov_vf(adev))
2252 /* AMD_CG_SUPPORT_SDMA_MGCG */
2253 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
2254 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
2255 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
2257 /* AMD_CG_SUPPORT_SDMA_LS */
2258 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
2259 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
2260 *flags |= AMD_CG_SUPPORT_SDMA_LS;
2263 const struct amd_ip_funcs sdma_v4_0_ip_funcs = {
2264 .name = "sdma_v4_0",
2265 .early_init = sdma_v4_0_early_init,
2266 .late_init = sdma_v4_0_late_init,
2267 .sw_init = sdma_v4_0_sw_init,
2268 .sw_fini = sdma_v4_0_sw_fini,
2269 .hw_init = sdma_v4_0_hw_init,
2270 .hw_fini = sdma_v4_0_hw_fini,
2271 .suspend = sdma_v4_0_suspend,
2272 .resume = sdma_v4_0_resume,
2273 .is_idle = sdma_v4_0_is_idle,
2274 .wait_for_idle = sdma_v4_0_wait_for_idle,
2275 .soft_reset = sdma_v4_0_soft_reset,
2276 .set_clockgating_state = sdma_v4_0_set_clockgating_state,
2277 .set_powergating_state = sdma_v4_0_set_powergating_state,
2278 .get_clockgating_state = sdma_v4_0_get_clockgating_state,
2281 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
2282 .type = AMDGPU_RING_TYPE_SDMA,
2284 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2285 .support_64bit_ptrs = true,
2286 .vmhub = AMDGPU_MMHUB_0,
2287 .get_rptr = sdma_v4_0_ring_get_rptr,
2288 .get_wptr = sdma_v4_0_ring_get_wptr,
2289 .set_wptr = sdma_v4_0_ring_set_wptr,
2291 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2292 3 + /* hdp invalidate */
2293 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2294 /* sdma_v4_0_ring_emit_vm_flush */
2295 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2296 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2297 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2298 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2299 .emit_ib = sdma_v4_0_ring_emit_ib,
2300 .emit_fence = sdma_v4_0_ring_emit_fence,
2301 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2302 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2303 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2304 .test_ring = sdma_v4_0_ring_test_ring,
2305 .test_ib = sdma_v4_0_ring_test_ib,
2306 .insert_nop = sdma_v4_0_ring_insert_nop,
2307 .pad_ib = sdma_v4_0_ring_pad_ib,
2308 .emit_wreg = sdma_v4_0_ring_emit_wreg,
2309 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2310 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2314 * On Arcturus, SDMA instance 5~7 has a different vmhub type(AMDGPU_MMHUB_1).
2315 * So create a individual constant ring_funcs for those instances.
2317 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs_2nd_mmhub = {
2318 .type = AMDGPU_RING_TYPE_SDMA,
2320 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2321 .support_64bit_ptrs = true,
2322 .vmhub = AMDGPU_MMHUB_1,
2323 .get_rptr = sdma_v4_0_ring_get_rptr,
2324 .get_wptr = sdma_v4_0_ring_get_wptr,
2325 .set_wptr = sdma_v4_0_ring_set_wptr,
2327 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2328 3 + /* hdp invalidate */
2329 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2330 /* sdma_v4_0_ring_emit_vm_flush */
2331 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2332 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2333 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2334 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2335 .emit_ib = sdma_v4_0_ring_emit_ib,
2336 .emit_fence = sdma_v4_0_ring_emit_fence,
2337 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2338 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2339 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2340 .test_ring = sdma_v4_0_ring_test_ring,
2341 .test_ib = sdma_v4_0_ring_test_ib,
2342 .insert_nop = sdma_v4_0_ring_insert_nop,
2343 .pad_ib = sdma_v4_0_ring_pad_ib,
2344 .emit_wreg = sdma_v4_0_ring_emit_wreg,
2345 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2346 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2349 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = {
2350 .type = AMDGPU_RING_TYPE_SDMA,
2352 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2353 .support_64bit_ptrs = true,
2354 .vmhub = AMDGPU_MMHUB_0,
2355 .get_rptr = sdma_v4_0_ring_get_rptr,
2356 .get_wptr = sdma_v4_0_page_ring_get_wptr,
2357 .set_wptr = sdma_v4_0_page_ring_set_wptr,
2359 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2360 3 + /* hdp invalidate */
2361 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2362 /* sdma_v4_0_ring_emit_vm_flush */
2363 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2364 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2365 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2366 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2367 .emit_ib = sdma_v4_0_ring_emit_ib,
2368 .emit_fence = sdma_v4_0_ring_emit_fence,
2369 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2370 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2371 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2372 .test_ring = sdma_v4_0_ring_test_ring,
2373 .test_ib = sdma_v4_0_ring_test_ib,
2374 .insert_nop = sdma_v4_0_ring_insert_nop,
2375 .pad_ib = sdma_v4_0_ring_pad_ib,
2376 .emit_wreg = sdma_v4_0_ring_emit_wreg,
2377 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2378 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2381 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs_2nd_mmhub = {
2382 .type = AMDGPU_RING_TYPE_SDMA,
2384 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2385 .support_64bit_ptrs = true,
2386 .vmhub = AMDGPU_MMHUB_1,
2387 .get_rptr = sdma_v4_0_ring_get_rptr,
2388 .get_wptr = sdma_v4_0_page_ring_get_wptr,
2389 .set_wptr = sdma_v4_0_page_ring_set_wptr,
2391 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2392 3 + /* hdp invalidate */
2393 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2394 /* sdma_v4_0_ring_emit_vm_flush */
2395 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2396 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2397 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2398 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2399 .emit_ib = sdma_v4_0_ring_emit_ib,
2400 .emit_fence = sdma_v4_0_ring_emit_fence,
2401 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2402 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2403 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2404 .test_ring = sdma_v4_0_ring_test_ring,
2405 .test_ib = sdma_v4_0_ring_test_ib,
2406 .insert_nop = sdma_v4_0_ring_insert_nop,
2407 .pad_ib = sdma_v4_0_ring_pad_ib,
2408 .emit_wreg = sdma_v4_0_ring_emit_wreg,
2409 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2410 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2413 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
2417 for (i = 0; i < adev->sdma.num_instances; i++) {
2418 if (adev->asic_type == CHIP_ARCTURUS && i >= 5)
2419 adev->sdma.instance[i].ring.funcs =
2420 &sdma_v4_0_ring_funcs_2nd_mmhub;
2422 adev->sdma.instance[i].ring.funcs =
2423 &sdma_v4_0_ring_funcs;
2424 adev->sdma.instance[i].ring.me = i;
2425 if (adev->sdma.has_page_queue) {
2426 if (adev->asic_type == CHIP_ARCTURUS && i >= 5)
2427 adev->sdma.instance[i].page.funcs =
2428 &sdma_v4_0_page_ring_funcs_2nd_mmhub;
2430 adev->sdma.instance[i].page.funcs =
2431 &sdma_v4_0_page_ring_funcs;
2432 adev->sdma.instance[i].page.me = i;
2437 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = {
2438 .set = sdma_v4_0_set_trap_irq_state,
2439 .process = sdma_v4_0_process_trap_irq,
2442 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = {
2443 .process = sdma_v4_0_process_illegal_inst_irq,
2446 static const struct amdgpu_irq_src_funcs sdma_v4_0_ecc_irq_funcs = {
2447 .set = sdma_v4_0_set_ecc_irq_state,
2448 .process = amdgpu_sdma_process_ecc_irq,
2453 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev)
2455 switch (adev->sdma.num_instances) {
2457 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1;
2458 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1;
2461 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
2462 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
2466 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2;
2467 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2;
2470 adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs;
2471 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs;
2472 adev->sdma.ecc_irq.funcs = &sdma_v4_0_ecc_irq_funcs;
2476 * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine
2478 * @ring: amdgpu_ring structure holding ring information
2479 * @src_offset: src GPU address
2480 * @dst_offset: dst GPU address
2481 * @byte_count: number of bytes to xfer
2483 * Copy GPU buffers using the DMA engine (VEGA10/12).
2484 * Used by the amdgpu ttm implementation to move pages if
2485 * registered as the asic copy callback.
2487 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib,
2488 uint64_t src_offset,
2489 uint64_t dst_offset,
2490 uint32_t byte_count,
2493 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
2494 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
2495 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
2496 ib->ptr[ib->length_dw++] = byte_count - 1;
2497 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
2498 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
2499 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
2500 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2501 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2505 * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine
2507 * @ring: amdgpu_ring structure holding ring information
2508 * @src_data: value to write to buffer
2509 * @dst_offset: dst GPU address
2510 * @byte_count: number of bytes to xfer
2512 * Fill GPU buffers using the DMA engine (VEGA10/12).
2514 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib,
2516 uint64_t dst_offset,
2517 uint32_t byte_count)
2519 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
2520 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2521 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2522 ib->ptr[ib->length_dw++] = src_data;
2523 ib->ptr[ib->length_dw++] = byte_count - 1;
2526 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = {
2527 .copy_max_bytes = 0x400000,
2529 .emit_copy_buffer = sdma_v4_0_emit_copy_buffer,
2531 .fill_max_bytes = 0x400000,
2533 .emit_fill_buffer = sdma_v4_0_emit_fill_buffer,
2536 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
2538 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
2539 if (adev->sdma.has_page_queue)
2540 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
2542 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
2545 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = {
2546 .copy_pte_num_dw = 7,
2547 .copy_pte = sdma_v4_0_vm_copy_pte,
2549 .write_pte = sdma_v4_0_vm_write_pte,
2550 .set_pte_pde = sdma_v4_0_vm_set_pte_pde,
2553 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev)
2555 struct drm_gpu_scheduler *sched;
2558 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
2559 for (i = 0; i < adev->sdma.num_instances; i++) {
2560 if (adev->sdma.has_page_queue)
2561 sched = &adev->sdma.instance[i].page.sched;
2563 sched = &adev->sdma.instance[i].ring.sched;
2564 adev->vm_manager.vm_pte_scheds[i] = sched;
2566 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
2569 static void sdma_v4_0_get_ras_error_count(uint32_t value,
2571 uint32_t *sec_count)
2576 /* double bits error (multiple bits) error detection is not supported */
2577 for (i = 0; i < ARRAY_SIZE(sdma_v4_0_ras_fields); i++) {
2578 /* the SDMA_EDC_COUNTER register in each sdma instance
2579 * shares the same sed shift_mask
2582 sdma_v4_0_ras_fields[i].sec_count_mask) >>
2583 sdma_v4_0_ras_fields[i].sec_count_shift;
2585 DRM_INFO("Detected %s in SDMA%d, SED %d\n",
2586 sdma_v4_0_ras_fields[i].name,
2588 *sec_count += sec_cnt;
2593 static int sdma_v4_0_query_ras_error_count(struct amdgpu_device *adev,
2594 uint32_t instance, void *ras_error_status)
2596 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
2597 uint32_t sec_count = 0;
2598 uint32_t reg_value = 0;
2600 reg_value = RREG32_SDMA(instance, mmSDMA0_EDC_COUNTER);
2601 /* double bit error is not supported */
2603 sdma_v4_0_get_ras_error_count(reg_value,
2604 instance, &sec_count);
2605 /* err_data->ce_count should be initialized to 0
2606 * before calling into this function */
2607 err_data->ce_count += sec_count;
2608 /* double bit error is not supported
2609 * set ue count to 0 */
2610 err_data->ue_count = 0;
2615 static void sdma_v4_0_reset_ras_error_count(struct amdgpu_device *adev)
2619 /* read back edc counter registers to clear the counters */
2620 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2621 for (i = 0; i < adev->sdma.num_instances; i++)
2622 RREG32_SDMA(i, mmSDMA0_EDC_COUNTER);
2626 static const struct amdgpu_sdma_ras_funcs sdma_v4_0_ras_funcs = {
2627 .ras_late_init = amdgpu_sdma_ras_late_init,
2628 .ras_fini = amdgpu_sdma_ras_fini,
2629 .query_ras_error_count = sdma_v4_0_query_ras_error_count,
2630 .reset_ras_error_count = sdma_v4_0_reset_ras_error_count,
2633 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev)
2635 switch (adev->asic_type) {
2638 adev->sdma.funcs = &sdma_v4_0_ras_funcs;
2645 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = {
2646 .type = AMD_IP_BLOCK_TYPE_SDMA,
2650 .funcs = &sdma_v4_0_ip_funcs,