2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
25 #include <linux/firmware.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
30 #include "amdgpu_ucode.h"
31 #include "amdgpu_trace.h"
33 #include "sdma0/sdma0_4_2_offset.h"
34 #include "sdma0/sdma0_4_2_sh_mask.h"
35 #include "sdma1/sdma1_4_2_offset.h"
36 #include "sdma1/sdma1_4_2_sh_mask.h"
37 #include "sdma2/sdma2_4_2_2_offset.h"
38 #include "sdma2/sdma2_4_2_2_sh_mask.h"
39 #include "sdma3/sdma3_4_2_2_offset.h"
40 #include "sdma3/sdma3_4_2_2_sh_mask.h"
41 #include "sdma4/sdma4_4_2_2_offset.h"
42 #include "sdma4/sdma4_4_2_2_sh_mask.h"
43 #include "sdma5/sdma5_4_2_2_offset.h"
44 #include "sdma5/sdma5_4_2_2_sh_mask.h"
45 #include "sdma6/sdma6_4_2_2_offset.h"
46 #include "sdma6/sdma6_4_2_2_sh_mask.h"
47 #include "sdma7/sdma7_4_2_2_offset.h"
48 #include "sdma7/sdma7_4_2_2_sh_mask.h"
49 #include "hdp/hdp_4_0_offset.h"
50 #include "sdma0/sdma0_4_1_default.h"
52 #include "soc15_common.h"
54 #include "vega10_sdma_pkt_open.h"
56 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h"
57 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h"
59 #include "amdgpu_ras.h"
61 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin");
62 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin");
63 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin");
64 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin");
65 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin");
66 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin");
67 MODULE_FIRMWARE("amdgpu/raven_sdma.bin");
68 MODULE_FIRMWARE("amdgpu/picasso_sdma.bin");
69 MODULE_FIRMWARE("amdgpu/raven2_sdma.bin");
70 MODULE_FIRMWARE("amdgpu/arcturus_sdma.bin");
71 MODULE_FIRMWARE("amdgpu/renoir_sdma.bin");
73 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L
74 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
76 #define WREG32_SDMA(instance, offset, value) \
77 WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value)
78 #define RREG32_SDMA(instance, offset) \
79 RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)))
81 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev);
82 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev);
83 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev);
84 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev);
86 static const struct soc15_reg_golden golden_settings_sdma_4[] = {
87 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
88 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
89 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),
90 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
91 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
92 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
93 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000),
94 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
95 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
96 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
97 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
98 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
99 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000),
100 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
101 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100),
102 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
103 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
104 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
105 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000),
106 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
107 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
108 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
109 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
110 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
111 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000)
114 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = {
115 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
116 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
117 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
118 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
119 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002)
122 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = {
123 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
124 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001),
125 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
126 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
127 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001)
130 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = {
131 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
132 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
133 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100),
134 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
135 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051),
136 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100),
137 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
138 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100),
139 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
140 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
141 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000)
144 static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = {
145 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
148 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] =
150 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
151 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
152 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
153 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
154 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
155 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
156 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
157 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
158 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003),
159 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
160 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
161 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
162 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
163 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
164 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
165 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
166 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
167 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
168 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
169 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
170 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
171 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
172 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
173 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
174 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
175 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
178 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = {
179 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
180 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
181 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
182 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
183 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
184 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
185 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
186 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
187 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003),
188 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
189 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
190 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
191 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
192 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
193 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
194 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
195 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
196 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
197 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
198 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
199 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
200 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
201 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
202 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
203 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
204 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
207 static const struct soc15_reg_golden golden_settings_sdma_rv1[] =
209 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
210 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002)
213 static const struct soc15_reg_golden golden_settings_sdma_rv2[] =
215 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001),
216 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001)
219 static const struct soc15_reg_golden golden_settings_sdma_arct[] =
221 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
222 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
223 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
224 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
225 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
226 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
227 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
228 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
229 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
230 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
231 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
232 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
233 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
234 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
235 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
236 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
237 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
238 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
239 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
240 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
241 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
242 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
243 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
244 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002)
247 static const struct soc15_reg_golden golden_settings_sdma_4_3[] = {
248 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
249 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
250 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
251 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002),
252 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
253 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051),
254 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
255 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
256 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
259 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
260 u32 instance, u32 offset)
264 return (adev->reg_offset[SDMA0_HWIP][0][0] + offset);
266 return (adev->reg_offset[SDMA1_HWIP][0][0] + offset);
268 return (adev->reg_offset[SDMA2_HWIP][0][1] + offset);
270 return (adev->reg_offset[SDMA3_HWIP][0][1] + offset);
272 return (adev->reg_offset[SDMA4_HWIP][0][1] + offset);
274 return (adev->reg_offset[SDMA5_HWIP][0][1] + offset);
276 return (adev->reg_offset[SDMA6_HWIP][0][1] + offset);
278 return (adev->reg_offset[SDMA7_HWIP][0][1] + offset);
285 static unsigned sdma_v4_0_seq_to_irq_id(int seq_num)
289 return SOC15_IH_CLIENTID_SDMA0;
291 return SOC15_IH_CLIENTID_SDMA1;
293 return SOC15_IH_CLIENTID_SDMA2;
295 return SOC15_IH_CLIENTID_SDMA3;
297 return SOC15_IH_CLIENTID_SDMA4;
299 return SOC15_IH_CLIENTID_SDMA5;
301 return SOC15_IH_CLIENTID_SDMA6;
303 return SOC15_IH_CLIENTID_SDMA7;
310 static int sdma_v4_0_irq_id_to_seq(unsigned client_id)
313 case SOC15_IH_CLIENTID_SDMA0:
315 case SOC15_IH_CLIENTID_SDMA1:
317 case SOC15_IH_CLIENTID_SDMA2:
319 case SOC15_IH_CLIENTID_SDMA3:
321 case SOC15_IH_CLIENTID_SDMA4:
323 case SOC15_IH_CLIENTID_SDMA5:
325 case SOC15_IH_CLIENTID_SDMA6:
327 case SOC15_IH_CLIENTID_SDMA7:
335 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
337 switch (adev->asic_type) {
339 soc15_program_register_sequence(adev,
340 golden_settings_sdma_4,
341 ARRAY_SIZE(golden_settings_sdma_4));
342 soc15_program_register_sequence(adev,
343 golden_settings_sdma_vg10,
344 ARRAY_SIZE(golden_settings_sdma_vg10));
347 soc15_program_register_sequence(adev,
348 golden_settings_sdma_4,
349 ARRAY_SIZE(golden_settings_sdma_4));
350 soc15_program_register_sequence(adev,
351 golden_settings_sdma_vg12,
352 ARRAY_SIZE(golden_settings_sdma_vg12));
355 soc15_program_register_sequence(adev,
356 golden_settings_sdma0_4_2_init,
357 ARRAY_SIZE(golden_settings_sdma0_4_2_init));
358 soc15_program_register_sequence(adev,
359 golden_settings_sdma0_4_2,
360 ARRAY_SIZE(golden_settings_sdma0_4_2));
361 soc15_program_register_sequence(adev,
362 golden_settings_sdma1_4_2,
363 ARRAY_SIZE(golden_settings_sdma1_4_2));
366 soc15_program_register_sequence(adev,
367 golden_settings_sdma_arct,
368 ARRAY_SIZE(golden_settings_sdma_arct));
371 soc15_program_register_sequence(adev,
372 golden_settings_sdma_4_1,
373 ARRAY_SIZE(golden_settings_sdma_4_1));
374 if (adev->rev_id >= 8)
375 soc15_program_register_sequence(adev,
376 golden_settings_sdma_rv2,
377 ARRAY_SIZE(golden_settings_sdma_rv2));
379 soc15_program_register_sequence(adev,
380 golden_settings_sdma_rv1,
381 ARRAY_SIZE(golden_settings_sdma_rv1));
384 soc15_program_register_sequence(adev,
385 golden_settings_sdma_4_3,
386 ARRAY_SIZE(golden_settings_sdma_4_3));
393 static int sdma_v4_0_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
396 const struct sdma_firmware_header_v1_0 *hdr;
398 err = amdgpu_ucode_validate(sdma_inst->fw);
402 hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
403 sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
404 sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
406 if (sdma_inst->feature_version >= 20)
407 sdma_inst->burst_nop = true;
412 static void sdma_v4_0_destroy_inst_ctx(struct amdgpu_device *adev)
416 for (i = 0; i < adev->sdma.num_instances; i++) {
417 if (adev->sdma.instance[i].fw != NULL)
418 release_firmware(adev->sdma.instance[i].fw);
420 /* arcturus shares the same FW memory across
421 all SDMA isntances */
422 if (adev->asic_type == CHIP_ARCTURUS)
426 memset((void*)adev->sdma.instance, 0,
427 sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
431 * sdma_v4_0_init_microcode - load ucode images from disk
433 * @adev: amdgpu_device pointer
435 * Use the firmware interface to load the ucode images into
436 * the driver (not loaded into hw).
437 * Returns 0 on success, error on failure.
440 // emulation only, won't work on real chip
441 // vega10 real chip need to use PSP to load firmware
442 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
444 const char *chip_name;
447 struct amdgpu_firmware_info *info = NULL;
448 const struct common_firmware_header *header = NULL;
452 switch (adev->asic_type) {
454 chip_name = "vega10";
457 chip_name = "vega12";
460 chip_name = "vega20";
463 if (adev->rev_id >= 8)
464 chip_name = "raven2";
465 else if (adev->pdev->device == 0x15d8)
466 chip_name = "picasso";
471 chip_name = "arcturus";
474 chip_name = "renoir";
480 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
482 err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);
486 err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[0]);
490 for (i = 1; i < adev->sdma.num_instances; i++) {
491 if (adev->asic_type == CHIP_ARCTURUS) {
492 /* Acturus will leverage the same FW memory
493 for every SDMA instance */
494 memcpy((void*)&adev->sdma.instance[i],
495 (void*)&adev->sdma.instance[0],
496 sizeof(struct amdgpu_sdma_instance));
499 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i);
501 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
505 err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[i]);
511 DRM_DEBUG("psp_load == '%s'\n",
512 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
514 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
515 for (i = 0; i < adev->sdma.num_instances; i++) {
516 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
517 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
518 info->fw = adev->sdma.instance[i].fw;
519 header = (const struct common_firmware_header *)info->fw->data;
520 adev->firmware.fw_size +=
521 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
527 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name);
528 sdma_v4_0_destroy_inst_ctx(adev);
534 * sdma_v4_0_ring_get_rptr - get the current read pointer
536 * @ring: amdgpu ring pointer
538 * Get the current rptr from the hardware (VEGA10+).
540 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring)
544 /* XXX check if swapping is necessary on BE */
545 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
547 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
548 return ((*rptr) >> 2);
552 * sdma_v4_0_ring_get_wptr - get the current write pointer
554 * @ring: amdgpu ring pointer
556 * Get the current wptr from the hardware (VEGA10+).
558 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
560 struct amdgpu_device *adev = ring->adev;
563 if (ring->use_doorbell) {
564 /* XXX check if swapping is necessary on BE */
565 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
566 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
568 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI);
570 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR);
571 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n",
579 * sdma_v4_0_ring_set_wptr - commit the write pointer
581 * @ring: amdgpu ring pointer
583 * Write the wptr back to the hardware (VEGA10+).
585 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
587 struct amdgpu_device *adev = ring->adev;
589 DRM_DEBUG("Setting write pointer\n");
590 if (ring->use_doorbell) {
591 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
593 DRM_DEBUG("Using doorbell -- "
594 "wptr_offs == 0x%08x "
595 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
596 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
598 lower_32_bits(ring->wptr << 2),
599 upper_32_bits(ring->wptr << 2));
600 /* XXX check if swapping is necessary on BE */
601 WRITE_ONCE(*wb, (ring->wptr << 2));
602 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
603 ring->doorbell_index, ring->wptr << 2);
604 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
606 DRM_DEBUG("Not using doorbell -- "
607 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
608 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
610 lower_32_bits(ring->wptr << 2),
612 upper_32_bits(ring->wptr << 2));
613 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR,
614 lower_32_bits(ring->wptr << 2));
615 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI,
616 upper_32_bits(ring->wptr << 2));
621 * sdma_v4_0_page_ring_get_wptr - get the current write pointer
623 * @ring: amdgpu ring pointer
625 * Get the current wptr from the hardware (VEGA10+).
627 static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring)
629 struct amdgpu_device *adev = ring->adev;
632 if (ring->use_doorbell) {
633 /* XXX check if swapping is necessary on BE */
634 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
636 wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI);
638 wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR);
645 * sdma_v4_0_ring_set_wptr - commit the write pointer
647 * @ring: amdgpu ring pointer
649 * Write the wptr back to the hardware (VEGA10+).
651 static void sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring *ring)
653 struct amdgpu_device *adev = ring->adev;
655 if (ring->use_doorbell) {
656 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
658 /* XXX check if swapping is necessary on BE */
659 WRITE_ONCE(*wb, (ring->wptr << 2));
660 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
662 uint64_t wptr = ring->wptr << 2;
664 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR,
665 lower_32_bits(wptr));
666 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI,
667 upper_32_bits(wptr));
671 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
673 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
676 for (i = 0; i < count; i++)
677 if (sdma && sdma->burst_nop && (i == 0))
678 amdgpu_ring_write(ring, ring->funcs->nop |
679 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
681 amdgpu_ring_write(ring, ring->funcs->nop);
685 * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine
687 * @ring: amdgpu ring pointer
688 * @ib: IB object to schedule
690 * Schedule an IB in the DMA ring (VEGA10).
692 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
693 struct amdgpu_job *job,
694 struct amdgpu_ib *ib,
697 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
699 /* IB packet must end on a 8 DW boundary */
700 sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
702 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
703 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
704 /* base must be 32 byte aligned */
705 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
706 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
707 amdgpu_ring_write(ring, ib->length_dw);
708 amdgpu_ring_write(ring, 0);
709 amdgpu_ring_write(ring, 0);
713 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring,
714 int mem_space, int hdp,
715 uint32_t addr0, uint32_t addr1,
716 uint32_t ref, uint32_t mask,
719 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
720 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) |
721 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) |
722 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
725 amdgpu_ring_write(ring, addr0);
726 amdgpu_ring_write(ring, addr1);
729 amdgpu_ring_write(ring, addr0 << 2);
730 amdgpu_ring_write(ring, addr1 << 2);
732 amdgpu_ring_write(ring, ref); /* reference */
733 amdgpu_ring_write(ring, mask); /* mask */
734 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
735 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */
739 * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
741 * @ring: amdgpu ring pointer
743 * Emit an hdp flush packet on the requested DMA ring.
745 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
747 struct amdgpu_device *adev = ring->adev;
748 u32 ref_and_mask = 0;
749 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
751 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
753 sdma_v4_0_wait_reg_mem(ring, 0, 1,
754 adev->nbio.funcs->get_hdp_flush_done_offset(adev),
755 adev->nbio.funcs->get_hdp_flush_req_offset(adev),
756 ref_and_mask, ref_and_mask, 10);
760 * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring
762 * @ring: amdgpu ring pointer
763 * @fence: amdgpu fence object
765 * Add a DMA fence packet to the ring to write
766 * the fence seq number and DMA trap packet to generate
767 * an interrupt if needed (VEGA10).
769 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
772 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
773 /* write the fence */
774 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
775 /* zero in first two bits */
777 amdgpu_ring_write(ring, lower_32_bits(addr));
778 amdgpu_ring_write(ring, upper_32_bits(addr));
779 amdgpu_ring_write(ring, lower_32_bits(seq));
781 /* optionally write high bits as well */
784 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
785 /* zero in first two bits */
787 amdgpu_ring_write(ring, lower_32_bits(addr));
788 amdgpu_ring_write(ring, upper_32_bits(addr));
789 amdgpu_ring_write(ring, upper_32_bits(seq));
792 /* generate an interrupt */
793 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
794 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
799 * sdma_v4_0_gfx_stop - stop the gfx async dma engines
801 * @adev: amdgpu_device pointer
803 * Stop the gfx async dma ring buffers (VEGA10).
805 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev)
807 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
808 u32 rb_cntl, ib_cntl;
811 for (i = 0; i < adev->sdma.num_instances; i++) {
812 sdma[i] = &adev->sdma.instance[i].ring;
814 if ((adev->mman.buffer_funcs_ring == sdma[i]) && unset != 1) {
815 amdgpu_ttm_set_buffer_funcs_status(adev, false);
819 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
820 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
821 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
822 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
823 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
824 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
826 sdma[i]->sched.ready = false;
831 * sdma_v4_0_rlc_stop - stop the compute async dma engines
833 * @adev: amdgpu_device pointer
835 * Stop the compute async dma queues (VEGA10).
837 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev)
843 * sdma_v4_0_page_stop - stop the page async dma engines
845 * @adev: amdgpu_device pointer
847 * Stop the page async dma ring buffers (VEGA10).
849 static void sdma_v4_0_page_stop(struct amdgpu_device *adev)
851 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
852 u32 rb_cntl, ib_cntl;
856 for (i = 0; i < adev->sdma.num_instances; i++) {
857 sdma[i] = &adev->sdma.instance[i].page;
859 if ((adev->mman.buffer_funcs_ring == sdma[i]) &&
861 amdgpu_ttm_set_buffer_funcs_status(adev, false);
865 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);
866 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
868 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
869 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL);
870 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL,
872 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
874 sdma[i]->sched.ready = false;
879 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
881 * @adev: amdgpu_device pointer
882 * @enable: enable/disable the DMA MEs context switch.
884 * Halt or unhalt the async dma engines context switch (VEGA10).
886 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
888 u32 f32_cntl, phase_quantum = 0;
891 if (amdgpu_sdma_phase_quantum) {
892 unsigned value = amdgpu_sdma_phase_quantum;
895 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
896 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
897 value = (value + 1) >> 1;
900 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
901 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
902 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
903 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
904 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
905 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
907 "clamping sdma_phase_quantum to %uK clock cycles\n",
911 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
912 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
915 for (i = 0; i < adev->sdma.num_instances; i++) {
916 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL);
917 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
918 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
919 if (enable && amdgpu_sdma_phase_quantum) {
920 WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum);
921 WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum);
922 WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum);
924 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl);
930 * sdma_v4_0_enable - stop the async dma engines
932 * @adev: amdgpu_device pointer
933 * @enable: enable/disable the DMA MEs.
935 * Halt or unhalt the async dma engines (VEGA10).
937 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable)
942 if (enable == false) {
943 sdma_v4_0_gfx_stop(adev);
944 sdma_v4_0_rlc_stop(adev);
945 if (adev->sdma.has_page_queue)
946 sdma_v4_0_page_stop(adev);
949 for (i = 0; i < adev->sdma.num_instances; i++) {
950 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
951 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
952 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl);
957 * sdma_v4_0_rb_cntl - get parameters for rb_cntl
959 static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl)
961 /* Set ring buffer size in dwords */
962 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4);
964 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
966 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
967 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
968 RPTR_WRITEBACK_SWAP_ENABLE, 1);
974 * sdma_v4_0_gfx_resume - setup and start the async dma engines
976 * @adev: amdgpu_device pointer
977 * @i: instance to resume
979 * Set up the gfx DMA ring buffers and enable them (VEGA10).
980 * Returns 0 for success, error for failure.
982 static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i)
984 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring;
985 u32 rb_cntl, ib_cntl, wptr_poll_cntl;
991 wb_offset = (ring->rptr_offs * 4);
993 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
994 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl);
995 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
997 /* Initialize the ring buffer's read and write pointers */
998 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0);
999 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0);
1000 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0);
1001 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0);
1003 /* set the wb address whether it's enabled or not */
1004 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI,
1005 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
1006 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO,
1007 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
1009 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
1010 RPTR_WRITEBACK_ENABLE, 1);
1012 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8);
1013 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40);
1017 /* before programing wptr to a less value, need set minor_ptr_update first */
1018 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1);
1020 doorbell = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL);
1021 doorbell_offset = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET);
1023 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE,
1024 ring->use_doorbell);
1025 doorbell_offset = REG_SET_FIELD(doorbell_offset,
1026 SDMA0_GFX_DOORBELL_OFFSET,
1027 OFFSET, ring->doorbell_index);
1028 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell);
1029 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset);
1031 sdma_v4_0_ring_set_wptr(ring);
1033 /* set minor_ptr_update to 0 after wptr programed */
1034 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0);
1036 /* setup the wptr shadow polling */
1037 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1038 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO,
1039 lower_32_bits(wptr_gpu_addr));
1040 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI,
1041 upper_32_bits(wptr_gpu_addr));
1042 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL);
1043 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
1044 SDMA0_GFX_RB_WPTR_POLL_CNTL,
1045 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
1046 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
1049 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
1050 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
1052 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
1053 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
1055 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
1057 /* enable DMA IBs */
1058 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
1060 ring->sched.ready = true;
1064 * sdma_v4_0_page_resume - setup and start the async dma engines
1066 * @adev: amdgpu_device pointer
1067 * @i: instance to resume
1069 * Set up the page DMA ring buffers and enable them (VEGA10).
1070 * Returns 0 for success, error for failure.
1072 static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i)
1074 struct amdgpu_ring *ring = &adev->sdma.instance[i].page;
1075 u32 rb_cntl, ib_cntl, wptr_poll_cntl;
1078 u32 doorbell_offset;
1081 wb_offset = (ring->rptr_offs * 4);
1083 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);
1084 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl);
1085 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
1087 /* Initialize the ring buffer's read and write pointers */
1088 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR, 0);
1089 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_HI, 0);
1090 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR, 0);
1091 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_HI, 0);
1093 /* set the wb address whether it's enabled or not */
1094 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_HI,
1095 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
1096 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_LO,
1097 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
1099 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
1100 RPTR_WRITEBACK_ENABLE, 1);
1102 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE, ring->gpu_addr >> 8);
1103 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE_HI, ring->gpu_addr >> 40);
1107 /* before programing wptr to a less value, need set minor_ptr_update first */
1108 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 1);
1110 doorbell = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL);
1111 doorbell_offset = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET);
1113 doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE,
1114 ring->use_doorbell);
1115 doorbell_offset = REG_SET_FIELD(doorbell_offset,
1116 SDMA0_PAGE_DOORBELL_OFFSET,
1117 OFFSET, ring->doorbell_index);
1118 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell);
1119 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset);
1121 /* paging queue doorbell range is setup at sdma_v4_0_gfx_resume */
1122 sdma_v4_0_page_ring_set_wptr(ring);
1124 /* set minor_ptr_update to 0 after wptr programed */
1125 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0);
1127 /* setup the wptr shadow polling */
1128 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1129 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO,
1130 lower_32_bits(wptr_gpu_addr));
1131 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI,
1132 upper_32_bits(wptr_gpu_addr));
1133 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL);
1134 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
1135 SDMA0_PAGE_RB_WPTR_POLL_CNTL,
1136 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
1137 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
1140 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1);
1141 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
1143 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL);
1144 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_ENABLE, 1);
1146 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1);
1148 /* enable DMA IBs */
1149 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
1151 ring->sched.ready = true;
1155 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable)
1159 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) {
1160 /* enable idle interrupt */
1161 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1162 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1165 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1167 /* disable idle interrupt */
1168 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1169 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1171 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1175 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev)
1179 /* Enable HW based PG. */
1180 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1181 data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK;
1183 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1185 /* enable interrupt */
1186 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1187 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1189 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1191 /* Configure hold time to filter in-valid power on/off request. Use default right now */
1192 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1193 data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK;
1194 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK);
1195 /* Configure switch time for hysteresis purpose. Use default right now */
1196 data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK;
1197 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK);
1199 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1202 static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
1204 if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA))
1207 switch (adev->asic_type) {
1210 sdma_v4_1_init_power_gating(adev);
1211 sdma_v4_1_update_power_gating(adev, true);
1219 * sdma_v4_0_rlc_resume - setup and start the async dma engines
1221 * @adev: amdgpu_device pointer
1223 * Set up the compute DMA queues and enable them (VEGA10).
1224 * Returns 0 for success, error for failure.
1226 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev)
1228 sdma_v4_0_init_pg(adev);
1234 * sdma_v4_0_load_microcode - load the sDMA ME ucode
1236 * @adev: amdgpu_device pointer
1238 * Loads the sDMA0/1 ucode.
1239 * Returns 0 for success, -EINVAL if the ucode is not available.
1241 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev)
1243 const struct sdma_firmware_header_v1_0 *hdr;
1244 const __le32 *fw_data;
1249 sdma_v4_0_enable(adev, false);
1251 for (i = 0; i < adev->sdma.num_instances; i++) {
1252 if (!adev->sdma.instance[i].fw)
1255 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
1256 amdgpu_ucode_print_sdma_hdr(&hdr->header);
1257 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1259 fw_data = (const __le32 *)
1260 (adev->sdma.instance[i].fw->data +
1261 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1263 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0);
1265 for (j = 0; j < fw_size; j++)
1266 WREG32_SDMA(i, mmSDMA0_UCODE_DATA,
1267 le32_to_cpup(fw_data++));
1269 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR,
1270 adev->sdma.instance[i].fw_version);
1277 * sdma_v4_0_start - setup and start the async dma engines
1279 * @adev: amdgpu_device pointer
1281 * Set up the DMA engines and enable them (VEGA10).
1282 * Returns 0 for success, error for failure.
1284 static int sdma_v4_0_start(struct amdgpu_device *adev)
1286 struct amdgpu_ring *ring;
1289 if (amdgpu_sriov_vf(adev)) {
1290 sdma_v4_0_ctx_switch_enable(adev, false);
1291 sdma_v4_0_enable(adev, false);
1294 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1295 r = sdma_v4_0_load_microcode(adev);
1300 /* unhalt the MEs */
1301 sdma_v4_0_enable(adev, true);
1302 /* enable sdma ring preemption */
1303 sdma_v4_0_ctx_switch_enable(adev, true);
1306 /* start the gfx rings and rlc compute queues */
1307 for (i = 0; i < adev->sdma.num_instances; i++) {
1310 WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0);
1311 sdma_v4_0_gfx_resume(adev, i);
1312 if (adev->sdma.has_page_queue)
1313 sdma_v4_0_page_resume(adev, i);
1315 /* set utc l1 enable flag always to 1 */
1316 temp = RREG32_SDMA(i, mmSDMA0_CNTL);
1317 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
1318 WREG32_SDMA(i, mmSDMA0_CNTL, temp);
1320 if (!amdgpu_sriov_vf(adev)) {
1322 temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
1323 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
1324 WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp);
1328 if (amdgpu_sriov_vf(adev)) {
1329 sdma_v4_0_ctx_switch_enable(adev, true);
1330 sdma_v4_0_enable(adev, true);
1332 r = sdma_v4_0_rlc_resume(adev);
1337 for (i = 0; i < adev->sdma.num_instances; i++) {
1338 ring = &adev->sdma.instance[i].ring;
1340 r = amdgpu_ring_test_helper(ring);
1344 if (adev->sdma.has_page_queue) {
1345 struct amdgpu_ring *page = &adev->sdma.instance[i].page;
1347 r = amdgpu_ring_test_helper(page);
1351 if (adev->mman.buffer_funcs_ring == page)
1352 amdgpu_ttm_set_buffer_funcs_status(adev, true);
1355 if (adev->mman.buffer_funcs_ring == ring)
1356 amdgpu_ttm_set_buffer_funcs_status(adev, true);
1363 * sdma_v4_0_ring_test_ring - simple async dma engine test
1365 * @ring: amdgpu_ring structure holding ring information
1367 * Test the DMA engine by writing using it to write an
1368 * value to memory. (VEGA10).
1369 * Returns 0 for success, error for failure.
1371 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring)
1373 struct amdgpu_device *adev = ring->adev;
1380 r = amdgpu_device_wb_get(adev, &index);
1384 gpu_addr = adev->wb.gpu_addr + (index * 4);
1386 adev->wb.wb[index] = cpu_to_le32(tmp);
1388 r = amdgpu_ring_alloc(ring, 5);
1392 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1393 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
1394 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
1395 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
1396 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
1397 amdgpu_ring_write(ring, 0xDEADBEEF);
1398 amdgpu_ring_commit(ring);
1400 for (i = 0; i < adev->usec_timeout; i++) {
1401 tmp = le32_to_cpu(adev->wb.wb[index]);
1402 if (tmp == 0xDEADBEEF)
1407 if (i >= adev->usec_timeout)
1411 amdgpu_device_wb_free(adev, index);
1416 * sdma_v4_0_ring_test_ib - test an IB on the DMA engine
1418 * @ring: amdgpu_ring structure holding ring information
1420 * Test a simple IB in the DMA ring (VEGA10).
1421 * Returns 0 on success, error on failure.
1423 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1425 struct amdgpu_device *adev = ring->adev;
1426 struct amdgpu_ib ib;
1427 struct dma_fence *f = NULL;
1433 r = amdgpu_device_wb_get(adev, &index);
1437 gpu_addr = adev->wb.gpu_addr + (index * 4);
1439 adev->wb.wb[index] = cpu_to_le32(tmp);
1440 memset(&ib, 0, sizeof(ib));
1441 r = amdgpu_ib_get(adev, NULL, 256, &ib);
1445 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1446 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1447 ib.ptr[1] = lower_32_bits(gpu_addr);
1448 ib.ptr[2] = upper_32_bits(gpu_addr);
1449 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1450 ib.ptr[4] = 0xDEADBEEF;
1451 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1452 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1453 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1456 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1460 r = dma_fence_wait_timeout(f, false, timeout);
1467 tmp = le32_to_cpu(adev->wb.wb[index]);
1468 if (tmp == 0xDEADBEEF)
1474 amdgpu_ib_free(adev, &ib, NULL);
1477 amdgpu_device_wb_free(adev, index);
1483 * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART
1485 * @ib: indirect buffer to fill with commands
1486 * @pe: addr of the page entry
1487 * @src: src addr to copy from
1488 * @count: number of page entries to update
1490 * Update PTEs by copying them from the GART using sDMA (VEGA10).
1492 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib,
1493 uint64_t pe, uint64_t src,
1496 unsigned bytes = count * 8;
1498 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1499 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1500 ib->ptr[ib->length_dw++] = bytes - 1;
1501 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1502 ib->ptr[ib->length_dw++] = lower_32_bits(src);
1503 ib->ptr[ib->length_dw++] = upper_32_bits(src);
1504 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1505 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1510 * sdma_v4_0_vm_write_pte - update PTEs by writing them manually
1512 * @ib: indirect buffer to fill with commands
1513 * @pe: addr of the page entry
1514 * @addr: dst addr to write into pe
1515 * @count: number of page entries to update
1516 * @incr: increase next addr by incr bytes
1517 * @flags: access flags
1519 * Update PTEs by writing them manually using sDMA (VEGA10).
1521 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1522 uint64_t value, unsigned count,
1525 unsigned ndw = count * 2;
1527 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1528 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1529 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1530 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1531 ib->ptr[ib->length_dw++] = ndw - 1;
1532 for (; ndw > 0; ndw -= 2) {
1533 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1534 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1540 * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA
1542 * @ib: indirect buffer to fill with commands
1543 * @pe: addr of the page entry
1544 * @addr: dst addr to write into pe
1545 * @count: number of page entries to update
1546 * @incr: increase next addr by incr bytes
1547 * @flags: access flags
1549 * Update the page tables using sDMA (VEGA10).
1551 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1553 uint64_t addr, unsigned count,
1554 uint32_t incr, uint64_t flags)
1556 /* for physically contiguous pages (vram) */
1557 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1558 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1559 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1560 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1561 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1562 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1563 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1564 ib->ptr[ib->length_dw++] = incr; /* increment size */
1565 ib->ptr[ib->length_dw++] = 0;
1566 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1570 * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw
1572 * @ib: indirect buffer to fill with padding
1575 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1577 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1581 pad_count = (8 - (ib->length_dw & 0x7)) % 8;
1582 for (i = 0; i < pad_count; i++)
1583 if (sdma && sdma->burst_nop && (i == 0))
1584 ib->ptr[ib->length_dw++] =
1585 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1586 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1588 ib->ptr[ib->length_dw++] =
1589 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1594 * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline
1596 * @ring: amdgpu_ring pointer
1598 * Make sure all previous operations are completed (CIK).
1600 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1602 uint32_t seq = ring->fence_drv.sync_seq;
1603 uint64_t addr = ring->fence_drv.gpu_addr;
1606 sdma_v4_0_wait_reg_mem(ring, 1, 0,
1608 upper_32_bits(addr) & 0xffffffff,
1609 seq, 0xffffffff, 4);
1614 * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA
1616 * @ring: amdgpu_ring pointer
1617 * @vm: amdgpu_vm pointer
1619 * Update the page table base and flush the VM TLB
1620 * using sDMA (VEGA10).
1622 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1623 unsigned vmid, uint64_t pd_addr)
1625 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1628 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring,
1629 uint32_t reg, uint32_t val)
1631 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1632 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1633 amdgpu_ring_write(ring, reg);
1634 amdgpu_ring_write(ring, val);
1637 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1638 uint32_t val, uint32_t mask)
1640 sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
1643 static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev)
1645 uint fw_version = adev->sdma.instance[0].fw_version;
1647 switch (adev->asic_type) {
1649 return fw_version >= 430;
1651 /*return fw_version >= 31;*/
1654 return fw_version >= 123;
1660 static int sdma_v4_0_early_init(void *handle)
1662 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1665 if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_RENOIR)
1666 adev->sdma.num_instances = 1;
1667 else if (adev->asic_type == CHIP_ARCTURUS)
1668 adev->sdma.num_instances = 8;
1670 adev->sdma.num_instances = 2;
1672 r = sdma_v4_0_init_microcode(adev);
1674 DRM_ERROR("Failed to load sdma firmware!\n");
1678 /* TODO: Page queue breaks driver reload under SRIOV */
1679 if ((adev->asic_type == CHIP_VEGA10) && amdgpu_sriov_vf((adev)))
1680 adev->sdma.has_page_queue = false;
1681 else if (sdma_v4_0_fw_support_paging_queue(adev))
1682 adev->sdma.has_page_queue = true;
1684 sdma_v4_0_set_ring_funcs(adev);
1685 sdma_v4_0_set_buffer_funcs(adev);
1686 sdma_v4_0_set_vm_pte_funcs(adev);
1687 sdma_v4_0_set_irq_funcs(adev);
1692 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
1693 struct ras_err_data *err_data,
1694 struct amdgpu_iv_entry *entry);
1696 static int sdma_v4_0_late_init(void *handle)
1698 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1699 struct ras_ih_if ih_info = {
1700 .cb = sdma_v4_0_process_ras_data_cb,
1702 struct ras_fs_if fs_info = {
1703 .sysfs_name = "sdma_err_count",
1704 .debugfs_name = "sdma_err_inject",
1708 if (!adev->sdma.ras_if) {
1709 adev->sdma.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
1710 if (!adev->sdma.ras_if)
1712 adev->sdma.ras_if->block = AMDGPU_RAS_BLOCK__SDMA;
1713 adev->sdma.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
1714 adev->sdma.ras_if->sub_block_index = 0;
1715 strcpy(adev->sdma.ras_if->name, "sdma");
1717 fs_info.head = ih_info.head = *adev->sdma.ras_if;
1719 r = amdgpu_ras_late_init(adev, adev->sdma.ras_if,
1720 &fs_info, &ih_info);
1724 if (amdgpu_ras_is_supported(adev, adev->sdma.ras_if->block)) {
1725 for (i = 0; i < adev->sdma.num_instances; i++) {
1726 r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq,
1727 AMDGPU_SDMA_IRQ_INSTANCE0 + i);
1732 kfree(adev->sdma.ras_if);
1736 amdgpu_ras_late_fini(adev, adev->sdma.ras_if, &ih_info);
1738 kfree(adev->sdma.ras_if);
1742 static int sdma_v4_0_sw_init(void *handle)
1744 struct amdgpu_ring *ring;
1746 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1748 /* SDMA trap event */
1749 for (i = 0; i < adev->sdma.num_instances; i++) {
1750 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1751 SDMA0_4_0__SRCID__SDMA_TRAP,
1752 &adev->sdma.trap_irq);
1757 /* SDMA SRAM ECC event */
1758 for (i = 0; i < adev->sdma.num_instances; i++) {
1759 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1760 SDMA0_4_0__SRCID__SDMA_SRAM_ECC,
1761 &adev->sdma.ecc_irq);
1766 for (i = 0; i < adev->sdma.num_instances; i++) {
1767 ring = &adev->sdma.instance[i].ring;
1768 ring->ring_obj = NULL;
1769 ring->use_doorbell = true;
1771 DRM_INFO("use_doorbell being set to: [%s]\n",
1772 ring->use_doorbell?"true":"false");
1774 /* doorbell size is 2 dwords, get DWORD offset */
1775 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1777 sprintf(ring->name, "sdma%d", i);
1778 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1779 AMDGPU_SDMA_IRQ_INSTANCE0 + i);
1783 if (adev->sdma.has_page_queue) {
1784 ring = &adev->sdma.instance[i].page;
1785 ring->ring_obj = NULL;
1786 ring->use_doorbell = true;
1788 /* paging queue use same doorbell index/routing as gfx queue
1789 * with 0x400 (4096 dwords) offset on second doorbell page
1791 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1792 ring->doorbell_index += 0x400;
1794 sprintf(ring->name, "page%d", i);
1795 r = amdgpu_ring_init(adev, ring, 1024,
1796 &adev->sdma.trap_irq,
1797 AMDGPU_SDMA_IRQ_INSTANCE0 + i);
1806 static int sdma_v4_0_sw_fini(void *handle)
1808 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1811 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA) &&
1812 adev->sdma.ras_if) {
1813 struct ras_common_if *ras_if = adev->sdma.ras_if;
1814 struct ras_ih_if ih_info = {
1819 amdgpu_ras_debugfs_remove(adev, ras_if);
1820 amdgpu_ras_sysfs_remove(adev, ras_if);
1822 amdgpu_ras_interrupt_remove_handler(adev, &ih_info);
1823 amdgpu_ras_feature_enable(adev, ras_if, 0);
1827 for (i = 0; i < adev->sdma.num_instances; i++) {
1828 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1829 if (adev->sdma.has_page_queue)
1830 amdgpu_ring_fini(&adev->sdma.instance[i].page);
1833 sdma_v4_0_destroy_inst_ctx(adev);
1838 static int sdma_v4_0_hw_init(void *handle)
1841 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1843 if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs &&
1844 adev->powerplay.pp_funcs->set_powergating_by_smu)
1845 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false);
1847 if (!amdgpu_sriov_vf(adev))
1848 sdma_v4_0_init_golden_registers(adev);
1850 r = sdma_v4_0_start(adev);
1855 static int sdma_v4_0_hw_fini(void *handle)
1857 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1860 if (amdgpu_sriov_vf(adev))
1863 for (i = 0; i < adev->sdma.num_instances; i++) {
1864 amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
1865 AMDGPU_SDMA_IRQ_INSTANCE0 + i);
1868 sdma_v4_0_ctx_switch_enable(adev, false);
1869 sdma_v4_0_enable(adev, false);
1871 if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs
1872 && adev->powerplay.pp_funcs->set_powergating_by_smu)
1873 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true);
1878 static int sdma_v4_0_suspend(void *handle)
1880 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1882 return sdma_v4_0_hw_fini(adev);
1885 static int sdma_v4_0_resume(void *handle)
1887 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1889 return sdma_v4_0_hw_init(adev);
1892 static bool sdma_v4_0_is_idle(void *handle)
1894 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1897 for (i = 0; i < adev->sdma.num_instances; i++) {
1898 u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG);
1900 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1907 static int sdma_v4_0_wait_for_idle(void *handle)
1910 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES];
1911 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1913 for (i = 0; i < adev->usec_timeout; i++) {
1914 for (j = 0; j < adev->sdma.num_instances; j++) {
1915 sdma[j] = RREG32_SDMA(j, mmSDMA0_STATUS_REG);
1916 if (!(sdma[j] & SDMA0_STATUS_REG__IDLE_MASK))
1919 if (j == adev->sdma.num_instances)
1926 static int sdma_v4_0_soft_reset(void *handle)
1933 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev,
1934 struct amdgpu_irq_src *source,
1936 enum amdgpu_interrupt_state state)
1940 sdma_cntl = RREG32_SDMA(type, mmSDMA0_CNTL);
1941 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1942 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1943 WREG32_SDMA(type, mmSDMA0_CNTL, sdma_cntl);
1948 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
1949 struct amdgpu_irq_src *source,
1950 struct amdgpu_iv_entry *entry)
1954 DRM_DEBUG("IH: SDMA trap\n");
1955 instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
1956 switch (entry->ring_id) {
1958 amdgpu_fence_process(&adev->sdma.instance[instance].ring);
1961 if (adev->asic_type == CHIP_VEGA20)
1962 amdgpu_fence_process(&adev->sdma.instance[instance].page);
1968 if (adev->asic_type != CHIP_VEGA20)
1969 amdgpu_fence_process(&adev->sdma.instance[instance].page);
1975 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
1976 struct ras_err_data *err_data,
1977 struct amdgpu_iv_entry *entry)
1979 uint32_t err_source;
1982 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) {
1983 instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
1987 switch (entry->src_id) {
1988 case SDMA0_4_0__SRCID__SDMA_SRAM_ECC:
1991 case SDMA0_4_0__SRCID__SDMA_ECC:
1998 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
2000 amdgpu_ras_reset_gpu(adev, 0);
2003 return AMDGPU_RAS_SUCCESS;
2006 static int sdma_v4_0_process_ecc_irq(struct amdgpu_device *adev,
2007 struct amdgpu_irq_src *source,
2008 struct amdgpu_iv_entry *entry)
2010 struct ras_common_if *ras_if = adev->sdma.ras_if;
2011 struct ras_dispatch_if ih_data = {
2018 ih_data.head = *ras_if;
2020 amdgpu_ras_interrupt_dispatch(adev, &ih_data);
2024 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev,
2025 struct amdgpu_irq_src *source,
2026 struct amdgpu_iv_entry *entry)
2030 DRM_ERROR("Illegal instruction in SDMA command stream\n");
2032 instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2036 switch (entry->ring_id) {
2038 drm_sched_fault(&adev->sdma.instance[instance].ring.sched);
2044 static int sdma_v4_0_set_ecc_irq_state(struct amdgpu_device *adev,
2045 struct amdgpu_irq_src *source,
2047 enum amdgpu_interrupt_state state)
2049 u32 sdma_edc_config;
2051 sdma_edc_config = RREG32_SDMA(type, mmSDMA0_EDC_CONFIG);
2052 sdma_edc_config = REG_SET_FIELD(sdma_edc_config, SDMA0_EDC_CONFIG, ECC_INT_ENABLE,
2053 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
2054 WREG32_SDMA(type, mmSDMA0_EDC_CONFIG, sdma_edc_config);
2059 static void sdma_v4_0_update_medium_grain_clock_gating(
2060 struct amdgpu_device *adev,
2066 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
2067 for (i = 0; i < adev->sdma.num_instances; i++) {
2068 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);
2069 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
2070 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
2071 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
2072 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
2073 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
2074 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
2075 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
2076 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
2078 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
2081 for (i = 0; i < adev->sdma.num_instances; i++) {
2082 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);
2083 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
2084 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
2085 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
2086 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
2087 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
2088 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
2089 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
2090 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
2092 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
2098 static void sdma_v4_0_update_medium_grain_light_sleep(
2099 struct amdgpu_device *adev,
2105 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
2106 for (i = 0; i < adev->sdma.num_instances; i++) {
2107 /* 1-not override: enable sdma mem light sleep */
2108 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);
2109 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
2111 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);
2114 for (i = 0; i < adev->sdma.num_instances; i++) {
2115 /* 0-override:disable sdma mem light sleep */
2116 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);
2117 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
2119 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);
2124 static int sdma_v4_0_set_clockgating_state(void *handle,
2125 enum amd_clockgating_state state)
2127 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2129 if (amdgpu_sriov_vf(adev))
2132 switch (adev->asic_type) {
2139 sdma_v4_0_update_medium_grain_clock_gating(adev,
2140 state == AMD_CG_STATE_GATE ? true : false);
2141 sdma_v4_0_update_medium_grain_light_sleep(adev,
2142 state == AMD_CG_STATE_GATE ? true : false);
2150 static int sdma_v4_0_set_powergating_state(void *handle,
2151 enum amd_powergating_state state)
2153 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2155 switch (adev->asic_type) {
2157 sdma_v4_1_update_power_gating(adev,
2158 state == AMD_PG_STATE_GATE ? true : false);
2167 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags)
2169 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2172 if (amdgpu_sriov_vf(adev))
2175 /* AMD_CG_SUPPORT_SDMA_MGCG */
2176 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
2177 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
2178 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
2180 /* AMD_CG_SUPPORT_SDMA_LS */
2181 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
2182 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
2183 *flags |= AMD_CG_SUPPORT_SDMA_LS;
2186 const struct amd_ip_funcs sdma_v4_0_ip_funcs = {
2187 .name = "sdma_v4_0",
2188 .early_init = sdma_v4_0_early_init,
2189 .late_init = sdma_v4_0_late_init,
2190 .sw_init = sdma_v4_0_sw_init,
2191 .sw_fini = sdma_v4_0_sw_fini,
2192 .hw_init = sdma_v4_0_hw_init,
2193 .hw_fini = sdma_v4_0_hw_fini,
2194 .suspend = sdma_v4_0_suspend,
2195 .resume = sdma_v4_0_resume,
2196 .is_idle = sdma_v4_0_is_idle,
2197 .wait_for_idle = sdma_v4_0_wait_for_idle,
2198 .soft_reset = sdma_v4_0_soft_reset,
2199 .set_clockgating_state = sdma_v4_0_set_clockgating_state,
2200 .set_powergating_state = sdma_v4_0_set_powergating_state,
2201 .get_clockgating_state = sdma_v4_0_get_clockgating_state,
2204 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
2205 .type = AMDGPU_RING_TYPE_SDMA,
2207 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2208 .support_64bit_ptrs = true,
2209 .vmhub = AMDGPU_MMHUB_0,
2210 .get_rptr = sdma_v4_0_ring_get_rptr,
2211 .get_wptr = sdma_v4_0_ring_get_wptr,
2212 .set_wptr = sdma_v4_0_ring_set_wptr,
2214 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2215 3 + /* hdp invalidate */
2216 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2217 /* sdma_v4_0_ring_emit_vm_flush */
2218 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2219 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2220 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2221 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2222 .emit_ib = sdma_v4_0_ring_emit_ib,
2223 .emit_fence = sdma_v4_0_ring_emit_fence,
2224 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2225 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2226 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2227 .test_ring = sdma_v4_0_ring_test_ring,
2228 .test_ib = sdma_v4_0_ring_test_ib,
2229 .insert_nop = sdma_v4_0_ring_insert_nop,
2230 .pad_ib = sdma_v4_0_ring_pad_ib,
2231 .emit_wreg = sdma_v4_0_ring_emit_wreg,
2232 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2233 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2237 * On Arcturus, SDMA instance 5~7 has a different vmhub type(AMDGPU_MMHUB_1).
2238 * So create a individual constant ring_funcs for those instances.
2240 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs_2nd_mmhub = {
2241 .type = AMDGPU_RING_TYPE_SDMA,
2243 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2244 .support_64bit_ptrs = true,
2245 .vmhub = AMDGPU_MMHUB_1,
2246 .get_rptr = sdma_v4_0_ring_get_rptr,
2247 .get_wptr = sdma_v4_0_ring_get_wptr,
2248 .set_wptr = sdma_v4_0_ring_set_wptr,
2250 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2251 3 + /* hdp invalidate */
2252 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2253 /* sdma_v4_0_ring_emit_vm_flush */
2254 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2255 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2256 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2257 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2258 .emit_ib = sdma_v4_0_ring_emit_ib,
2259 .emit_fence = sdma_v4_0_ring_emit_fence,
2260 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2261 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2262 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2263 .test_ring = sdma_v4_0_ring_test_ring,
2264 .test_ib = sdma_v4_0_ring_test_ib,
2265 .insert_nop = sdma_v4_0_ring_insert_nop,
2266 .pad_ib = sdma_v4_0_ring_pad_ib,
2267 .emit_wreg = sdma_v4_0_ring_emit_wreg,
2268 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2269 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2272 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = {
2273 .type = AMDGPU_RING_TYPE_SDMA,
2275 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2276 .support_64bit_ptrs = true,
2277 .vmhub = AMDGPU_MMHUB_0,
2278 .get_rptr = sdma_v4_0_ring_get_rptr,
2279 .get_wptr = sdma_v4_0_page_ring_get_wptr,
2280 .set_wptr = sdma_v4_0_page_ring_set_wptr,
2282 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2283 3 + /* hdp invalidate */
2284 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2285 /* sdma_v4_0_ring_emit_vm_flush */
2286 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2287 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2288 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2289 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2290 .emit_ib = sdma_v4_0_ring_emit_ib,
2291 .emit_fence = sdma_v4_0_ring_emit_fence,
2292 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2293 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2294 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2295 .test_ring = sdma_v4_0_ring_test_ring,
2296 .test_ib = sdma_v4_0_ring_test_ib,
2297 .insert_nop = sdma_v4_0_ring_insert_nop,
2298 .pad_ib = sdma_v4_0_ring_pad_ib,
2299 .emit_wreg = sdma_v4_0_ring_emit_wreg,
2300 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2301 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2304 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs_2nd_mmhub = {
2305 .type = AMDGPU_RING_TYPE_SDMA,
2307 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2308 .support_64bit_ptrs = true,
2309 .vmhub = AMDGPU_MMHUB_1,
2310 .get_rptr = sdma_v4_0_ring_get_rptr,
2311 .get_wptr = sdma_v4_0_page_ring_get_wptr,
2312 .set_wptr = sdma_v4_0_page_ring_set_wptr,
2314 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2315 3 + /* hdp invalidate */
2316 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2317 /* sdma_v4_0_ring_emit_vm_flush */
2318 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2319 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2320 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2321 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2322 .emit_ib = sdma_v4_0_ring_emit_ib,
2323 .emit_fence = sdma_v4_0_ring_emit_fence,
2324 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2325 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2326 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2327 .test_ring = sdma_v4_0_ring_test_ring,
2328 .test_ib = sdma_v4_0_ring_test_ib,
2329 .insert_nop = sdma_v4_0_ring_insert_nop,
2330 .pad_ib = sdma_v4_0_ring_pad_ib,
2331 .emit_wreg = sdma_v4_0_ring_emit_wreg,
2332 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2333 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2336 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
2340 for (i = 0; i < adev->sdma.num_instances; i++) {
2341 if (adev->asic_type == CHIP_ARCTURUS && i >= 5)
2342 adev->sdma.instance[i].ring.funcs =
2343 &sdma_v4_0_ring_funcs_2nd_mmhub;
2345 adev->sdma.instance[i].ring.funcs =
2346 &sdma_v4_0_ring_funcs;
2347 adev->sdma.instance[i].ring.me = i;
2348 if (adev->sdma.has_page_queue) {
2349 if (adev->asic_type == CHIP_ARCTURUS && i >= 5)
2350 adev->sdma.instance[i].page.funcs =
2351 &sdma_v4_0_page_ring_funcs_2nd_mmhub;
2353 adev->sdma.instance[i].page.funcs =
2354 &sdma_v4_0_page_ring_funcs;
2355 adev->sdma.instance[i].page.me = i;
2360 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = {
2361 .set = sdma_v4_0_set_trap_irq_state,
2362 .process = sdma_v4_0_process_trap_irq,
2365 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = {
2366 .process = sdma_v4_0_process_illegal_inst_irq,
2369 static const struct amdgpu_irq_src_funcs sdma_v4_0_ecc_irq_funcs = {
2370 .set = sdma_v4_0_set_ecc_irq_state,
2371 .process = sdma_v4_0_process_ecc_irq,
2376 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev)
2378 switch (adev->sdma.num_instances) {
2380 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1;
2381 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1;
2384 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
2385 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
2389 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2;
2390 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2;
2393 adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs;
2394 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs;
2395 adev->sdma.ecc_irq.funcs = &sdma_v4_0_ecc_irq_funcs;
2399 * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine
2401 * @ring: amdgpu_ring structure holding ring information
2402 * @src_offset: src GPU address
2403 * @dst_offset: dst GPU address
2404 * @byte_count: number of bytes to xfer
2406 * Copy GPU buffers using the DMA engine (VEGA10/12).
2407 * Used by the amdgpu ttm implementation to move pages if
2408 * registered as the asic copy callback.
2410 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib,
2411 uint64_t src_offset,
2412 uint64_t dst_offset,
2413 uint32_t byte_count)
2415 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
2416 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
2417 ib->ptr[ib->length_dw++] = byte_count - 1;
2418 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
2419 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
2420 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
2421 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2422 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2426 * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine
2428 * @ring: amdgpu_ring structure holding ring information
2429 * @src_data: value to write to buffer
2430 * @dst_offset: dst GPU address
2431 * @byte_count: number of bytes to xfer
2433 * Fill GPU buffers using the DMA engine (VEGA10/12).
2435 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib,
2437 uint64_t dst_offset,
2438 uint32_t byte_count)
2440 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
2441 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2442 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2443 ib->ptr[ib->length_dw++] = src_data;
2444 ib->ptr[ib->length_dw++] = byte_count - 1;
2447 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = {
2448 .copy_max_bytes = 0x400000,
2450 .emit_copy_buffer = sdma_v4_0_emit_copy_buffer,
2452 .fill_max_bytes = 0x400000,
2454 .emit_fill_buffer = sdma_v4_0_emit_fill_buffer,
2457 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
2459 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
2460 if (adev->sdma.has_page_queue)
2461 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
2463 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
2466 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = {
2467 .copy_pte_num_dw = 7,
2468 .copy_pte = sdma_v4_0_vm_copy_pte,
2470 .write_pte = sdma_v4_0_vm_write_pte,
2471 .set_pte_pde = sdma_v4_0_vm_set_pte_pde,
2474 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev)
2476 struct drm_gpu_scheduler *sched;
2479 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
2480 for (i = 0; i < adev->sdma.num_instances; i++) {
2481 if (adev->sdma.has_page_queue)
2482 sched = &adev->sdma.instance[i].page.sched;
2484 sched = &adev->sdma.instance[i].ring.sched;
2485 adev->vm_manager.vm_pte_rqs[i] =
2486 &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
2488 adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
2491 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = {
2492 .type = AMD_IP_BLOCK_TYPE_SDMA,
2496 .funcs = &sdma_v4_0_ip_funcs,