2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/firmware.h>
27 #include "amdgpu_ucode.h"
28 #include "amdgpu_trace.h"
30 #include "sdma0/sdma0_4_2_offset.h"
31 #include "sdma0/sdma0_4_2_sh_mask.h"
32 #include "sdma1/sdma1_4_2_offset.h"
33 #include "sdma1/sdma1_4_2_sh_mask.h"
34 #include "hdp/hdp_4_0_offset.h"
35 #include "sdma0/sdma0_4_1_default.h"
37 #include "soc15_common.h"
39 #include "vega10_sdma_pkt_open.h"
41 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h"
42 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h"
44 #include "amdgpu_ras.h"
46 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin");
47 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin");
48 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin");
49 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin");
50 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin");
51 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin");
52 MODULE_FIRMWARE("amdgpu/raven_sdma.bin");
53 MODULE_FIRMWARE("amdgpu/picasso_sdma.bin");
54 MODULE_FIRMWARE("amdgpu/raven2_sdma.bin");
56 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L
57 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
59 #define WREG32_SDMA(instance, offset, value) \
60 WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value)
61 #define RREG32_SDMA(instance, offset) \
62 RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)))
64 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev);
65 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev);
66 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev);
67 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev);
69 static const struct soc15_reg_golden golden_settings_sdma_4[] = {
70 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
71 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
72 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),
73 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
74 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
75 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
76 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000),
77 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
78 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
79 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
80 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
81 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
82 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000),
83 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
84 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100),
85 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
86 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
87 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
88 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000),
89 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
90 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
91 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
92 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
93 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
94 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000)
97 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = {
98 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
99 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
100 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
101 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
102 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002)
105 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = {
106 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
107 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001),
108 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
109 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
110 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001)
113 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = {
114 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
115 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
116 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100),
117 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
118 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051),
119 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100),
120 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
121 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100),
122 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
123 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
124 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000)
127 static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = {
128 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
131 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] =
133 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
134 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
135 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
136 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
137 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
138 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
139 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
140 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
141 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003),
142 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
143 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
144 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
145 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
146 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
147 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
148 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
149 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
150 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
151 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
152 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
153 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
154 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
155 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
156 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
157 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
158 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
159 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xFE000000, 0x00000000),
162 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = {
163 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
164 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
165 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
166 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
167 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
168 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
169 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
170 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
171 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003),
172 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
173 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
174 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
175 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
176 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
177 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
178 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
179 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
180 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
181 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
182 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
183 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
184 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
185 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
186 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
187 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
188 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
189 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xFE000000, 0x00000000),
192 static const struct soc15_reg_golden golden_settings_sdma_rv1[] =
194 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
195 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002)
198 static const struct soc15_reg_golden golden_settings_sdma_rv2[] =
200 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001),
201 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001)
204 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
205 u32 instance, u32 offset)
207 return ( 0 == instance ? (adev->reg_offset[SDMA0_HWIP][0][0] + offset) :
208 (adev->reg_offset[SDMA1_HWIP][0][0] + offset));
211 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
213 switch (adev->asic_type) {
215 soc15_program_register_sequence(adev,
216 golden_settings_sdma_4,
217 ARRAY_SIZE(golden_settings_sdma_4));
218 soc15_program_register_sequence(adev,
219 golden_settings_sdma_vg10,
220 ARRAY_SIZE(golden_settings_sdma_vg10));
223 soc15_program_register_sequence(adev,
224 golden_settings_sdma_4,
225 ARRAY_SIZE(golden_settings_sdma_4));
226 soc15_program_register_sequence(adev,
227 golden_settings_sdma_vg12,
228 ARRAY_SIZE(golden_settings_sdma_vg12));
231 soc15_program_register_sequence(adev,
232 golden_settings_sdma0_4_2_init,
233 ARRAY_SIZE(golden_settings_sdma0_4_2_init));
234 soc15_program_register_sequence(adev,
235 golden_settings_sdma0_4_2,
236 ARRAY_SIZE(golden_settings_sdma0_4_2));
237 soc15_program_register_sequence(adev,
238 golden_settings_sdma1_4_2,
239 ARRAY_SIZE(golden_settings_sdma1_4_2));
242 soc15_program_register_sequence(adev,
243 golden_settings_sdma_4_1,
244 ARRAY_SIZE(golden_settings_sdma_4_1));
245 if (adev->rev_id >= 8)
246 soc15_program_register_sequence(adev,
247 golden_settings_sdma_rv2,
248 ARRAY_SIZE(golden_settings_sdma_rv2));
250 soc15_program_register_sequence(adev,
251 golden_settings_sdma_rv1,
252 ARRAY_SIZE(golden_settings_sdma_rv1));
260 * sdma_v4_0_init_microcode - load ucode images from disk
262 * @adev: amdgpu_device pointer
264 * Use the firmware interface to load the ucode images into
265 * the driver (not loaded into hw).
266 * Returns 0 on success, error on failure.
269 // emulation only, won't work on real chip
270 // vega10 real chip need to use PSP to load firmware
271 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
273 const char *chip_name;
276 struct amdgpu_firmware_info *info = NULL;
277 const struct common_firmware_header *header = NULL;
278 const struct sdma_firmware_header_v1_0 *hdr;
282 switch (adev->asic_type) {
284 chip_name = "vega10";
287 chip_name = "vega12";
290 chip_name = "vega20";
293 if (adev->rev_id >= 8)
294 chip_name = "raven2";
295 else if (adev->pdev->device == 0x15d8)
296 chip_name = "picasso";
304 for (i = 0; i < adev->sdma.num_instances; i++) {
306 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
308 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
309 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
312 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
315 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
316 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
317 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
318 if (adev->sdma.instance[i].feature_version >= 20)
319 adev->sdma.instance[i].burst_nop = true;
320 DRM_DEBUG("psp_load == '%s'\n",
321 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
323 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
324 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
325 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
326 info->fw = adev->sdma.instance[i].fw;
327 header = (const struct common_firmware_header *)info->fw->data;
328 adev->firmware.fw_size +=
329 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
334 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name);
335 for (i = 0; i < adev->sdma.num_instances; i++) {
336 release_firmware(adev->sdma.instance[i].fw);
337 adev->sdma.instance[i].fw = NULL;
344 * sdma_v4_0_ring_get_rptr - get the current read pointer
346 * @ring: amdgpu ring pointer
348 * Get the current rptr from the hardware (VEGA10+).
350 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring)
354 /* XXX check if swapping is necessary on BE */
355 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
357 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
358 return ((*rptr) >> 2);
362 * sdma_v4_0_ring_get_wptr - get the current write pointer
364 * @ring: amdgpu ring pointer
366 * Get the current wptr from the hardware (VEGA10+).
368 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
370 struct amdgpu_device *adev = ring->adev;
373 if (ring->use_doorbell) {
374 /* XXX check if swapping is necessary on BE */
375 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
376 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
378 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI);
380 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR);
381 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n",
389 * sdma_v4_0_ring_set_wptr - commit the write pointer
391 * @ring: amdgpu ring pointer
393 * Write the wptr back to the hardware (VEGA10+).
395 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
397 struct amdgpu_device *adev = ring->adev;
399 DRM_DEBUG("Setting write pointer\n");
400 if (ring->use_doorbell) {
401 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
403 DRM_DEBUG("Using doorbell -- "
404 "wptr_offs == 0x%08x "
405 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
406 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
408 lower_32_bits(ring->wptr << 2),
409 upper_32_bits(ring->wptr << 2));
410 /* XXX check if swapping is necessary on BE */
411 WRITE_ONCE(*wb, (ring->wptr << 2));
412 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
413 ring->doorbell_index, ring->wptr << 2);
414 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
416 DRM_DEBUG("Not using doorbell -- "
417 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
418 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
420 lower_32_bits(ring->wptr << 2),
422 upper_32_bits(ring->wptr << 2));
423 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR,
424 lower_32_bits(ring->wptr << 2));
425 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI,
426 upper_32_bits(ring->wptr << 2));
431 * sdma_v4_0_page_ring_get_wptr - get the current write pointer
433 * @ring: amdgpu ring pointer
435 * Get the current wptr from the hardware (VEGA10+).
437 static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring)
439 struct amdgpu_device *adev = ring->adev;
442 if (ring->use_doorbell) {
443 /* XXX check if swapping is necessary on BE */
444 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
446 wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI);
448 wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR);
455 * sdma_v4_0_ring_set_wptr - commit the write pointer
457 * @ring: amdgpu ring pointer
459 * Write the wptr back to the hardware (VEGA10+).
461 static void sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring *ring)
463 struct amdgpu_device *adev = ring->adev;
465 if (ring->use_doorbell) {
466 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
468 /* XXX check if swapping is necessary on BE */
469 WRITE_ONCE(*wb, (ring->wptr << 2));
470 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
472 uint64_t wptr = ring->wptr << 2;
474 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR,
475 lower_32_bits(wptr));
476 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI,
477 upper_32_bits(wptr));
481 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
483 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
486 for (i = 0; i < count; i++)
487 if (sdma && sdma->burst_nop && (i == 0))
488 amdgpu_ring_write(ring, ring->funcs->nop |
489 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
491 amdgpu_ring_write(ring, ring->funcs->nop);
495 * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine
497 * @ring: amdgpu ring pointer
498 * @ib: IB object to schedule
500 * Schedule an IB in the DMA ring (VEGA10).
502 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
503 struct amdgpu_job *job,
504 struct amdgpu_ib *ib,
507 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
509 /* IB packet must end on a 8 DW boundary */
510 sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
512 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
513 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
514 /* base must be 32 byte aligned */
515 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
516 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
517 amdgpu_ring_write(ring, ib->length_dw);
518 amdgpu_ring_write(ring, 0);
519 amdgpu_ring_write(ring, 0);
523 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring,
524 int mem_space, int hdp,
525 uint32_t addr0, uint32_t addr1,
526 uint32_t ref, uint32_t mask,
529 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
530 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) |
531 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) |
532 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
535 amdgpu_ring_write(ring, addr0);
536 amdgpu_ring_write(ring, addr1);
539 amdgpu_ring_write(ring, addr0 << 2);
540 amdgpu_ring_write(ring, addr1 << 2);
542 amdgpu_ring_write(ring, ref); /* reference */
543 amdgpu_ring_write(ring, mask); /* mask */
544 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
545 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */
549 * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
551 * @ring: amdgpu ring pointer
553 * Emit an hdp flush packet on the requested DMA ring.
555 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
557 struct amdgpu_device *adev = ring->adev;
558 u32 ref_and_mask = 0;
559 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
562 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
564 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
566 sdma_v4_0_wait_reg_mem(ring, 0, 1,
567 adev->nbio_funcs->get_hdp_flush_done_offset(adev),
568 adev->nbio_funcs->get_hdp_flush_req_offset(adev),
569 ref_and_mask, ref_and_mask, 10);
573 * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring
575 * @ring: amdgpu ring pointer
576 * @fence: amdgpu fence object
578 * Add a DMA fence packet to the ring to write
579 * the fence seq number and DMA trap packet to generate
580 * an interrupt if needed (VEGA10).
582 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
585 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
586 /* write the fence */
587 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
588 /* zero in first two bits */
590 amdgpu_ring_write(ring, lower_32_bits(addr));
591 amdgpu_ring_write(ring, upper_32_bits(addr));
592 amdgpu_ring_write(ring, lower_32_bits(seq));
594 /* optionally write high bits as well */
597 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
598 /* zero in first two bits */
600 amdgpu_ring_write(ring, lower_32_bits(addr));
601 amdgpu_ring_write(ring, upper_32_bits(addr));
602 amdgpu_ring_write(ring, upper_32_bits(seq));
605 /* generate an interrupt */
606 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
607 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
612 * sdma_v4_0_gfx_stop - stop the gfx async dma engines
614 * @adev: amdgpu_device pointer
616 * Stop the gfx async dma ring buffers (VEGA10).
618 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev)
620 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
621 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
622 u32 rb_cntl, ib_cntl;
625 if ((adev->mman.buffer_funcs_ring == sdma0) ||
626 (adev->mman.buffer_funcs_ring == sdma1))
627 amdgpu_ttm_set_buffer_funcs_status(adev, false);
629 for (i = 0; i < adev->sdma.num_instances; i++) {
630 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
631 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
632 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
633 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
634 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
635 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
638 sdma0->sched.ready = false;
639 sdma1->sched.ready = false;
643 * sdma_v4_0_rlc_stop - stop the compute async dma engines
645 * @adev: amdgpu_device pointer
647 * Stop the compute async dma queues (VEGA10).
649 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev)
655 * sdma_v4_0_page_stop - stop the page async dma engines
657 * @adev: amdgpu_device pointer
659 * Stop the page async dma ring buffers (VEGA10).
661 static void sdma_v4_0_page_stop(struct amdgpu_device *adev)
663 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].page;
664 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].page;
665 u32 rb_cntl, ib_cntl;
668 if ((adev->mman.buffer_funcs_ring == sdma0) ||
669 (adev->mman.buffer_funcs_ring == sdma1))
670 amdgpu_ttm_set_buffer_funcs_status(adev, false);
672 for (i = 0; i < adev->sdma.num_instances; i++) {
673 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);
674 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
676 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
677 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL);
678 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL,
680 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
683 sdma0->sched.ready = false;
684 sdma1->sched.ready = false;
688 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
690 * @adev: amdgpu_device pointer
691 * @enable: enable/disable the DMA MEs context switch.
693 * Halt or unhalt the async dma engines context switch (VEGA10).
695 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
697 u32 f32_cntl, phase_quantum = 0;
700 if (amdgpu_sdma_phase_quantum) {
701 unsigned value = amdgpu_sdma_phase_quantum;
704 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
705 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
706 value = (value + 1) >> 1;
709 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
710 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
711 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
712 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
713 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
714 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
716 "clamping sdma_phase_quantum to %uK clock cycles\n",
720 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
721 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
724 for (i = 0; i < adev->sdma.num_instances; i++) {
725 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL);
726 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
727 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
728 if (enable && amdgpu_sdma_phase_quantum) {
729 WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum);
730 WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum);
731 WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum);
733 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl);
739 * sdma_v4_0_enable - stop the async dma engines
741 * @adev: amdgpu_device pointer
742 * @enable: enable/disable the DMA MEs.
744 * Halt or unhalt the async dma engines (VEGA10).
746 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable)
751 if (enable == false) {
752 sdma_v4_0_gfx_stop(adev);
753 sdma_v4_0_rlc_stop(adev);
754 if (adev->sdma.has_page_queue)
755 sdma_v4_0_page_stop(adev);
758 for (i = 0; i < adev->sdma.num_instances; i++) {
759 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
760 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
761 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl);
766 * sdma_v4_0_rb_cntl - get parameters for rb_cntl
768 static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl)
770 /* Set ring buffer size in dwords */
771 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4);
773 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
775 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
776 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
777 RPTR_WRITEBACK_SWAP_ENABLE, 1);
783 * sdma_v4_0_gfx_resume - setup and start the async dma engines
785 * @adev: amdgpu_device pointer
786 * @i: instance to resume
788 * Set up the gfx DMA ring buffers and enable them (VEGA10).
789 * Returns 0 for success, error for failure.
791 static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i)
793 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring;
794 u32 rb_cntl, ib_cntl, wptr_poll_cntl;
800 wb_offset = (ring->rptr_offs * 4);
802 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
803 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl);
804 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
806 /* Initialize the ring buffer's read and write pointers */
807 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0);
808 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0);
809 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0);
810 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0);
812 /* set the wb address whether it's enabled or not */
813 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI,
814 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
815 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO,
816 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
818 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
819 RPTR_WRITEBACK_ENABLE, 1);
821 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8);
822 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40);
826 /* before programing wptr to a less value, need set minor_ptr_update first */
827 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1);
829 doorbell = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL);
830 doorbell_offset = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET);
832 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE,
834 doorbell_offset = REG_SET_FIELD(doorbell_offset,
835 SDMA0_GFX_DOORBELL_OFFSET,
836 OFFSET, ring->doorbell_index);
837 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell);
838 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset);
840 sdma_v4_0_ring_set_wptr(ring);
842 /* set minor_ptr_update to 0 after wptr programed */
843 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0);
845 /* setup the wptr shadow polling */
846 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
847 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO,
848 lower_32_bits(wptr_gpu_addr));
849 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI,
850 upper_32_bits(wptr_gpu_addr));
851 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL);
852 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
853 SDMA0_GFX_RB_WPTR_POLL_CNTL,
854 F32_POLL_ENABLE, amdgpu_sriov_vf(adev));
855 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
858 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
859 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
861 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
862 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
864 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
867 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
869 ring->sched.ready = true;
873 * sdma_v4_0_page_resume - setup and start the async dma engines
875 * @adev: amdgpu_device pointer
876 * @i: instance to resume
878 * Set up the page DMA ring buffers and enable them (VEGA10).
879 * Returns 0 for success, error for failure.
881 static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i)
883 struct amdgpu_ring *ring = &adev->sdma.instance[i].page;
884 u32 rb_cntl, ib_cntl, wptr_poll_cntl;
890 wb_offset = (ring->rptr_offs * 4);
892 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);
893 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl);
894 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
896 /* Initialize the ring buffer's read and write pointers */
897 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR, 0);
898 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_HI, 0);
899 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR, 0);
900 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_HI, 0);
902 /* set the wb address whether it's enabled or not */
903 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_HI,
904 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
905 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_LO,
906 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
908 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
909 RPTR_WRITEBACK_ENABLE, 1);
911 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE, ring->gpu_addr >> 8);
912 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE_HI, ring->gpu_addr >> 40);
916 /* before programing wptr to a less value, need set minor_ptr_update first */
917 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 1);
919 doorbell = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL);
920 doorbell_offset = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET);
922 doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE,
924 doorbell_offset = REG_SET_FIELD(doorbell_offset,
925 SDMA0_PAGE_DOORBELL_OFFSET,
926 OFFSET, ring->doorbell_index);
927 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell);
928 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset);
930 /* paging queue doorbell range is setup at sdma_v4_0_gfx_resume */
931 sdma_v4_0_page_ring_set_wptr(ring);
933 /* set minor_ptr_update to 0 after wptr programed */
934 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0);
936 /* setup the wptr shadow polling */
937 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
938 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO,
939 lower_32_bits(wptr_gpu_addr));
940 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI,
941 upper_32_bits(wptr_gpu_addr));
942 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL);
943 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
944 SDMA0_PAGE_RB_WPTR_POLL_CNTL,
945 F32_POLL_ENABLE, amdgpu_sriov_vf(adev));
946 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
949 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1);
950 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
952 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL);
953 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_ENABLE, 1);
955 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1);
958 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
960 ring->sched.ready = true;
964 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable)
968 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) {
969 /* enable idle interrupt */
970 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
971 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
974 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
976 /* disable idle interrupt */
977 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
978 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
980 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
984 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev)
988 /* Enable HW based PG. */
989 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
990 data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK;
992 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
994 /* enable interrupt */
995 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
996 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
998 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1000 /* Configure hold time to filter in-valid power on/off request. Use default right now */
1001 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1002 data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK;
1003 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK);
1004 /* Configure switch time for hysteresis purpose. Use default right now */
1005 data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK;
1006 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK);
1008 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1011 static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
1013 if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA))
1016 switch (adev->asic_type) {
1018 sdma_v4_1_init_power_gating(adev);
1019 sdma_v4_1_update_power_gating(adev, true);
1027 * sdma_v4_0_rlc_resume - setup and start the async dma engines
1029 * @adev: amdgpu_device pointer
1031 * Set up the compute DMA queues and enable them (VEGA10).
1032 * Returns 0 for success, error for failure.
1034 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev)
1036 sdma_v4_0_init_pg(adev);
1042 * sdma_v4_0_load_microcode - load the sDMA ME ucode
1044 * @adev: amdgpu_device pointer
1046 * Loads the sDMA0/1 ucode.
1047 * Returns 0 for success, -EINVAL if the ucode is not available.
1049 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev)
1051 const struct sdma_firmware_header_v1_0 *hdr;
1052 const __le32 *fw_data;
1057 sdma_v4_0_enable(adev, false);
1059 for (i = 0; i < adev->sdma.num_instances; i++) {
1060 if (!adev->sdma.instance[i].fw)
1063 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
1064 amdgpu_ucode_print_sdma_hdr(&hdr->header);
1065 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1067 fw_data = (const __le32 *)
1068 (adev->sdma.instance[i].fw->data +
1069 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1071 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0);
1073 for (j = 0; j < fw_size; j++)
1074 WREG32_SDMA(i, mmSDMA0_UCODE_DATA,
1075 le32_to_cpup(fw_data++));
1077 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR,
1078 adev->sdma.instance[i].fw_version);
1085 * sdma_v4_0_start - setup and start the async dma engines
1087 * @adev: amdgpu_device pointer
1089 * Set up the DMA engines and enable them (VEGA10).
1090 * Returns 0 for success, error for failure.
1092 static int sdma_v4_0_start(struct amdgpu_device *adev)
1094 struct amdgpu_ring *ring;
1097 if (amdgpu_sriov_vf(adev)) {
1098 sdma_v4_0_ctx_switch_enable(adev, false);
1099 sdma_v4_0_enable(adev, false);
1102 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1103 r = sdma_v4_0_load_microcode(adev);
1108 /* unhalt the MEs */
1109 sdma_v4_0_enable(adev, true);
1110 /* enable sdma ring preemption */
1111 sdma_v4_0_ctx_switch_enable(adev, true);
1114 /* start the gfx rings and rlc compute queues */
1115 for (i = 0; i < adev->sdma.num_instances; i++) {
1118 WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0);
1119 sdma_v4_0_gfx_resume(adev, i);
1120 if (adev->sdma.has_page_queue)
1121 sdma_v4_0_page_resume(adev, i);
1123 /* set utc l1 enable flag always to 1 */
1124 temp = RREG32_SDMA(i, mmSDMA0_CNTL);
1125 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
1126 WREG32_SDMA(i, mmSDMA0_CNTL, temp);
1128 if (!amdgpu_sriov_vf(adev)) {
1130 temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
1131 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
1132 WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp);
1136 if (amdgpu_sriov_vf(adev)) {
1137 sdma_v4_0_ctx_switch_enable(adev, true);
1138 sdma_v4_0_enable(adev, true);
1140 r = sdma_v4_0_rlc_resume(adev);
1145 for (i = 0; i < adev->sdma.num_instances; i++) {
1146 ring = &adev->sdma.instance[i].ring;
1148 r = amdgpu_ring_test_helper(ring);
1152 if (adev->sdma.has_page_queue) {
1153 struct amdgpu_ring *page = &adev->sdma.instance[i].page;
1155 r = amdgpu_ring_test_helper(page);
1159 if (adev->mman.buffer_funcs_ring == page)
1160 amdgpu_ttm_set_buffer_funcs_status(adev, true);
1163 if (adev->mman.buffer_funcs_ring == ring)
1164 amdgpu_ttm_set_buffer_funcs_status(adev, true);
1171 * sdma_v4_0_ring_test_ring - simple async dma engine test
1173 * @ring: amdgpu_ring structure holding ring information
1175 * Test the DMA engine by writing using it to write an
1176 * value to memory. (VEGA10).
1177 * Returns 0 for success, error for failure.
1179 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring)
1181 struct amdgpu_device *adev = ring->adev;
1188 r = amdgpu_device_wb_get(adev, &index);
1192 gpu_addr = adev->wb.gpu_addr + (index * 4);
1194 adev->wb.wb[index] = cpu_to_le32(tmp);
1196 r = amdgpu_ring_alloc(ring, 5);
1200 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1201 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
1202 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
1203 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
1204 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
1205 amdgpu_ring_write(ring, 0xDEADBEEF);
1206 amdgpu_ring_commit(ring);
1208 for (i = 0; i < adev->usec_timeout; i++) {
1209 tmp = le32_to_cpu(adev->wb.wb[index]);
1210 if (tmp == 0xDEADBEEF)
1215 if (i >= adev->usec_timeout)
1219 amdgpu_device_wb_free(adev, index);
1224 * sdma_v4_0_ring_test_ib - test an IB on the DMA engine
1226 * @ring: amdgpu_ring structure holding ring information
1228 * Test a simple IB in the DMA ring (VEGA10).
1229 * Returns 0 on success, error on failure.
1231 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1233 struct amdgpu_device *adev = ring->adev;
1234 struct amdgpu_ib ib;
1235 struct dma_fence *f = NULL;
1241 r = amdgpu_device_wb_get(adev, &index);
1245 gpu_addr = adev->wb.gpu_addr + (index * 4);
1247 adev->wb.wb[index] = cpu_to_le32(tmp);
1248 memset(&ib, 0, sizeof(ib));
1249 r = amdgpu_ib_get(adev, NULL, 256, &ib);
1253 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1254 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1255 ib.ptr[1] = lower_32_bits(gpu_addr);
1256 ib.ptr[2] = upper_32_bits(gpu_addr);
1257 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1258 ib.ptr[4] = 0xDEADBEEF;
1259 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1260 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1261 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1264 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1268 r = dma_fence_wait_timeout(f, false, timeout);
1275 tmp = le32_to_cpu(adev->wb.wb[index]);
1276 if (tmp == 0xDEADBEEF)
1282 amdgpu_ib_free(adev, &ib, NULL);
1285 amdgpu_device_wb_free(adev, index);
1291 * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART
1293 * @ib: indirect buffer to fill with commands
1294 * @pe: addr of the page entry
1295 * @src: src addr to copy from
1296 * @count: number of page entries to update
1298 * Update PTEs by copying them from the GART using sDMA (VEGA10).
1300 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib,
1301 uint64_t pe, uint64_t src,
1304 unsigned bytes = count * 8;
1306 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1307 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1308 ib->ptr[ib->length_dw++] = bytes - 1;
1309 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1310 ib->ptr[ib->length_dw++] = lower_32_bits(src);
1311 ib->ptr[ib->length_dw++] = upper_32_bits(src);
1312 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1313 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1318 * sdma_v4_0_vm_write_pte - update PTEs by writing them manually
1320 * @ib: indirect buffer to fill with commands
1321 * @pe: addr of the page entry
1322 * @addr: dst addr to write into pe
1323 * @count: number of page entries to update
1324 * @incr: increase next addr by incr bytes
1325 * @flags: access flags
1327 * Update PTEs by writing them manually using sDMA (VEGA10).
1329 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1330 uint64_t value, unsigned count,
1333 unsigned ndw = count * 2;
1335 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1336 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1337 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1338 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1339 ib->ptr[ib->length_dw++] = ndw - 1;
1340 for (; ndw > 0; ndw -= 2) {
1341 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1342 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1348 * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA
1350 * @ib: indirect buffer to fill with commands
1351 * @pe: addr of the page entry
1352 * @addr: dst addr to write into pe
1353 * @count: number of page entries to update
1354 * @incr: increase next addr by incr bytes
1355 * @flags: access flags
1357 * Update the page tables using sDMA (VEGA10).
1359 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1361 uint64_t addr, unsigned count,
1362 uint32_t incr, uint64_t flags)
1364 /* for physically contiguous pages (vram) */
1365 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1366 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1367 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1368 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1369 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1370 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1371 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1372 ib->ptr[ib->length_dw++] = incr; /* increment size */
1373 ib->ptr[ib->length_dw++] = 0;
1374 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1378 * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw
1380 * @ib: indirect buffer to fill with padding
1383 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1385 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1389 pad_count = (8 - (ib->length_dw & 0x7)) % 8;
1390 for (i = 0; i < pad_count; i++)
1391 if (sdma && sdma->burst_nop && (i == 0))
1392 ib->ptr[ib->length_dw++] =
1393 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1394 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1396 ib->ptr[ib->length_dw++] =
1397 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1402 * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline
1404 * @ring: amdgpu_ring pointer
1406 * Make sure all previous operations are completed (CIK).
1408 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1410 uint32_t seq = ring->fence_drv.sync_seq;
1411 uint64_t addr = ring->fence_drv.gpu_addr;
1414 sdma_v4_0_wait_reg_mem(ring, 1, 0,
1416 upper_32_bits(addr) & 0xffffffff,
1417 seq, 0xffffffff, 4);
1422 * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA
1424 * @ring: amdgpu_ring pointer
1425 * @vm: amdgpu_vm pointer
1427 * Update the page table base and flush the VM TLB
1428 * using sDMA (VEGA10).
1430 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1431 unsigned vmid, uint64_t pd_addr)
1433 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1436 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring,
1437 uint32_t reg, uint32_t val)
1439 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1440 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1441 amdgpu_ring_write(ring, reg);
1442 amdgpu_ring_write(ring, val);
1445 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1446 uint32_t val, uint32_t mask)
1448 sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
1451 static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev)
1453 uint fw_version = adev->sdma.instance[0].fw_version;
1455 switch (adev->asic_type) {
1457 return fw_version >= 430;
1459 /*return fw_version >= 31;*/
1462 return fw_version >= 123;
1468 static int sdma_v4_0_early_init(void *handle)
1470 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1473 if (adev->asic_type == CHIP_RAVEN)
1474 adev->sdma.num_instances = 1;
1476 adev->sdma.num_instances = 2;
1478 r = sdma_v4_0_init_microcode(adev);
1480 DRM_ERROR("Failed to load sdma firmware!\n");
1484 /* TODO: Page queue breaks driver reload under SRIOV */
1485 if ((adev->asic_type == CHIP_VEGA10) && amdgpu_sriov_vf((adev)))
1486 adev->sdma.has_page_queue = false;
1487 else if (sdma_v4_0_fw_support_paging_queue(adev))
1488 adev->sdma.has_page_queue = true;
1490 sdma_v4_0_set_ring_funcs(adev);
1491 sdma_v4_0_set_buffer_funcs(adev);
1492 sdma_v4_0_set_vm_pte_funcs(adev);
1493 sdma_v4_0_set_irq_funcs(adev);
1498 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
1499 struct amdgpu_iv_entry *entry);
1501 static int sdma_v4_0_late_init(void *handle)
1503 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1504 struct ras_common_if **ras_if = &adev->sdma.ras_if;
1505 struct ras_ih_if ih_info = {
1506 .cb = sdma_v4_0_process_ras_data_cb,
1508 struct ras_fs_if fs_info = {
1509 .sysfs_name = "sdma_err_count",
1510 .debugfs_name = "sdma_err_inject",
1512 struct ras_common_if ras_block = {
1513 .block = AMDGPU_RAS_BLOCK__SDMA,
1514 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
1515 .sub_block_index = 0,
1520 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
1521 amdgpu_ras_feature_enable(adev, &ras_block, 0);
1525 *ras_if = kmalloc(sizeof(**ras_if), GFP_KERNEL);
1529 **ras_if = ras_block;
1531 r = amdgpu_ras_feature_enable(adev, *ras_if, 1);
1535 ih_info.head = **ras_if;
1536 fs_info.head = **ras_if;
1538 r = amdgpu_ras_interrupt_add_handler(adev, &ih_info);
1542 r = amdgpu_ras_debugfs_create(adev, &fs_info);
1546 r = amdgpu_ras_sysfs_create(adev, &fs_info);
1550 r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_ECC0);
1554 r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_ECC1);
1556 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_ECC0);
1562 amdgpu_ras_sysfs_remove(adev, *ras_if);
1564 amdgpu_ras_debugfs_remove(adev, *ras_if);
1566 amdgpu_ras_interrupt_remove_handler(adev, &ih_info);
1568 amdgpu_ras_feature_enable(adev, *ras_if, 0);
1575 static int sdma_v4_0_sw_init(void *handle)
1577 struct amdgpu_ring *ring;
1579 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1581 /* SDMA trap event */
1582 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, SDMA0_4_0__SRCID__SDMA_TRAP,
1583 &adev->sdma.trap_irq);
1587 /* SDMA trap event */
1588 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, SDMA1_4_0__SRCID__SDMA_TRAP,
1589 &adev->sdma.trap_irq);
1593 /* SDMA SRAM ECC event */
1594 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, SDMA0_4_0__SRCID__SDMA_SRAM_ECC,
1595 &adev->sdma.ecc_irq);
1599 /* SDMA SRAM ECC event */
1600 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, SDMA1_4_0__SRCID__SDMA_SRAM_ECC,
1601 &adev->sdma.ecc_irq);
1605 for (i = 0; i < adev->sdma.num_instances; i++) {
1606 ring = &adev->sdma.instance[i].ring;
1607 ring->ring_obj = NULL;
1608 ring->use_doorbell = true;
1610 DRM_INFO("use_doorbell being set to: [%s]\n",
1611 ring->use_doorbell?"true":"false");
1613 /* doorbell size is 2 dwords, get DWORD offset */
1614 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1616 sprintf(ring->name, "sdma%d", i);
1617 r = amdgpu_ring_init(adev, ring, 1024,
1618 &adev->sdma.trap_irq,
1620 AMDGPU_SDMA_IRQ_TRAP0 :
1621 AMDGPU_SDMA_IRQ_TRAP1);
1625 if (adev->sdma.has_page_queue) {
1626 ring = &adev->sdma.instance[i].page;
1627 ring->ring_obj = NULL;
1628 ring->use_doorbell = true;
1630 /* paging queue use same doorbell index/routing as gfx queue
1631 * with 0x400 (4096 dwords) offset on second doorbell page
1633 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1634 ring->doorbell_index += 0x400;
1636 sprintf(ring->name, "page%d", i);
1637 r = amdgpu_ring_init(adev, ring, 1024,
1638 &adev->sdma.trap_irq,
1640 AMDGPU_SDMA_IRQ_TRAP0 :
1641 AMDGPU_SDMA_IRQ_TRAP1);
1650 static int sdma_v4_0_sw_fini(void *handle)
1652 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1655 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA) &&
1656 adev->sdma.ras_if) {
1657 struct ras_common_if *ras_if = adev->sdma.ras_if;
1658 struct ras_ih_if ih_info = {
1663 amdgpu_ras_debugfs_remove(adev, ras_if);
1664 amdgpu_ras_sysfs_remove(adev, ras_if);
1666 amdgpu_ras_interrupt_remove_handler(adev, &ih_info);
1667 amdgpu_ras_feature_enable(adev, ras_if, 0);
1671 for (i = 0; i < adev->sdma.num_instances; i++) {
1672 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1673 if (adev->sdma.has_page_queue)
1674 amdgpu_ring_fini(&adev->sdma.instance[i].page);
1677 for (i = 0; i < adev->sdma.num_instances; i++) {
1678 release_firmware(adev->sdma.instance[i].fw);
1679 adev->sdma.instance[i].fw = NULL;
1685 static int sdma_v4_0_hw_init(void *handle)
1688 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1690 if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs &&
1691 adev->powerplay.pp_funcs->set_powergating_by_smu)
1692 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false);
1694 sdma_v4_0_init_golden_registers(adev);
1696 r = sdma_v4_0_start(adev);
1701 static int sdma_v4_0_hw_fini(void *handle)
1703 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1705 if (amdgpu_sriov_vf(adev))
1708 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_ECC0);
1709 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_ECC1);
1711 sdma_v4_0_ctx_switch_enable(adev, false);
1712 sdma_v4_0_enable(adev, false);
1714 if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs
1715 && adev->powerplay.pp_funcs->set_powergating_by_smu)
1716 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true);
1721 static int sdma_v4_0_suspend(void *handle)
1723 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1725 return sdma_v4_0_hw_fini(adev);
1728 static int sdma_v4_0_resume(void *handle)
1730 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1732 return sdma_v4_0_hw_init(adev);
1735 static bool sdma_v4_0_is_idle(void *handle)
1737 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1740 for (i = 0; i < adev->sdma.num_instances; i++) {
1741 u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG);
1743 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1750 static int sdma_v4_0_wait_for_idle(void *handle)
1754 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1756 for (i = 0; i < adev->usec_timeout; i++) {
1757 sdma0 = RREG32_SDMA(0, mmSDMA0_STATUS_REG);
1758 sdma1 = RREG32_SDMA(1, mmSDMA0_STATUS_REG);
1760 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1767 static int sdma_v4_0_soft_reset(void *handle)
1774 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev,
1775 struct amdgpu_irq_src *source,
1777 enum amdgpu_interrupt_state state)
1779 unsigned int instance = (type == AMDGPU_SDMA_IRQ_TRAP0) ? 0 : 1;
1782 sdma_cntl = RREG32_SDMA(instance, mmSDMA0_CNTL);
1783 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1784 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1785 WREG32_SDMA(instance, mmSDMA0_CNTL, sdma_cntl);
1790 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
1791 struct amdgpu_irq_src *source,
1792 struct amdgpu_iv_entry *entry)
1796 DRM_DEBUG("IH: SDMA trap\n");
1797 switch (entry->client_id) {
1798 case SOC15_IH_CLIENTID_SDMA0:
1801 case SOC15_IH_CLIENTID_SDMA1:
1808 switch (entry->ring_id) {
1810 amdgpu_fence_process(&adev->sdma.instance[instance].ring);
1813 if (adev->asic_type == CHIP_VEGA20)
1814 amdgpu_fence_process(&adev->sdma.instance[instance].page);
1820 if (adev->asic_type != CHIP_VEGA20)
1821 amdgpu_fence_process(&adev->sdma.instance[instance].page);
1827 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
1828 struct amdgpu_iv_entry *entry)
1830 uint32_t instance, err_source;
1832 switch (entry->client_id) {
1833 case SOC15_IH_CLIENTID_SDMA0:
1836 case SOC15_IH_CLIENTID_SDMA1:
1843 switch (entry->src_id) {
1844 case SDMA0_4_0__SRCID__SDMA_SRAM_ECC:
1847 case SDMA0_4_0__SRCID__SDMA_ECC:
1854 amdgpu_ras_reset_gpu(adev, 0);
1856 return AMDGPU_RAS_UE;
1859 static int sdma_v4_0_process_ecc_irq(struct amdgpu_device *adev,
1860 struct amdgpu_irq_src *source,
1861 struct amdgpu_iv_entry *entry)
1863 struct ras_dispatch_if ih_data = {
1864 .head = *adev->sdma.ras_if,
1867 amdgpu_ras_interrupt_dispatch(adev, &ih_data);
1871 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1872 struct amdgpu_irq_src *source,
1873 struct amdgpu_iv_entry *entry)
1877 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1879 switch (entry->client_id) {
1880 case SOC15_IH_CLIENTID_SDMA0:
1883 case SOC15_IH_CLIENTID_SDMA1:
1890 switch (entry->ring_id) {
1892 drm_sched_fault(&adev->sdma.instance[instance].ring.sched);
1898 static int sdma_v4_0_set_ecc_irq_state(struct amdgpu_device *adev,
1899 struct amdgpu_irq_src *source,
1901 enum amdgpu_interrupt_state state)
1903 u32 sdma_edc_config;
1905 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_ECC0) ?
1906 sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_EDC_CONFIG) :
1907 sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_EDC_CONFIG);
1909 sdma_edc_config = RREG32(reg_offset);
1910 sdma_edc_config = REG_SET_FIELD(sdma_edc_config, SDMA0_EDC_CONFIG, ECC_INT_ENABLE,
1911 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1912 WREG32(reg_offset, sdma_edc_config);
1917 static void sdma_v4_0_update_medium_grain_clock_gating(
1918 struct amdgpu_device *adev,
1923 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1924 /* enable sdma0 clock gating */
1925 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
1926 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1927 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1928 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1929 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1930 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1931 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1932 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1933 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1935 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);
1937 if (adev->sdma.num_instances > 1) {
1938 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));
1939 data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1940 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1941 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1942 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1943 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1944 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1945 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1946 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1948 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);
1951 /* disable sdma0 clock gating */
1952 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
1953 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1954 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1955 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1956 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1957 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1958 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1959 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1960 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1963 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);
1965 if (adev->sdma.num_instances > 1) {
1966 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));
1967 data |= (SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1968 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1969 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1970 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1971 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1972 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1973 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1974 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1976 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);
1982 static void sdma_v4_0_update_medium_grain_light_sleep(
1983 struct amdgpu_device *adev,
1988 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1989 /* 1-not override: enable sdma0 mem light sleep */
1990 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1991 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1993 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1995 /* 1-not override: enable sdma1 mem light sleep */
1996 if (adev->sdma.num_instances > 1) {
1997 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));
1998 data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
2000 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);
2003 /* 0-override:disable sdma0 mem light sleep */
2004 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
2005 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
2007 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
2009 /* 0-override:disable sdma1 mem light sleep */
2010 if (adev->sdma.num_instances > 1) {
2011 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));
2012 data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
2014 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);
2019 static int sdma_v4_0_set_clockgating_state(void *handle,
2020 enum amd_clockgating_state state)
2022 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2024 if (amdgpu_sriov_vf(adev))
2027 switch (adev->asic_type) {
2032 sdma_v4_0_update_medium_grain_clock_gating(adev,
2033 state == AMD_CG_STATE_GATE ? true : false);
2034 sdma_v4_0_update_medium_grain_light_sleep(adev,
2035 state == AMD_CG_STATE_GATE ? true : false);
2043 static int sdma_v4_0_set_powergating_state(void *handle,
2044 enum amd_powergating_state state)
2046 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2048 switch (adev->asic_type) {
2050 sdma_v4_1_update_power_gating(adev,
2051 state == AMD_PG_STATE_GATE ? true : false);
2060 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags)
2062 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2065 if (amdgpu_sriov_vf(adev))
2068 /* AMD_CG_SUPPORT_SDMA_MGCG */
2069 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
2070 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
2071 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
2073 /* AMD_CG_SUPPORT_SDMA_LS */
2074 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
2075 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
2076 *flags |= AMD_CG_SUPPORT_SDMA_LS;
2079 const struct amd_ip_funcs sdma_v4_0_ip_funcs = {
2080 .name = "sdma_v4_0",
2081 .early_init = sdma_v4_0_early_init,
2082 .late_init = sdma_v4_0_late_init,
2083 .sw_init = sdma_v4_0_sw_init,
2084 .sw_fini = sdma_v4_0_sw_fini,
2085 .hw_init = sdma_v4_0_hw_init,
2086 .hw_fini = sdma_v4_0_hw_fini,
2087 .suspend = sdma_v4_0_suspend,
2088 .resume = sdma_v4_0_resume,
2089 .is_idle = sdma_v4_0_is_idle,
2090 .wait_for_idle = sdma_v4_0_wait_for_idle,
2091 .soft_reset = sdma_v4_0_soft_reset,
2092 .set_clockgating_state = sdma_v4_0_set_clockgating_state,
2093 .set_powergating_state = sdma_v4_0_set_powergating_state,
2094 .get_clockgating_state = sdma_v4_0_get_clockgating_state,
2097 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
2098 .type = AMDGPU_RING_TYPE_SDMA,
2100 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2101 .support_64bit_ptrs = true,
2102 .vmhub = AMDGPU_MMHUB,
2103 .get_rptr = sdma_v4_0_ring_get_rptr,
2104 .get_wptr = sdma_v4_0_ring_get_wptr,
2105 .set_wptr = sdma_v4_0_ring_set_wptr,
2107 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2108 3 + /* hdp invalidate */
2109 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2110 /* sdma_v4_0_ring_emit_vm_flush */
2111 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2112 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2113 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2114 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2115 .emit_ib = sdma_v4_0_ring_emit_ib,
2116 .emit_fence = sdma_v4_0_ring_emit_fence,
2117 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2118 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2119 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2120 .test_ring = sdma_v4_0_ring_test_ring,
2121 .test_ib = sdma_v4_0_ring_test_ib,
2122 .insert_nop = sdma_v4_0_ring_insert_nop,
2123 .pad_ib = sdma_v4_0_ring_pad_ib,
2124 .emit_wreg = sdma_v4_0_ring_emit_wreg,
2125 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2126 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2129 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = {
2130 .type = AMDGPU_RING_TYPE_SDMA,
2132 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2133 .support_64bit_ptrs = true,
2134 .vmhub = AMDGPU_MMHUB,
2135 .get_rptr = sdma_v4_0_ring_get_rptr,
2136 .get_wptr = sdma_v4_0_page_ring_get_wptr,
2137 .set_wptr = sdma_v4_0_page_ring_set_wptr,
2139 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2140 3 + /* hdp invalidate */
2141 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2142 /* sdma_v4_0_ring_emit_vm_flush */
2143 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2144 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2145 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2146 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2147 .emit_ib = sdma_v4_0_ring_emit_ib,
2148 .emit_fence = sdma_v4_0_ring_emit_fence,
2149 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2150 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2151 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2152 .test_ring = sdma_v4_0_ring_test_ring,
2153 .test_ib = sdma_v4_0_ring_test_ib,
2154 .insert_nop = sdma_v4_0_ring_insert_nop,
2155 .pad_ib = sdma_v4_0_ring_pad_ib,
2156 .emit_wreg = sdma_v4_0_ring_emit_wreg,
2157 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2158 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2161 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
2165 for (i = 0; i < adev->sdma.num_instances; i++) {
2166 adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs;
2167 adev->sdma.instance[i].ring.me = i;
2168 if (adev->sdma.has_page_queue) {
2169 adev->sdma.instance[i].page.funcs = &sdma_v4_0_page_ring_funcs;
2170 adev->sdma.instance[i].page.me = i;
2175 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = {
2176 .set = sdma_v4_0_set_trap_irq_state,
2177 .process = sdma_v4_0_process_trap_irq,
2180 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = {
2181 .process = sdma_v4_0_process_illegal_inst_irq,
2184 static const struct amdgpu_irq_src_funcs sdma_v4_0_ecc_irq_funcs = {
2185 .set = sdma_v4_0_set_ecc_irq_state,
2186 .process = sdma_v4_0_process_ecc_irq,
2191 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev)
2193 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
2194 adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs;
2195 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs;
2196 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
2197 adev->sdma.ecc_irq.funcs = &sdma_v4_0_ecc_irq_funcs;
2201 * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine
2203 * @ring: amdgpu_ring structure holding ring information
2204 * @src_offset: src GPU address
2205 * @dst_offset: dst GPU address
2206 * @byte_count: number of bytes to xfer
2208 * Copy GPU buffers using the DMA engine (VEGA10/12).
2209 * Used by the amdgpu ttm implementation to move pages if
2210 * registered as the asic copy callback.
2212 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib,
2213 uint64_t src_offset,
2214 uint64_t dst_offset,
2215 uint32_t byte_count)
2217 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
2218 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
2219 ib->ptr[ib->length_dw++] = byte_count - 1;
2220 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
2221 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
2222 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
2223 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2224 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2228 * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine
2230 * @ring: amdgpu_ring structure holding ring information
2231 * @src_data: value to write to buffer
2232 * @dst_offset: dst GPU address
2233 * @byte_count: number of bytes to xfer
2235 * Fill GPU buffers using the DMA engine (VEGA10/12).
2237 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib,
2239 uint64_t dst_offset,
2240 uint32_t byte_count)
2242 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
2243 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2244 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2245 ib->ptr[ib->length_dw++] = src_data;
2246 ib->ptr[ib->length_dw++] = byte_count - 1;
2249 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = {
2250 .copy_max_bytes = 0x400000,
2252 .emit_copy_buffer = sdma_v4_0_emit_copy_buffer,
2254 .fill_max_bytes = 0x400000,
2256 .emit_fill_buffer = sdma_v4_0_emit_fill_buffer,
2259 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
2261 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
2262 if (adev->sdma.has_page_queue)
2263 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
2265 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
2268 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = {
2269 .copy_pte_num_dw = 7,
2270 .copy_pte = sdma_v4_0_vm_copy_pte,
2272 .write_pte = sdma_v4_0_vm_write_pte,
2273 .set_pte_pde = sdma_v4_0_vm_set_pte_pde,
2276 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev)
2278 struct drm_gpu_scheduler *sched;
2281 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
2282 for (i = 0; i < adev->sdma.num_instances; i++) {
2283 if (adev->sdma.has_page_queue)
2284 sched = &adev->sdma.instance[i].page.sched;
2286 sched = &adev->sdma.instance[i].ring.sched;
2287 adev->vm_manager.vm_pte_rqs[i] =
2288 &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
2290 adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
2293 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = {
2294 .type = AMD_IP_BLOCK_TYPE_SDMA,
2298 .funcs = &sdma_v4_0_ip_funcs,