drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24
  25 #include <linux/delay.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_ucode.h"
  31 #include "amdgpu_trace.h"
  32 #include "vi.h"
  33 #include "vid.h"
  34
  35 #include "oss/oss_3_0_d.h"
  36 #include "oss/oss_3_0_sh_mask.h"
  37
  38 #include "gmc/gmc_8_1_d.h"
  39 #include "gmc/gmc_8_1_sh_mask.h"
  40
  41 #include "gca/gfx_8_0_d.h"
  42 #include "gca/gfx_8_0_enum.h"
  43 #include "gca/gfx_8_0_sh_mask.h"
  44
  45 #include "bif/bif_5_0_d.h"
  46 #include "bif/bif_5_0_sh_mask.h"
  47
  48 #include "tonga_sdma_pkt_open.h"
  49
  50 #include "ivsrcid/ivsrcid_vislands30.h"
  51
  52 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev);
  53 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev);
  54 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  55 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev);
  56
  57 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin");
  58 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin");
  59 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin");
  60 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin");
  61 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin");
  62 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin");
  63 MODULE_FIRMWARE("amdgpu/stoney_sdma.bin");
  64 MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin");
  65 MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin");
  66 MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin");
  67 MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin");
  68 MODULE_FIRMWARE("amdgpu/polaris12_sdma.bin");
  69 MODULE_FIRMWARE("amdgpu/polaris12_sdma1.bin");
  70 MODULE_FIRMWARE("amdgpu/vegam_sdma.bin");
  71 MODULE_FIRMWARE("amdgpu/vegam_sdma1.bin");
  72
  73
  74 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  75 {
  76         SDMA0_REGISTER_OFFSET,
  77         SDMA1_REGISTER_OFFSET
  78 };
  79
  80 static const u32 golden_settings_tonga_a11[] =
  81 {
  82         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  83         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
  84         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  85         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  86         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  87         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  88         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
  89         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  90         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  91         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  92 };
  93
  94 static const u32 tonga_mgcg_cgcg_init[] =
  95 {
  96         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
  97         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
  98 };
  99
 100 static const u32 golden_settings_fiji_a10[] =
 101 {
 102         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 103         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 104         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 105         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 106         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 107         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 108         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 109         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 110 };
 111
 112 static const u32 fiji_mgcg_cgcg_init[] =
 113 {
 114         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
 115         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
 116 };
 117
 118 static const u32 golden_settings_polaris11_a11[] =
 119 {
 120         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 121         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
 122         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 123         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 124         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 125         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 126         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
 127         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 128         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 129         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 130 };
 131
 132 static const u32 golden_settings_polaris10_a11[] =
 133 {
 134         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 135         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
 136         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 137         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 138         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 139         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 140         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
 141         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 142         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 143         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 144 };
 145
 146 static const u32 cz_golden_settings_a11[] =
 147 {
 148         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 149         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
 150         mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
 151         mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
 152         mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 153         mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 154         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 155         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
 156         mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100,
 157         mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800,
 158         mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 159         mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 160 };
 161
 162 static const u32 cz_mgcg_cgcg_init[] =
 163 {
 164         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
 165         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
 166 };
 167
 168 static const u32 stoney_golden_settings_a11[] =
 169 {
 170         mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
 171         mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
 172         mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 173         mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 174 };
 175
 176 static const u32 stoney_mgcg_cgcg_init[] =
 177 {
 178         mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100,
 179 };
 180
 181 /*
 182  * sDMA - System DMA
 183  * Starting with CIK, the GPU has new asynchronous
 184  * DMA engines.  These engines are used for compute
 185  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
 186  * and each one supports 1 ring buffer used for gfx
 187  * and 2 queues used for compute.
 188  *
 189  * The programming model is very similar to the CP
 190  * (ring buffer, IBs, etc.), but sDMA has it's own
 191  * packet format that is different from the PM4 format
 192  * used by the CP. sDMA supports copying data, writing
 193  * embedded data, solid fills, and a number of other
 194  * things.  It also has support for tiling/detiling of
 195  * buffers.
 196  */
 197
 198 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
 199 {
 200         switch (adev->asic_type) {
 201         case CHIP_FIJI:
 202                 amdgpu_device_program_register_sequence(adev,
 203                                                         fiji_mgcg_cgcg_init,
 204                                                         ARRAY_SIZE(fiji_mgcg_cgcg_init));
 205                 amdgpu_device_program_register_sequence(adev,
 206                                                         golden_settings_fiji_a10,
 207                                                         ARRAY_SIZE(golden_settings_fiji_a10));
 208                 break;
 209         case CHIP_TONGA:
 210                 amdgpu_device_program_register_sequence(adev,
 211                                                         tonga_mgcg_cgcg_init,
 212                                                         ARRAY_SIZE(tonga_mgcg_cgcg_init));
 213                 amdgpu_device_program_register_sequence(adev,
 214                                                         golden_settings_tonga_a11,
 215                                                         ARRAY_SIZE(golden_settings_tonga_a11));
 216                 break;
 217         case CHIP_POLARIS11:
 218         case CHIP_POLARIS12:
 219         case CHIP_VEGAM:
 220                 amdgpu_device_program_register_sequence(adev,
 221                                                         golden_settings_polaris11_a11,
 222                                                         ARRAY_SIZE(golden_settings_polaris11_a11));
 223                 break;
 224         case CHIP_POLARIS10:
 225                 amdgpu_device_program_register_sequence(adev,
 226                                                         golden_settings_polaris10_a11,
 227                                                         ARRAY_SIZE(golden_settings_polaris10_a11));
 228                 break;
 229         case CHIP_CARRIZO:
 230                 amdgpu_device_program_register_sequence(adev,
 231                                                         cz_mgcg_cgcg_init,
 232                                                         ARRAY_SIZE(cz_mgcg_cgcg_init));
 233                 amdgpu_device_program_register_sequence(adev,
 234                                                         cz_golden_settings_a11,
 235                                                         ARRAY_SIZE(cz_golden_settings_a11));
 236                 break;
 237         case CHIP_STONEY:
 238                 amdgpu_device_program_register_sequence(adev,
 239                                                         stoney_mgcg_cgcg_init,
 240                                                         ARRAY_SIZE(stoney_mgcg_cgcg_init));
 241                 amdgpu_device_program_register_sequence(adev,
 242                                                         stoney_golden_settings_a11,
 243                                                         ARRAY_SIZE(stoney_golden_settings_a11));
 244                 break;
 245         default:
 246                 break;
 247         }
 248 }
 249
 250 static void sdma_v3_0_free_microcode(struct amdgpu_device *adev)
 251 {
 252         int i;
 253         for (i = 0; i < adev->sdma.num_instances; i++) {
 254                 release_firmware(adev->sdma.instance[i].fw);
 255                 adev->sdma.instance[i].fw = NULL;
 256         }
 257 }
 258
 259 /**
 260  * sdma_v3_0_init_microcode - load ucode images from disk
 261  *
 262  * @adev: amdgpu_device pointer
 263  *
 264  * Use the firmware interface to load the ucode images into
 265  * the driver (not loaded into hw).
 266  * Returns 0 on success, error on failure.
 267  */
 268 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
 269 {
 270         const char *chip_name;
 271         char fw_name[30];
 272         int err = 0, i;
 273         struct amdgpu_firmware_info *info = NULL;
 274         const struct common_firmware_header *header = NULL;
 275         const struct sdma_firmware_header_v1_0 *hdr;
 276
 277         DRM_DEBUG("\n");
 278
 279         switch (adev->asic_type) {
 280         case CHIP_TONGA:
 281                 chip_name = "tonga";
 282                 break;
 283         case CHIP_FIJI:
 284                 chip_name = "fiji";
 285                 break;
 286         case CHIP_POLARIS10:
 287                 chip_name = "polaris10";
 288                 break;
 289         case CHIP_POLARIS11:
 290                 chip_name = "polaris11";
 291                 break;
 292         case CHIP_POLARIS12:
 293                 chip_name = "polaris12";
 294                 break;
 295         case CHIP_VEGAM:
 296                 chip_name = "vegam";
 297                 break;
 298         case CHIP_CARRIZO:
 299                 chip_name = "carrizo";
 300                 break;
 301         case CHIP_STONEY:
 302                 chip_name = "stoney";
 303                 break;
 304         default: BUG();
 305         }
 306
 307         for (i = 0; i < adev->sdma.num_instances; i++) {
 308                 if (i == 0)
 309                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 310                 else
 311                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 312                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 313                 if (err)
 314                         goto out;
 315                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 316                 if (err)
 317                         goto out;
 318                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 319                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 320                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 321                 if (adev->sdma.instance[i].feature_version >= 20)
 322                         adev->sdma.instance[i].burst_nop = true;
 323
 324                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 325                 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 326                 info->fw = adev->sdma.instance[i].fw;
 327                 header = (const struct common_firmware_header *)info->fw->data;
 328                 adev->firmware.fw_size +=
 329                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 330
 331         }
 332 out:
 333         if (err) {
 334                 pr_err("sdma_v3_0: Failed to load firmware \"%s\"\n", fw_name);
 335                 for (i = 0; i < adev->sdma.num_instances; i++) {
 336                         release_firmware(adev->sdma.instance[i].fw);
 337                         adev->sdma.instance[i].fw = NULL;
 338                 }
 339         }
 340         return err;
 341 }
 342
 343 /**
 344  * sdma_v3_0_ring_get_rptr - get the current read pointer
 345  *
 346  * @ring: amdgpu ring pointer
 347  *
 348  * Get the current rptr from the hardware (VI+).
 349  */
 350 static uint64_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
 351 {
 352         /* XXX check if swapping is necessary on BE */
 353         return ring->adev->wb.wb[ring->rptr_offs] >> 2;
 354 }
 355
 356 /**
 357  * sdma_v3_0_ring_get_wptr - get the current write pointer
 358  *
 359  * @ring: amdgpu ring pointer
 360  *
 361  * Get the current wptr from the hardware (VI+).
 362  */
 363 static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
 364 {
 365         struct amdgpu_device *adev = ring->adev;
 366         u32 wptr;
 367
 368         if (ring->use_doorbell || ring->use_pollmem) {
 369                 /* XXX check if swapping is necessary on BE */
 370                 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
 371         } else {
 372                 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
 373         }
 374
 375         return wptr;
 376 }
 377
 378 /**
 379  * sdma_v3_0_ring_set_wptr - commit the write pointer
 380  *
 381  * @ring: amdgpu ring pointer
 382  *
 383  * Write the wptr back to the hardware (VI+).
 384  */
 385 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
 386 {
 387         struct amdgpu_device *adev = ring->adev;
 388
 389         if (ring->use_doorbell) {
 390                 u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs];
 391                 /* XXX check if swapping is necessary on BE */
 392                 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));
 393                 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr) << 2);
 394         } else if (ring->use_pollmem) {
 395                 u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs];
 396
 397                 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));
 398         } else {
 399                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);
 400         }
 401 }
 402
 403 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 404 {
 405         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 406         int i;
 407
 408         for (i = 0; i < count; i++)
 409                 if (sdma && sdma->burst_nop && (i == 0))
 410                         amdgpu_ring_write(ring, ring->funcs->nop |
 411                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 412                 else
 413                         amdgpu_ring_write(ring, ring->funcs->nop);
 414 }
 415
 416 /**
 417  * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
 418  *
 419  * @ring: amdgpu ring pointer
 420  * @ib: IB object to schedule
 421  *
 422  * Schedule an IB in the DMA ring (VI).
 423  */
 424 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
 425                                    struct amdgpu_job *job,
 426                                    struct amdgpu_ib *ib,
 427                                    uint32_t flags)
 428 {
 429         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 430
 431         /* IB packet must end on a 8 DW boundary */
 432         sdma_v3_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 433
 434         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 435                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 436         /* base must be 32 byte aligned */
 437         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 438         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 439         amdgpu_ring_write(ring, ib->length_dw);
 440         amdgpu_ring_write(ring, 0);
 441         amdgpu_ring_write(ring, 0);
 442
 443 }
 444
 445 /**
 446  * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 447  *
 448  * @ring: amdgpu ring pointer
 449  *
 450  * Emit an hdp flush packet on the requested DMA ring.
 451  */
 452 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 453 {
 454         u32 ref_and_mask = 0;
 455
 456         if (ring->me == 0)
 457                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
 458         else
 459                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
 460
 461         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 462                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 463                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 464         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 465         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 466         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 467         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 468         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 469                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 470 }
 471
 472 /**
 473  * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
 474  *
 475  * @ring: amdgpu ring pointer
 476  * @fence: amdgpu fence object
 477  *
 478  * Add a DMA fence packet to the ring to write
 479  * the fence seq number and DMA trap packet to generate
 480  * an interrupt if needed (VI).
 481  */
 482 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 483                                       unsigned flags)
 484 {
 485         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 486         /* write the fence */
 487         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 488         amdgpu_ring_write(ring, lower_32_bits(addr));
 489         amdgpu_ring_write(ring, upper_32_bits(addr));
 490         amdgpu_ring_write(ring, lower_32_bits(seq));
 491
 492         /* optionally write high bits as well */
 493         if (write64bit) {
 494                 addr += 4;
 495                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 496                 amdgpu_ring_write(ring, lower_32_bits(addr));
 497                 amdgpu_ring_write(ring, upper_32_bits(addr));
 498                 amdgpu_ring_write(ring, upper_32_bits(seq));
 499         }
 500
 501         /* generate an interrupt */
 502         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 503         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 504 }
 505
 506 /**
 507  * sdma_v3_0_gfx_stop - stop the gfx async dma engines
 508  *
 509  * @adev: amdgpu_device pointer
 510  *
 511  * Stop the gfx async dma ring buffers (VI).
 512  */
 513 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
 514 {
 515         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 516         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 517         u32 rb_cntl, ib_cntl;
 518         int i;
 519
 520         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 521             (adev->mman.buffer_funcs_ring == sdma1))
 522                 amdgpu_ttm_set_buffer_funcs_status(adev, false);
 523
 524         for (i = 0; i < adev->sdma.num_instances; i++) {
 525                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 526                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 527                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 528                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 529                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 530                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 531         }
 532         sdma0->sched.ready = false;
 533         sdma1->sched.ready = false;
 534 }
 535
 536 /**
 537  * sdma_v3_0_rlc_stop - stop the compute async dma engines
 538  *
 539  * @adev: amdgpu_device pointer
 540  *
 541  * Stop the compute async dma queues (VI).
 542  */
 543 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev)
 544 {
 545         /* XXX todo */
 546 }
 547
 548 /**
 549  * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch
 550  *
 551  * @adev: amdgpu_device pointer
 552  * @enable: enable/disable the DMA MEs context switch.
 553  *
 554  * Halt or unhalt the async dma engines context switch (VI).
 555  */
 556 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 557 {
 558         u32 f32_cntl, phase_quantum = 0;
 559         int i;
 560
 561         if (amdgpu_sdma_phase_quantum) {
 562                 unsigned value = amdgpu_sdma_phase_quantum;
 563                 unsigned unit = 0;
 564
 565                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 566                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 567                         value = (value + 1) >> 1;
 568                         unit++;
 569                 }
 570                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 571                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 572                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 573                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 574                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 575                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 576                         WARN_ONCE(1,
 577                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 578                                   value << unit);
 579                 }
 580                 phase_quantum =
 581                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 582                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 583         }
 584
 585         for (i = 0; i < adev->sdma.num_instances; i++) {
 586                 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
 587                 if (enable) {
 588                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 589                                         AUTO_CTXSW_ENABLE, 1);
 590                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 591                                         ATC_L1_ENABLE, 1);
 592                         if (amdgpu_sdma_phase_quantum) {
 593                                 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],
 594                                        phase_quantum);
 595                                 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],
 596                                        phase_quantum);
 597                         }
 598                 } else {
 599                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 600                                         AUTO_CTXSW_ENABLE, 0);
 601                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 602                                         ATC_L1_ENABLE, 1);
 603                 }
 604
 605                 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
 606         }
 607 }
 608
 609 /**
 610  * sdma_v3_0_enable - stop the async dma engines
 611  *
 612  * @adev: amdgpu_device pointer
 613  * @enable: enable/disable the DMA MEs.
 614  *
 615  * Halt or unhalt the async dma engines (VI).
 616  */
 617 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
 618 {
 619         u32 f32_cntl;
 620         int i;
 621
 622         if (!enable) {
 623                 sdma_v3_0_gfx_stop(adev);
 624                 sdma_v3_0_rlc_stop(adev);
 625         }
 626
 627         for (i = 0; i < adev->sdma.num_instances; i++) {
 628                 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 629                 if (enable)
 630                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
 631                 else
 632                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
 633                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
 634         }
 635 }
 636
 637 /**
 638  * sdma_v3_0_gfx_resume - setup and start the async dma engines
 639  *
 640  * @adev: amdgpu_device pointer
 641  *
 642  * Set up the gfx DMA ring buffers and enable them (VI).
 643  * Returns 0 for success, error for failure.
 644  */
 645 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
 646 {
 647         struct amdgpu_ring *ring;
 648         u32 rb_cntl, ib_cntl, wptr_poll_cntl;
 649         u32 rb_bufsz;
 650         u32 wb_offset;
 651         u32 doorbell;
 652         u64 wptr_gpu_addr;
 653         int i, j, r;
 654
 655         for (i = 0; i < adev->sdma.num_instances; i++) {
 656                 ring = &adev->sdma.instance[i].ring;
 657                 amdgpu_ring_clear_ring(ring);
 658                 wb_offset = (ring->rptr_offs * 4);
 659
 660                 mutex_lock(&adev->srbm_mutex);
 661                 for (j = 0; j < 16; j++) {
 662                         vi_srbm_select(adev, 0, 0, 0, j);
 663                         /* SDMA GFX */
 664                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 665                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 666                 }
 667                 vi_srbm_select(adev, 0, 0, 0, 0);
 668                 mutex_unlock(&adev->srbm_mutex);
 669
 670                 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
 671                        adev->gfx.config.gb_addr_config & 0x70);
 672
 673                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 674
 675                 /* Set ring buffer size in dwords */
 676                 rb_bufsz = order_base_2(ring->ring_size / 4);
 677                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 678                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 679 #ifdef __BIG_ENDIAN
 680                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 681                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 682                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 683 #endif
 684                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 685
 686                 /* Initialize the ring buffer's read and write pointers */
 687                 ring->wptr = 0;
 688                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 689                 sdma_v3_0_ring_set_wptr(ring);
 690                 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
 691                 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
 692
 693                 /* set the wb address whether it's enabled or not */
 694                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 695                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 696                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 697                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 698
 699                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 700
 701                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 702                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 703
 704                 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
 705
 706                 if (ring->use_doorbell) {
 707                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,
 708                                                  OFFSET, ring->doorbell_index);
 709                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 710                 } else {
 711                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 712                 }
 713                 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
 714
 715                 /* setup the wptr shadow polling */
 716                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 717
 718                 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i],
 719                        lower_32_bits(wptr_gpu_addr));
 720                 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i],
 721                        upper_32_bits(wptr_gpu_addr));
 722                 wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]);
 723                 if (ring->use_pollmem) {
 724                         /*wptr polling is not enogh fast, directly clean the wptr register */
 725                         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 726                         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 727                                                        SDMA0_GFX_RB_WPTR_POLL_CNTL,
 728                                                        ENABLE, 1);
 729                 } else {
 730                         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 731                                                        SDMA0_GFX_RB_WPTR_POLL_CNTL,
 732                                                        ENABLE, 0);
 733                 }
 734                 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl);
 735
 736                 /* enable DMA RB */
 737                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 738                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 739
 740                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 741                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 742 #ifdef __BIG_ENDIAN
 743                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 744 #endif
 745                 /* enable DMA IBs */
 746                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 747
 748                 ring->sched.ready = true;
 749         }
 750
 751         /* unhalt the MEs */
 752         sdma_v3_0_enable(adev, true);
 753         /* enable sdma ring preemption */
 754         sdma_v3_0_ctx_switch_enable(adev, true);
 755
 756         for (i = 0; i < adev->sdma.num_instances; i++) {
 757                 ring = &adev->sdma.instance[i].ring;
 758                 r = amdgpu_ring_test_helper(ring);
 759                 if (r)
 760                         return r;
 761
 762                 if (adev->mman.buffer_funcs_ring == ring)
 763                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 764         }
 765
 766         return 0;
 767 }
 768
 769 /**
 770  * sdma_v3_0_rlc_resume - setup and start the async dma engines
 771  *
 772  * @adev: amdgpu_device pointer
 773  *
 774  * Set up the compute DMA queues and enable them (VI).
 775  * Returns 0 for success, error for failure.
 776  */
 777 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev)
 778 {
 779         /* XXX todo */
 780         return 0;
 781 }
 782
 783 /**
 784  * sdma_v3_0_start - setup and start the async dma engines
 785  *
 786  * @adev: amdgpu_device pointer
 787  *
 788  * Set up the DMA engines and enable them (VI).
 789  * Returns 0 for success, error for failure.
 790  */
 791 static int sdma_v3_0_start(struct amdgpu_device *adev)
 792 {
 793         int r;
 794
 795         /* disable sdma engine before programing it */
 796         sdma_v3_0_ctx_switch_enable(adev, false);
 797         sdma_v3_0_enable(adev, false);
 798
 799         /* start the gfx rings and rlc compute queues */
 800         r = sdma_v3_0_gfx_resume(adev);
 801         if (r)
 802                 return r;
 803         r = sdma_v3_0_rlc_resume(adev);
 804         if (r)
 805                 return r;
 806
 807         return 0;
 808 }
 809
 810 /**
 811  * sdma_v3_0_ring_test_ring - simple async dma engine test
 812  *
 813  * @ring: amdgpu_ring structure holding ring information
 814  *
 815  * Test the DMA engine by writing using it to write an
 816  * value to memory. (VI).
 817  * Returns 0 for success, error for failure.
 818  */
 819 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
 820 {
 821         struct amdgpu_device *adev = ring->adev;
 822         unsigned i;
 823         unsigned index;
 824         int r;
 825         u32 tmp;
 826         u64 gpu_addr;
 827
 828         r = amdgpu_device_wb_get(adev, &index);
 829         if (r)
 830                 return r;
 831
 832         gpu_addr = adev->wb.gpu_addr + (index * 4);
 833         tmp = 0xCAFEDEAD;
 834         adev->wb.wb[index] = cpu_to_le32(tmp);
 835
 836         r = amdgpu_ring_alloc(ring, 5);
 837         if (r)
 838                 goto error_free_wb;
 839
 840         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 841                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 842         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 843         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 844         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
 845         amdgpu_ring_write(ring, 0xDEADBEEF);
 846         amdgpu_ring_commit(ring);
 847
 848         for (i = 0; i < adev->usec_timeout; i++) {
 849                 tmp = le32_to_cpu(adev->wb.wb[index]);
 850                 if (tmp == 0xDEADBEEF)
 851                         break;
 852                 udelay(1);
 853         }
 854
 855         if (i >= adev->usec_timeout)
 856                 r = -ETIMEDOUT;
 857
 858 error_free_wb:
 859         amdgpu_device_wb_free(adev, index);
 860         return r;
 861 }
 862
 863 /**
 864  * sdma_v3_0_ring_test_ib - test an IB on the DMA engine
 865  *
 866  * @ring: amdgpu_ring structure holding ring information
 867  *
 868  * Test a simple IB in the DMA ring (VI).
 869  * Returns 0 on success, error on failure.
 870  */
 871 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 872 {
 873         struct amdgpu_device *adev = ring->adev;
 874         struct amdgpu_ib ib;
 875         struct dma_fence *f = NULL;
 876         unsigned index;
 877         u32 tmp = 0;
 878         u64 gpu_addr;
 879         long r;
 880
 881         r = amdgpu_device_wb_get(adev, &index);
 882         if (r)
 883                 return r;
 884
 885         gpu_addr = adev->wb.gpu_addr + (index * 4);
 886         tmp = 0xCAFEDEAD;
 887         adev->wb.wb[index] = cpu_to_le32(tmp);
 888         memset(&ib, 0, sizeof(ib));
 889         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 890         if (r)
 891                 goto err0;
 892
 893         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 894                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 895         ib.ptr[1] = lower_32_bits(gpu_addr);
 896         ib.ptr[2] = upper_32_bits(gpu_addr);
 897         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
 898         ib.ptr[4] = 0xDEADBEEF;
 899         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 900         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 901         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 902         ib.length_dw = 8;
 903
 904         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 905         if (r)
 906                 goto err1;
 907
 908         r = dma_fence_wait_timeout(f, false, timeout);
 909         if (r == 0) {
 910                 r = -ETIMEDOUT;
 911                 goto err1;
 912         } else if (r < 0) {
 913                 goto err1;
 914         }
 915         tmp = le32_to_cpu(adev->wb.wb[index]);
 916         if (tmp == 0xDEADBEEF)
 917                 r = 0;
 918         else
 919                 r = -EINVAL;
 920 err1:
 921         amdgpu_ib_free(adev, &ib, NULL);
 922         dma_fence_put(f);
 923 err0:
 924         amdgpu_device_wb_free(adev, index);
 925         return r;
 926 }
 927
 928 /**
 929  * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART
 930  *
 931  * @ib: indirect buffer to fill with commands
 932  * @pe: addr of the page entry
 933  * @src: src addr to copy from
 934  * @count: number of page entries to update
 935  *
 936  * Update PTEs by copying them from the GART using sDMA (CIK).
 937  */
 938 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
 939                                   uint64_t pe, uint64_t src,
 940                                   unsigned count)
 941 {
 942         unsigned bytes = count * 8;
 943
 944         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
 945                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 946         ib->ptr[ib->length_dw++] = bytes;
 947         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 948         ib->ptr[ib->length_dw++] = lower_32_bits(src);
 949         ib->ptr[ib->length_dw++] = upper_32_bits(src);
 950         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 951         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 952 }
 953
 954 /**
 955  * sdma_v3_0_vm_write_pte - update PTEs by writing them manually
 956  *
 957  * @ib: indirect buffer to fill with commands
 958  * @pe: addr of the page entry
 959  * @value: dst addr to write into pe
 960  * @count: number of page entries to update
 961  * @incr: increase next addr by incr bytes
 962  *
 963  * Update PTEs by writing them manually using sDMA (CIK).
 964  */
 965 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
 966                                    uint64_t value, unsigned count,
 967                                    uint32_t incr)
 968 {
 969         unsigned ndw = count * 2;
 970
 971         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 972                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 973         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 974         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 975         ib->ptr[ib->length_dw++] = ndw;
 976         for (; ndw > 0; ndw -= 2) {
 977                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
 978                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 979                 value += incr;
 980         }
 981 }
 982
 983 /**
 984  * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA
 985  *
 986  * @ib: indirect buffer to fill with commands
 987  * @pe: addr of the page entry
 988  * @addr: dst addr to write into pe
 989  * @count: number of page entries to update
 990  * @incr: increase next addr by incr bytes
 991  * @flags: access flags
 992  *
 993  * Update the page tables using sDMA (CIK).
 994  */
 995 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
 996                                      uint64_t addr, unsigned count,
 997                                      uint32_t incr, uint64_t flags)
 998 {
 999         /* for physically contiguous pages (vram) */
1000         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
1001         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1002         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1003         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1004         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1005         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1006         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1007         ib->ptr[ib->length_dw++] = incr; /* increment size */
1008         ib->ptr[ib->length_dw++] = 0;
1009         ib->ptr[ib->length_dw++] = count; /* number of entries */
1010 }
1011
1012 /**
1013  * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw
1014  *
1015  * @ib: indirect buffer to fill with padding
1016  *
1017  */
1018 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1019 {
1020         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1021         u32 pad_count;
1022         int i;
1023
1024         pad_count = (-ib->length_dw) & 7;
1025         for (i = 0; i < pad_count; i++)
1026                 if (sdma && sdma->burst_nop && (i == 0))
1027                         ib->ptr[ib->length_dw++] =
1028                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1029                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1030                 else
1031                         ib->ptr[ib->length_dw++] =
1032                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1033 }
1034
1035 /**
1036  * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline
1037  *
1038  * @ring: amdgpu_ring pointer
1039  *
1040  * Make sure all previous operations are completed (CIK).
1041  */
1042 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1043 {
1044         uint32_t seq = ring->fence_drv.sync_seq;
1045         uint64_t addr = ring->fence_drv.gpu_addr;
1046
1047         /* wait for idle */
1048         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1049                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1050                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1051                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1052         amdgpu_ring_write(ring, addr & 0xfffffffc);
1053         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1054         amdgpu_ring_write(ring, seq); /* reference */
1055         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1056         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1057                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1058 }
1059
1060 /**
1061  * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
1062  *
1063  * @ring: amdgpu_ring pointer
1064  * @vm: amdgpu_vm pointer
1065  *
1066  * Update the page table base and flush the VM TLB
1067  * using sDMA (VI).
1068  */
1069 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1070                                          unsigned vmid, uint64_t pd_addr)
1071 {
1072         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1073
1074         /* wait for flush */
1075         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1076                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1077                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
1078         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1079         amdgpu_ring_write(ring, 0);
1080         amdgpu_ring_write(ring, 0); /* reference */
1081         amdgpu_ring_write(ring, 0); /* mask */
1082         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1083                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
1084 }
1085
1086 static void sdma_v3_0_ring_emit_wreg(struct amdgpu_ring *ring,
1087                                      uint32_t reg, uint32_t val)
1088 {
1089         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1090                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1091         amdgpu_ring_write(ring, reg);
1092         amdgpu_ring_write(ring, val);
1093 }
1094
1095 static int sdma_v3_0_early_init(void *handle)
1096 {
1097         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1098
1099         switch (adev->asic_type) {
1100         case CHIP_STONEY:
1101                 adev->sdma.num_instances = 1;
1102                 break;
1103         default:
1104                 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
1105                 break;
1106         }
1107
1108         sdma_v3_0_set_ring_funcs(adev);
1109         sdma_v3_0_set_buffer_funcs(adev);
1110         sdma_v3_0_set_vm_pte_funcs(adev);
1111         sdma_v3_0_set_irq_funcs(adev);
1112
1113         return 0;
1114 }
1115
1116 static int sdma_v3_0_sw_init(void *handle)
1117 {
1118         struct amdgpu_ring *ring;
1119         int r, i;
1120         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1121
1122         /* SDMA trap event */
1123         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP,
1124                               &adev->sdma.trap_irq);
1125         if (r)
1126                 return r;
1127
1128         /* SDMA Privileged inst */
1129         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241,
1130                               &adev->sdma.illegal_inst_irq);
1131         if (r)
1132                 return r;
1133
1134         /* SDMA Privileged inst */
1135         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE,
1136                               &adev->sdma.illegal_inst_irq);
1137         if (r)
1138                 return r;
1139
1140         r = sdma_v3_0_init_microcode(adev);
1141         if (r) {
1142                 DRM_ERROR("Failed to load sdma firmware!\n");
1143                 return r;
1144         }
1145
1146         for (i = 0; i < adev->sdma.num_instances; i++) {
1147                 ring = &adev->sdma.instance[i].ring;
1148                 ring->ring_obj = NULL;
1149                 if (!amdgpu_sriov_vf(adev)) {
1150                         ring->use_doorbell = true;
1151                         ring->doorbell_index = adev->doorbell_index.sdma_engine[i];
1152                 } else {
1153                         ring->use_pollmem = true;
1154                 }
1155
1156                 sprintf(ring->name, "sdma%d", i);
1157                 r = amdgpu_ring_init(adev, ring, 1024,
1158                                      &adev->sdma.trap_irq,
1159                                      (i == 0) ?
1160                                      AMDGPU_SDMA_IRQ_INSTANCE0 :
1161                                      AMDGPU_SDMA_IRQ_INSTANCE1);
1162                 if (r)
1163                         return r;
1164         }
1165
1166         return r;
1167 }
1168
1169 static int sdma_v3_0_sw_fini(void *handle)
1170 {
1171         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1172         int i;
1173
1174         for (i = 0; i < adev->sdma.num_instances; i++)
1175                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1176
1177         sdma_v3_0_free_microcode(adev);
1178         return 0;
1179 }
1180
1181 static int sdma_v3_0_hw_init(void *handle)
1182 {
1183         int r;
1184         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1185
1186         sdma_v3_0_init_golden_registers(adev);
1187
1188         r = sdma_v3_0_start(adev);
1189         if (r)
1190                 return r;
1191
1192         return r;
1193 }
1194
1195 static int sdma_v3_0_hw_fini(void *handle)
1196 {
1197         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1198
1199         sdma_v3_0_ctx_switch_enable(adev, false);
1200         sdma_v3_0_enable(adev, false);
1201
1202         return 0;
1203 }
1204
1205 static int sdma_v3_0_suspend(void *handle)
1206 {
1207         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1208
1209         return sdma_v3_0_hw_fini(adev);
1210 }
1211
1212 static int sdma_v3_0_resume(void *handle)
1213 {
1214         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1215
1216         return sdma_v3_0_hw_init(adev);
1217 }
1218
1219 static bool sdma_v3_0_is_idle(void *handle)
1220 {
1221         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1222         u32 tmp = RREG32(mmSRBM_STATUS2);
1223
1224         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1225                    SRBM_STATUS2__SDMA1_BUSY_MASK))
1226             return false;
1227
1228         return true;
1229 }
1230
1231 static int sdma_v3_0_wait_for_idle(void *handle)
1232 {
1233         unsigned i;
1234         u32 tmp;
1235         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1236
1237         for (i = 0; i < adev->usec_timeout; i++) {
1238                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1239                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1240
1241                 if (!tmp)
1242                         return 0;
1243                 udelay(1);
1244         }
1245         return -ETIMEDOUT;
1246 }
1247
1248 static bool sdma_v3_0_check_soft_reset(void *handle)
1249 {
1250         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1251         u32 srbm_soft_reset = 0;
1252         u32 tmp = RREG32(mmSRBM_STATUS2);
1253
1254         if ((tmp & SRBM_STATUS2__SDMA_BUSY_MASK) ||
1255             (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)) {
1256                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1257                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1258         }
1259
1260         if (srbm_soft_reset) {
1261                 adev->sdma.srbm_soft_reset = srbm_soft_reset;
1262                 return true;
1263         } else {
1264                 adev->sdma.srbm_soft_reset = 0;
1265                 return false;
1266         }
1267 }
1268
1269 static int sdma_v3_0_pre_soft_reset(void *handle)
1270 {
1271         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1272         u32 srbm_soft_reset = 0;
1273
1274         if (!adev->sdma.srbm_soft_reset)
1275                 return 0;
1276
1277         srbm_soft_reset = adev->sdma.srbm_soft_reset;
1278
1279         if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1280             REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1281                 sdma_v3_0_ctx_switch_enable(adev, false);
1282                 sdma_v3_0_enable(adev, false);
1283         }
1284
1285         return 0;
1286 }
1287
1288 static int sdma_v3_0_post_soft_reset(void *handle)
1289 {
1290         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1291         u32 srbm_soft_reset = 0;
1292
1293         if (!adev->sdma.srbm_soft_reset)
1294                 return 0;
1295
1296         srbm_soft_reset = adev->sdma.srbm_soft_reset;
1297
1298         if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1299             REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1300                 sdma_v3_0_gfx_resume(adev);
1301                 sdma_v3_0_rlc_resume(adev);
1302         }
1303
1304         return 0;
1305 }
1306
1307 static int sdma_v3_0_soft_reset(void *handle)
1308 {
1309         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1310         u32 srbm_soft_reset = 0;
1311         u32 tmp;
1312
1313         if (!adev->sdma.srbm_soft_reset)
1314                 return 0;
1315
1316         srbm_soft_reset = adev->sdma.srbm_soft_reset;
1317
1318         if (srbm_soft_reset) {
1319                 tmp = RREG32(mmSRBM_SOFT_RESET);
1320                 tmp |= srbm_soft_reset;
1321                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1322                 WREG32(mmSRBM_SOFT_RESET, tmp);
1323                 tmp = RREG32(mmSRBM_SOFT_RESET);
1324
1325                 udelay(50);
1326
1327                 tmp &= ~srbm_soft_reset;
1328                 WREG32(mmSRBM_SOFT_RESET, tmp);
1329                 tmp = RREG32(mmSRBM_SOFT_RESET);
1330
1331                 /* Wait a little for things to settle down */
1332                 udelay(50);
1333         }
1334
1335         return 0;
1336 }
1337
1338 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev,
1339                                         struct amdgpu_irq_src *source,
1340                                         unsigned type,
1341                                         enum amdgpu_interrupt_state state)
1342 {
1343         u32 sdma_cntl;
1344
1345         switch (type) {
1346         case AMDGPU_SDMA_IRQ_INSTANCE0:
1347                 switch (state) {
1348                 case AMDGPU_IRQ_STATE_DISABLE:
1349                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1350                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1351                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1352                         break;
1353                 case AMDGPU_IRQ_STATE_ENABLE:
1354                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1355                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1356                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1357                         break;
1358                 default:
1359                         break;
1360                 }
1361                 break;
1362         case AMDGPU_SDMA_IRQ_INSTANCE1:
1363                 switch (state) {
1364                 case AMDGPU_IRQ_STATE_DISABLE:
1365                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1366                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1367                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1368                         break;
1369                 case AMDGPU_IRQ_STATE_ENABLE:
1370                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1371                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1372                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1373                         break;
1374                 default:
1375                         break;
1376                 }
1377                 break;
1378         default:
1379                 break;
1380         }
1381         return 0;
1382 }
1383
1384 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev,
1385                                       struct amdgpu_irq_src *source,
1386                                       struct amdgpu_iv_entry *entry)
1387 {
1388         u8 instance_id, queue_id;
1389
1390         instance_id = (entry->ring_id & 0x3) >> 0;
1391         queue_id = (entry->ring_id & 0xc) >> 2;
1392         DRM_DEBUG("IH: SDMA trap\n");
1393         switch (instance_id) {
1394         case 0:
1395                 switch (queue_id) {
1396                 case 0:
1397                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1398                         break;
1399                 case 1:
1400                         /* XXX compute */
1401                         break;
1402                 case 2:
1403                         /* XXX compute */
1404                         break;
1405                 }
1406                 break;
1407         case 1:
1408                 switch (queue_id) {
1409                 case 0:
1410                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1411                         break;
1412                 case 1:
1413                         /* XXX compute */
1414                         break;
1415                 case 2:
1416                         /* XXX compute */
1417                         break;
1418                 }
1419                 break;
1420         }
1421         return 0;
1422 }
1423
1424 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1425                                               struct amdgpu_irq_src *source,
1426                                               struct amdgpu_iv_entry *entry)
1427 {
1428         u8 instance_id, queue_id;
1429
1430         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1431         instance_id = (entry->ring_id & 0x3) >> 0;
1432         queue_id = (entry->ring_id & 0xc) >> 2;
1433
1434         if (instance_id <= 1 && queue_id == 0)
1435                 drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched);
1436         return 0;
1437 }
1438
1439 static void sdma_v3_0_update_sdma_medium_grain_clock_gating(
1440                 struct amdgpu_device *adev,
1441                 bool enable)
1442 {
1443         uint32_t temp, data;
1444         int i;
1445
1446         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1447                 for (i = 0; i < adev->sdma.num_instances; i++) {
1448                         temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1449                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1450                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1451                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1452                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1453                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1454                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1455                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1456                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1457                         if (data != temp)
1458                                 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1459                 }
1460         } else {
1461                 for (i = 0; i < adev->sdma.num_instances; i++) {
1462                         temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1463                         data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1464                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1465                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1466                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1467                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1468                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1469                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1470                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK;
1471
1472                         if (data != temp)
1473                                 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1474                 }
1475         }
1476 }
1477
1478 static void sdma_v3_0_update_sdma_medium_grain_light_sleep(
1479                 struct amdgpu_device *adev,
1480                 bool enable)
1481 {
1482         uint32_t temp, data;
1483         int i;
1484
1485         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1486                 for (i = 0; i < adev->sdma.num_instances; i++) {
1487                         temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1488                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1489
1490                         if (temp != data)
1491                                 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1492                 }
1493         } else {
1494                 for (i = 0; i < adev->sdma.num_instances; i++) {
1495                         temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1496                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1497
1498                         if (temp != data)
1499                                 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1500                 }
1501         }
1502 }
1503
1504 static int sdma_v3_0_set_clockgating_state(void *handle,
1505                                           enum amd_clockgating_state state)
1506 {
1507         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1508
1509         if (amdgpu_sriov_vf(adev))
1510                 return 0;
1511
1512         switch (adev->asic_type) {
1513         case CHIP_FIJI:
1514         case CHIP_CARRIZO:
1515         case CHIP_STONEY:
1516                 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev,
1517                                 state == AMD_CG_STATE_GATE);
1518                 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev,
1519                                 state == AMD_CG_STATE_GATE);
1520                 break;
1521         default:
1522                 break;
1523         }
1524         return 0;
1525 }
1526
1527 static int sdma_v3_0_set_powergating_state(void *handle,
1528                                           enum amd_powergating_state state)
1529 {
1530         return 0;
1531 }
1532
1533 static void sdma_v3_0_get_clockgating_state(void *handle, u32 *flags)
1534 {
1535         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1536         int data;
1537
1538         if (amdgpu_sriov_vf(adev))
1539                 *flags = 0;
1540
1541         /* AMD_CG_SUPPORT_SDMA_MGCG */
1542         data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]);
1543         if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK))
1544                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1545
1546         /* AMD_CG_SUPPORT_SDMA_LS */
1547         data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]);
1548         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1549                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1550 }
1551
1552 static const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
1553         .name = "sdma_v3_0",
1554         .early_init = sdma_v3_0_early_init,
1555         .late_init = NULL,
1556         .sw_init = sdma_v3_0_sw_init,
1557         .sw_fini = sdma_v3_0_sw_fini,
1558         .hw_init = sdma_v3_0_hw_init,
1559         .hw_fini = sdma_v3_0_hw_fini,
1560         .suspend = sdma_v3_0_suspend,
1561         .resume = sdma_v3_0_resume,
1562         .is_idle = sdma_v3_0_is_idle,
1563         .wait_for_idle = sdma_v3_0_wait_for_idle,
1564         .check_soft_reset = sdma_v3_0_check_soft_reset,
1565         .pre_soft_reset = sdma_v3_0_pre_soft_reset,
1566         .post_soft_reset = sdma_v3_0_post_soft_reset,
1567         .soft_reset = sdma_v3_0_soft_reset,
1568         .set_clockgating_state = sdma_v3_0_set_clockgating_state,
1569         .set_powergating_state = sdma_v3_0_set_powergating_state,
1570         .get_clockgating_state = sdma_v3_0_get_clockgating_state,
1571 };
1572
1573 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
1574         .type = AMDGPU_RING_TYPE_SDMA,
1575         .align_mask = 0xf,
1576         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1577         .support_64bit_ptrs = false,
1578         .get_rptr = sdma_v3_0_ring_get_rptr,
1579         .get_wptr = sdma_v3_0_ring_get_wptr,
1580         .set_wptr = sdma_v3_0_ring_set_wptr,
1581         .emit_frame_size =
1582                 6 + /* sdma_v3_0_ring_emit_hdp_flush */
1583                 3 + /* hdp invalidate */
1584                 6 + /* sdma_v3_0_ring_emit_pipeline_sync */
1585                 VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v3_0_ring_emit_vm_flush */
1586                 10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */
1587         .emit_ib_size = 7 + 6, /* sdma_v3_0_ring_emit_ib */
1588         .emit_ib = sdma_v3_0_ring_emit_ib,
1589         .emit_fence = sdma_v3_0_ring_emit_fence,
1590         .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync,
1591         .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
1592         .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
1593         .test_ring = sdma_v3_0_ring_test_ring,
1594         .test_ib = sdma_v3_0_ring_test_ib,
1595         .insert_nop = sdma_v3_0_ring_insert_nop,
1596         .pad_ib = sdma_v3_0_ring_pad_ib,
1597         .emit_wreg = sdma_v3_0_ring_emit_wreg,
1598 };
1599
1600 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
1601 {
1602         int i;
1603
1604         for (i = 0; i < adev->sdma.num_instances; i++) {
1605                 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;
1606                 adev->sdma.instance[i].ring.me = i;
1607         }
1608 }
1609
1610 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
1611         .set = sdma_v3_0_set_trap_irq_state,
1612         .process = sdma_v3_0_process_trap_irq,
1613 };
1614
1615 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = {
1616         .process = sdma_v3_0_process_illegal_inst_irq,
1617 };
1618
1619 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
1620 {
1621         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1622         adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;
1623         adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;
1624 }
1625
1626 /**
1627  * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine
1628  *
1629  * @ring: amdgpu_ring structure holding ring information
1630  * @src_offset: src GPU address
1631  * @dst_offset: dst GPU address
1632  * @byte_count: number of bytes to xfer
1633  *
1634  * Copy GPU buffers using the DMA engine (VI).
1635  * Used by the amdgpu ttm implementation to move pages if
1636  * registered as the asic copy callback.
1637  */
1638 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib,
1639                                        uint64_t src_offset,
1640                                        uint64_t dst_offset,
1641                                        uint32_t byte_count)
1642 {
1643         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1644                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1645         ib->ptr[ib->length_dw++] = byte_count;
1646         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1647         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1648         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1649         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1650         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1651 }
1652
1653 /**
1654  * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine
1655  *
1656  * @ring: amdgpu_ring structure holding ring information
1657  * @src_data: value to write to buffer
1658  * @dst_offset: dst GPU address
1659  * @byte_count: number of bytes to xfer
1660  *
1661  * Fill GPU buffers using the DMA engine (VI).
1662  */
1663 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib,
1664                                        uint32_t src_data,
1665                                        uint64_t dst_offset,
1666                                        uint32_t byte_count)
1667 {
1668         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1669         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1670         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1671         ib->ptr[ib->length_dw++] = src_data;
1672         ib->ptr[ib->length_dw++] = byte_count;
1673 }
1674
1675 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
1676         .copy_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */
1677         .copy_num_dw = 7,
1678         .emit_copy_buffer = sdma_v3_0_emit_copy_buffer,
1679
1680         .fill_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */
1681         .fill_num_dw = 5,
1682         .emit_fill_buffer = sdma_v3_0_emit_fill_buffer,
1683 };
1684
1685 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
1686 {
1687         adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
1688         adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1689 }
1690
1691 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
1692         .copy_pte_num_dw = 7,
1693         .copy_pte = sdma_v3_0_vm_copy_pte,
1694
1695         .write_pte = sdma_v3_0_vm_write_pte,
1696         .set_pte_pde = sdma_v3_0_vm_set_pte_pde,
1697 };
1698
1699 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1700 {
1701         unsigned i;
1702
1703         adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
1704         for (i = 0; i < adev->sdma.num_instances; i++) {
1705                 adev->vm_manager.vm_pte_scheds[i] =
1706                          &adev->sdma.instance[i].ring.sched;
1707         }
1708         adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1709 }
1710
1711 const struct amdgpu_ip_block_version sdma_v3_0_ip_block =
1712 {
1713         .type = AMD_IP_BLOCK_TYPE_SDMA,
1714         .major = 3,
1715         .minor = 0,
1716         .rev = 0,
1717         .funcs = &sdma_v3_0_ip_funcs,
1718 };
1719
1720 const struct amdgpu_ip_block_version sdma_v3_1_ip_block =
1721 {
1722         .type = AMD_IP_BLOCK_TYPE_SDMA,
1723         .major = 3,
1724         .minor = 1,
1725         .rev = 0,
1726         .funcs = &sdma_v3_0_ip_funcs,
1727 };