drivers/gpu/drm/amd/amdgpu/psp_v14_0.c

   1 /*
   2  * Copyright 2023 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <drm/drm_drv.h>
  24 #include <linux/vmalloc.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_psp.h"
  27 #include "amdgpu_ucode.h"
  28 #include "soc15_common.h"
  29 #include "psp_v14_0.h"
  30
  31 #include "mp/mp_14_0_2_offset.h"
  32 #include "mp/mp_14_0_2_sh_mask.h"
  33
  34 MODULE_FIRMWARE("amdgpu/psp_14_0_2_sos.bin");
  35 MODULE_FIRMWARE("amdgpu/psp_14_0_3_sos.bin");
  36
  37 /* For large FW files the time to complete can be very long */
  38 #define USBC_PD_POLLING_LIMIT_S 240
  39
  40 /* Read USB-PD from LFB */
  41 #define GFX_CMD_USB_PD_USE_LFB 0x480
  42
  43 /* VBIOS gfl defines */
  44 #define MBOX_READY_MASK 0x80000000
  45 #define MBOX_STATUS_MASK 0x0000FFFF
  46 #define MBOX_COMMAND_MASK 0x00FF0000
  47 #define MBOX_READY_FLAG 0x80000000
  48 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2
  49 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3
  50 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4
  51
  52 /* memory training timeout define */
  53 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US   3000000
  54
  55 static int psp_v14_0_init_microcode(struct psp_context *psp)
  56 {
  57         struct amdgpu_device *adev = psp->adev;
  58         char ucode_prefix[30];
  59         int err = 0;
  60
  61         amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
  62
  63         switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
  64         case IP_VERSION(14, 0, 2):
  65         case IP_VERSION(14, 0, 3):
  66                 err = psp_init_sos_microcode(psp, ucode_prefix);
  67                 if (err)
  68                         return err;
  69                 break;
  70         default:
  71                 BUG();
  72         }
  73
  74         return 0;
  75 }
  76
  77 static bool psp_v14_0_is_sos_alive(struct psp_context *psp)
  78 {
  79         struct amdgpu_device *adev = psp->adev;
  80         uint32_t sol_reg;
  81
  82         sol_reg = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81);
  83
  84         return sol_reg != 0x0;
  85 }
  86
  87 static int psp_v14_0_wait_for_bootloader(struct psp_context *psp)
  88 {
  89         struct amdgpu_device *adev = psp->adev;
  90
  91         int ret;
  92         int retry_loop;
  93
  94         for (retry_loop = 0; retry_loop < 10; retry_loop++) {
  95                 /* Wait for bootloader to signify that is
  96                     ready having bit 31 of C2PMSG_35 set to 1 */
  97                 ret = psp_wait_for(psp,
  98                                    SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35),
  99                                    0x80000000,
 100                                    0x80000000,
 101                                    false);
 102
 103                 if (ret == 0)
 104                         return 0;
 105         }
 106
 107         return ret;
 108 }
 109
 110 static int psp_v14_0_bootloader_load_component(struct psp_context       *psp,
 111                                                struct psp_bin_desc      *bin_desc,
 112                                                enum psp_bootloader_cmd  bl_cmd)
 113 {
 114         int ret;
 115         uint32_t psp_gfxdrv_command_reg = 0;
 116         struct amdgpu_device *adev = psp->adev;
 117
 118         /* Check tOS sign of life register to confirm sys driver and sOS
 119          * are already been loaded.
 120          */
 121         if (psp_v14_0_is_sos_alive(psp))
 122                 return 0;
 123
 124         ret = psp_v14_0_wait_for_bootloader(psp);
 125         if (ret)
 126                 return ret;
 127
 128         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 129
 130         /* Copy PSP KDB binary to memory */
 131         memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes);
 132
 133         /* Provide the PSP KDB to bootloader */
 134         WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36,
 135                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 136         psp_gfxdrv_command_reg = bl_cmd;
 137         WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35,
 138                psp_gfxdrv_command_reg);
 139
 140         ret = psp_v14_0_wait_for_bootloader(psp);
 141
 142         return ret;
 143 }
 144
 145 static int psp_v14_0_bootloader_load_kdb(struct psp_context *psp)
 146 {
 147         return psp_v14_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
 148 }
 149
 150 static int psp_v14_0_bootloader_load_spl(struct psp_context *psp)
 151 {
 152         return psp_v14_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE);
 153 }
 154
 155 static int psp_v14_0_bootloader_load_sysdrv(struct psp_context *psp)
 156 {
 157         return psp_v14_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
 158 }
 159
 160 static int psp_v14_0_bootloader_load_soc_drv(struct psp_context *psp)
 161 {
 162         return psp_v14_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV);
 163 }
 164
 165 static int psp_v14_0_bootloader_load_intf_drv(struct psp_context *psp)
 166 {
 167         return psp_v14_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV);
 168 }
 169
 170 static int psp_v14_0_bootloader_load_dbg_drv(struct psp_context *psp)
 171 {
 172         return psp_v14_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV);
 173 }
 174
 175 static int psp_v14_0_bootloader_load_ras_drv(struct psp_context *psp)
 176 {
 177         return psp_v14_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV);
 178 }
 179
 180
 181 static int psp_v14_0_bootloader_load_sos(struct psp_context *psp)
 182 {
 183         int ret;
 184         unsigned int psp_gfxdrv_command_reg = 0;
 185         struct amdgpu_device *adev = psp->adev;
 186
 187         /* Check sOS sign of life register to confirm sys driver and sOS
 188          * are already been loaded.
 189          */
 190         if (psp_v14_0_is_sos_alive(psp))
 191                 return 0;
 192
 193         ret = psp_v14_0_wait_for_bootloader(psp);
 194         if (ret)
 195                 return ret;
 196
 197         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 198
 199         /* Copy Secure OS binary to PSP memory */
 200         memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes);
 201
 202         /* Provide the PSP secure OS to bootloader */
 203         WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36,
 204                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 205         psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
 206         WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35,
 207                psp_gfxdrv_command_reg);
 208
 209         /* there might be handshake issue with hardware which needs delay */
 210         mdelay(20);
 211         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_81),
 212                            RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81),
 213                            0, true);
 214
 215         return ret;
 216 }
 217
 218 static int psp_v14_0_ring_stop(struct psp_context *psp,
 219                                enum psp_ring_type ring_type)
 220 {
 221         int ret = 0;
 222         struct amdgpu_device *adev = psp->adev;
 223
 224         if (amdgpu_sriov_vf(adev)) {
 225                 /* Write the ring destroy command*/
 226                 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101,
 227                              GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
 228                 /* there might be handshake issue with hardware which needs delay */
 229                 mdelay(20);
 230                 /* Wait for response flag (bit 31) */
 231                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101),
 232                                    0x80000000, 0x80000000, false);
 233         } else {
 234                 /* Write the ring destroy command*/
 235                 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64,
 236                              GFX_CTRL_CMD_ID_DESTROY_RINGS);
 237                 /* there might be handshake issue with hardware which needs delay */
 238                 mdelay(20);
 239                 /* Wait for response flag (bit 31) */
 240                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
 241                                    0x80000000, 0x80000000, false);
 242         }
 243
 244         return ret;
 245 }
 246
 247 static int psp_v14_0_ring_create(struct psp_context *psp,
 248                                  enum psp_ring_type ring_type)
 249 {
 250         int ret = 0;
 251         unsigned int psp_ring_reg = 0;
 252         struct psp_ring *ring = &psp->km_ring;
 253         struct amdgpu_device *adev = psp->adev;
 254
 255         if (amdgpu_sriov_vf(adev)) {
 256                 ret = psp_v14_0_ring_stop(psp, ring_type);
 257                 if (ret) {
 258                         DRM_ERROR("psp_v14_0_ring_stop_sriov failed!\n");
 259                         return ret;
 260                 }
 261
 262                 /* Write low address of the ring to C2PMSG_102 */
 263                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 264                 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102, psp_ring_reg);
 265                 /* Write high address of the ring to C2PMSG_103 */
 266                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 267                 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_103, psp_ring_reg);
 268
 269                 /* Write the ring initialization command to C2PMSG_101 */
 270                 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101,
 271                              GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
 272
 273                 /* there might be handshake issue with hardware which needs delay */
 274                 mdelay(20);
 275
 276                 /* Wait for response flag (bit 31) in C2PMSG_101 */
 277                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101),
 278                                    0x80000000, 0x8000FFFF, false);
 279
 280         } else {
 281                 /* Wait for sOS ready for ring creation */
 282                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
 283                                    0x80000000, 0x80000000, false);
 284                 if (ret) {
 285                         DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
 286                         return ret;
 287                 }
 288
 289                 /* Write low address of the ring to C2PMSG_69 */
 290                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 291                 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_69, psp_ring_reg);
 292                 /* Write high address of the ring to C2PMSG_70 */
 293                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 294                 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_70, psp_ring_reg);
 295                 /* Write size of ring to C2PMSG_71 */
 296                 psp_ring_reg = ring->ring_size;
 297                 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_71, psp_ring_reg);
 298                 /* Write the ring initialization command to C2PMSG_64 */
 299                 psp_ring_reg = ring_type;
 300                 psp_ring_reg = psp_ring_reg << 16;
 301                 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64, psp_ring_reg);
 302
 303                 /* there might be handshake issue with hardware which needs delay */
 304                 mdelay(20);
 305
 306                 /* Wait for response flag (bit 31) in C2PMSG_64 */
 307                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
 308                                    0x80000000, 0x8000FFFF, false);
 309         }
 310
 311         return ret;
 312 }
 313
 314 static int psp_v14_0_ring_destroy(struct psp_context *psp,
 315                                   enum psp_ring_type ring_type)
 316 {
 317         int ret = 0;
 318         struct psp_ring *ring = &psp->km_ring;
 319         struct amdgpu_device *adev = psp->adev;
 320
 321         ret = psp_v14_0_ring_stop(psp, ring_type);
 322         if (ret)
 323                 DRM_ERROR("Fail to stop psp ring\n");
 324
 325         amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 326                               &ring->ring_mem_mc_addr,
 327                               (void **)&ring->ring_mem);
 328
 329         return ret;
 330 }
 331
 332 static uint32_t psp_v14_0_ring_get_wptr(struct psp_context *psp)
 333 {
 334         uint32_t data;
 335         struct amdgpu_device *adev = psp->adev;
 336
 337         if (amdgpu_sriov_vf(adev))
 338                 data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102);
 339         else
 340                 data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67);
 341
 342         return data;
 343 }
 344
 345 static void psp_v14_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
 346 {
 347         struct amdgpu_device *adev = psp->adev;
 348
 349         if (amdgpu_sriov_vf(adev)) {
 350                 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102, value);
 351                 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101,
 352                              GFX_CTRL_CMD_ID_CONSUME_CMD);
 353         } else
 354                 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67, value);
 355 }
 356
 357 static int psp_v14_0_memory_training_send_msg(struct psp_context *psp, int msg)
 358 {
 359         int ret;
 360         int i;
 361         uint32_t data_32;
 362         int max_wait;
 363         struct amdgpu_device *adev = psp->adev;
 364
 365         data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
 366         WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36, data_32);
 367         WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35, msg);
 368
 369         max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
 370         for (i = 0; i < max_wait; i++) {
 371                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35),
 372                                    0x80000000, 0x80000000, false);
 373                 if (ret == 0)
 374                         break;
 375         }
 376         if (i < max_wait)
 377                 ret = 0;
 378         else
 379                 ret = -ETIME;
 380
 381         dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n",
 382                   (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
 383                   (ret == 0) ? "succeed" : "failed",
 384                   i, adev->usec_timeout/1000);
 385         return ret;
 386 }
 387
 388
 389 static int psp_v14_0_memory_training(struct psp_context *psp, uint32_t ops)
 390 {
 391         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 392         uint32_t *pcache = (uint32_t *)ctx->sys_cache;
 393         struct amdgpu_device *adev = psp->adev;
 394         uint32_t p2c_header[4];
 395         uint32_t sz;
 396         void *buf;
 397         int ret, idx;
 398
 399         if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
 400                 dev_dbg(adev->dev, "Memory training is not supported.\n");
 401                 return 0;
 402         } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
 403                 dev_err(adev->dev, "Memory training initialization failure.\n");
 404                 return -EINVAL;
 405         }
 406
 407         if (psp_v14_0_is_sos_alive(psp)) {
 408                 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n");
 409                 return 0;
 410         }
 411
 412         amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
 413         dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
 414                   pcache[0], pcache[1], pcache[2], pcache[3],
 415                   p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
 416
 417         if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
 418                 dev_dbg(adev->dev, "Short training depends on restore.\n");
 419                 ops |= PSP_MEM_TRAIN_RESTORE;
 420         }
 421
 422         if ((ops & PSP_MEM_TRAIN_RESTORE) &&
 423             pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
 424                 dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n");
 425                 ops |= PSP_MEM_TRAIN_SAVE;
 426         }
 427
 428         if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
 429             !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
 430               pcache[3] == p2c_header[3])) {
 431                 dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
 432                 ops |= PSP_MEM_TRAIN_SAVE;
 433         }
 434
 435         if ((ops & PSP_MEM_TRAIN_SAVE) &&
 436             p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
 437                 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n");
 438                 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
 439         }
 440
 441         if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
 442                 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
 443                 ops |= PSP_MEM_TRAIN_SAVE;
 444         }
 445
 446         dev_dbg(adev->dev, "Memory training ops:%x.\n", ops);
 447
 448         if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
 449                 /*
 450                  * Long training will encroach a certain amount on the bottom of VRAM;
 451                  * save the content from the bottom of VRAM to system memory
 452                  * before training, and restore it after training to avoid
 453                  * VRAM corruption.
 454                  */
 455                 sz = BIST_MEM_TRAINING_ENCROACHED_SIZE;
 456
 457                 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) {
 458                         dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n",
 459                                   adev->gmc.visible_vram_size,
 460                                   adev->mman.aper_base_kaddr);
 461                         return -EINVAL;
 462                 }
 463
 464                 buf = vmalloc(sz);
 465                 if (!buf) {
 466                         dev_err(adev->dev, "failed to allocate system memory.\n");
 467                         return -ENOMEM;
 468                 }
 469
 470                 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
 471                         memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);
 472                         ret = psp_v14_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
 473                         if (ret) {
 474                                 DRM_ERROR("Send long training msg failed.\n");
 475                                 vfree(buf);
 476                                 drm_dev_exit(idx);
 477                                 return ret;
 478                         }
 479
 480                         memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
 481                         adev->hdp.funcs->flush_hdp(adev, NULL);
 482                         vfree(buf);
 483                         drm_dev_exit(idx);
 484                 } else {
 485                         vfree(buf);
 486                         return -ENODEV;
 487                 }
 488         }
 489
 490         if (ops & PSP_MEM_TRAIN_SAVE) {
 491                 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
 492         }
 493
 494         if (ops & PSP_MEM_TRAIN_RESTORE) {
 495                 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
 496         }
 497
 498         if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
 499                 ret = psp_v14_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
 500                                                          PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
 501                 if (ret) {
 502                         dev_err(adev->dev, "send training msg failed.\n");
 503                         return ret;
 504                 }
 505         }
 506         ctx->training_cnt++;
 507         return 0;
 508 }
 509
 510 static int psp_v14_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr)
 511 {
 512         struct amdgpu_device *adev = psp->adev;
 513         uint32_t reg_status;
 514         int ret, i = 0;
 515
 516         /*
 517          * LFB address which is aligned to 1MB address and has to be
 518          * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P
 519          * register
 520          */
 521         WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));
 522
 523         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35),
 524                              0x80000000, 0x80000000, false);
 525         if (ret)
 526                 return ret;
 527
 528         /* Fireup interrupt so PSP can pick up the address */
 529         WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16));
 530
 531         /* FW load takes very long time */
 532         do {
 533                 msleep(1000);
 534                 reg_status = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35);
 535
 536                 if (reg_status & 0x80000000)
 537                         goto done;
 538
 539         } while (++i < USBC_PD_POLLING_LIMIT_S);
 540
 541         return -ETIME;
 542 done:
 543
 544         if ((reg_status & 0xFFFF) != 0) {
 545                 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n",
 546                                 reg_status & 0xFFFF);
 547                 return -EIO;
 548         }
 549
 550         return 0;
 551 }
 552
 553 static int psp_v14_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
 554 {
 555         struct amdgpu_device *adev = psp->adev;
 556         int ret;
 557
 558         WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
 559
 560         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35),
 561                                      0x80000000, 0x80000000, false);
 562         if (!ret)
 563                 *fw_ver = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36);
 564
 565         return ret;
 566 }
 567
 568 static int psp_v14_0_exec_spi_cmd(struct psp_context *psp, int cmd)
 569 {
 570         uint32_t reg_status = 0, reg_val = 0;
 571         struct amdgpu_device *adev = psp->adev;
 572         int ret;
 573
 574         /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */
 575         reg_val |= (cmd << 16);
 576         WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_115,  reg_val);
 577
 578         /* Ring the doorbell */
 579         WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_73, 1);
 580
 581         if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE)
 582                 ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115),
 583                                                  MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT);
 584         else
 585                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115),
 586                                    MBOX_READY_FLAG, MBOX_READY_MASK, false);
 587
 588         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115),
 589                                 MBOX_READY_FLAG, MBOX_READY_MASK, false);
 590         if (ret) {
 591                 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret);
 592                 return ret;
 593         }
 594
 595         reg_status = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_115);
 596         if ((reg_status & 0xFFFF) != 0) {
 597                 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n",
 598                                 cmd, reg_status & 0xFFFF);
 599                 return -EIO;
 600         }
 601
 602         return 0;
 603 }
 604
 605 static int psp_v14_0_update_spirom(struct psp_context *psp,
 606                                    uint64_t fw_pri_mc_addr)
 607 {
 608         struct amdgpu_device *adev = psp->adev;
 609         int ret;
 610
 611         /* Confirm PSP is ready to start */
 612         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115),
 613                            MBOX_READY_FLAG, MBOX_READY_MASK, false);
 614         if (ret) {
 615                 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret);
 616                 return ret;
 617         }
 618
 619         WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr));
 620
 621         ret = psp_v14_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO);
 622         if (ret)
 623                 return ret;
 624
 625         WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr));
 626
 627         ret = psp_v14_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI);
 628         if (ret)
 629                 return ret;
 630
 631         psp->vbflash_done = true;
 632
 633         ret = psp_v14_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE);
 634         if (ret)
 635                 return ret;
 636
 637         return 0;
 638 }
 639
 640 static int psp_v14_0_vbflash_status(struct psp_context *psp)
 641 {
 642         struct amdgpu_device *adev = psp->adev;
 643
 644         return RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_115);
 645 }
 646
 647 static const struct psp_funcs psp_v14_0_funcs = {
 648         .init_microcode = psp_v14_0_init_microcode,
 649         .bootloader_load_kdb = psp_v14_0_bootloader_load_kdb,
 650         .bootloader_load_spl = psp_v14_0_bootloader_load_spl,
 651         .bootloader_load_sysdrv = psp_v14_0_bootloader_load_sysdrv,
 652         .bootloader_load_soc_drv = psp_v14_0_bootloader_load_soc_drv,
 653         .bootloader_load_intf_drv = psp_v14_0_bootloader_load_intf_drv,
 654         .bootloader_load_dbg_drv = psp_v14_0_bootloader_load_dbg_drv,
 655         .bootloader_load_ras_drv = psp_v14_0_bootloader_load_ras_drv,
 656         .bootloader_load_sos = psp_v14_0_bootloader_load_sos,
 657         .ring_create = psp_v14_0_ring_create,
 658         .ring_stop = psp_v14_0_ring_stop,
 659         .ring_destroy = psp_v14_0_ring_destroy,
 660         .ring_get_wptr = psp_v14_0_ring_get_wptr,
 661         .ring_set_wptr = psp_v14_0_ring_set_wptr,
 662         .mem_training = psp_v14_0_memory_training,
 663         .load_usbc_pd_fw = psp_v14_0_load_usbc_pd_fw,
 664         .read_usbc_pd_fw = psp_v14_0_read_usbc_pd_fw,
 665         .update_spirom = psp_v14_0_update_spirom,
 666         .vbflash_stat = psp_v14_0_vbflash_status
 667 };
 668
 669 void psp_v14_0_set_psp_funcs(struct psp_context *psp)
 670 {
 671         psp->funcs = &psp_v14_0_funcs;
 672 }