drivers/gpu/drm/amd/amdgpu/psp_v13_0.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <drm/drm_drv.h>
  24 #include <linux/vmalloc.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_psp.h"
  27 #include "amdgpu_ucode.h"
  28 #include "soc15_common.h"
  29 #include "psp_v13_0.h"
  30
  31 #include "mp/mp_13_0_2_offset.h"
  32 #include "mp/mp_13_0_2_sh_mask.h"
  33
  34 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin");
  35 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin");
  36 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin");
  37 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin");
  38 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin");
  39 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin");
  40 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin");
  41 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin");
  42 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin");
  43 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin");
  44 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin");
  45 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin");
  46 MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin");
  47 MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin");
  48
  49 /* For large FW files the time to complete can be very long */
  50 #define USBC_PD_POLLING_LIMIT_S 240
  51
  52 /* Read USB-PD from LFB */
  53 #define GFX_CMD_USB_PD_USE_LFB 0x480
  54
  55 /* VBIOS gfl defines */
  56 #define MBOX_READY_MASK 0x80000000
  57 #define MBOX_STATUS_MASK 0x0000FFFF
  58 #define MBOX_COMMAND_MASK 0x00FF0000
  59 #define MBOX_READY_FLAG 0x80000000
  60 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2
  61 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3
  62 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4
  63
  64 /* memory training timeout define */
  65 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US   3000000
  66
  67 static int psp_v13_0_init_microcode(struct psp_context *psp)
  68 {
  69         struct amdgpu_device *adev = psp->adev;
  70         const char *chip_name;
  71         char ucode_prefix[30];
  72         int err = 0;
  73
  74         switch (adev->ip_versions[MP0_HWIP][0]) {
  75         case IP_VERSION(13, 0, 2):
  76                 chip_name = "aldebaran";
  77                 break;
  78         case IP_VERSION(13, 0, 1):
  79         case IP_VERSION(13, 0, 3):
  80                 chip_name = "yellow_carp";
  81                 break;
  82         default:
  83                 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
  84                 chip_name = ucode_prefix;
  85                 break;
  86         }
  87
  88         switch (adev->ip_versions[MP0_HWIP][0]) {
  89         case IP_VERSION(13, 0, 2):
  90                 err = psp_init_sos_microcode(psp, chip_name);
  91                 if (err)
  92                         return err;
  93                 /* It's not necessary to load ras ta on Guest side */
  94                 if (!amdgpu_sriov_vf(adev)) {
  95                         err = psp_init_ta_microcode(&adev->psp, chip_name);
  96                         if (err)
  97                                 return err;
  98                 }
  99                 break;
 100         case IP_VERSION(13, 0, 1):
 101         case IP_VERSION(13, 0, 3):
 102         case IP_VERSION(13, 0, 5):
 103         case IP_VERSION(13, 0, 8):
 104                 err = psp_init_toc_microcode(psp, chip_name);
 105                 if (err)
 106                         return err;
 107                 err = psp_init_ta_microcode(psp, chip_name);
 108                 if (err)
 109                         return err;
 110                 break;
 111         case IP_VERSION(13, 0, 0):
 112         case IP_VERSION(13, 0, 7):
 113         case IP_VERSION(13, 0, 10):
 114                 err = psp_init_sos_microcode(psp, chip_name);
 115                 if (err)
 116                         return err;
 117                 /* It's not necessary to load ras ta on Guest side */
 118                 err = psp_init_ta_microcode(psp, chip_name);
 119                 if (err)
 120                         return err;
 121                 break;
 122         default:
 123                 BUG();
 124         }
 125
 126         return 0;
 127 }
 128
 129 static bool psp_v13_0_is_sos_alive(struct psp_context *psp)
 130 {
 131         struct amdgpu_device *adev = psp->adev;
 132         uint32_t sol_reg;
 133
 134         sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
 135
 136         return sol_reg != 0x0;
 137 }
 138
 139 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp)
 140 {
 141         struct amdgpu_device *adev = psp->adev;
 142
 143         int ret;
 144         int retry_loop;
 145
 146         for (retry_loop = 0; retry_loop < 10; retry_loop++) {
 147                 /* Wait for bootloader to signify that is
 148                     ready having bit 31 of C2PMSG_35 set to 1 */
 149                 ret = psp_wait_for(psp,
 150                                    SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 151                                    0x80000000,
 152                                    0x80000000,
 153                                    false);
 154
 155                 if (ret == 0)
 156                         return 0;
 157         }
 158
 159         return ret;
 160 }
 161
 162 static int psp_v13_0_bootloader_load_component(struct psp_context       *psp,
 163                                                struct psp_bin_desc      *bin_desc,
 164                                                enum psp_bootloader_cmd  bl_cmd)
 165 {
 166         int ret;
 167         uint32_t psp_gfxdrv_command_reg = 0;
 168         struct amdgpu_device *adev = psp->adev;
 169
 170         /* Check tOS sign of life register to confirm sys driver and sOS
 171          * are already been loaded.
 172          */
 173         if (psp_v13_0_is_sos_alive(psp))
 174                 return 0;
 175
 176         ret = psp_v13_0_wait_for_bootloader(psp);
 177         if (ret)
 178                 return ret;
 179
 180         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 181
 182         /* Copy PSP KDB binary to memory */
 183         memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes);
 184
 185         /* Provide the PSP KDB to bootloader */
 186         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
 187                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 188         psp_gfxdrv_command_reg = bl_cmd;
 189         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
 190                psp_gfxdrv_command_reg);
 191
 192         ret = psp_v13_0_wait_for_bootloader(psp);
 193
 194         return ret;
 195 }
 196
 197 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp)
 198 {
 199         return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
 200 }
 201
 202 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp)
 203 {
 204         return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE);
 205 }
 206
 207 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp)
 208 {
 209         return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
 210 }
 211
 212 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp)
 213 {
 214         return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV);
 215 }
 216
 217 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp)
 218 {
 219         return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV);
 220 }
 221
 222 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp)
 223 {
 224         return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV);
 225 }
 226
 227 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp)
 228 {
 229         int ret;
 230         unsigned int psp_gfxdrv_command_reg = 0;
 231         struct amdgpu_device *adev = psp->adev;
 232
 233         /* Check sOS sign of life register to confirm sys driver and sOS
 234          * are already been loaded.
 235          */
 236         if (psp_v13_0_is_sos_alive(psp))
 237                 return 0;
 238
 239         ret = psp_v13_0_wait_for_bootloader(psp);
 240         if (ret)
 241                 return ret;
 242
 243         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 244
 245         /* Copy Secure OS binary to PSP memory */
 246         memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes);
 247
 248         /* Provide the PSP secure OS to bootloader */
 249         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
 250                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 251         psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
 252         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
 253                psp_gfxdrv_command_reg);
 254
 255         /* there might be handshake issue with hardware which needs delay */
 256         mdelay(20);
 257         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),
 258                            RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81),
 259                            0, true);
 260
 261         return ret;
 262 }
 263
 264 static int psp_v13_0_ring_init(struct psp_context *psp,
 265                               enum psp_ring_type ring_type)
 266 {
 267         int ret = 0;
 268         struct psp_ring *ring;
 269         struct amdgpu_device *adev = psp->adev;
 270
 271         ring = &psp->km_ring;
 272
 273         ring->ring_type = ring_type;
 274
 275         /* allocate 4k Page of Local Frame Buffer memory for ring */
 276         ring->ring_size = 0x1000;
 277         ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
 278                                       AMDGPU_GEM_DOMAIN_VRAM,
 279                                       &adev->firmware.rbuf,
 280                                       &ring->ring_mem_mc_addr,
 281                                       (void **)&ring->ring_mem);
 282         if (ret) {
 283                 ring->ring_size = 0;
 284                 return ret;
 285         }
 286
 287         return 0;
 288 }
 289
 290 static int psp_v13_0_ring_stop(struct psp_context *psp,
 291                                enum psp_ring_type ring_type)
 292 {
 293         int ret = 0;
 294         struct amdgpu_device *adev = psp->adev;
 295
 296         if (amdgpu_sriov_vf(adev)) {
 297                 /* Write the ring destroy command*/
 298                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
 299                              GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
 300                 /* there might be handshake issue with hardware which needs delay */
 301                 mdelay(20);
 302                 /* Wait for response flag (bit 31) */
 303                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
 304                                    0x80000000, 0x80000000, false);
 305         } else {
 306                 /* Write the ring destroy command*/
 307                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
 308                              GFX_CTRL_CMD_ID_DESTROY_RINGS);
 309                 /* there might be handshake issue with hardware which needs delay */
 310                 mdelay(20);
 311                 /* Wait for response flag (bit 31) */
 312                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
 313                                    0x80000000, 0x80000000, false);
 314         }
 315
 316         return ret;
 317 }
 318
 319 static int psp_v13_0_ring_create(struct psp_context *psp,
 320                                  enum psp_ring_type ring_type)
 321 {
 322         int ret = 0;
 323         unsigned int psp_ring_reg = 0;
 324         struct psp_ring *ring = &psp->km_ring;
 325         struct amdgpu_device *adev = psp->adev;
 326
 327         if (amdgpu_sriov_vf(adev)) {
 328                 ret = psp_v13_0_ring_stop(psp, ring_type);
 329                 if (ret) {
 330                         DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n");
 331                         return ret;
 332                 }
 333
 334                 /* Write low address of the ring to C2PMSG_102 */
 335                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 336                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg);
 337                 /* Write high address of the ring to C2PMSG_103 */
 338                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 339                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg);
 340
 341                 /* Write the ring initialization command to C2PMSG_101 */
 342                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
 343                              GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
 344
 345                 /* there might be handshake issue with hardware which needs delay */
 346                 mdelay(20);
 347
 348                 /* Wait for response flag (bit 31) in C2PMSG_101 */
 349                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
 350                                    0x80000000, 0x8000FFFF, false);
 351
 352         } else {
 353                 /* Wait for sOS ready for ring creation */
 354                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
 355                                    0x80000000, 0x80000000, false);
 356                 if (ret) {
 357                         DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
 358                         return ret;
 359                 }
 360
 361                 /* Write low address of the ring to C2PMSG_69 */
 362                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 363                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg);
 364                 /* Write high address of the ring to C2PMSG_70 */
 365                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 366                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg);
 367                 /* Write size of ring to C2PMSG_71 */
 368                 psp_ring_reg = ring->ring_size;
 369                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg);
 370                 /* Write the ring initialization command to C2PMSG_64 */
 371                 psp_ring_reg = ring_type;
 372                 psp_ring_reg = psp_ring_reg << 16;
 373                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg);
 374
 375                 /* there might be handshake issue with hardware which needs delay */
 376                 mdelay(20);
 377
 378                 /* Wait for response flag (bit 31) in C2PMSG_64 */
 379                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
 380                                    0x80000000, 0x8000FFFF, false);
 381         }
 382
 383         return ret;
 384 }
 385
 386 static int psp_v13_0_ring_destroy(struct psp_context *psp,
 387                                   enum psp_ring_type ring_type)
 388 {
 389         int ret = 0;
 390         struct psp_ring *ring = &psp->km_ring;
 391         struct amdgpu_device *adev = psp->adev;
 392
 393         ret = psp_v13_0_ring_stop(psp, ring_type);
 394         if (ret)
 395                 DRM_ERROR("Fail to stop psp ring\n");
 396
 397         amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 398                               &ring->ring_mem_mc_addr,
 399                               (void **)&ring->ring_mem);
 400
 401         return ret;
 402 }
 403
 404 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp)
 405 {
 406         uint32_t data;
 407         struct amdgpu_device *adev = psp->adev;
 408
 409         if (amdgpu_sriov_vf(adev))
 410                 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102);
 411         else
 412                 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
 413
 414         return data;
 415 }
 416
 417 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
 418 {
 419         struct amdgpu_device *adev = psp->adev;
 420
 421         if (amdgpu_sriov_vf(adev)) {
 422                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value);
 423                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
 424                              GFX_CTRL_CMD_ID_CONSUME_CMD);
 425         } else
 426                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value);
 427 }
 428
 429 static int psp_v13_0_memory_training_send_msg(struct psp_context *psp, int msg)
 430 {
 431         int ret;
 432         int i;
 433         uint32_t data_32;
 434         int max_wait;
 435         struct amdgpu_device *adev = psp->adev;
 436
 437         data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
 438         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, data_32);
 439         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, msg);
 440
 441         max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
 442         for (i = 0; i < max_wait; i++) {
 443                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 444                                    0x80000000, 0x80000000, false);
 445                 if (ret == 0)
 446                         break;
 447         }
 448         if (i < max_wait)
 449                 ret = 0;
 450         else
 451                 ret = -ETIME;
 452
 453         dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n",
 454                   (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
 455                   (ret == 0) ? "succeed" : "failed",
 456                   i, adev->usec_timeout/1000);
 457         return ret;
 458 }
 459
 460
 461 static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops)
 462 {
 463         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 464         uint32_t *pcache = (uint32_t *)ctx->sys_cache;
 465         struct amdgpu_device *adev = psp->adev;
 466         uint32_t p2c_header[4];
 467         uint32_t sz;
 468         void *buf;
 469         int ret, idx;
 470
 471         if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
 472                 dev_dbg(adev->dev, "Memory training is not supported.\n");
 473                 return 0;
 474         } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
 475                 dev_err(adev->dev, "Memory training initialization failure.\n");
 476                 return -EINVAL;
 477         }
 478
 479         if (psp_v13_0_is_sos_alive(psp)) {
 480                 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n");
 481                 return 0;
 482         }
 483
 484         amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
 485         dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
 486                   pcache[0], pcache[1], pcache[2], pcache[3],
 487                   p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
 488
 489         if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
 490                 dev_dbg(adev->dev, "Short training depends on restore.\n");
 491                 ops |= PSP_MEM_TRAIN_RESTORE;
 492         }
 493
 494         if ((ops & PSP_MEM_TRAIN_RESTORE) &&
 495             pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
 496                 dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n");
 497                 ops |= PSP_MEM_TRAIN_SAVE;
 498         }
 499
 500         if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
 501             !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
 502               pcache[3] == p2c_header[3])) {
 503                 dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
 504                 ops |= PSP_MEM_TRAIN_SAVE;
 505         }
 506
 507         if ((ops & PSP_MEM_TRAIN_SAVE) &&
 508             p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
 509                 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n");
 510                 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
 511         }
 512
 513         if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
 514                 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
 515                 ops |= PSP_MEM_TRAIN_SAVE;
 516         }
 517
 518         dev_dbg(adev->dev, "Memory training ops:%x.\n", ops);
 519
 520         if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
 521                 /*
 522                  * Long training will encroach a certain amount on the bottom of VRAM;
 523                  * save the content from the bottom of VRAM to system memory
 524                  * before training, and restore it after training to avoid
 525                  * VRAM corruption.
 526                  */
 527                 sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE;
 528
 529                 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) {
 530                         dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n",
 531                                   adev->gmc.visible_vram_size,
 532                                   adev->mman.aper_base_kaddr);
 533                         return -EINVAL;
 534                 }
 535
 536                 buf = vmalloc(sz);
 537                 if (!buf) {
 538                         dev_err(adev->dev, "failed to allocate system memory.\n");
 539                         return -ENOMEM;
 540                 }
 541
 542                 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
 543                         memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);
 544                         ret = psp_v13_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
 545                         if (ret) {
 546                                 DRM_ERROR("Send long training msg failed.\n");
 547                                 vfree(buf);
 548                                 drm_dev_exit(idx);
 549                                 return ret;
 550                         }
 551
 552                         memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
 553                         adev->hdp.funcs->flush_hdp(adev, NULL);
 554                         vfree(buf);
 555                         drm_dev_exit(idx);
 556                 } else {
 557                         vfree(buf);
 558                         return -ENODEV;
 559                 }
 560         }
 561
 562         if (ops & PSP_MEM_TRAIN_SAVE) {
 563                 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
 564         }
 565
 566         if (ops & PSP_MEM_TRAIN_RESTORE) {
 567                 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
 568         }
 569
 570         if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
 571                 ret = psp_v13_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
 572                                                          PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
 573                 if (ret) {
 574                         dev_err(adev->dev, "send training msg failed.\n");
 575                         return ret;
 576                 }
 577         }
 578         ctx->training_cnt++;
 579         return 0;
 580 }
 581
 582 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr)
 583 {
 584         struct amdgpu_device *adev = psp->adev;
 585         uint32_t reg_status;
 586         int ret, i = 0;
 587
 588         /*
 589          * LFB address which is aligned to 1MB address and has to be
 590          * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P
 591          * register
 592          */
 593         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));
 594
 595         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 596                              0x80000000, 0x80000000, false);
 597         if (ret)
 598                 return ret;
 599
 600         /* Fireup interrupt so PSP can pick up the address */
 601         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16));
 602
 603         /* FW load takes very long time */
 604         do {
 605                 msleep(1000);
 606                 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35);
 607
 608                 if (reg_status & 0x80000000)
 609                         goto done;
 610
 611         } while (++i < USBC_PD_POLLING_LIMIT_S);
 612
 613         return -ETIME;
 614 done:
 615
 616         if ((reg_status & 0xFFFF) != 0) {
 617                 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n",
 618                                 reg_status & 0xFFFF);
 619                 return -EIO;
 620         }
 621
 622         return 0;
 623 }
 624
 625 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
 626 {
 627         struct amdgpu_device *adev = psp->adev;
 628         int ret;
 629
 630         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
 631
 632         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 633                                      0x80000000, 0x80000000, false);
 634         if (!ret)
 635                 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36);
 636
 637         return ret;
 638 }
 639
 640 static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd)
 641 {
 642         uint32_t reg_status = 0, reg_val = 0;
 643         struct amdgpu_device *adev = psp->adev;
 644         int ret;
 645
 646         /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */
 647         reg_val |= (cmd << 16);
 648         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115,  reg_val);
 649
 650         /* Ring the doorbell */
 651         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1);
 652
 653         if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE)
 654                 return 0;
 655
 656         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
 657                                 MBOX_READY_FLAG, MBOX_READY_MASK, false);
 658         if (ret) {
 659                 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret);
 660                 return ret;
 661         }
 662
 663         reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
 664         if ((reg_status & 0xFFFF) != 0) {
 665                 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n",
 666                                 cmd, reg_status & 0xFFFF);
 667                 return -EIO;
 668         }
 669
 670         return 0;
 671 }
 672
 673 static int psp_v13_0_update_spirom(struct psp_context *psp,
 674                                    uint64_t fw_pri_mc_addr)
 675 {
 676         struct amdgpu_device *adev = psp->adev;
 677         int ret;
 678
 679         /* Confirm PSP is ready to start */
 680         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
 681                            MBOX_READY_FLAG, MBOX_READY_MASK, false);
 682         if (ret) {
 683                 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret);
 684                 return ret;
 685         }
 686
 687         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr));
 688
 689         ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO);
 690         if (ret)
 691                 return ret;
 692
 693         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr));
 694
 695         ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI);
 696         if (ret)
 697                 return ret;
 698
 699         psp->vbflash_done = true;
 700
 701         ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE);
 702         if (ret)
 703                 return ret;
 704
 705         return 0;
 706 }
 707
 708 static int psp_v13_0_vbflash_status(struct psp_context *psp)
 709 {
 710         struct amdgpu_device *adev = psp->adev;
 711
 712         return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
 713 }
 714
 715 static const struct psp_funcs psp_v13_0_funcs = {
 716         .init_microcode = psp_v13_0_init_microcode,
 717         .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb,
 718         .bootloader_load_spl = psp_v13_0_bootloader_load_spl,
 719         .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv,
 720         .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv,
 721         .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv,
 722         .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv,
 723         .bootloader_load_sos = psp_v13_0_bootloader_load_sos,
 724         .ring_init = psp_v13_0_ring_init,
 725         .ring_create = psp_v13_0_ring_create,
 726         .ring_stop = psp_v13_0_ring_stop,
 727         .ring_destroy = psp_v13_0_ring_destroy,
 728         .ring_get_wptr = psp_v13_0_ring_get_wptr,
 729         .ring_set_wptr = psp_v13_0_ring_set_wptr,
 730         .mem_training = psp_v13_0_memory_training,
 731         .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw,
 732         .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw,
 733         .update_spirom = psp_v13_0_update_spirom,
 734         .vbflash_stat = psp_v13_0_vbflash_status
 735 };
 736
 737 void psp_v13_0_set_psp_funcs(struct psp_context *psp)
 738 {
 739         psp->funcs = &psp_v13_0_funcs;
 740 }